ACM SIGARCH Student Scholarships for ACM Turing Centenary Celebration

Submitted by Sarita Adve
April 2, 2012

Submitted by Sarita Adve
Call for Nominations
15-16 June 2012
Palace Hotel, San Francisco, CA

Nomination Deadline: 2 April 2012

ACM SIGARCH has a limited number of $1K scholarships to award to
worthy students to attend the ACM Turing Centenary Celebration 15-16
June 2012 at the Palace Hotel in San Francisco, CA. $500 of the award
must be used to cover 2 nights stay at the Palace Hotel. The
remaining balance will go toward travel expenses.

Important Dates:
* Submission Deadline: 2 April 2012.
* Notification of Awards: 9 April 2012.
* ACM Turing Centenary Celebration 15-16 June 2012

A nominee must be a student in good standing who is actively pursuing
research in computer architecture and an ACM SIGARCH student
member/member at the time of the Turing Celebration.

Submission Procedure:
A nomination should consist of the following items:
1. Name, address, phone number, and email address of the person making
the nomination (the nominator).
2. Name, address, phone number, and email address of the candidate for
whom the scholarship is recommended (the nominee).
3. A short statement (200-500 words) summarizing the nominee’s
standing in graduate school (include years in school and estimated
years to completion) and explaining why the nominee deserves the
scholarship (include membership in under represented groups).

Nominations and questions should be submitted to:
Sarita Adve, Vice Chair, ACM SIGARCH

MSPC 2012 extended deadline (March 22)

Submitted by Onur Mutlu
March 22, 2012

Submitted by Onur Mutlu
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness

June 16, 2012
Co-located with PLDI 2012, Beijing, China

Extended submission deadline: March 22, 2012 (11:59pm EDT)
Author notification: April 23, 2012
Final submission: May 1, 2012


Memory continues to be a major bottleneck in almost all computing systems. It
is becoming more so as more cores and agents are sharing parts of the memory
system and as applications that run on the cores are becoming increasingly data
intensive. Continuing the tradition of six previous successful incarnations,
MSPC 2012 will provide a forum for publishing and discussing all aspects of
memory performance and correctness on a variety of systems (multi-core,
desktop, embedded, server/cloud, high-performance computing, sensor, etc) and
related software and hardware innovations at various levels of the technology
stack. We invite new submissions that tackle issues in memory system
performance, efficiency, correctness, and dependability in both hardware and
software layers. Example areas of interest include but are not limited to the

* Hardware, software, and hybrid techniques for better memory performance,
correctness, reliability, efficiency
* Memory hierarchy design for chip multiprocessors (CMPs)
* Emerging memory technologies (e.g., Phase Change Memory, MRAM)
* Characterization and analysis of memory systems performance
* Insightful experimental evaluation and analysis of memory-intensive
* Static and dynamic techniques for understanding and improving memory
performance and efficiency
* Managed memory and garbage collection optimizations
* Hardware and software techniques for ensuring memory safety and detecting
memory-related bugs
* Hardware and software memory models and their impact on programmability
and performance
* Memory system issues in accelerator-based computing (e.g., GPGPU)
* Memory system issues in embedded computers and tiny devices
* Prefetching, compression, latency tolerance techniques for memory
* Memory power and energy management techniques
* Memory reliability management techniques

Software, hardware, and hybrid approaches are encouraged. In addition, we
solicit papers from practitioners describing problems and experiences with
memory performance and correctness in specific application domains.

Submission Guidelines: We encourage the submission of not-fully-polished but
provocative short papers (6-8 pages; 8 pages maximum) or position abstracts
(1-2 pages; 2 pages maximum). Paper submissions should use standard ACM
SIGPLAN conference format (10pt). Copies of accepted papers will be made
available at the workshop and published in the ACM digital library. Submitted
papers must not be simultaneously under review for any other conference or
journal, and authors should point out any substantial overlap with their
previously published or currently submitted work.


General Chair:
Lixin Zhang, ICT, Chinese Academy of Sciences

Program Chair:
Onur Mutlu, Carnegie Mellon University

Program Committee:
Rajeev Balasubramonian, Utah
Emery Berger, UMass Amherst
John Carter, IBM Research
Jichuan Chang, HP Labs
Andrew Chien, Chicago
Trishul Chilimbi, Microsoft Research
Cliff Click, Azul Systems
Eiman Ebrahimi, UT-Austin
Mattan Erez, UT-Austin
Eugene Gorbatov, Intel
Nikos Hardavellas, Northwestern
Maurice Herlihy, Brown
Brian Hirano, Oracle
Hillery Hunter, IBM Research
Jim Larus, Microsoft Research
Alvy Lebeck, Duke
Thomas Moscibroda, Microsoft Research
Naveen Muralimanohar, HP Labs
Satish Narayanasamy, Michigan
Erez Petrank, Technion
Moinuddin Qureshi, Georgia Tech
Xipeng Shen, William and Mary
Osman Unsal, BSC
Chris Wilkerson, Intel
Ben Zorn, Microsoft Research

Steering Committee:
Emery Berger, UMass Amherst
Brad Chen, Google
Trishul Chilimbi, Microsoft Research
Chen Ding, Rochester
Madan Musuvathi, Microsoft Research
Xipeng Shen, College of William & Mary
Jeffrey S. Vetter, Oak Ridge National Lab & Georgia Tech
Ben Zorn, Microsoft Research

Web and Submissions Chairs
Chris Fallin, Carnegie Mellon University
Vivek Seshadri, Carnegie Mellon University

CFP: ICA3PP-2012 in Fukuoka, Japan

Submitted by Toshinori Sato
September 4 to September 7, 2012

Submitted by Toshinori Sato
ICA3PP 2012 Call For Papers
12th International Conference on Algorithms and Architectures for
Parallel Processing (ICA3PP 2012)
Fukuoka, Japan, September 04-07, 2012

ICA3PP-12 is the 12th in this series of conferences started in 1995 that
are devoted to algorithms and architectures for parallel processing.
ICA3PP is now recognized as the main regular event of the world that
covers the many dimensions of parallel algorithms and architectures,
encompassing fundamental theoretical approaches, practical experimental
projects, and commercial components and systems. As applications of
computing systems have permeated in every aspects of daily life, the
power of computing system has become increasingly critical. This
conference provides a forum for academics and practitioners from
countries around the world to exchange ideas for improving the
efficiency, performance, reliability, security and interoperability of
computing systems and applications.

ICA3PP-12 will be run in technical co-sponsorship (pending) with the
IEEE and the IEEE Computer Society Technical Committee on Scalable
Computing. ICA3PP-2012 will be co-located with UIC-2012 and ATC-2012

Topics of interest include, but not limited to:
– Cluster, Distributed & Parallel Operating Systems and Middleware
– Cloud, Grid, and Services Computing
– Reliability and Fault-tolerant Computing
– Multi-core Programming and Software Tools
– Distributed Scheduling and Load Balancing
– High-performance Scientific Computing
– Parallel Algorithms
– Parallel Architectures
– Parallel and Distributed Databases
– Parallel I/O Systems and Storage Systems
– Parallel Programming Paradigms
– Performance of Parallel & Distributed Computing Systems
– Resource Management and Scheduling
– Tools and Environments for Parallel & Distributed Software Development
– Software and Hardware Reliability, Testing, Verification and Validation
– Security, Privacy, and Trusted Computing
– Self-healing, Self-protecting and Fault-tolerant Systems
– Information Security In Internet
– Multimedia in Parallel Computing
– Parallel Computing in Bioinformatics
– Dependability Issues in Computer Networks and Communications
– Dependability Issues in Distributed and Parallel Systems
– Dependability Issues in Embedded Parallel Systems
– Industrial Applications
– Scientific Applications

Submission Guidelines:
Submitted papers must not substantially overlap with papers that have
been published or that are simultaneously submitted to a journal or a
conference with proceedings. Papers must be clearly presented in
English, must not exceed 15 pages in LNCS format, including tables,
figures, references and appendixes, with Portable Document Format
(.pdf). Papers will be selected based on their originality,
significance, relevance, and clarity of presentation assessed by at
least three reviewers. Submission of a paper should be regarded as a
commitment that, should the paper be accepted, at least one of the
authors will register and attend the conference to present the work.

The publication will be Springer Lecture Notes in Computer Science (EI
indexed). Best Paper Awards will be presented to high quality papers.
Selected best papers will be published in some high quality
international journals: Concurrency and Computation: Practice and
Experience (Wiley) and Future Generation Computer Systems (Elsevier),
all SCI and EI indexed.

Important Dates:
Paper Submission Deadline: March 31, 2012
Authors Notification: May 15, 2012
Final Manuscript Due: June 15, 2012


Honorary General Chair
Iwao Yamamoto, Kyushu Sangyo University, Japan

General Chairs
Koji Nakano, Hiroshima University, Japan
Albert Zomaya, The University of Sydney, Australia
Yang Xiang, Deakin University, Australia

Program Chairs
Ivan Stojmenovic, University of Ottawa, Canada
Bernady O. Apduhan, Kyushu Sangyo University, Japan
Guojun Wang, Central South University, China

International Advisory Committee
Tadashi Dohi, Hiroshima University, Japan (Chair)
Takashi Naka, Kyushu Sangyo University, Japan
Toshinori Sueyoshi, Kumamoto University, Japan
More to be added.

Steering Committee
Laurence T. Yang, St. Francis Xavier University, Canada
Wanlei Zhou, Deakin University, Australia
Yi Pan, Georgia State University, USA
Andrzej Goscinski, Deakin University, Australia

Workshop Chairs
Xu Huang, University of Canberra, Australia
Bin Xiao, Hong Kong Polytechnic University, Hong Kong

Publicity Chairs
Kejie Lu, University of Puerto Rico at Mayaguez, Puerto Rico
Wen Tao Zhu, Chinese Academy of Sciences, China
Muhammad Khurram Khan, King Saud University, Saudi Arabia
Toshinori Sato, Fukuoka University, Japan

Program Committee
Bechini Alessio, University of Pisa, Italy
Giuseppe Amato, ISTI-CNR, Italy
Cosimo Anglano, Universita del Piemonte Orientale, Italy
Novella Bartolini, Univ. of Rome La Sapienza, Italy
Ladjel Bellatreche, ENSMA, France
Ateet Bhalla, NRI Institute of Information Science and Technology, India
Massimo Cafaro, University of Salento, Italy
Andre Carvalho, Universidade de Sao Paulo, Brasil
Tania Cerquitelli, Politecnico di Torino, Italy
Ruay-Shiung Chang, National Dong Hwa University, Taiwan
Yue-Shan Chang, National Taipei University, Taiwan
Tzung-Shi Chen, National University of Tainan, Taiwan
Zizhong Chen, Colorado School of Mines, USA
Raphaël Couturier, University of Franche Comte, France
Gennaro Della Vecchia, Gennaro Della Vecchia – ICAR-CNR, Italy
Susan Donohue, The College of New Jersey, USA
Todd Eavis, Concordia University, Canada
Jinzhu Gao, University of the Pacific, USA
Jose Daniel Garcia, University Carlos III of Madrid, Spain
Harald Gjermundrod, University of Nicosia, Cyprus
Houcine Hassan, Univ. Politecnica de Valencia, Spain
Pilar Herero, Univ. Politecnica de Madrid, Spain
Ching-Hsien Hsu, Chung Hua University, Taiwan
Yo-Ping Huang, National Taipei University of Technology, Taiwan
Muhammad Khurram Khan, King Saud University, Saudi Arabia
Soo-Kyun Kim, PaiChai University, Korea
Changhoon Lee, Hanshin University, Korea
Laurent Lefevre, “Laurent Lefevre, INRIA, University of Lyon”, France
Keqin Li, State University of New York at New Paltz, USA
Keqin Li, SAP Research, France
Keqiu Li, Dalian University of Technology, China
Kai Lin, Dalian University of Technology, China
Tomas Margalef, Universitat Autonoma de Barcelona, Spain
Amiya Nayak, University of Ottawa, Canada
Marion Oswald, Hungarian Academy of Sciences, Hungary
Deng Pan, Florida International University, USA
Apostolos Papadopoulos, Aristotle Univ of Thessaloniki, Greece
Dana Petcu, West University of Timisoara, Romania
Pedro Pereira Rodrigues, University of Porto, Portugal
Marcel C. Rosu, IBM, USA
Giovanni Maria Sacco, Universita di Torino, Italy
Erich Schikuta, University of Vienna, Austria
Martin Schulz, Lawrence Livermore National Laboratory, USA
Edwin Sha, University of Texas at Dallas, USA
Rahul Shah, Louisiana State University, USA
Giandomenico Spezzano, ICAR-CNR, Italy
Peter Strazdins, The Australian National University, Australia
Uwe Tangen, Ruhr-Universitaet Bochum, Germany
Chen Wang, CSIRO ICT Centre, Australia
Xiaofang Wang, Villanova University, USA
Qishi Wu, University of Memphis, USA
Fatos Xhafa, Polytechnic University of Catalonia, Spain
Chao-Tung Yang, Tunghai University, Taiwan
Zhiwen Yu, Northwestern Polytechnical University, China
Sotirios G. Ziavras, NJIT, USA
Roger Zimmermann, National University of Singapore, Singapore
Akihiro Fujiwara, Kyushu Institute of Technology, Japan
Wei Sun, NEC Coporation, Japan
Shuichi Ichikawa, Toyohashi University of Technology, Japan
Susumu Matsumae, Saga University, Japan
Yasuhiko Takenaga, The University of Electro-Communications, Japan
Hirotaka Ono, Kyushu University, Japan
Tomoaki Tsumura, Nagoya Institute of Technology, Japan
Hidetsugu Irie, The University of Electro-Communications, Japan
Hideharu Amano, Keio University, Japan
Anthony Sulistio, High Performance Computing Center Stuttgart (HLRS),
Purushotham Bangalore, University of Alabama, USA
Surendra Byna, Lawrence Berkeley National Lab, USA
Christian Engelman, Oak Ridge National Lab, USA
Rama Govindaraju, Google, USA
Amit Majudar, San Diego Supercomputer Center, USA
Esmond Ng, Lawrence Berkeley National Lab, USA
Kalyan Perumalla, Oak Ridge National Lab, USA
Fabrizio Petrini, IBM Research, USA
Sushil Prasad, University of Georgia, USA
Rajeev Raje, Indiana University-Purdue University Indianapolis, USA
Subhash Saini, NASA, USA
C.D. Sudheer, Sri Sathya Sai Institute of Higher Learning, India
Ramesh Thirumale, Boeing, USA
Wei Lu, Keene University, USA
Kosuke Takano, Kanagawa Institute of Technology, Japan
Martine Wedlake, IBM, USA
Marco Lapegna, University of Napoli Federico II, Italy
Keivan Kian-Mehr, University of Western Ontario, Canada
Michael O’Grady, University College Dublin, Ireland
Tansel Ozyer, TOBB University of Economics and Technology, Turkey
Karampelas Panagiotis, Hellenic American University, Greece
Eric Pardede, La Trobe University, Australia
Xingquan(Hill) Zhu, Florida Atlantic University, USA
Ananth Kalyanaraman, Washington State University, USA
Alexandros Stamatakis, Heidelberg Institute for Theoretical Studies, Germany
Srinivas Aluru, Iowa State University, USA
George Bosilca, University of Tennessee, USA
Stéphane Genaud, Université de Strasbourg, France
Paul Lu, University of Alberta, Canada
Thomas Rauber, University of Bayreuth, Germany
Cal Ribbens, Virginia Polytechnic Institute and State University, USA
Morris Riedel, Jülich Supercomputing Centre, USA
Paolo Trunfio, University of Calabria, Italy
Cosimo Anglano, Universita del Piemonte Orientale, Italy
Eugen Dedu, University of Franche-Comté, France
Etienne Rivière, University of Neuchatel, Switzerland
Françoise Sailhan, CNAM, France
Chryssis Georgiou, University of Cyprus, Cyprus
Shi-Jinn Horng, Natl Taiwan U. of Science & Technology, Taiwan
Helen Karatza, Aristotle University of Thessaloniki, Greece
Yingshu Li, Georgia State University, USA
Laurence T. Yang, St. Francis Xavier University, Canada
Feng-Tsun Chien, National Chiao Tung University, Taiwan
Shiwen Mao, Auburn University, USA
Natalija Vlajic, York University, Canada
Weiwei Fang, Beijing Jiaotong University, China
Qing Dong, Naval Research Laboratory, USA
Feiyu Xiong, Drexel University, USA
Bo Yang, University of Electronic Science and Technology of China, China
Kenin Coloma, Aol, USA
Joel Koshy, Yahoo!, USA
Vidhyashankar Venkataraman, Yahoo!, USA
Rob Latham, Argonne National Laboratory, USA
David Expósito, University Carlos III, Spain
Franco Frattolillo, Universitá del Sannio, Italy
Karl Fuerlinger, Ludwig-Maximilians-University Munich, Germany
Javier García, University Carlos III, Spain
Enrique Quintana, Universidad Jaume I, Spain
Yong Zhao, University of Electronic Science and Technology of China, China
Jorge Bernal Bernabe, University of Murcia, Spain
Scott Fowler, Linköping University, Sweden
Longxiang Gao, Deakin University, Australia
Juan M. Marin, University of Murcia, Spain
Ronald Petrlic, University of Paderborn, Germany
Kenji Saito, Keio University, Japan
Gaocai Wang, Guangxi University, China
Sherali Zeadally, University of the District of Columbia, USA
Jing Chen, National Cheng Kung University, Taiwan
Michael Glass, University Erlangen-Nurember, Germany
Edmund Lai, Massey University, NewZealand
Pramod Kumar, institute for Infocomms Research, Singapore
Jogesh Muppala, Hong Kong University of Science and Technology, Hong Kong
Ching-Lung Su, National Yunlin University of Science and Technology, Taiwan
Hiroyuki Tomiyama, Ritsumeikan University, Japan
Jiang Xu, Hong Kong University of Science and Technology, Hong Kong
Jason Xue, Hong Kong City University, Hong Kong
Alejandro Masrur, Technology University of Munich, Germany
Arndt Bode, Technische Universität München, Germany
Luc Bougé, ENS Cachan, France
Harald Kosch, University Passau, Germany
Henrique Andrade, Goldman Sachs, USA
Dorian Arnold, University of New Mexico, USA
Rajkumar Buyya, The University of Melbourne, Australia
Che-Rung Lee, National Tsing Hua University, Taiwan
Kevin Pedretti, Sandia National Laboratories, USA
Luis Javier García Villalba, Universidad Complutense de Madrid (UCM), Spain
Koji Nakano, University of Hiroshima, Japan
Mineo Takai, University of California, USA
Kamesh Madduri, Penn State University, USA
Toshihiro Yamauchi, Okayama University, Japan
Morihiro Kuga, Kumamoto University, Japan
Rafael Santos, National Institute for Space Research, Brazil


Submitted by Koen De Bosschere

Submitted by Koen De Bosschere
ACACES 2012 Call for participation

Eighth International Summer School on
Advanced Computer Architecture and Compilation
for High-Performance and Embedded Systems
Fiuggi, Italy
Sunday July 8 – Saturday July 14, 2012
Organized by the HiPEAC Network of Excellence
sponsored by the 7th European framework programme

The ACACES Summer School is a one week summer school for computer architects
and tool builders working in the field of high performance computer
architecture, compilation and embedded systems. The school aims at the
dissemination of advanced scientific knowledge and the promotion of
international contacts among scientists from academia and industry.
A distinguishing feature of this Summer School is its broad scope ranging
from low level technological issues to advanced compilation techniques. In
the design of modern computer systems one has to be knowledgeable about
architecture as well as about the quality of the code, and how to improve
it. This summer school offers the ideal mix of the two worlds, both at
the entry level and at the most advanced level.

The ACACES Summer School is organized by the HiPEAC Network of Excellence
(, but it is open to everybody. However, previous
training and/or experience in computer science as well as a background in
computer architecture or compilation is indispensable.

The Summer School will take place in Fiuggi, a small town near Rome, Italy.
Students and lecturers will be accommodated in private hotel rooms with
standard hotel accommodation. There will be lots of opportunities for
interaction among the participants, both in and out of the classrooms,
during the meals, at the bar or at the swimming pool, in the fitness room,
in the spa and in the city. Long after-the-lecture discussions are one of
the major assets of this summer school. You will remember this summer
school for a long time.

Scientific program
Sunday July 8: Opening ceremony with a keynote.
Monday July 9: “From little Acorns: the early history of ARM”,
by John Biggs, ARM

Starting on Monday 9, 2012:
12 courses spread over two morning slots and two afternoon slots. Per slot
there are three parallel courses of which one can be taken. The topics
of this year’s Summer School will be presented by the following world-class
experts in their domain.

Murali Annavaram, University of Southern California, USA
the next frontier for systematic benchmarking and monitoring tools
David August, Princeton University, USA
Next generation automatic parallelization
Katherine Compton, University of Wisconsin-Madison, USA
Resource management in reconfigurable computing systems
Natalie Enright Jerger, University of Toronto, Canada
Networks-on-Chip: communication challenges for many-core architectures
Antonio Gonzalez, Intel & UPC, Barcelona, Spain
Processor microarchitecture
Ted Huffmire, Naval Postgraduate School, USA
Hardware support for trustworthy systems
Krishna Palem, NTU Singapore & Rice University, USA
What to do about the end of Moore’s law (probably)?
Keshav Pingali, University of Texas, Austin, USA
Multi-core parallel programming using the Galois system
Ravi Rajwar, Intel, USA
Transactional memory and synchronization
Josh Simons, VMware, USA
Virtualization and High Performance Computing
Juergen Teich, University of Erlangen-Nuremberg, Germany
Domain-specific and resource-aware computing on multi-core architectures
Thomas Wenisch, University of Michigan, USA
Designing efficient data centers

Monday evening: invited talk.

Wednesday afternoon: Poster session
Friday evening: Farewell dinner and party

All participants will receive a certificate of attendance with a
description of the courses followed. Some universities will accept
this certificate in their PhD program.

Poster Session
The poster session on Wednesday afternoon will provide an ideal
opportunity for students to present their own work in progress
and get feedback from senior researchers and fellow-students,
and can be the beginning of future collaboration. A booklet with
a 1 to 4 page abstract per poster will be distributed to all
summer school participants.

To stimulate maximum interaction between lecturers and
participants, the steering committee of the Summer School will
limit the attendance to about 200 participants. The application
form is on the website, and the deadline for application is
April 1, 2012.

Important dates
March 31, 2012: deadline for admission application
April 15, 2012: notification of admission
May 15, 2012: deadline for payment
June 1, 2012: deadline for poster abstract

1000 euro, all inclusive:
– Transfer from Rome FCO airport to Fiuggi by bus on Sunday July 8, 2012.
– 6 nights in private room with bathroom.
– 6 breakfasts
– 5 three course lunches
– 5 three course dinners
– Farewell dinner on Friday evening
– 2 half-hour coffee breaks per day
– Registration for 4 top-quality courses + printed handouts
– Student kit
– Access to the poster session + book of abstracts
– Free Internet during the duration of the summer school
– Free access to the spa
– Free transfer from Fiuggi to Rome FCO airport or to downtown Rome on
Saturday July 14, 2012.

Steering Committee
Koen De Bosschere, Ghent University, Belgium, Chair
Philippe Bonnot, Thales, France
Giuseppe Desoli, ST, Italy
Marc Duranton, CEA, France
Paul Heysters, Recore, The Netherlands
Manolis Katevenis, FORTH, Greece
Rainer Leupers, RWTH Aachen, Germany
Bilha Mendelson, IBM, Haifa
Mike O’Boyle, University of Edinburgh, UK
Emre Ozer, ARM, UK
Per Stenstrom, Chalmers, Sweden
Olivier Temam, INRIA, France
Adras Vajda, Ericsson, Sweden
Mateo Valero, UPC, Barcelona, Spain

Contact information
Koen De Bosschere

HOT CHIPS 24: A Symposium on High-Performance Chips

Submitted by Don Draper
March 30, 2012

Submitted by Don Draper
Stanford University, Palo Alto, California

August 2012

Deadline for submissions: March 30, 2012
Notification of acceptance: May 1, 2012
Deadline for final version: July 1, 2012

* General Purpose Processor Chips
– High-Performance and Low-Power
– Multi-Core and Highly-Reliable Systems

* Mobile and Embedded Devices
– Graphics/Multimedia/Game
– SoC, Security, and DSP chips

* Communications and Networking
– Wireless LAN/WAN/PAN
– Network and IO Processors

* Other Chips
– FPGAs and FPGA-Based Systems
– Memory Technologies and Chipsets

* Software for multi-Core and Heterogeneous Systems
– Programming models, Runtime Systems
– Compilers and Operating Systems
– Performance and Power Debug and Evaluations

* Other Technologies
– Power and Thermal Management
– Packaging and Testing
– Display Technologies
– On-Chip Optics & Sensors
– Novel Computing Technologies

Presentations at HOT CHIPS are in the form of
30-minute talks in PowerPoint or .PDF. Presentation
slides will be published in the HOT CHIPS Proceedings.
Participants are not required to submit written
papers, but a select group will be invited to submit
a paper for inclusion in a special issue of IEEE Micro.

A limited number of Student Posters describing applied
research performed at a university will be accepted for
presentation at the conference. Student poster submissions
consist of 4 slides and a one-page summary. The most
outstanding poster will receive a Best Poster Award.

Submissions must specify “Presentation” or “Student
Poster” and consist of a title, extended abstract
(two pages maximum.), and the presenter’s contact
information (name, affiliation, job title, address,
phone(s), fax, and email). Please indicate whether
you have submitted, intend to submit, or have already
presented or published a similar or overlapping
submission to another conference or journal. Also
indicate if you would like the submission to be held
confidential. If so indicated, these submissions
remain confidential until the first day of the conference.

Submissions are evaluated by the Program Committee on
the basis of performance of the device(s), degree of
innovation, use of advanced technology, potential market
significance, and anticipated interest to the audience.
Research and software contributions will be evaluated
with similar criteria. To the extent that you are
describing a product, you must indicate its status
– design, development, tape out, silicon, shipping, etc.

Submit extended abstracts in plain text or .PDF, which
may contain figures, with a minimum 10-point font by
following instructions on the Hot Chips 24 website:

Authors will be notified of acceptance decisions by May 1,
2012. Send questions relating to the program to the
program chairs at:
and questions relating to conference operation or
organization to the general chair, Larry Lewis, at:

Sponsored by the Technical Committee on Microprocessors
and Microcomputers of the IEEE Computer Society and the
Solid State Circuits Society.

To view Hot Chips 2011 presentations and videos, which are
now open to the public, go to:

Program Committee Co-Chairs:
Christos Kozyrakis Stanford University
Rumi Zahir Intel