IISWC 2012 Call for Papers

Submitted by Thomas Wenisch
http://www.iiswc.org/
November 4 to November 6, 2012

Submitted by Thomas Wenisch
http://www.iiswc.org/
2012 Annual IEEE International Symposium on Workload Characterization
(IISWC 2012)
Nov. 4-6, 2012 – La Jolla, CA

Abstracts Due: May 25, 2012, 11:59pm PDT.
Paper Submission: June 1, 2012. 11:59pm PDT.

This symposium is dedicated to the understanding and characterization of
workloads that run on all types of computing systems. New applications and
programming paradigms continue to emerge as the diversity and performance of
computers increase. On the one hand, computing workloads evolve and change
with advances in microarchitecture, compilers, programming languages, and
networking/communication technologies. On the other hand, improvements in
computing technology are usually based on a solid understanding and analysis
of existing workloads. Whether they are PDAs, wireless and embedded systems
at the low end or massively parallel systems at the high end, the design of
future computing machines can be significantly improved if we understand the
characteristics of the workloads that are expected to run on them. This
symposium, sponsored by IEEE Computer Society and the Technical Committee
on Computer Architecture, will focus on characterizing and understanding
modern computer applications, commercial and scientific computing.

We solicit papers in all areas related to characterization of computing system
workloads. Topics of interest include (but are not limited to):

• Characterization of applications in areas including
o Search engines, e-commerce, web services, databases, file/appl. servers
o Embedded, mobile, multimedia, real-time, graphics, gaming, telepresence
o Life sciences, bioinformatics, scientific computing, finance, forecasting
o Security, reliability, biometrics
o Grid and Could computing
• Characterization of OS, Virtual Machine, middleware and library behavior
o Virtual machines, Websphere, .NET, Java VM, databases
o Graphics libraries, scientific libraries
• Characterization of system behavior, including
o Operating system and hypervisor effects and overheads
o Effects due to virtualization and dynamic optimization
o Hardware accelerators (GPGPU, XML, crypto, etc)
o Failures, availability, and reliability
o User behavior and system-user interaction
o Instrumentation methodologies for workload verification & characterization
o Techniques for accurate analysis/measurement of production systems
• Implications of workloads in design issues, such as
o Power management, reliability, security, performance
o Processors, memory hierarchy, I/O, and networks
o Design of accelerators, FPGA’s, GPU’s, etc.
• Benchmark creation, analysis, and evaluation issues, including
o Multithreaded benchmarks, benchmark cloning
o Profiling, trace collection, synthetic traces o Validation of benchmarks
• Analytical and abstract modeling of program behavior and systems
• Emerging and future workloads
o Transactional memory workloads; workloads for multi/many-core systems
o Stream-based computing workloads; web2.0/internet workloads

General Chair: Allan Snavely, UCSD
Program Chair: Thomas Wenisch, U. Michigan

Program Committee
Tor Aamodt, UBC
Murali Annavaram, USC
James Balfour, NVIDIA
Leslie Barnes, AMD
Sangyeun Cho, U. Pittsburgh
Reetu Das, U. Michigan
Stijn Eyerman, Ghent
Babak Falsafi, EPFL
Boris Grot, EPFL
Nikos Hardavellas, Northwestern U.
Engin Ipek, U. Rochester
Ravi Iyer, Intel
Jangwoo Kim, POSTECH
Hsien-Hsin Lee, Georgia Tech
Kevin Lim, HP Labs
Vijay Reddi, UT-Austin
Ali Saidi, ARM
Jennifer Sartor, U. Ghent
Martin Schulz, LLNL
Ravi Soundararajan, VMWare
Viji Srinivasan, IBM
Kushagra Vaid, Microsoft
Philip Wells, Google

BigHouse v0.1 released

Submitted by David Meisner
http://www.eecs.umich.edu/BigHouse

Submitted by David Meisner
http://www.eecs.umich.edu/BigHouse
BigHouse is a simulation infrastructure for data center systems to help
understand issues such as performance, power management, and
fault tolerance. Unlike traditional microarchitectural simulators, it
raises the level of abstraction to tasks/requests in a data center.
Leveraging queuing theory and stochastic modeling, BigHouse
can simulate interesting data center problems in minutes rather than days.

Source and documentation available at:
http://www.eecs.umich.edu/BigHouse
Questions? Email bighouse@eecs.umich.edu

Extended Submission Deadline — Dark Silicon Workshop 2012 submission deadline extended to April 9

Submitted by Jack Sampson
http://darksilicon.ucsd.edu
April 9, 2012 at 23:45

Submitted by Jack Sampson
http://darksilicon.ucsd.edu
Update: The DaSi 2012 submission deadline has been extended to April 9th
(from April 2nd).

**** Call For Presentations ****

http://darksilicon.ucsd.edu
The 1st Dark Silicon Workshop
Portland, Oregon USA
June 10th, 2012. Held in conjunction with ISCA

The first Dark Silicon Workshop provides a unique forum for discussing
the challenges and opportunities that Dark Silicon presents. There are
many research questions left to answer before new architectures built
specifically to mitigate or exploit dark silicon become the default
platforms for general purpose computing. To scale alongside dark
silicon, architects will need to design and verify specialized
processors in increasing numbers. Making heterogeneous platforms easy
to program will require us to reconsider traditional language and OS
abstractions. Traditionally, many of the performance gains from
specialized hardware stem from customized memory designs, and it is
not yet clear how best to integrate multiple such memory designs
together into a single architecture. These and other challenges will
face researchers as they shed light on silicon’s dark future.

The organizing committee is soliciting presentations on any topic
related to Dark Silicon, including (but not limited to):
– Architectural approaches to managing and exploiting dark silicon
– Power management techniques
– Energy/power-efficient circuit designs
– Energy/power-efficient memory systems
– Scalable design and synthesis techniques for customizable and
specialized cores
– Novel applications for idle chip area
The goal is to facilitate the exchange of the latest ideas, insights,
and knowledge that can propel future progress. In lieu of printed
proceedings, we will post the slides and extended abstracts of the
presentations online. Presentation of new work at the workshop does
not preclude future publication.

Workshop submissions should be in the form of a 2-page presentation
abstract. Submissions will be evaluated on the basis of impact,
novelty, and general interest. The submission deadline is April 9,
2012, with notification of acceptance by May 3, 2012.

Further details on abstract submission, technical program, tutorials,
travel, social program, and travel grants are provided at the
workshop website:
http://DarkSilicon.ucsd.edu

Organizing Committee:
Babak Falsafi, EPFL
Jack Sampson, UCSD
Steven Swanson, UCSD
Michael B. Taylor, UCSD

Program Committee:
Krste Asanovic, Berkeley
David Brooks, Harvard
Calin Cascaval, Qualcomm
Babak Falsafi, EPFL
Nikos Hardavellas, Northwestern University
James Hoe, Carnegie Mellon
Norm Jouppi, HP Labs
Brucek Khailany, Nvidia
Martha Kim, Columbia
Scott Mahlke, University of Michigan
Milo Martin, University of Pennsylvania
Jack Sampson, UCSD
Karthikeyan Sankaralingam, University of Wisconsin
Kevin Skadron, University of Virginia
Guri Sohi, University of Wisconsin
Steven Swanson, UCSD
Michael B. Taylor, UCSD

Call For Submissions: JWAC-3 (Memory Scheduling Championship)

Submitted by Niladrish Chatterjee
http://www.cs.utah.edu/~rajeev/jwac12/
June 9, 2012

Submitted by Niladrish Chatterjee
http://www.cs.utah.edu/~rajeev/jwac12/
3rd JILP Workshop on Computer Architecture Competitions (JWAC-3)
Memory Scheduling Championship (MSC)
June 9th 2012, in conjuction with ISCA-39

The workshop on computer architecture competitions is a forum for holding
competitions to evaluate computer architecture research topics. The third
workshop is organized around a competition for memory scheduling
algorithms. The Memory Scheduling Championship (MSC) invites contestants
to submit their memory scheduling code to participate in this competition.
Contestants must develop algorithms to optimize multiple metrics on a
common evaluation framework provided by the organizing committee.

Contestants must submit their scheduler code along with a short paper
that summarizes the design and results of their scheduler.

More details on the competition can be found here:
http://www.cs.utah.edu/~rajeev/jwac12/

Submissions due: April 23, 2012
Acceptance notification: April 30, 2012
Final version due (code and report): June 1, 2012
Results announced: at workshop (June 9, 2012)

Simulation infrastructure resources:
USIMM Version 1.1 Download : http://www.cs.utah.edu/~rajeev/usimm-v1.1.tar.gz
USIMM Technical Report : http://www.cs.utah.edu/~rajeev/pubs/usimm.pdf
USIMM-users mailing list :
http://mailman.cs.utah.edu/mailman/listinfo/usimm-users
Blog post for comments and updates:
http://utaharch.blogspot.com/2012/02/usimm.html

Organizing Committee: Rajeev Balasubramonian (Univ. of Utah),
Niladrish Chatterjee (Univ. of Utah), Zeshan Chishti (Intel)

Steering Committee: Alaa R. Alameldeen (Intel), Eric Rotenberg (NC State)

HiPEAC 2013 Call For Papers

Submitted by Nikola Puzovic
http://www.hipeac.net/conference
January 21 to January 23, 2013

Submitted by Nikola Puzovic
http://www.hipeac.net/conference

Call for Papers

HiPEAC 2013: 8th International Conference on
High-Performance and Embedded Architectures and Compilers
January 21-23, 2013, Berlin, GERMANY

http://www.hipeac.net/hipeac2013
==========

IMPORTANT DATES:
* Workshops/tutorials: June 1, 2012
* Papers: June 18, 2012
* Paper selection: November 15, 2012
* Posters: October 15, 2012

==========

The HiPEAC conference is the premier scientific networking forum for experts in
computer architecture, programming models, compilers and operating systems for
embedded and general-purpose systems. Emphasis is given on cross-cutting
research and innovative ideas (new programming models, novel architecture
approaches, new technologies, etc.). The conference hosts a number of
associated workshops, tutorials, a large poster session and an exhibition that
run in parallel with the conference. The 8th HiPEAC conference will take place
in Berlin, Germany from Monday 21 to Wednesday January 23, 2013.

JOURNAL FIRST PUBLICATION MODEL

In 2011, TACO and HiPEAC jointly carried out an experiment with a publication
model where original contributions on HiPEAC topics were solicited for TACO.
Record-high numbers of submitted and accepted papers witness the significant
interest in this model. This year, TACO seeks original submissions at any time.
Accepted TACO papers by November 15, 2012 and whose topics match those of
HiPEAC will be selected and invited for presentation at HiPEAC conference. In
order to enjoy two rounds of review, and to be considered for invitation to
present at the HiPEAC 2013 conference, papers should be submitted no later than
June 18, 2012. Accepted papers will be published in regular issues of ACM TACO.

For submission details, please refer to http://mc.manuscriptcentral.com/taco.

Topics of interest to HiPEAC 2013 include, but are not limited to:

– Processor architectures
– Memory system optimization
– Power, performance and implementation efficient designs
– Reliability and real-time support in processors, compilers
and run-time systems
– Network and security processors
– Application-specific processors and accelerators
– Reconfigurable architectures
– Simulation and methodology
– Hardware and run-time support for programming languages
– Compiler techniques
– Feedback-directed optimization
– Program characterization and analysis techniques
– Dynamic compilation, adaptive execution, and continuous profiling/optimization
– Binary translation/optimization
– Code size/memory footprint optimizations

ORGANIZING COMMITTEE

HiPEAC 2013 General Chairs:
* Ben Juurlink (Technische Universität Berlin, Germany)
* Keshav Pingali (University of Texas Austin, USA)

Program Chairs:
* André Seznec (INRIA/IRISA, France)
* Lawrence Rauchwerger (Texas A&M University, USA)

Editor-in-chief of ACM Transactions on Architecture and Code Optimization:
* Tom Conte (Georgia Institute of Technology, USA)

Poster Chairs:
* Koen De Bosschere (Ghent University, Belgium)
* Qing Yi (University of San Antonio, USA)

Workshops/Tutorials Chair:
* Sascha Uhrig (Technische Universität Dortmund, Germany)

Industrial exhibit and European projects sub-committee:
* Henri-Pierre Charles (CEA, France)
* Rosa M. Badia (Barcelona Supercomputing Center, Spain)

Publicity Chairs:
* Philip Brisk (U.C Riverside, USA)
* Nikola Puzovic (Barcelona Supercomputing Center, Spain)

Finance Chair:
* Jeroen Borghs (Ghent University, Belgium)

Submission Chair:
* Michiel Ronsse (Ghent University, Belgium)

Web and Registrations Chair:
* Klaas Millet (Ghent University, Belgium)

Local organizing committee:
* Nico Moser (Technische Universität Berlin, Germany)
* Paula Herber (Technische Universität Berlin, Germany)
* Reinier van Kampenhout (Fraunhofer FIRST, Germany)

Steering Committee:
* Anant Agarwal (MIT, USA)
* Koen De Bosschere (Ghent University, Belgium)
* Albert Cohen (INRIA, France)
* Tom Conte (Georgia Institute of Technology, USA)
* Wen-mei W. Hwu (UIUC, USA)
* Walid Najjar (UC Riverside, USA)
* Per Stenstrom (Chalmers University, Sweden, Chair)
* Theo Ungerer (University of Augsburg, Germany)
* Mateo Valero (UPC, Spain)