Call for Participation : ICCD 2012

Submitted by John Kim
September 30 to October 3, 2012

Submitted by John Kim

Call for Participation

IEEE International Conference on Computer Design (ICCD 2012)

September 30 – October 3, 2012

Montreal, Quebec, Canada

Sponsored by:
IEEE Computer Society
IEEE Circuits and Systems Society


We cordially invite you to attend ICCD 2012 in Montreal. The 2012
edition of the ICCD conference marks its 30th anniversary, where
special sessions, keynotes, and other events will commemorate this
milestone. ICCD is proud to be one of the venues with the longest
tradition in the area.

The International Conference on Computer Design encompasses a wide
range of topics in the research, design, and implementation of
computer systems and their components. ICCD’s multi-disciplinary
emphasis provides an ideal environment for developers and researchers
to discuss practical and theoretical work covering system and computer
architecture, verification and test, design and technology, and tools
and methodologies.


The conference will be held at Ecole de technologie superieure (ETS) and
Concordia University, both located in the heart of Montreal’s downtown.
A special 30th anniversary social event will take place on the evening of
Tuesday, Oct. 1 on board a cruise boat, including conference dinner and a
special 30 years retrospective program.

ICCD 2012 has negotiated special rates for the attendees of ICCD 2012
in Montreal. These ICCD special rates are on a first-come-first-serve
basis and will be honored only until August 30, 2012. Please make your
reservations early. For more information, please visit

Giovanni DeMicheli, EPFL
Technologies and Platforms for Cyberphysical Systems

Valentina Salapura, IBM
Cloud Computing: Virtualization and Resiliency for Data Center Computing

Joe Macri, AMD
Heterogeneous System Architecture

A selection of high-impact papers from ICCD’s 30-year history.

Host: Guy Rabbat, General Chair of ICCD’83

Presenters (tentative):

Josep Torrellas, UIUC
FlexRAM: Toward an Advanced Intelligent Memory System

John Seng, Cal Poly
Power-Sensitive Multithreaded Architecture

Prasant Mohapatra, UC Davis
Architectural Impact of Secure Socket Layer on Internet Servers

Davide Bertozzi, Univ. di Ferrara
Xpipes: A Latency Insensitive Parameterized Network-on-chip
Architecture for Multi-Processor SoCs

Premkishore Shivakumar, Intel
Exploiting Microarchitectural Redundancy for Defect Tolerance

Hardware Security and Trust

This (Free) Tutorial will highlight why hardware security and trust are
important objectives from the economics, security, and safety
perspectives. It will address various attacks and countermeasure, hardware
based security primitives, security vs. reliability vs. quality trade-offs.

Ramesh Karri (Polytechnic Inst. of New York University),
Yiorgos Makris (University of Texas at Dallas) and
Ozgur Sinanoglu (New York University)

Sunday, September 29
13:00-18:00 Hardware Security and Trust Tutorial
for more information)

18:00-20:00 Welcome Reception at Concordia University

Monday, October 1

08:30 Keynote:
Technologies and Platforms for Cyberphysical Systems
Giovanni De Micheli, EPFL

09:40-10:30 Parallel Sessions

Computer Systems 1

Task Model Suitable for Dynamic Load Balancing of Real-Time
Applications in NoC-based MPSoCs
Sergio Johann Filho, Alexandra Aguiar, Felipe Gohring de Magalhaes,
Oliver Longhi and Fabiano Hessel

BIXBAR: A Low Cost Solution to Support Dynamic Link
Reconfiguration in CMP Networks on Chip
Pablo Abad, Pablo Prieto, Valentin Puente and Jose-Angel Gregorio

Processor Architecture 1

Exploiting Multi-Level Scratchpad Memories for Time-Predictable
Multicore Computing
Yu Liu and Wei Zhang

SECRET: Selective Error Correction for Refresh Energy
reducTion in DRAMs
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang
and Michael Wang

Electronic Design Automation 1

DuSCA: A Multi-Channeling Strategy for Doubling Communication
Capacity in Wireless NoC
Yi Wang, Danella Zhao and Jian Li

Reinforcement Learning Based Dynamic Power Management with
Hybrid Power Supply
Siyu Yue, Di Zhu, Yanzhi Wang and Massoud Pedram

10:30-11:00 Coffee Break

11:00-11:50 Parallel Sessions

Computer Systems 2

A PRET Microarchitecture Implementation with Repeatable Timing
and Competitive Performance
Isaac Liu, Jan Reineke, David Broman, Michael Zimmer and Edward Lee

Flash Correct-and-Refresh: Retention-Aware Error Management
for Increased Flash Memory Lifetime
Yu Cai, Gulay Yalcin, Onur Mutlu, Erich Haratsch, Adrian Cristal,
Osman Unsal and Ken Mai

Processor Architecture 2

A High-Performance, Low-Overhead Microarchitecture for
Secure Program Execution
Arun Karthik Kanuparthi, Ramesh Karri and Sateesh Addepalli

Robust Optimization of A Chip Multiprocessor’s Performance
under Power and Thermal Constraints
Mohammad Ghasemazar, Hadi Goudarzi and Massoud Pedram

Electronic Design Automation 2

Hierarchical Modeling of Phase Change Memory for Reliable Design
Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti and Yu Cao

Clock Mesh Synthesis Method using the Earth Mover’s
Distance under Transformations
Ying Teng and Baris Taskin

11:50-13:00 Lunch Break

13:00-14:15 Special Session Hardware Security

Malicious Key Emission via Hardware Trojan Against Encryption System
David Hely, Jeremy Dubeuf and Maurin Augagneur

Exposing Vulnerabilities of Untrusted Computing Platforms
Yier Jin, Michail Maniatakos and Yiorgos Makris

A Physical Unclonable Function based on setup time violations
David Hely, Jeremy Dubeuf, Maurin Augagneur and Yves Clauzel

Stealth Assessment of Hardware Trojans in a Microcontroller
Trey Reece, Daniel Limbrick, Xiaowen Wang, Bradley Kiddie
and William Robinson

Design and Evaluation of a Delay-Based FPGA Physically Unclonable Function
Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta,
Phillip Jones and Joseph Zambreno

14:25-15:40 Parallel Sessions

Test, Verification and Security 1

Adaptable Intrusion Detection Using Partial Runtime Reconfiguration
Mehryar Rahmatian, Hessam Kooti, Ian G. Harris and Eli Bozorgzadeh

Timing Aware Partitioning for FPGA based Logic Simulation using
Top-down Selective Hierarchy Flattening
Subramanian Swaminathan, Pey-Chang Kent Lin and Sunil Khatri

Maximizing Crosstalk-Induced Slow-down during Path Delay Test
Dibakar Gope and Duncan Henry M. Walker

Processor Architecture 3

Embedded Way Prediction for Last-Level Caches
Faissal Sleiman, Ronald Dreslinski and Thomas Wenisch

Thermal Characterisation of Cloud Workloads on a
Low-power Server-on-Chip
Dragomir Milo jevic, Sachin Idgunji, Djordje Jevdjic, Emre Ozer,

Pejman Lotfi-Kamran, Andreas Panteli, Andreas Prodromou,
Chrysostomos Nicopoulos,
Damien Hardy, Babak Falsafi and Yiannakis Sazeides

RFiop: RF-Memory Path to Address On-package I/O pad and
Memory Controller Scalability
Mario Donato Marino

Electronic Design Automation 3

Design Methodology for Sample Preparation on Digital Microfluidic Biochips
Yi-Ling Hsieh, Tsung-Yi Ho and Krishnendu Chakrabarty

An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication
Approach for FIR Filters and DFT
Rajeev Kumar, Ayan Mandal and Sunil Khatri

Multi-Voltage Domain Clock Mesh Design
Ahmet Can Sitik and Baris Taskin

15:40-17:00 Coffee Break with integrated Poster Session
(26 Poster Presentations)

Logic and Circuit Design

1. Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri
and Ozgur Sinanoglu.
Engineering Crossbar based Emerging Memory Technologies

2. Jakob Lechner and Martin Lampacher.
Protecting Pipelined Asynchronous Communication Channels
against Single Event Upsets

Computer Systems and Applications

1. Ayan Mandal, Sunil Khatri and Rabi Mahapatra.
Architectural Simulations of a Fast, Source-Synchronous
Ring-based Network-on-Chip Design

2. Justin Meza, Jing Li and Onur Mutlu.
A Case for Small Row Buffers in Non-Volatile Main Memories

3. Mickael Lanoe and Eric Senn.
Energy modelling of embedded multimedia streaming
applications with GStreamer on heterogeneous MPSoC

4. Moo-Kyoung Chung, Yeongon Cho and Soojung Ryu.
Efficient Code Compression for Coarse Grained
Reconfigurable Architectures

5. Alena Simalatsar, Liangpeng Guo, Marius Bozga and
Roberto Passerone.
Integration of Correct-by-Construction BIP Models into
the MetroII Design Space Exploration Flow

6. Mohammadreza Binesh Marvasti and Ted H. Szymanski.
A Power-Area Analysis of Hypermesh NoCs in FPGAs

7. Mohammad Hosseinabady and John Mcallister.
A Structured High-Level Model Towards Generating and Tuning
OpenCL Code

8. Yingnan Cui, Wei Zhang and Hao Yu.
Distributed thermal-aware task scheduling for 3D Network-on-Chip

9. Richard Lee, Doug Regehr, Frederic Risacher and Samar Abdi.
System Level Modeling of Real-Time Embedded Software

Processor Architecture

1. George R. Voicu, Marius Enachescu and Sorin D. Cotofana.
3D Stacked High Performance Scalable Architecture for
3D Fourier Transform

2. Kiyeon Lee, Moo-Kyoung Chung, Soojung Ryu, Yeon-Gon Cho
and Sangyeun Cho.
Design and Evaluation of a Four-Port Data Cache for High
Instruction Level Parallelism Reconfigurable Processors

3. Libo Huang.
Dynamic Vectorization for SIMD Engines via Streamization Model Execution

4. Ahmad Lashgar, Amirali Baniasadi and Ahmad Khonsari.
Dynamic Warp Resizing: Analysis and Benefits in High-Performance SIMT

Electronic Design Automation

1. Jin-Tai Yan and Zhi-Wei Chen.
Post-Layout OPE-Predicted Redundant Wire Insertion for
Clock Skew Minimization

2. Qiong Zhao and Jiang Hu.
Track Assignment Considering Crosstalk-induced Performance Degradation

3. Yiding Han, Koushik Chakraborty and Sanghamitra Roy.
DOC: Fast and Accurate Congestion Analysis for Global Routing

Test, Verification and Security

1. Leandro Freitas, Gabriel Andrade and Luiz Santos.
Efficient Verification of Out-of-Order Behaviors with Relaxed Scoreboards

2. Jeongkyu Hong and Soontae Kim.
ECC String: Flexible ECC Management for Low-cost
Error Protection of L2 Caches

3. Ahish Mysore Somashekar, Sreenivas Gangadhar, Spyros Tragoudas
and Rathish Jayabharathi.
Non-enumerative generation of statistical path delays for ATPG

4. Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki
and Tomoo Inoue.
Modeling Economics of LSI Design and
Manufacturing for Test Design Selection

5. Jerry Backer and Ramesh Karri.
Balancing Performance and Fault Detection for GPGPU Workloads

6. Kai Cong and Fei Xie.
Symbolic Execution of Virtual Devices

7. Shohreh Sharif Mansouri and Elena Dubrova.
Ring Oscillator Physical Unclonable Function with
Multi Level Supply Voltages

8. Shohei Ono, Takeshi Matsumoto and Masahiro Fujita.
Automatic Assertion Extraction in Gate-Level Simulation Using GPGPUs

17:00-18:00 Panel:Embedded Systems in Avionics

Tuesday, October 2

08:30 Keynote: Joe Macri, AMD

09:40-10:30 Parallel Sessions

Computer Systems 3

Acceleration of Monte-Carlo Molecular Simulations on
Hybrid Computing Architectures
Claus Braun, Stefan Holst, Hans-Joachim Wunderlich,
Juan Manuel Castillo and Joachim Gross

Understanding Variance Propagation in Stochastic Computing System
Chengguang Ma, Shunan Zhong and Hua Dang

Electronic Design Automation 4

Parametric Throughput Analysis of Scenario-Aware Dataflow Graphs
Morteza Damavandpeyma, Sander Stuijk, Marc Geilen,
Twan Basten and Henk Corporaal

A Polynomial Time Flow for Implementing Free-Choice Petri-Nets
Pavlos Mattheakis, Christos Sotiriou and Peter Beerel

Circuit Design 1

A Flexible Structure of Standard Cell and Its Optimization Method
for Near-Threshold Voltage Operation
Shinichi Nishizawa, Tohru Ishihara and Hidetoshi Onodera

WaveSync: Low-Latency Source Synchronous
Bypass Network-On-Chip Architecture
Yoon Seok Yang, Reeshav Kumar, Gwan Choi and Paul Gratz

10:30-11:00 Coffee Break

11:00-12:40 Parallel Sessions

Computer Systems 4

HPRA: A Pro-Active Hotspot-Preventive High-Performance
Routing Algorithm for Networks-on-Chips
Elena Kakoulli, Vassos Soteriou and Theocharis Theocharides

Phase-based Passive Stereovision Systems Dedicated to
Cortical Visual Stimulators
Firas Hawi and Mohamad Sawan

Interface Design for Synthesized Structural Hybrid Microarchitectural
Zhuo Ruan and David Penry

A Comparative Study of Wearout Mechanisms in
State-of-Art Microprocessors
Chang-Chih Chen, Fahad Ahmed and Linda Milor

Processor Architecture 4

Mamba – A Scalable Communication Centric

Multithreaded Processor Architecture
Gregory Chadwick and Simon Moore

Dynamic Phase-based Tuning for Embedded Systems
Using Phase Distance Mapping
Tosiron Adegbija, Ann Gordon-Ross and Arslan Munir

SOLE: Speculative One-cycle Load Execution with scalability,
high-performance and energy-efficiency
Zhenhao Zhang, Dong Tong, Xiaoyin Wang, Jiangfang Yi and Keyi Wang

Analyzing the Optimal Ratio of SRAM banks in Hybrid Caches
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro Lopez
and Jose Duato

Circuit Design 2

A Stochastic Reconfigurable Architecture for Fault-Tolerant
Computation with Sequential Logic
Peng Li, Weikang Qian and David Lilja

Enhancing 3T DRAMs for SRAM replacement under 10nm
Tri-Gate SOI FinFETs
Zoran Jaksic and Ramon Canal

A Spectral Transform Approach to Stochastic Circuits
Armin Alaghi and John P. Hayes

Fast Error Aware Model for Arithmetic and Logic Circuits
Samy Zaynoun, Muhammad S. Khairy, Ahmed M. Eltawil,
Fadi J. Kurdahi and Amin Khajeh

12:40-13:45 Lunch Break

13:45-15:50 Best Paper Session

Designing Pipelined Delay Lines with Dynamically-Adaptive Granularity for
Low-Energy Applications
Christos Vezyrtzis, Steven Nowick and Yannis Tsividis

A High-Performance and Energy-Efficient Row Buffer Locality-Aware
Caching Policy for Hybrid Memories
Hanbin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding
and Onur Mutlu

Mitigating NBTI in the Physical Register File through Stress Prediction
Saurabh Kothawade, Dean Michael Ancajas, Koushik Chakraborty and
Sanghamitra Roy

An Efficient Reliability Simulation Flow for Evaluating the Hot Carrier
Injection Effect in CMOS VLSI Circuits
Mehdi Kamal, Qing Xie, Massoud Pedram, Ali Afzali-Kusha and Saeed Safari

Memory Module-level Testing and Error Behaviors for Phase Change Memory
Zhe Zhang, Weijun Xiao, Nohhyun Park and David Lilja

15:50-16:20 Coffee Break

18:00-23:00 Cruise Boat Excursion & Conference Dinner (Montreal Harbor)
including 30th anniversary special session from 19:30-20:30

Wednesday, October 3

08:30 Keynote
Cloud Computing: Virtualization and Resiliency for Data Center Computing
Valentina Salapura, IBM

09:40-10:30 Parallel Sessions

Computer Systems 5

Dynamic Application Mapping for Congestion Reduction in
Many-Core Systems
Mohamamd Fattah, Marco Ramirez, Masoud Daneshtalab,
Pasi Liljeberg and Juha Plosila

DIPLOMA: Consistent and Coherent Shared Memory over Mobile Phones
Jason Gao, Anirudh Sivaraman, Niket Agarwal, Haoqi Li and Li-Shiuan Peh

Processor Architecture 5

Aurora: A Thermally Resilient Photonic Network-on-Chip Architecture
Amer Qouneh, Zhongqi Li, Madhura Joshi, Wangyuan Zhang, Xin Fu and Tao Li

Improving Inclusive Cache Performance with Two-level Eviction Priority
Lingda Li, Dong Tong, Zichao Xie, Junlin Lu and Xu Cheng

Electronic Design Automation 5

Fast Development of Hardware-Based Run-Time Monitors Through
Architecture Framework and High-Level Synthesis
Mohamed Ismail and G. Edward Suh

Parameterized Free Space Redistribution for Engineering Change in
Placement of Integrated Circuits
Taraneh Taghavi, Shyam Ramji, Frank Musante and Suhasini Rege

10:30-11:00 Coffee Break

11:00-12:40 Parallel Sessions

Computer Systems 6

Providing Cost-effective On-Chip Network Bandwidth in GPGPUs
Hanjoon Kim, John Kim, Woong Seo, Yeongon Cho and Soojung Ryu

3D-NoC: Reconfigurable 3D Photonic On-Chip Interconnect for Multicores
Randy Morris, Avinash Kodi and Ahmed Louri

Adaptive Backpressure: Efficient Buffer Management for On-Chip Networks
Daniel U. Becker, Nan Jiang, George Michelogiannakis and William J. Dally

An Oblivious Routing Algorithm for Mesh Networks to Achieve a New
Worst-Case Throughput Bound
Guang Sun, Chia-Wei Chang, Bill Lin and Lieguang Zeng

Test, Verification and Security 2

A Novel Profiled Side-Channel Attack in Presence of High Algorithmic Noise
Mostafa Taha and Patrick Schaumont

Architecture and Design Flow for a Debug Event Distribution Interconnect
Arnaldo Azevedo, Bart Vermeulen and Kees Goossens

MSE Minimization and Fault-Tolerant Data Fusion for Multi-Sensor Systems
Atena Roshan Fekr, Ma jid Janidarmian, Omid Sarbishei, Benjamin Nahill,
Katarzyna Radecka and Zeljko Zilic

Locating Faults in Application-Dependent Interconnects of SRAM Based FPGAs
Nandha Kumar Thulasiraman, Haider Almurib and Fabrizio Lombardi

Circuit Design 3
Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning
Mineo Kaneko

Adaptive Memory Architecture for Real-Time Image Warping
Andy Motten, Luc Claesen and Yun Pan

A Novel Variation-Tolerant 4T-DRAM with Enhanced Soft-Error Tolerance
Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro,
Antonio Gonzalez and Antonio Rubio

12:50-13:00 Concluding Remarks

13:00-14:00 Lunch

Call for Participation: PACT-21 (Hotel reservation deadline – August 30, 2012)

Submitted by Sangyeun Cho
September 19 to September 23, 2012

Submitted by Sangyeun Cho
International Conference on Parallel Architecture and Compilation
Technologies (PACT-21)
Minneapolis, MN, USA, September 19-23 , 2012

** Please Note important deadlines for early registration and hotel reservation

Conference early registration deadline – September 5, 2012

Conference hotel reservation deadline – August 30, 2012

Student travel grant deadline – August 24, 2012

** The conference program is now available at

1. The Changing Role of Supercomputing, Peter J. Ungaro (Cray)
2. Compiling to Avoid Communication, Kathy Yelick
(UC Berkeley and Lawrence Berkeley National Lab)
3. Top500 Versus Sustained Performance – Or the Top Problems with
the Top500 List – And What to Do About Them, William Kramer
(National Center for Supercomputing Applications, University
of Illinois at Urbana-Champaign)

1. WSRAS 2012: First International Workshop on Secure and
Resilient Architectures and Systems
2. ADC-1: First Workshop on Architectures for Data Intensive Computing
3. DFM 2012: Data-Flow Execution Models for Extreme Scale Computing

1. MARSS: A Cycle-Accurate Full System Simulator for Multicore
2. GPU Computing Development with GPU Ocelot
3. Using OpenACC/HMPP Directives to Develop and Tune Many-core Programs
4. The Piloot Library: A Friendly Face for MPI
5. GPGPU-Sim 3.x: An (Updated) Performance Simulator for
Manycore Accelerator Research
6. Emerging Nonvolatile Memory Applications in Computer Architectures
7. Parallelizing and Optimizing Programs for GPU Acceleration
Using CUDA
8. Programming Models and Optimizations for GPUs and Multicores

Call for Papers: HPCA-19

Submitted by Onur Mutlu
February 23 to February 27, 2013

Submitted by Onur Mutlu
The 19th International Symposium on High-Performance Computer Architecture

Co-located with PPoPP-2013 and CGO-2013

Feb. 23-27, 2013, Shenzhen, China

Important dates
* Abstract deadline: August 30, 2012, 11:59 PM EDT (firm deadline)
* Paper deadline: September 7, 2012, 11:59 PM EDT (firm deadline)
* Workshop and tutorial proposals due: September 7, 2012
* Industrial track submissions due: October 19, 2012, 11:59 PM EDT

The International Symposium on High-Performance Computer Architecture provides
a high-quality forum for scientists and engineers to present their latest
research findings in this rapidly-changing field. Authors are invited to submit
papers on all aspects of high-performance computer architecture. Topics of
interest include, but are not limited to:

* Processor, cache, and memory architectures
* Parallel computer architectures
* Multicore architectures
* Impact of technology on architecture
* Power-efficient architectures and techniques
* Dependable/secure architectures
* High-performance I/O systems
* Embedded and reconfigurable architectures
* Interconnect and network interface architectures
* Architectures for cloud-based HPC
* Innovative hardware/software trade-offs
* Impact of compilers and system software on architecture
* Performance modeling and evaluation
* Architectures for emerging technology and applications

Authors should submit an abstract by Thursday, August 30, 2012, 11:59 PM EDT.
They should submit the full version of the paper by Friday, September 7, 2012,
11:59 PM EDT. No extensions will be granted. The full version should be a PDF
file that does not exceed 12 pages according to the format and instructions in Papers that exceed the length limit or that
cannot be viewed using Adobe Reader (version 3.0 or higher) may not be reviewed.
Papers should be submitted for double-blind review. We anticipate making a Best
Paper award; all papers will be evaluated based on their novelty, fundamental
insights, and potential for long-term impact. New-idea papers are encouraged.
Submission issues should be directed to the program chair at .

Workshop and tutorial submissions should be directed to the workshop
and tutorial
co-chairs (,

Industrial track submissions should be directed to the Industrial Session Chair
Brad Beckmann (