Call for Papers: ICPE 2013

Submitted by Kai Sachs
April 21 to April 24, 2013

Submitted by Kai Sachs

ICPE 2013
4th ACM/SPEC International Conference on Performance Engineering

Prague, Czech Republic, April 21-24, 2013

A Joint Meeting of WOSP/SIPEW sponsored by
ACM SIGMETRICS and ACM SIGSOFT in Cooperation with SPEC.


Research Papers Extended to 5th October 2012
Industrial / Experience Papers 23 October 2012
Poster and Demo Papers 13 November 2012
Tutorial Proposals 10 November 2012
Work-in-Progress and Vision Papers 14 January 2013


The goal of the International Conference on Performance Engineering (ICPE)
is to integrate theory and practice in the field of performance engineering
by providing a forum for sharing ideas and experiences between industry
and academia. ICPE is established as a joint meeting of the ACM Workshop
on Software and Performance (WOSP) and the SPEC International Performance
Evaluation Workshop (SIPEW). The conference brings together researchers
and industry practitioners to share and present their experiences, discuss
challenges, and report state-of-the-art and in-progress research on
performance engineering of software and systems, including performance
measurement, modeling, benchmark design, and run-time performance

Topics of interest include, but are not limited to:

Performance and software development processes
* Techniques to elicit and incorporate performance, availability,
power and other extra-functional requirements throughout
the software and system lifecycle
* Agile, performance-test-driven development
* Performance engineering in Commercial-of-the-Shelf (COTS)
system, Service-Oriented Architectures (SOA), web-based
systems and services, smart systems, automated control systems,
transport systems, embedded, real-time, and mobile systems
* Performance-requirement reengineering and design for software
performance predictability
* Software performance modeling, patterns and anti-patterns

Performance modeling and prediction
* Languages, annotations, tools and methodologies to support
model-based performance engineering
* Analytical, simulation, statistical, AI-based, and hybrid modeling/
prediction methods
* Automated model discovery and model building
* Model validation and calibration techniques

Performance measurement, and experimental analysis
* Performance measurement, monitoring, and workload characterization
* Test planning, tools for performance, load testing, measurement,
profiling and tuning
* Automated model extraction for functional or partially functional
* Methodologies for performance testing and for functional testing
* Reproduction and reproducibility of performance studies

Benchmarking, configuration, sizing, and capacity planning
* Benchmark design and benchmarking methods, metrics, and suites
* Development of new, configurable, and/or scalable benchmarks
* Use of benchmarks in industry and academia
* System configuration, sizing and capacity planning techniques

System management/optimization
* Use of models for run-time configuration/management
* Online performance prediction and model parameter estimation
* Adaptive resource management

Performance in Cloud, Virtualized and multi-core systems
* Modeling, monitoring, and testing of cloud computing platforms
and applications
* Performance/management of virtualized machines, storage and networks
* Performance engineering of multi-core and parallel systems

Performance and Power
* Algorithms for combined power and performance management
* Instrumentation, profiling, modeling and measurement of power consumption
* Power/performance engineering in
grid/cluster/cloud/mobile computing systems

Performance modeling and evaluation in other domains such as:
* Web-based systems, e-business, web services, SOAs
* Transaction-oriented and event-based systems
* Embedded and autonomous systems
* Real-time and multimedia systems
* Peer-to-peer, mobile and wireless systems

Authors are invited to submit original, unpublished papers that are not
being considered in another forum. A variety of contribution styles for
papers are solicited including: basic and applied research, industrial
experience reports, and work-in-progress/vision papers. Different
acceptance criteria apply for each category, please refer to the website
for details. At least one author of each accepted paper is required to
attend the conference and present the paper. Only the accepted and
presented papers will be published in the ICPE 2013 conference
proceedings that will be published by ACM and included in the
ACM Digital Library.


Papers will be thoroughly reviewed for novelty, technical quality, scientific
soundness and relevance.
Research track submissions should be clearly indicated
in the text either as “Full Research Paper” or “Short Research Paper”.
Submissions must be in the standard ACM format for conference proceedings
Full research papers should not exceed 12 pages double column
including figures and tables; short research papers
are limited to 6 pages. Industrial/Experience papers are
limited to 8 pages double column including figures and tables.
Work-in-Progress and Vision papers should not exceed
4 pages double column including figures and tables. Research track
papers, Industry and Experience papers and Work-in-Progress and
Vision papers should be submitted via EasyChair. Tutorial proposals and
Poster and Demonstration submissions must not exceed 2 pages
and should be sent directly to the relevant chair. Detailed submission
instructions are available on the conference website.


Petr Tuma, Charles University, Czech Republic
Giuliano Casale, Imperial College London, UK

J. Nelson Amaral, University of Alberta, Canada
Tony Field, Imperial College London, UK

Seetharami R. Seelam, IBM Research, USA

Mirco Tribastone, Ludwig-Maximilians University of Munich, Germany

Kaustubh Joshi, AT&T Labs Research, USA

Evgenia Smirni, College of William and Mary, USA

Lubomir Bulej, Charles University, Czech Republic

John Murphy, University College Dublin, Ireland
Kai Sachs, SAP Research, Germany

Lucy Cherkasova, HP Labs, USA
Vittorio Cortellessa, Universita’ dell’Aquila, Italy

Research Track

Martin Arlitt, HP Labs, USA, and University of Calgary, Canada
Alberto Avritzer, Siemens Corporate Research, USA
Steffen Becker, University of Paderborn, Germany
Anne Benoit, ENS Lyon – LIP, France
Steve Blackburn, ANU, Australia
Andre Bondi, Siemens Corporate Research, USA
Edson Borin, Universidade de Campinas, Brazil
Jeremy Bradley, Imperial College London, UK
Lydia Chen, IBM Zurich, Switzerland
Lucy Cherkasova, Hewlett-Packard Laboratories, USA
Lawrence Chung, University of Texas at Dallas, USA
Susanna Donatelli, Universita’ di Torino, Italy
Sandhya Dwarkadas, University of Rochester, USA
Dick Epema, Delft University of Technology, Netherlands
Dror Feitelson, Hebrew University, Israel
Sebastian Fischmeister, University of Waterloo, Canada
Stephen Gilmore, University of Edinburgh, UK
Lars Grunske, TU Kaiserslautern, Germany
Wilhelm Hasselbring, University of Kiel, Germany
Michael Hind, IBM T.J. Watson Research Center, USA
Robert Hundt, Google Inc., USA
Alexandru Iosup, TU Delft, The Netherlands
Stephen Jarvis, University of Warwick, UK
Carlos Juiz, University of the Balearic Islands, Spain
David Kaeli, Northeastern University, USA
William Knottenbelt, Imperial College London, UK
Samuel Kounev, Karlsruhe Institute of Technology, Germany
Heiko Koziolek, ABB Corporate Research, Germany
Anirban Mahanti, NICTA, Australia
Pat Martin, Queen’s University, Canada
Daniel Menasce, George Mason University, USA
Raffaela Mirandola, Politecnico di Milano, Italy
David Pearce, Victoria University of Wellington, N. Zealand
Dorina Petriu, Carleton University, Canada
Meikel Poess, Oracle Corporation, USA
Lawrence Rauchwerger, Texas A&M University, USA
Ralf Reussner, Karlsruhe Institute of Technology, Germany
George Riley, Georgia Institute of Technology, USA
Alma Riska, EMC, USA
Jerry Rolia, HP Labs, USA
Peter Sweeney, IBM T.J. Watson Research Center, USA
Mirco Tribastone, Ludwig-Maximilians University of Munich, Germany
Catia Trubiani, Universita’ dell’Aquila, Italy
Carey Williamson, University of Calgary, Canada
Murray Woodside, Carleton University, Canada
Peng Wu, IBM T. J. Watson Research Center, USA
Xiaoyun Zhu, VMware, USA

Industrial Track
Walter Bays, Oracle Corporation, USA
Andrew Bond, Red Hat, USA
Winnie Cheng, American Express, USA
Pankaj K. Garg, ZeeSource, USA
Klaus-Dieter Lange, HP, USA
Elmoustapha Ould-Ahmed-Vall, Intel, USA
Meikel Poess, Oracle Corporation, USA
Kai Sachs, SAP AG, Germany
Connie U. Smith, Performance Engineering Services, USA
Ian Whalley, Google, USA

Call for Papers: NOCS 2013

Submitted by Carole-Jean Wu
April 21 to April 24, 2013

Submitted by Carole-Jean Wu
Seventh ACM/IEEE International Symposium on Networks-on-Chip
April 2013
Tempe, Arizona

The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip and chip-scale communication
technology, architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and applications
from inter-related research communities, including computer architecture,
networking, circuits and systems, embedded systems, and design automation.
Topics of interest include, but are not limited to:

NoC architecture and implementation
– Network architecture (topology, routing, arbitration)
– NoC Quality of Service
– Timing, synchronous/asynchronous communication
– NoC reliability issues
– Network interface issues
– NoC design methodologies and tools
– Signaling & circuit design for NoC links
– Physical design of interconnect & NoC

NoC analysis and verification
– Power, energy & thermal issues (at the NoC, un-core and/or system-level)
– Benchmarking & experience with real NoC-based hardware
– Modeling, simulation, and synthesis of NoCs
– Verification, debug & test of NoCs
– Metrics and benchmarks for NoCs

NoC application
– Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
– Network design for 2.5D & 3D stacked logic and memory

NoC at the un-core and system-level
– Design of memory subsystem (un-core) including memory controllers, caches,
cache coherence protocols & NoCs
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing and novel
programming models
– Multi/many-core workload characterization & evaluation
– Optical, RF, & emerging technologies for on-chip/inpackage interconnects
– Issues related to large-scale systems (datacenters, supercomputers) with
NoC-based systems as building blocks

Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation. Submitted papers must describe original
work that has not been published before or is under review by another conference
at the same time. Each submission will be checked for any significant similarity
to previously published works or for simultaneous submission to other archival
venues, and such papers will be rejected. Furthermore, NOCS will notify the
technical chair of the venue where the duplicate was submitted. Please see the
paper submission instructions for details.

Proposals for tutorials, special sessions, and panels are also invited. Please
see the detailed submission instructions for paper, tutorial, special sessions,
and panel proposals at the submission page. A special section related to the
theme of the conference will be organized in one of the IEEE journals.

Important Dates
Abstract registration deadline Nov 19, 2012
Full paper submission deadline Nov 26, 2012
Proposals for tutorials, special sessions and panels Jan 11, 2013
Notification of acceptance Feb 1, 2013
Final version due Mar 1, 2013

Organizing Committee
General Co-Chairs:
Karam S. Chatha, Arizona State University, USA
Chita R. Das, Penn State University, USA
Finance Chair:
Sudeep Pasricha, Colorado State, USA
Registration Chair:
Mohammed Al Faruque, Siemens, USA
Publicity Chair:
Carole Jean Wu, Arizona State University, USA
Program Co-Chairs:
John Bainbridge, Sonics Inc., USA
Natalie Enright Jerger, University of Toronto, CA
Publications Chair:
Paul Gratz, Texas A&M, USA
Tutorials/Demo Chair
Zhonghai Lu, KTH, Sweden
Industrial Chair
Umit Ogras, Intel, USA

Contact Information
Karam Chatha,
John Bainbridge,
Chita Das,
Natalie Enright Jerger,

Call for Papers: ARCS 2013

Submitted by Josef Hlavac
February 19 to February 22, 2013

Submitted by Josef Hlavac
The ARCS series of conferences has over 30 years of tradition reporting top
notch results in computer architecture and operating systems research. This
year’s focus will be on architectural aspects for application acceleration.
Like the previous conferences in this series, it continues to be an important
forum for computer architecture research. In 2013 ARCS will be hosted by the
Czech Technical University in Prague, February 19-22, 2013.

The proceedings of ARCS 2013 will be published in the Springer Lecture Notes
on Computer Science (LNCS) series (pending). After the conference, authors
of selected papers will be invited to submit an extended version of their
contribution for publication in a special issue of the Journal of Systems
Architecture. Also, the best paper and best presentation award will be
presented at the conference.

The deadline for submitting papers has been extended to October 1, 2012.

Call for Participation: ANCS 2012

Submitted by April Mosqus
October 29 to October 30, 2012

Submitted by April Mosqus
The 8th ACM/IEEE Symposium on Architectures
for Networking and Communications Systems

ANCS 2012

October 29-30, 2012
AT&T Conference Center
University of Texas
Austin, Texas, USA

You are invited to participate in the Eighth ACM/IEEE Symposium on
Architectures for Networking and Communications Systems (ANCS), which
will be held October 29-30 at the AT&T Executive Education and
Conference Center on the campus of the University of Texas in Austin,
TX, USA. We have an exciting program with 19 high-quality papers and
14 posters: . In addition,
there will be keynote presentations by Gordon Brebner (Distinguished
Engineer, Xilinx, Inc.) and Teemu Koponen (Sr. Staff Engineer, VMware,
Inc.): . For registration details,
please see the conference web site. A limited number of student travel
grants is available (application deadline September 20, 2012).

This year, ANCS is co-located with ICNP 2012 to reduce travel expenses
for those who plan to attend both conferences.


ANCS is a systems-oriented research conference, presenting original
work that explores the relationship between the architecture of modern
computer networks and the architecture of the individual hardware and
software elements from which these networks are built. This year’s
conference emphasizes in its paper selection research on computer
and network systems that provide the foundations of emerging network
technologies and the future Internet.


ACM Special Interest Group on Computer Architecture (SIGARCH)
ACM Special Interest Group on Communications (SIGCOMM)
IEEE Computer Society Tech. Committee on Computer Architecture (TCCA)
ANCS is also supported by Intel Corporation and Netronome.


General Chair: Tilman Wolf (University of Massachusetts, USA)
Program Chairs: Andrew W. Moore (University of Cambridge, UK)
Viktor Prasanna (Univ. of Southern Calif., USA)
Finance Chair: Michela Becchi (Univ. of Missouri, Columbia, USA)
Poster Chair: Charlie Wiseman (Wentworth Inst. of Tech., USA)
Local Arrangements: EJ Kim (Texas A&M University, USA)
Student Travel Grants: Michela Becchi (Univ. of Missouri, Columbia, USA)
Web Chair: Xinming Chen (University of Massachusetts, USA)

Call for Papers: WNTC 2012 Workshop (with MICRO 2012)

Submitted by Radu Teodorescu
December 2, 2012

Submitted by Radu Teodorescu
Workshop on Near-threshold Computing (WNTC)
held in conjunction with the International Symposium on Microarchitecture
(MICRO) 2012

Near-threshold computing (NTC) has emerged as a promising approach to achieving
an order of magnitude improvement in energy efficiency of microprocessors. The
key feature of NTC is to lower the supply voltage of chips to a value only
slightly higher than the threshold voltage. NTC lowers power consumption by an
order of magnitude or more. The reduction in power however comes with associated
costs and challenges that include low operating frequency, less reliable
operation of both logic and memory and much higher sensitivity to parameter
variability. Industry is actively investigating the technology and has produced
prototypes that show promising initial results. However, many challenges
remain before NTC becomes mainstream.

This workshop seeks original contributions on topics that include, but are not
limited to:

– Software/Architecture/Circuit solutions for addressing performance,
reliability or variability challenges in NTC.
– Novel applications of NTC in mobile systems,
high-performance/high-parallelism environments.
– Tradeoff analyses and performance/energy studies that help
identify new application domains for NTC.
– Other low-voltage techniques, designs, architectures.

In addition to regular presentations, the workshop will include half a day of
invited talks, tutorial presentations and a panel discussion.

– Radu Teodorescu, The Ohio State University
– Nam Sung Kim, University of Wisconsin
– Ulya Karpuzcu, University of Minnesota

Abstract deadline: Monday, October 8th
Submission deadline: Monday, October 15th
Acceptance notification: Monday, October 29th
Camera-ready: Friday, November 16th
Workshop: December 2nd

Amin Ansari, University of Illinois
David Brooks, Harvard University
Leland Chang, IBM
Steven Hsu, Intel
Ulya Karpuzcu, University of Minnesota
Nam Sung Kim, University of Wisconsin
Trevor Mudge, University of Michigan
Radu Teodorescu, The Ohio State University
Josep Torrellas, University of Illinois

All papers should be submitted in PDF format, double column, using 10 point or
larger font for text (8 points or larger for figures and tables), total length
not to exceed 6 pages. Submissions are anonymous; all identifying information
should be removed from the paper.

Submission information on the WNTC website:

Call for Participation: SELSE 2013

Submitted by William H. Robinson
March 26 to March 27, 2013

Submitted by William H. Robinson
March 26-27, 2013
Stanford University

The growing complexity and shrinking geometries of modern device technologies
are making high-density, low-voltage devices increasingly susceptible to the
influences of electrical noise, process variation, transistor aging, and the
effects of natural radiation. The system-level impact of these errors can be
far-reaching. Growing concern about intermittent errors, unstable storage
cells, and the effects of aging are influencing system design. This workshop
provides a forum for discussing current research and practice in system-level
error management. Participants from industry and academia explore both current
technologies and future research directions (including nanotechnology). SELSE
is soliciting papers that address the system-level effects of errors from a
variety of perspectives: architectural, logical, circuit-level, and
semiconductor processes. Case studies are also solicited.

Key areas of interest are (but not limited to):
* Technology trends and the impact on error rates.
* New error mitigation techniques.
* Characterizing the overhead and design complexity of error mitigation
* Case studies describing the engineering tradeoffs necessary to decide what
mitigation technique to apply.
* Experimental data.
* System-level models: derating factors and validation of error models.
* Error handling protocols (higher-level protocols for robust system design).

Authors are requested to submit extended abstracts for review before December
14, 2012. Extended abstracts will be considered for both oral and poster
presentation. All accepted submissions are included in the workshop
proceedings. Authors will be notified of paper outcome by February 2, 2013.
Camera-ready papers are due on March 4, 2013.

Additional information and guidelines for submission are available at Submissions should be PDF or Microsoft Word files in IEEE format
that do not exceed four printed pages. Camera-ready papers can be up to six
pages in length in IEEE format. Papers are not made available through IEEE and
authors retain the copyright of their work. Authors may optionally choose to
make their final papers available online through the SELSE webpage.

Organizing committee (see for complete membership):

General Chair: Vilas Sridharan, AMD
Past General Chair: Alan Wood, Oracle
Program Co-chairs: Adrian Evans, iRoC Technologies
Yanos Sazeides, University of Cyprus
Finance Chairs: Anand Dixit, Oracle
Sarah Michalak, LANL
Local Arrangements Chair: Helia Naemi, Intel
Publicity Chair: William H. Robinson, Vanderbilt University
Webmaster: Marios Kleanthous, University of Cyprus

Call for Papers: ACM International Conference on Computing Frontiers 2013

Submitted by Josef Weidendorfer
May 14 to May 16, 2013

Submitted by Josef Weidendorfer

Call for papers
ACM International Conference on Computing Frontiers
Ischia, Italy, May 14-16 2013


The increasing complexity, performance, cost and energy efficiency
needs of current and future applications require novel and innovative
approaches for the design of computing systems. Boundaries between
state of the art and revolutionary innovation constitute the computing
frontiers that must be pushed forward to provide the support required
for the advancement of science, engineering and information
technology. The Computing Frontiers conference focuses on a wide
spectrum of advanced technologies and radically new solutions relevant
to the development of the whole spectrum of computer systems, from
embedded to high-performance computing.

Submission Deadline: January 18, 2013
Ph.D. Forum Deadline: February 8, 2013
Notification of Acceptance: February 28, 2013
Final Papers Due: March 15, 2013

We seek contributions on novel algorithms, computing paradigms,
computational models, application paradigms, computer architecture,
development environments, compilers, or operating environments. In
recognition of the maturation of several exciting areas at the
frontiers, this year, we are soliciting papers in thematic tracks in
addition to the general track. The topics of these tracks listed below
are suggestive and authors are invited to submit their papers in the
track that they believe matches their interests the best. In case the
authors prefer not to submit to any of the thematic tracks, they are
invited to submit their papers for review through the general
track. The program committee has identified the following tracks for
CF2013. In each track, a few key words identifying suggested topics
for research are listed below. These topics are not meant to be
exhaustive but instead, are broadly indicative of the range topics
being considered.

Thematic Tracks:

* Algorithms and Models of Computing: Approximate and Inexact, Quantum
and Probabilistic Computing, Neuromorphic Architectures
* Big Data: Analytics, Machine Learning, Search and Representation,
System Design
* System Complexity Management: Cloud Systems, Datacenters,
Computational Neuroscience, Neuromorphic and Biologically-inspired
* Computers and Society: Education, Health and Frugal Design
delivering significantly lower energy and cost, Smart Cities and
Urban Design
* Security: Architecture and Systems support for Side-channel attacks,
* Technology Scaling and Moore’s Law: Defect- and variability-tolerant
designs, Graphene and other novel materials, Inexact computing,
Nanoscale Design, Optoelectronics, coping with the Power Wall
* User Experience and Interfaces: Technology Convergence Enabling
Psychology and Neuroscience guided design

General track:

Topics in the general track can intersect with the above themes and/or
provide cutting-edge solutions in established disciplines such as:
Applications, programming and performance analysis of advanced
architectures next-generation high performance computing and systems,
Accelerators: many-core, GPU, custom, reconfigurable, embedded, and
hybrid, Virtualization and virtual machines, Compilers and operating
systems: adaptive, run-time, and auto-tuning, System management and
security, Computational aspects of intelligent systems and robotics,
Reconfigurable, autonomic, organic, and self-organizing computation
and systems, Sensors and sensor networks.

Demo Night:

We are pleased to announce that this year Computing Frontiers will
feature a special DEMO NIGHT session, to present EU and National
collaborative projects, to promote inter-project clustering and
networking, and to show demonstrations (hardware platforms, prototypes,
design frameworks, tools.). Short papers up to 3 pages, presenting the
projects, their technical challenges and the objectives of the
demonstration, are going to be included in the Computing Frontiers
proceedings. The proposals should be submitted through the conference
submission site and should include a description of the resources
required for the demo.


Authors are invited to submit full papers to the main conference and
short papers with the proposal for the demo night. Ph.D. students are
invited to submit an extended abstract for a special Ph.D. forum and
poster session.

Full papers should not exceed 10 double-column pages in standard ACM
conference format, including figures, tables, and references. Papers
will be reviewed in a double blind fashion. This means that submissions
must be anonymous. When submitting for a double blind process, authors
need to take special care in removing their names and any hints that
might reveal their identities to the reviewers.

Short papers for the demo night and extended abstracts for the Ph.D.
forum cannot exceed 3 double-column pages. If accepted, both are going
to be included in the Computing Frontiers proceedings.

As per ACM guidelines, at least one of the authors of accepted papers
is required to register for the conference.


General Chairs: Hubertus Franke, IBM, US
Alexander Heinecke, TU Muenchen, DE

Program Chairs: Krishna Palem, Rice University, US
and Nanyang Technological University, SG
Eli Upfal, Brown University, US

Workshop/Demo Chairs: Francesca Palumbo, University of Cagliari, IT
Paolo Meloni, University of Cagliari, IT

Finance Chair: Carsten Trinitis, TU Muenchen, DE
and University of Bedfordshire, UK

Scholarships Chair: Yanyong Zhang, Rutgers University, US

Poster Chair: Rui Hou, Chinese Academy of Science, CN

Local Arrangements Chairs: Claudia Di Napoli, CNR, IT
Maurizio Giordano, CNR, IT

Publicity Chairs: Gokul Kandiraju, IBM, US
Josef Weidendorfer, TU Muenchen, DE

Publication Chair: Mohamed Zahran, New York University, US

Web Chair: Karl Fuerlinger, LMU Muenchen, DE


Monica Alderighi, INAF, IT
Steven Beaty, National Center for Atmospheric Research, US
Calin Cascaval, Qualcomm Research, US
Sergio D’Angelo, INAF, IT
Kemal Ebcioglu, Global Supercomputing, US
Paolo Faraboschi, HP, ES
John Feo, Pacific Northwest National Lab, US
Gearold Johnson, Colorado State Univ., US
Sally A. McKee, Chalmers Univ. of Tech., SE
Cecilia Metra, University of Bologna, IT
Viktor Prasanna, USC, US
Valentina Salapura, IBM TJ Watson, US
Pedro Trancoso, University of Cyprus, CY
Carsten Trinitis, TU Muenchen, DE
Oreste Villa, Pacific Northwest National Lab, US

Call for papers: ADAPT 2013 (3rd International Workshop Adaptive Self-tuning Computing Systems)

Submitted by Grigori Fursin

Submitted by Grigori Fursin

ADAPT: 3rd International Workshop on
Adaptive Self-tuning Computing Systems

January 22nd, 2012, Berlin, Germany
(co-located with HiPEAC 2013)

Computing systems are rapidly evolving into heterogeneous machines
featuring many processor cores. This leads to a tremendous complexity
with an unprecedented number of available design and optimization
choices for architectures, applications, compilers and run-time
systems. Using outdated, non-adaptive technology results in an
enormous waste of expensive computing resources and energy, while
slowing down time to market.

The 3rd International Workshop on Adaptive Self-tuning Computing
Systems is an interdisciplinary forum for researchers, practitioners,
developers and application writers to discuss ideas, experience,
methodology, applications, practical techniques and tools to improve
or change current and future computing systems using self-tuning
technology. Such systems should be able to automatically adjust their
behaviour to multi-objective usage scenarios at all levels (hardware
and software) based on empirical, dynamic, iterative, statistical,
collective, bio-inspired, machine learning and alternative techniques
while fully utilizing available resources.

All papers will be peer-reviewed including short position papers and
should include ideas on how to simplify, automate and standardize the
design, programming, optimization and adaptation of large-scale
computing systems for multiple objectives to improve performance,
power consumption, utilization, reliability and scalability.

Important Dates
* Abstract deadline: October 15, 2012
* Paper submission deadline: October 22, 2012
* Author notification: November 26, 2012
* Final paper version: December 10, 2012

Program Chairs/organizers:
* Christophe Dubach (University of Edinburgh, UK)
* Grigori Fursin (INRIA Saclay, France)

Program Committee:
* Erik Altman (IBM TJ Watson, USA)
* Marisa Gil (UPC, Spain)
* Vijay Janapa Reddi (UT Austin, USA)
* Timothy Jones (University of Cambridge, UK)
* Jaejin Lee (Seoul National University, Korea)
* Anton Lokmotov (ARM, UK)
* Chi-Keung Luk (Intel, USA)
* Tipp Moseley (Google, USA)
* Lasse Natvig (NTNU, Norway)
* David Padua (UIUC, USA)
* Markus Pueschel (ETH Zurich, Switzerland)
* Juergen Teich (University of Erlangen-Nuremberg, Germany)
* Chengyong Wu (ICT, China)

Paper Submission Guidelines

We invite papers in two categories:

* Full papers should be at most 6 pages long (excluding
bibliography). Papers in this category are expected to have relatively
mature content.

* Position papers should be between 1-2 pages long (excluding
bibliography). Preliminary and exploratory work are welcome in this
category, including wild & crazy ideas. Authors submitting papers in
this category must prepend “Position Paper:” to the title of the
submitted paper.

Paper submission information:

Call for Papers: MULTIPROG 2013: Sixth Workshop on Programmability Issues for Heterogeneous Multicores

Submitted by Osman Unsal
January 21 to January 23, 2013

Submitted by Osman Unsal

Sixth Workshop on Programmability Issues for Heterogeneous Multicores

Held in conjunction with the 8th International Conference on High-Performance
and Embedded Architectures and Compilers (HiPEAC)
Berlin, Germany, January 21-23, 2013
Workshop website:

Goal of the Workshop
Computer manufacturers have already embarked on the multi-core roadmap,
promising to add more and more cores/hardware threads on a chip: many-cores are
on the horizon. This shift to an increasing number of cores and heterogeneous
architectures has placed new burdens on the programming community. Until now,
software has been developed with a single processor in mind and it needs to be
parallelized and optimized for accelerators such as GPUs to take advantage of
the new breed of multi-/many-core computers. As a result, progress in how to
easily harness the computing power of multi-core architectures is in
great demand.

The sixth edition of the MULTIPROG workshop aims to bring together, and cause
fruitful interaction between, researchers interested in programming models and
their implementation and in computer architecture, with special emphases on
heterogeneous architectures. A wide spectrum of issues are central themes for
this workshop such as what the future programming models should look like to
accelerate software productivity, how compilers, run-times and architectures
should support these new programming models, innovative algorithm and data
structure development, and heterogeneous embedded, accelerated systems.

MULTIPROG is intended for quick publication of early results, work-in-progress,
etc, and is not intended to prevent later publication of extended papers. We
will prioritize papers addressing cross-cutting issues and that provide thought-
provoking insights into the main themes. Informal proceedings with accepted
papers will be made available at the workshop.

One AMD Best Paper Award will be presented to the most outstanding paper
presented at MULTIPROG’13. The winner will receive a high-end ATi graphics
card sponsored by AMD.

Topics of interest
Papers are sought on topics including, but not limited to:
* Multi-core architectures
o Architectural support for compilers/programming models
o Processor (core) architecture and accelerators, in particular GPUs
o Memory system architecture
o Performance, power, temperature, and reliability issues
* Heterogeneous computing
o Algorithms and data structures for heterogeneous systems
o Applications for heterogeneous computing and real-time graphics
* Programming models for multi-core architectures
o Language extensions
o Run-time systems
o Compiler optimizations and techniques
o Tools for discovering and understanding parallelism
* Benchmarking of multi-/many-core architectures
o Tools for understanding performance and debugging
o Case studies and performance evaluation

Eduard Ayguade, UPC and Barcelona Supercomputing Center
Benedict R. Gaster, Advanced Micro Devices (AMD)
Lee Howes, Advanced Micro Devices (AMD)
Per Stenstrom, Chalmers University of Technology
Osman S. Unsal, BSC-Microsoft Research Centre

Important dates
Abstract Submission: October 8, 2012
Final Submission: October 15, 2012
Author Notification: December 3, 2012

Paper submission
Submitted papers should use the LNCS format and should be 12 pages maximum.

Manuscript preparation guidelines can be found at the LNCS web site.

Please check that (i) pages are numbered, and (ii) graphs etc. remain
legible when printed in black and white. Additional information about
paper submission is available through the workshop website.

Program committee
Manuel Chakravarty, U. of New South Wales, Australia
Mats Brorsson, KTH, Sweden
Bryan Catanzaro, NVIDIA, USA
Pascal Felber, U. of Neuchatel, Switzerland
Isaac Gelado, BSC, Spain
Roberto Giorgi, U. of Siena, Italy
Hakan Grahn, Blekinge Institute of Technology, Sweden
Tim Harris, Oracle, UK
Paul Kelly, Imperial College of London, UK
Mikel Lujan, U. of Manchester, UK
Tim Mattson, Intel Research, USA
Simon McIntosh-Smith, U. of Bristol, UK
Avi Mendelson, Microsoft, Israel
Dimitris Nikolopoulos, Queens U., UK
Andy Pimentel, U. of Amsterdam, The Netherlands
Oscar Plata, U. of Malaga, Spain
Yanos Sazeides, U. of Cyprus, Cyprus
David Black-Schaffer, Uppsala U., Sweden
Nir Shavit, MIT, USA
John E. Stone, U. of Illinois, USA
Dongping Zhang, AMD, USA