Call for Papers: NOCS 2013, extended deadline

Submitted by Carole Wu
April 21 to April 24, 2013

Submitted by Carole Wu

Call for Papers [Deadline Extension]
The 7th ACM/IEEE International Symposium on Networks-on-Chip
April 21-24, 2013
Tempe, Arizona, USA

The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip and chip-scale communication
technology, architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and applications
from inter-related research communities, including computer architecture,
networking, circuits and systems, embedded systems, and design automation.
Topics of interest include, but are not limited to:

NoC architecture and implementation
– Network architecture (topology, routing, arbitration)
– NoC Quality of Service
– Timing, synchronous/asynchronous communication
– NoC reliability issues
– Network interface issues
– NoC design methodologies and tools
– Signaling & circuit design for NoC links
– Physical design of interconnect & NoC

NoC analysis and verification
– Power, energy & thermal issues (at the NoC, un-core and/or system-level)
– Benchmarking & experience with real NoC-based hardware
– Modeling, simulation, and synthesis of NoCs
– Verification, debug & test of NoCs
– Metrics and benchmarks for NoCs

NoC application
– Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
– Network design for 2.5D & 3D stacked logic and memory

NoC at the un-core and system-level
– Design of memory subsystem (un-core) including memory controllers, caches,
cache coherence protocols & NoCs
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing and novel
programming models
– Multi/many-core workload characterization & evaluation
– Optical, RF, & emerging technologies for on-chip/inpackage interconnects
– Issues related to large-scale systems (datacenters, supercomputers) with
NoC-based systems as building blocks

Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation. Submitted papers must describe original
work that has not been published before or is under review by another conference
at the same time. Each submission will be checked for any significant similarity
to previously published works or for simultaneous submission to other archival
venues, and such papers will be rejected. Furthermore, NOCS will notify the
technical chair of the venue where the duplicate was submitted. Please see the
paper submission instructions for details.

Proposals for tutorials, special sessions, and panels are also invited. Please
see the detailed submission instructions for paper, tutorial, special sessions,
and panel proposals at the submission page. A special section related to the
theme of the conference will be organized in one of the IEEE journals.

Abstract registration deadline Dec. 4, 2012
Full paper submission deadline Dec. 7, 2012
Proposals for tutorials, special sessions and panels Jan 11, 2013
Notification of acceptance Feb 1, 2013
Final version due Mar 1, 2013

Organizing Committee
General Co-Chairs:
Karam S. Chatha, Arizona State University, USA
Chita R. Das, Penn State University, USA
Finance Chair:
Sudeep Pasricha, Colorado State, USA
Registration Chair:
Mohammed Al Faruque, UC-Riverside, USA
Publicity Chair:
Carole Jean Wu, Arizona State University, USA
Program Co-Chairs:
John Bainbridge, Sonics Inc., USA
Natalie Enright Jerger, University of Toronto, CA
Publications Chair:
Paul Gratz, Texas A&M, USA
Tutorials/Demo Chair
Zhonghai Lu, KTH, Sweden
Industrial Chair
Umit Ogras, Intel, USA

Contact Information
Karam Chatha,
John Bainbridge,
Chita Das,
Natalie Enright Jerger,

Call for Papers: SELSE 2013

Submitted by William H. Robinson
March 26 to March 27, 2013

Submitted by William H. Robinson
The growing complexity and shrinking geometries of modern device technologies
are making high-density, low-voltage devices increasingly susceptible to the
influences of electrical noise, process variation, transistor aging, and the
effects of natural radiation. The system-level impact of these errors can be
far-reaching. Growing concern about intermittent errors, unstable storage
cells, and the effects of aging are influencing system design. This workshop
provides a forum for discussing current research and practice in system-level
error management. Participants from industry and academia explore both current
technologies and future research directions (including nanotechnology). SELSE
is soliciting papers that address the system-level effects of errors from a
variety of perspectives: architectural, logical, circuit-level, and
semiconductor processes. Case studies are also solicited.

Key areas of interest are (but not limited to):
* Technology trends and the impact on error rates.
* New error mitigation techniques.
* Characterizing the overhead and design complexity of error mitigation
* Case studies describing the engineering tradeoffs necessary to decide what
mitigation technique to apply.
* Experimental data.
* System-level models: derating factors and validation of error models.
* Error handling protocols (higher-level protocols for robust system design).

Authors are requested to submit extended abstracts for review before December
14, 2012. Extended abstracts will be considered for both oral and poster
presentation. All accepted submissions are included in the workshop
proceedings. Authors will be notified of paper outcome by February 2, 2013.
Camera-ready papers are due on March 4, 2013.

Additional information and guidelines for submission are available at Submissions should be PDF or Microsoft Word files in IEEE format
that do not exceed four printed pages. Camera-ready papers can be up to six
pages in length in IEEE format. Papers are not made available through IEEE and
authors retain the copyright of their work. Authors may optionally choose to
make their final papers available online through the SELSE webpage.

Organizing committee (see for complete membership):

General Chair: Vilas Sridharan, AMD
Past General Chair: Alan Wood, Oracle
Program Co-chairs: Adrian Evans, iRoC Technologies
Yanos Sazeides, University of Cyprus
Finance Chairs: Anand Dixit, Oracle
Sarah Michalak, LANL
Local Arrangements Chair: Helia Naemi, Intel
Publicity Chair: William H. Robinson, Vanderbilt University
Webmaster: Marios Kleanthous, University of Cyprus

Call for Papers: 3rd Workshop on Systems for Future Multi-core Architectures (SFMA'13)

Submitted by Joseph Devietti
April 14, 2013

Submitted by Joseph Devietti
3rd Workshop on Systems for Future Multi-core Architectures (SFMA’13)
co-located with EuroSys 2013 in Prague
Sunday, April 14, 2013

Future multi-core architectures will present a variety of challenges for system
developers, such as non-cache-coherent memory, heterogeneous processing cores
and the exploitation of novel architectural features. To achieve high
performance on these platforms, application developers will need to exploit
parallelism to a much greater extent than before. The SFMA’13 workshop is a
forum for researchers in the operating systems, language runtime, virtual
machine and architecture communities to present and discuss their experiences
with the new generation of highly-parallel hardware. Topics of interest include
(but are not limited to):

* novel multi-core operating system designs,
* runtime systems and programming environments for future hardware,
* OS or runtime support for heterogeneous processing cores,
* scheduling on many-core architectures,
* energy efficiency, fault tolerance and resource management on future
multi-core architectures,
* performance evaluation of potential future hardware,
* architectural support for systems-level software, and
* case studies of system-level software design for current or future
multi-core hardware.

SFMA’13 will be the third iteration of this workshop, co-located with EuroSys
2013 in Prague. The first iteration was held at EuroSys 2011 in Salzburg with
approximately 50 attendees. The second iteration was held at EuroSys 2012 in
Bern, with approximately 40 attendees. Websites, including proceedings, for
previous SFMAs are here:

* SFMA’11:
* SFMA’12:

Authors are invited to submit original and unpublished work that exposes a new
problem, advocates a specific solution, or reports on actual experience. Papers
are limited to 6 pages (including figures, tables and references).

Final papers will be made available to participants electronically at the
meeting, but to facilitate resubmission to more formal venues, no archival
proceedings will be published, and papers will not be sent to the ACM Digital
Library. Authors will be given the option of having their final paper accessible
from the workshop website.

Important Dates

Submission deadline: Friday, February 1, 2013
Notification: Sunday, February 24, 2013
Workshop: Sunday, April 14, 2013

Workshop Organizers

Simon Peter (University of Washington)
Joseph Devietti (University of Pennsylvania)

Call For Papers: HARSH 2013

Submitted by Augusto Vega
February 24, 2013

Submitted by Augusto Vega

HARSH 2013
First Workshop on Highly-Reliable Power-Efficient Embedded Designs

February 24th, 2013, Shenzhen, China
In conjunction with HPCA-2013, CGO-2013, and PPoPP-2013

HARSH-2013 will provide a unique forum for the discussion of the challenges in
the design and operation of harsh environment-capable embedded processors.

Nowadays, embedded chips are deployed almost everywhere, from mobile phones to
on-board electronics in automobiles and satellites. Different from conventional
microprocessor designs, the operation conditions of embedded processors are
severely constrained by the environment. For example, in aerospace applications,
the computer installed on Mars rover “Curiosity” has to tolerate extreme space
radiation and temperatures, operate at low power, and provide enough computation
capability to perform mission-critical tasks. Embedded designs for Unmanned
Aerial Vehicles (UAVs) also encounter extremely challenging design requirements.
Despite their tight power budget, UAV chips demand significant throughput for
real-time high-speed image processing. In the context of oil and gas exploration
and extraction, embedded processors can be found even on the drill string
itself, to process sensor inputs in real time while withstanding high
temperatures and humidity levels.

To guarantee reliability across these drastically diverse environments, the
design and operation of embedded processors should not be solely confined to the
chip but traverse different layers in the computing system, involving firmware,
operating system, applications, as well as power management units and
communication interfaces. The goal of HARSH-2013 is to facilitate the exchange
of the latest ideas, insights, and knowledge related to all critical aspects of
new-generation harsh environment-capable embedded processors, including
micro-architectural approaches, cross-stack hardware/software techniques, and
emerging challenges and opportunities. We hope to attract a group of
interdisciplinary researchers from academia, industry, and government research

In addition to the presentation of selected paper submissions, keynote speakers
will be invited to kick-off the workshop sessions and a “Best Paper” award
will be presented at the conclusion of the workshop. To encourage discussion
between participants, HARSH-2013 will organize dedicated programs for discussion
between presenters and the audience.

Topics of interest include but are not limited to:

(1) Architecture design and implementation for highly-reliable
power-efficient embedded processors:
– Architectural approaches for reliability assurance under
very-low power budgets.
– Availability, soft-error tolerance and recovery issues.
– Highly-reliable cache/memory hierarchies.
– Massive heterogeneous processing capabilities.
– Power management techniques.
– Very-low power, reliable real-time processing.
– Specialized accelerator architectures and unique designs.
– Reusable and/or reconfigurable embedded designs.
– Packaging and cooling.

(2) Cross-stack hardware/software techniques:
– Cross-stack approaches for reliability assurance under
very-low power budgets.
– Reliability- and power-aware operating systems, compilers,
workload managers, firmware and other software.
– Workload analysis and optimization for reliable low-power
embedded systems.

(3) Applications:
– Aerospace: unmanned aerial vehicles (UAVs), planetary rovers
and space probes, satellites, avionic systems, etc.
– Medical support: lifesaving monitors, portable medical devices,
high-end imaging systems, etc.
– Oil and gas exploration and extraction: unmanned underwater
vehicles (UUVs), measurement while drilling (MWD), logging while
drilling (LWD), etc.
– Aerial surveillance.
– Disaster search, rescue, and relief.
– Novel applications for highly-reliable low-power embedded chips.

To submit regular papers to the workshop, please visit:

If you have questions regarding submission, please contact us:

Important Dates:

– Dec 21, 2012: Submission deadline
– Jan 14, 2013: Notification of acceptance
– Feb 4, 2013: Final paper submission
– Feb 24, 2013: Workshop date

– Xuan Zhang (Harvard University)
– Augusto Vega (IBM)
– David Brooks (Harvard University)
– Alper Buyuktosunoglu (IBM)
– Pradip Bose (IBM)

– Pradip Bose (IBM)
– David Brooks (Harvard University)
– Alper Buyuktosunoglu (IBM)
– Jeff Derby (IBM)
– Ann Gordon-Ross (University of Florida)
– Subhasish Mitra (Stanford University)
– Alex Ramirex (Barcelona Supercomputing Center)
– Brian Rogers (IBM)
– Eric Rotenberg (NC State University)
– Li Shang (University of Colorado)
– Aviral Shrivastava (Arizona State University)
– Augusto Vega (IBM)
– Xuan Zhang (Harvard University)