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Call for Papers: Special Issue on NOCS

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Start:
December 11, 2012
End:
January 18, 2013

Submitted by Carole Wu
http://carole-jean.wu@asu.edu
ACM Transactions on Design Automation on Electronic Systems Special
Section on Networks on Chip: Architecture, Tools, and Methodologies

Continuous technology scaling has enabled the integration of hundreds of
processing cores on the same silicon substrate, therefore allowing for the
concurrent execution of multiple applications on a chip. For such systems,
traditional solutions for on chip communication are likely unable to scale,
thereby requiring a departure from classic on-chip communication paradigms.
The Networks-on-Chip (NoC) approach has emerged as the most promising
communication paradigm for massively integrated multicore systems.
This special section will report on recent advances in development of on-chip
communication technology, architecture, design methods and applications while
encouraging innovation from inter-related research communities, including
computer architecture, networking, circuits and systems, embedded systems,
and design automation. Topics of interest include, but are not limited to:

• Network architecture (topology, routing, arbitration)
• Network design for 3D stacked logic and memory
• Mapping of applications onto NoCs
• Power and energy issues
• Timing, synchronous/asynchronous communication
• NoC reliability issues
• OS support for NoCs
• Programming models
• Multi/many-core workload characterization & evaluation
• Network interface issues
• NoC case studies, application-specific NoC design
• Modeling, simulation, and synthesis of NoCs
• NoC support for memory and cache access
• NoC design methodologies and tools
• NoC Quality of Service
• NoCs for FPGAs and structured ASICs
• NoC support for CMP/MPSoCs
• Novel interconnect links/switches/routers
• Optical & RF for on-chip/in-package interconnects
• Signaling and circuit design for NoC links
• Physical design of interconnect and NoC
• Verification, debug & test of NoCs
• Metrics and benchmarks for NoCs

Authors are encouraged to submit high-quality research contributions that will
not require major revisions. Extensions of papers presented at the NOCS 12 –
the International Symposium on Networks on a Chip, Copenhagen, Denmark,
May 9-11, 2012 (http://www.nocsymposium.org ) are especially encouraged.
Please identify clearly the additional material from the original symposium
paper in your submitted manuscript. Submissions of relevant original work
not presented at NOCS 12 are also welcome. All manuscripts are subject to
standard ACM Transactions on Design Automation of Electronic Systems
review process. Prospective authors should submit their manuscripts
electronically on the TODAES Web site: http://mc.manuscriptcentral.com/todaes

Authors should clearly identify their papers as submissions for the Special
Section on NOC:ATM 2012 on their manuscript and in the Note to Editor field
of the web submission form. Instructions on how to submit a paper can be
found at http://mc.manuscriptcentral.com/todaes and authors can contact
Annie Yu at todaes@ceng.usc.edu for further assistance.

Important Dates:
Submission Deadline: January 18, 2013
Notification Date: April 26, 2013
Final Version Due: June 7, 2013

Guest Editors:
Diana Marculescu
Carnegie Mellon University
Pittsburgh, PA
dianam@cmu.edu

Chita Das
Penn State University
State College, PA
das@cse.psu.edu