Call for Papers: ASAP 2013 (Deadline Extension)

Submitted by Kubilay Atasu
June 5 to June 7, 2013

Submitted by Kubilay Atasu

ASAP 2013
Abstract due: February 8, 2013
Paper due: February 15, 2013

24th IEEE International Conference on
Application-specific Systems, Architectures and Processors
5-7 June 2013
Washington D.C., USA

The conference will cover the theory and practice of
application-specific systems, architectures and processors.
The 2013 conference will build upon traditional strengths
in areas such as computer arithmetic, cryptography,
compression, signal and image processing, network processing,
reconfigurable computing, application-specific instruction-set
processors, and hardware accelerators. We especially encourage
submissions in the following areas:
* Bioinformatics and computational biology – life sciences
present a host of interesting problems that can benefit from
application-specific solutions
* Computational finance – the financial community has significant
needs for high performance computing
* Big data analytics – extracting and correlating information from
large scale unstructured data using application-specific systems
* Architecturally diverse systems – systems that use heterogeneous
computing resources including FPGAs, GPUs, and CGRAs
* Architectural and system level design space exploration and
customization techniques for improving the design efficiency
* Architectures for emerging platforms, such as smartphones,
tablets, and data centers, with emphasis on energy efficiency

Guidelines for Submission:
ASAP will accept 8-page full papers for oral presentation,
4-page short papers for short oral or poster presentation.
All submissions should be written in the English language.
An online submission link will be available on the ASAP 2013
website starting in early January. Papers should use the
IEEE formatting template linked at the submission page.

Conference Committee:
General Chair:
Tarek El-Ghazawi, The George Washington University, USA
General Co-Chair:
Alan George, UoF, USA
Program Chair:
Melissa Smith, Clemson University, USA
Program Co-Chair:
Kubilay Atasu, IBM Research – Zurich, Switzerland

Important Dates:
* Abstract Due – February 8, 2013
* Paper Due – February 15, 2013
* Notification of Acceptance – March 15, 2013
* Camera Ready Paper – April 5, 2013
* Conference – June 5-7 2013

Call for Participation: PPoPP 2013

Submitted by Arun Kejariwal
February 24 to February 27, 2013

Submitted by Arun Kejariwal

PPoPP 2013
18th ACM SIGPLAN Annual Symposium on Principles
and Practice of Parallel Programming
23-27 February 2013
Intercontinental Hotel, Shenzhen, China
(Collocated with HPCA-2013 and CGO-2013)

PPoPP is a forum for leading work on all aspects of parallel programming,
including foundational and theoretical aspects, techniques, languages,
compilers, runtime systems, tools, and practical experiences. In the context
of the symposium, “parallel programming” encompasses work on concurrent
and parallel systems (multicore, multithreaded, heterogeneous, clustered
systems, distributed systems, grids, clouds, and large scale machines).


PPoPP 2013 will feature 26 full papers and 19 poster papers. The technical
program is now posted at

PPoPP 2013 will also co-host several workshops and tutorials details of which
are given at

Early Registration 26th January 2013, 11:59pm EST
Workshops and Tutorials 23-24 Feb, 2013

Keynote speakers will be announced shortly.

General Chairs
* Alex Nicolau, UC Irvine
* Xiaowei Shen, IBM China

Program Chairs
* Saman Amarasinghe, MIT
* Richard Vuduc, Georgia Tech

Workshops and Tutorials Co-Chairs:
* Harry Xu, University of California, Irvine

Call for Participation: 4th Annual Non-Volatile Memories Workshop

Submitted by Steven Swanson
March 3 to March 5, 2013

Submitted by Steven Swanson

The 4th Annual Non-Volatile Memories Workshop
San Diego CA
March 3-5, 2013


The 4th Annual Non-Volatile Memories Workshop (NVMW 2013)
provides a unique showcase for outstanding research on solid
state, non-volatile memories. It features a “vertically
integrated”program that includes presentations on a wide range of
topics spanning devices, data encoding, systems architecture, and

* Big data applications for NVMs
* Flash-based SSD optimization
* Power management in NVMs
* Operating system optimizations
* SSD wear management
* Persistent objects
* Novel NVM array architectures
* Error coding for NVMs

The workshop included 35 speakers from top universities (e.g,
CMU, UCSD, University of Washington, Caltech, UCLA, and UCSB),
industrial research labs (e.g., Intel, Google, FusionIO, IBM,
Texas Instruments, SanDisk, and Spansion), and around the
world (e.g., Switzerland, Israel, Korea, Japan, and Denmark).

Workshop information is available here

** Early registration ends February 24th. **
** Travel grant applications are due February 6th. **






Microsoft Research



Al Borchers, Google
Alexander Driskill-Smith, Samsung
Andrew Jiang, Texas A & M
Anirudh Badam, Microsoft Research
Bongki Moon, Univ. of Arizona
Brian Kurkoski, JAIST
Bruce Childers, Univ. of Pittsburgh
Chaitan Baru, SDSC
Christophe Chevallier, Rambus
David Bader, Georgia Tech
David Lilja, Univ. of Minnesota
Douglas Santry, NetApp
Eitan Yaakobi, Caltech
Ethan Miller, UC Santa Cruz
Hironori Uchikawa, Toshiba
Janice Nickel, HP
John Davis, Microsoft Research
Lara Dolocek, UCLA
Luis Lastras, IBM
Maya Gokhale, LLNL
Mike Mesnier, Intel
Mike Swift, Univ. of Wisconsin
Mircea Stan, Univ. of Virginia
Moin Qureshi, Georgia Tech
Nisha Talagala, FusionIO
Nitin Agrawal, NEC
Partha Ranganathan, HP
Rick Coulson, Intel
Robert Sinkovits, SDSC
Simon Litsyn, Tel Aviv University
Steven Hetzler, IBM
Sudhanva Gurumurthi, AMD Research and Univ. of Virginia
Xinmiao Zhang, Case Western
Zvonimir Bandic, Hitachi

Call for Papers: FastPath

Submitted by Mark Hempstead
April 21, 2013

Submitted by Mark Hempstead

FastPath 2013 Second International Workshop on
Performance Analysis of Workload Optimized Systems
April 21st, 2013, Austin, TX (In Conjunction with ISPASS-2013 )

The goal of FastPath is to bring together researchers and practitioners
involved in cross-stack hardware/software performance analysis, modeling, and
evaluation of workload optimized systems. With microprocessor clock speeds
being held constant, optimizing systems around specific workloads is an
increasingly attractive means to improve performance. The importance of
workload optimized systems is seen in their ubiquitous deployment in diverse
systems from cellphones to tablets to routers to game machines to Top500
supercomputers, and IT appliances such as IBM’s DataPower and Netezza, and
Oracle’s Exadata. More precisely, workload optimized systems have hardware
and/or software specifically designed to run well for a particular application
or application class. The types and components of workload optimized systems
vary, but a partial list includes traditional CPUs assisted with accelerators
(ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators, hybrid systems,
and IT appliances. Exploiting CPU savings and speed-ups offered by workload
optimized systems for application level performance improvement poses several
cross stack hardware and software challenges. These include developing
alternate programming models to exploit massive parallelism offered by
accelerators, designing low-latency, high-throughput H/W-S/W interfaces, and
developing techniques to efficiently map processing logic on hardware.

FastPath seeks to facilitate the exchange of ideas on performance analysis and
evaluation of workload optimized systems and seeks papers on a wide range of
topics including, but not limited to:

Industrial Experiences
GPUs, FPGAs, ASIC Accelerators
Game Consoles and their Sensors
RDMA and Infiniband
Measurements on accelerated systems
Analytical Techniques
Programming Models
MapReduce, Hadoop
Runtime Management Systems

Key Dates
Submission: March 10, 2013
Notification: April 1, 2013
Final Materials Due: April 11, 2013

Call for Papers: IEEE MASCOTS 2013

Submitted by Ricardo Lent
August 14 to August 16, 2013

Submitted by Ricardo Lent

International Symposium on Modeling, Analysis and Simulation of Computer and
Telecommunication Systems
August 14-16, 2013, San Francisco, CA, USA

The MASCOTS conference is a well-established forum for state-of-the-art
research on the measurement, modeling, and performance analysis of
computer systems and networks. The 21st edition of this conference will
take place August 14-16, 2013 in San Francisco, CA. The conference will
bring together academics and industry practitioners to present and discuss
their latest research results. The technical program for the 3-day conference
will include keynote talks, refereed full and work-in-progress papers, and

We encourage original submissions describing state-of-the-art research in
the areas of computer networks and performance evaluation of computer
systems. The MASCOTS conference encourages papers describing results
of theoretic and/or practical significance. Papers presenting new performance
evaluation methods or those applying existing methods to provide new
insights to design trade-offs in computer and networked systems are
particularly encouraged. Broad topics of interest include:
• Computer architectures, multi-core processors, and memory systems
• Computer networks, protocols, and algorithms
• Distributed and cloud computing
• Energy efficient computer systems
• Operating systems, file systems, and databases
• Mobile systems
• Multimedia systems
• Smart grids
• Social networks
• Storage systems and networks
• Web-based systems and services
• Wireless, mobile, ad-hoc, and sensor networks

Papers must be unpublished and must not be submitted or under
review for publication elsewhere. Technical Program Committee members
and other experts active in the field will review submitted papers to ensure
high quality and relevance to the conference program. Accepted papers will
appear in the conference proceedings to be published by IEEE press.
For accepted papers, attendance by at least one author is mandatory.

We invite both full and work-in-progress papers as described below.
Full Papers: Submissions may be up to 10 pages in length (including
figures and references), formatted in two-column IEEE conference style
with font size 10 point or greater.
Work-in-Progress Papers: Work-in-progress papers provide a
peer-reviewed forum for late-breaking or preliminary research results,
giving an opportunity for researchers and practitioners to present and
demonstrate their recent research, and to obtain feedback from their
peers in an informal setting. Unsuccessful full paper submissions,
where appropriate, will automatically be considered for publication
as a work-in-progress paper.
Work-in-progress paper submissions may be up to 3 pages in length
(including figures and references), with the option of purchasing one
extra page upon acceptance, formatted in two-column IEEE conference
style with font size 10 point or greater.

Abstracts submission deadline: March 22, 2013
Papers submission deadline: April 8, 2013
Author notification due: June 8, 2013
Camera ready due: June 22, 2013

General Chair George Riley, Georgia Institute of Technology, USA
Program Co-Chair Erol Gelenbe, Imperial College, London, UK
Program Co-Chair Anirban Mahanti, NICTA, Australia
Publicity Co-Chair Guillaume Jourjon, NICTA, Australia
Publicity Co-Chair Ricardo Lent, Imperial College, London, UK
Web Chair Christoph Dwertmann, NICTA, Australia

Call for Papers: IISWC 2013

Submitted by Kushagra Vaid
September 22 to September 24, 2013

Submitted by Kushagra Vaid

2013 Annual IEEE International Symposium on Workload Characterization
Portland, Oregon, September 22-24, 2013


This symposium is dedicated to the understanding and characterization of
Workloads that run on all types of computing systems. New applications and
programming paradigms continue to emerge rapidly as the diversity and
performance of computers increase. On one hand, improvements in computing
technology are usually based on a solid understanding and analysis of
existing workloads. On the other hand, computing workloads evolve and
change with advances in microarchitecture, compilers, programming languages,
and networking/communication technologies. Whether they are smart phones
and deeply embedded systems at the low end or massively parallel systems
at the high end, the design of future computing machines can be significantly
improved if we understand the characteristics of the workloads that are
expected to run on them. This symposium will focus on characterizing and
understanding emerging applications in consumer, commercial and scientific

We solicit papers in all areas related to characterization of computing
system workloads. Topics of interest include (but are not limited to):

o Characterization of applications in areas including
Search engines, e-commerce, web services, databases, and
file/application servers
Embedded, mobile, multimedia, real-time, 3D-Graphics, gaming, telepresence
Life sciences, bioinformatics, scientific computing, finance, forecasting
Machine Learning, Analytics, Data mining
Security, reliability, biometrics
Grid and Cloud computing

o Characterization of OS, Virtual Machine, middleware and library behavior
Virtual machines, Websphere, .NET, Java VM, databases
Graphics libraries, scientific libraries

o Characterization of system behavior, including
Operating system and hypervisor effects and overheads
Hardware accelerators (GPGPU, XML, crypto, etc)
User behavior and system-user interaction
Instrumentation methodologies for workload verification
and characterization
Techniques for accurate analysis/measurement of production systems

o Implications of workloads in design issues, such as
Power management, reliability, security, performance
Processors, memory hierarchy, I/O, and networks
Design of accelerators, FPGA’s, GPU’s, etc.
Novel architectures (non-Von-Neumann)

o Benchmark creation, analysis, and evaluation issues, including
Multithreaded benchmarks, benchmark cloning
Profiling, trace collection, synthetic traces
Validation of benchmarks

o Analytical and abstract modeling of program behavior and systems

o Emerging and future workloads
Transactional memory workloads; workloads for multi/many-core systems
Stream-based computing workloads; web2.0/internet workloads;
Cyber-physical workloads


Important Dates:
Abstracts Due……………..Mar 29, 2013
Papers Due………………..April 5, 2013
Author Notification………..June 14, 2013


General Chair…………………Ravi Iyer, Intel
Program Chair…………………David Brooks, Harvard
Workshop/Tutorials Chair……….Eriko Nurvitadhi, Intel
Finance Chair…………………Rajeev Balasubramonian, U. of Utah
Local Arrangements Chair……….Omesh Tickoo, Intel
Publications Chair…………….Vijay Janapa Reddi, UT-Austin
Publicity Chair……………….Kushagra Vaid, Microsoft
Registration Chair…………….Guangdeng Liao, Intel
Web Chair…………………….Mi Sun Park, Penn State University
Submissions Chair……………..Glenn Holloway, Harvard
Program Committee……………..TBD

Call for Papers: JSSPP 2013

Submitted by Narayan Desai
May 24, 2013

Submitted by Narayan Desai

in conjunction with IPDPS
Boston, USA, May 24, 2013

The JSSPP workshop addresses all scheduling aspects of parallel

Large parallel systems have been in production for over 15 years.
Initially, they were primarily used in scientific computing. But with
the advance of Cloud computing and new processor paradigms such as
multi-core systems and reconfigurable architectures, scheduling in
parallel systems has grown in relevance and scope, significantly
extending its original focus. JSSPP has evolved with the area and now
fully covers parallel scheduling for commercial environments while
still maintaining strong interest in its traditional areas: scientific
computing, supercomputing and cluster platforms.

From its very beginning, JSSPP has strived to balance practice and
theory in its program. This combination provides a rich environment
for technical debate about scheduling approaches including both
academic researchers as well as participants from industry. JSSPP is a
high-visibility workshop, which has been ranking repeatedly in the top
10% of Citeseer’s venue impact list. JSSPP solicits papers that belong
to any of the following topics, although papers on other themes that
are relevant in the context of JSSPP are welcome as well: Performance
evaluation of scheduling approaches, including methodology,
benchmarks, and metrics. Design of, and experience with, scheduling
approaches for production systems. Workloads on parallel processing
systems, including characterization, classification, and modeling.
Consideration of additional constraints in scheduling systems, like
job priorities, accounting, load estimation, and quality of service
guarantees. Scaling and composition of very large scheduling systems.
Interaction between schedulers on different levels, like processor
level as well as whole single- or even multi-owner systems. Impact of
scheduling strategies on application performance, user friendliness,
cost efficiency, and energy efficiency.

Submission dates and guidelines
DEADLINE: February 17, 2013
NOTIFICATION: March 20, 2013

Papers should be no longer than 20 single-spaced pages, 10pt font,
including figures and references. All papers in scope will be reviewed
by at least three members of the program committee. All submissions
must follow the LNCS format, see the instructions at Springer’s web

Files must be submitted electronically in PDF format and must be
formatted for 8.5×11 inch paper. Submission procedures can be found at
the workshop’s homepage:

Papers can be submitted via EDAS:

Goals Continuing the tradition started at IPPS’95, the workshop is
intended to attract people from academia, industry, computing centers,
national laboratories, Cloud and Grid initiatives, and parallel
computer vendors to address scheduling in parallel systems, and
attempt to resolve often conflicting goals expressed by system owners.
The workshop intends to achieve a balance between – reports of current
practices in the entire range of parallel systems, – proposals of
novel schemes that have not yet been tested in a real environment, and
– realistic models and their analysis.

Registration Registration will be part of the IPDPS process and is
handled by the IEEE. For details, see the IPDPS web site

Proceedings Interim proceedings containing a collection of the papers
presented will be distributed at the workshop in electronic form. It
is planned to also publish a post-workshop proceedings in the Springer
Lecture Notes on Computer Science series, as was done in previous
years (pending approval from Springer).

Workshop organizers
Walfredo Cirne, Google
Narayan Desai, Argonne National Laboratory

Program Committee
Henri Casanova, University of Hawaii at Manoa
Julita Corbalan, Technical University of Catalonia
Dick Epema, Delft University of Technology
Gilles Fedak, INRIA
Dror G. Feitelson, The Hebrew University
Liana Fong, IBM T. J. Watson Research Center
Eitan Frachtenberg, Facebook
Alfredo Goldman, USP
Allan Gottlieb, NYU
Alexandru Iosup, Delft University of Technology
Morris Jette, SchedMD LLC
Rajkumar Kettimuthu, Argonne National Lab
Dalibor Klusáček, Masaryk University
Zhiling Lan, Illinois Institute of Technology
Bill Nitzberg, Altair
David Oppenheimer, Google
Uwe Schwiegelshohn, TU Dortmund University
Mark Squillante, IBM Thomas J. Watson Research Center
Wei Tang, Argonne National Laboratory
Dan Tsafrir, Technion – Israel Institute of Technology
Ramin Yahyapour, GWDG – University Göttingen

Henri Casanova, University of Hawaii at Manoa
Julita Corbalan, Technical University of Catalunya
Dick Epema, Delft University of Technology
Dror G. Feitelson, The Hebrew University
Ian Foster, Argonne National Laboratory
Alfredo Goldman, University of Sao Paulo
Allan Gottlieb, New York University
Morris Jette, SchedMD
Rajkumar Kettimuthu, Argonne National Lab
Derrick Kondo, INRIA
Zhiling Lan, Illinois Institute of Technology
Virginia Lo, University of Oregon
Satoshi Matsuoka, Tokyo Institute of Technology
Jose Moreira, IBM T.J. Watson Research Center
Bill Nitzberg, Altair Engineering
Mark Squillante, IBM Thomas J. Watson Research Center
Dan Tsafrir, Technion
John Wilkes, Google
Ramin Yahyapour, The University of Göttingen

Call for Papers: IEEE Micro Special Issue on Reliability

Submitted by Vijay—reliability-aware-design
December 17 to February 8, 2013

Submitted by Vijay Reddi—reliability-aware-design
Call for Papers, IEEE Micro Special Issue on Reliability

Submissions due: February 8th, 2013 (Extension from January 8th)
Publication date: July ~ August 2013

Over the past decade, designers have sought after efficient design points with
respect to power, performance and cost. Of these, power has undoubtedly emerged
as a first-order design challenge. In the coming era, this challenge may be
subsumed by the challenge of building robust and reliable systems. As technology
advances, susceptibility of systems to transient errors, such as timing
violations, parameter variations, aging and infant mortality, is steadily
increasing. Without innovations in the areas of microprocessor and software
reliability, future systems may face continuous failure. Thus, new computing
paradigms are required that incorporate adaptive techniques at both the hardware
and software layers to ensure robust and resilient execution. The system, as a
whole, must dynamically detect and recover from errors to meet historically
established high reliability standards without exceeding power budgets and cost
constraints, and violating performance targets. To this end, the goal of this
IEEE Micro issue is to seek original papers on all topics related to reliability
that span the spectrum of layers in the system stack, from device, circuit and
architecture design to the role of software in enabling robust and reliable

Areas of interest include, but are not limited to:

* Characterizing the trade-offs between power, performance and reliability
* Resilient circuit and memory system design
* Emerging process technology issues
* Case-studies, applications and experience reports on system reliability
* Benchmarking for reliability
* Approximate computing solutions
* Near/Sub-threshold computing paradigm
* Algorithmic resiliency
* Hardware and software co-design
* Programming and language support for reliability
* Security
* Warehouse-scale resilient computer system design

Submission procedure:

Please log onto IEEE CS Manuscript Central (
/micro-cs) to submit your manuscript to the Reliability” issue. Please direct
questions to the IEEE Micro magazine assistant ( For the
manuscript submission, acceptable file formats include Microsoft Word and PDF.
Manuscripts should not exceed 5,000 words including references, with each
average-size figure counting as 150 words toward this limit. Please include all
figures and tables, as well as a cover page with all the relevant author contact
information (name, postal address, phone, fax, and e-mail address) and a
200-word abstract. Submitted manuscripts must not have been previously published
or currently submitted for publication elsewhere, and all manuscripts must be
cleared for publication. All previously published papers must have at least 30%
new content compared to any conference (or other) publication. Accepted articles
will be edited for structure, style, clarity, and readability. For more
information, please visit the IEEE Micro Author Center

Important dates:

Initial submissions due: Feb. 8, 2013 (Extension: Was Jan 8, 2013)
Author notification: Mar 19, 2013
Final version due: Apr 9, 2013
Publication time-frame: July ~ August 2013


For any further information and questions please contact this issue’s Guest
Editor Vijay Janapa Reddi (

Call for Papers: IEEE NAS 2013

Submitted by Chao Li
July 10 to July 12, 2013

Submitted by Chao Li

The 8th IEEE International Conference on Networking, Architecture, and Storage
(NAS 2013) will be held from July 10 − 12, 2013 at Xi’an, Shaanxi, China.
It will serve as an international forum to bring together researchers and
practitioners from academia and industry to discuss cutting-edge research on
networking, high-performance computer architecture, and parallel and
distributed data storage technologies. NAS 2013 will expose participants to
the most recent developments in the interdisciplinary areas. Papers are
solicited on a broad range of topics, including (but not limited to):

– Network security and privacy
– Virtual and overlay networks
– Network applications and services
– Ad hoc and sensor networks
– Networks and protocols
– Network architectures
– Processor architectures
– Cache and memory systems
– Parallel and multi-core systems
– Impact of (emerging) technologies on architectures
– Network information theory & network coding
– Power and energy efficient architectures and techniques
– Storage management
– Storage performance and scalability
– File systems, object-based storage, and block storage
– Energy-aware storage
– Architecture and applications of solid state disks
– Cloud Storage
– Storage Virtualization
– HW/SW tradeoffs

Submission Deadline: March 1st, 2013
Notification of acceptance: April 22nd, 2013
Camera-ready Paper: May 13th, 2013
Conference: July 10-12, 2013

NAS 2013 will be held in Xi’an, an amazing ancient city in China.
Read more about Xi’an:’an

Call for Papers: SYSTOR 2013

Submitted by Ronen Kat
June 30 to July 2, 2013

Submitted by Ronen Kat
On behalf of SYSTOR 2013, the 6th Annual International Systems and Storage
Conference, we invite you to submit original and innovative papers. The
conference will take place June 30 – July 2, 2013 in Haifa, Israel, shortly
following the ACM/IEEE International Symposium on Computer Architecture
(ISCA 2013) in Tel Aviv.

SYSTOR promotes experimental and practical computer systems research including
(but not limited to) the following topics:
* operating systems, computer architecture, and their interactions
* distributed, parallel, and cloud systems
* networked, mobile, wireless, peer-to-peer, and sensor systems
* runtime systems and compiler/programming-language support
* energy/power management
* file and storage systems
* security, privacy, and trust
* virtualization
* embedded and real-time systems
* fault tolerance, reliability, and availability
* deployment, usage, and experience
* performance evaluation and workload characterization

Paper submission (full and short): March 14, 2013 (11:59pm GMT)
Paper submission to highlights category: April 15, 2013 (11:59pm GMT)
Paper notification: April 29, 2013
Camera-ready submission: May 20, 2013 (11:59pm GMT)
Poster submission: May 20, 2013 (11:59pm GMT)
Poster notification: May 27, 2013

Mary Baker, HP Labs
Sivan Toledo, Tel Aviv University

Ronen Kat, IBM Research