Call for Participation: ISPASS 2013 — Workshops and Tutorials

Submitted by Ioana Baldini
April 21, 2013

Submitted by Ioana Baldini
Call for Participation: ISPASS 2013 — Workshops and Tutorials:

The following two tutorials and one workshop are being held on
Sunday April 21, 2013 in conjunction with ISPASS:

Modeling Exascale Applications with SST/macro and Eiger
(half day)

GPUWattch + GPGPU-Sim: An Integrated Framework for
Energy Optimizations in Manycore (half day)

FastPath 2013 Workshop on Performance Analysis
of Workload Optimized Systems (full day)
Submission deadline: March 10, 2013

Detailed information:

Modeling Exascale Applications with SST/macro and Eiger
(half day)

In high performance computing (HPC), the importance of fast, large
scale models of high fidelity are only increasing as we move towards
the next frontier of exascale. Hardware/software codesign is viewed as
a key methodology to reaching this end. The SST/macro toolkit[1]
provides HPC engineers the ability to explore current and future
hardware/software design constraints. Instead of costly (in time and
user effort) cycle-accurate simulation, macro-scale simulation can
provide valuable insight into the performance of large
applications. The value of these tools lies in high quality
application models for increasingly complex hardware designs.

The Eiger Performance Modeling Framework[2] generates models by
applying statistical techniques from the field of machine learning on
empirical performance data. While macro-scale simulation can provide a
reasonable overview of system wide phenomena, Eiger can leverage data
acquired from micro-scale sources to inform large scale simulations in
SST/macro. Eiger provides an API and data store for aggregating data
from micro-scale sources such as simulators, emulators, and runtime

This tutorial will present attendees with the techniques and
methodologies to leverage SST/macro and Eiger for modelling large
scale applications on upcoming supercomputer hardware. This
presentation is geared towards domain experts and HPC hardware
designers, as well as students and researchers whose work requires
exploration of programming models, interaction between computation and
communication, and data-driven modelling techniques for large scale
systems. These tools are geared toward ease of use and rapid
iteration, allowing area experts to generate verbose performance
models without requiring intricate knowledge of every facet of the
computing environment. This tutorial will require only a basic level
of programming skill.

GPUWattch + GPGPU-Sim: An Integrated Framework for
Energy Optimizations in Manycore (half day)

The objective of this tutorial is to present an overview of the design
and implementation of the GPGPU- Sim simulation infrastructure along
with a newly developed power model. The integrated GPUWattch power
model is highly configurable and extensible.

GPGPU-Sim version 3.x represents a significant update to GPGPU-Sim,
featuring a more accurate and detailed microarchitectural model. It
includes support for NVIDIA’s native ISA and the Fermi
Architecture. With the tightly-coupled GPUWattch, the simulation
infrastructure is now a complete platform for performance and energy
optimization research. The infrastructure follows a rigorous design
methodology that has been tested and validated against hardware
performance and power measurements for both the Fermi and Quadro

FastPath 2013 Workshop on Performance Analysis
of Workload Optimized Systems (full day)

The goal of FastPath is to bring together researchers and
practitioners involved in cross-stack hardware/software performance
analysis, modeling, and evaluation of workload optimized systems.

With microprocessor clock speeds being held constant, optimizing
systems around specific workloads is an increasingly attractive means
to improve performance. The importance of workload optimized systems
is seen in their ubiquitous deployment in diverse systems from
cellphones to tablets to routers to game machines to Top500
supercomputers, and IT appliances such as IBM’s DataPower and Netezza,
and Oracle’s Exadata.

More precisely, workload optimized systems have hardware and/or
software specifically designed to run well for a particular
application or application class. The types and components of workload
optimized systems vary, but a partial list includes traditional CPUs
assisted with accelerators (ASICs, FPGAs, GPUs), memory accelerators,
I/O accelerators, hybrid systems, and IT appliances.

Exploiting CPU savings and speed-ups offered by workload optimized
systems for application level performance improvement poses several
cross stack hardware and software challenges. These include developing
alternate programming models to exploit massive parallelism offered by
accelerators, designing low-latency, high-throughput H/W-S/W
interfaces, and developing techniques to efficiently map processing
logic on hardware.

Call for Participation: ASPLOS 2013 Tutorial — Using Queuing Theory to Model Data Center Systems

Submitted by Thomas Wenisch
March 17, 2013 at 13:30

Submitted by Thomas Wenisch

Using Queuing Theory to Model Data Center Systems
Tutorial with ASPLOS 2013
3/17 1:30-5:00pm

David Meisner, Facebook,
Mor Harchol-Balter, Carnegie Mellon University,
Thomas Wenisch, University of Michigan,

Recently, there has been an explosive growth in Internet services, greatly
increasing the importance of data center systems. Applications served from
ìthe cloudî are driving data center growth and quickly overtaking traditional
workstations. Although there are many analytic and simulation tools for
evaluating components of desktop and server architectures in detail, scalable
modeling tools are noticeably missing.

We believe that stochastic methods and queueing theory together provide an
avenue to answer important questions about data center systems. In the first
half of this tutorial, we present a crash-course (or perhaps, a refresher for
some) on the essential elements of queueing theory with particular applications
to modeling data center systems. We also illustrate how queueing theory can be
used to solve problems related to the design and analysis of computer systems.

In the second part of the tutorial, we describe BigHouse, a simulation
infrastructure that combines queuing theory and stochastic methods to model
data centers systems. Instead of simulating servers using detailed
microarchitectural models, BigHouse raises the level of abstraction using the
tools of queuing theory, enabling simulation at 1000-server scale in less
than an hour. We include brief background on data center power modeling, a
description of the statistical methods used by BigHouse, parallelization
techniques, a tour of the simulator code, and a case study of using BigHouse
to model data center power capping.

Call for Presentations: 2nd Dark Silicon Workshop (DaSi 2013)

Submitted by Jack Sampson
March 29, 2013 at 23:45

Submitted by Jack Sampson

The 2nd Dark Silicon Workshop
Tel-Aviv, Israel.
June 24th, 2013. Held in conjunction with ISCA 2013

The second Dark Silicon Workshop provides a unique forum for discussing
the challenges and opportunities that Dark Silicon presents. There are
many research questions left to answer before new architectures built
specifically to mitigate or exploit dark silicon become the default
platforms for general purpose computing. To scale alongside dark
silicon, architects will need to design and verify specialized
processors in increasing numbers. Making heterogeneous platforms easy
to program will require us to reconsider traditional language and OS
abstractions. Traditionally, many of the performance gains from
specialized hardware stem from customized memory designs, and it is
not yet clear how best to integrate multiple such memory designs
together into a single architecture. These and other challenges will
face researchers as they shed light on silicon’s dark future.

The organizing committee is soliciting presentations on any topic
related to Dark Silicon, including (but not limited to):
– Architectural approaches to managing and exploiting dark silicon
– Power management techniques
– Energy/power-efficient circuit designs
– Energy/power-efficient memory systems
– Scalable design and synthesis techniques for customizable and
specialized cores
– Novel applications for idle chip area

The goal is to facilitate the exchange of the latest ideas, insights,
and knowledge that can propel future progress. In lieu of printed
proceedings, we will post the slides and extended abstracts of the
presentations online. Presentation of new work at the workshop does
not preclude future publication.

Workshop submissions should be in the form of a 2-page presentation
abstract. Submissions will be evaluated on the basis of impact,
novelty, and general interest. The submission deadline is March 29,
2013, with notification of acceptance by May 10, 2013.

Further details on abstract submission, technical program, tutorials,
travel, social program, and travel grants will be provided at the
workshop website:

Organizing Committee:
Jack Sampson, UCSD
Steven Swanson, UCSD
Michael B. Taylor, UCSD

Call for Papers: IEEE Micro Special Issue on Dark Silicon

Submitted by Michael Bedford Taylor
March 8, 2013

Submitted by Michael Bedford Taylor

Call for Papers, IEEE Micro Special Issue on Dark Silicon
Guest Editors: Michael Taylor and Steven Swanson (UCSD)

Submissions due: March 8, 2013
Publication date: Sept-Oct 2013

Over the last five years, the phenomenon known as Dark Silicon has
emerged as the most fundamental factor that shapes our ability to
exploit the exponentially increasing resources that Moore’s Law
provides. Dark Silicon refers to the exponentially increasing number
of a chip’s transistors that must remain passive, or “dark”, in order
to stay within a chip’s power budget.

Due to the breakdown of Dennard Scaling, multicore chips will not
be able to scale with die area; the fraction of a chip that can be
filled with cores running at full frequency is dropping exponentially
with each process generation. This reality will force designers to
ensure that, at any point in time, large fractions of their chips are
effectively dark or dim – either idle or significantly underclocked.
As exponentially larger fractions of a chip’s transistors become dark
transistors, silicon area becomes an exponentially cheaper resource
relative to power and energy consumption. This shift calls for new
architectural techniques that “spend” silicon area to “buy” energy
efficiency, or for new circuit technologies that overcome the inherent
limitations of CMOS that lead to dark silicon. To this end, this IEEE
Micro issue seeks original papers on all topics related to dark
silicon that span the spectrum of layers in the system stack, from
device, circuit and architecture design to the role of software in
maximize computing capabilities in the face of dark silicon.

Areas of interest include, but are not limited to:

– Approaches that offer new insight into the dark silicon problem
– Architectural approaches to managing and exploiting dark silicon
– Scalable design and synthesis techniques for customizable and
specialized cores
– Promising Beyond-CMOS approaches that enable post-Dennardian circuit scaling
– Novel applications for idle chip area
– Software systems for adapting to dark silicon
– Power management techniques for dark silicon
– Energy/power-efficient circuit designs and memory systems for dark silicon

Submission procedure:

Please log onto IEEE CS Manuscript Central
( to submit your manuscript
to the “Dark Silicon” issue. Please direct questions to the IEEE
Micro magazine assistant ( For the manuscript
submission, acceptable file formats include Microsoft Word and PDF.
Manuscripts should not exceed 5,000 words including references, with
each average-size figure counting as 150 words toward this limit.
Please include all figures and tables, as well as a cover page with
all the relevant author contact information (name, postal address,
phone, fax, and e-mail address) and a 200-word abstract. Submitted
manuscripts must not have been previously published or currently
submitted for publication elsewhere, and all manuscripts must be
cleared for publication. All previously published papers must have at
least 30% new content compared to any conference (or other)
publication. Accepted articles will be edited for structure, style,
clarity, and readability. For more information, please visit the IEEE
Micro Author Center

Important dates:
Initial submissions due: March 8, 2013
Author notification: April 30, 2013
Final version due: June 14, 2013
Publication timeframe: Sept-Oct, 2013


For any further information and questions please contact Guest Editor
Michael Taylor (

Call for Papers: ICCD 2013

Submitted by Rainer Buchty
October 6 to October 9, 2013

Submitted by Rainer Buchty

31st IEEE International Conference on Computer Design
ICCD 2013

THEME: The Next 30 Years

Asheville, NC, USA
October 6-9, 2013


Abstract submission: May 6
Paper submission: May 13
Author notification: July 22
Final paper: August 26

range of topics in the research, design, and implementation of
computer systems and their components. ICCD’s multi-disciplinary
emphasis provides an ideal environment for developers and researchers
to discuss practical and theoretical work covering system and computer
architecture, test, verification and security, design and technology,
and tools and methodologies.

In 2012, ICCD celebrated its 30th edition with a retrospective of
developments since 1983. This year, the conference theme is:

The Next 30 Years

We especially encourage submissions that look forward to future
systems and technologies. Manuscripts describing original work on any
topic from the scope of ICCD are welcome. Authors are asked to submit
technical papers in accordance to the author’s instructions in one of
the following five conference tracks:

Advanced computer architecture for general and application-specific
enhancement; Software design for embedded, mobile, general-purpose,
cloud, and high-performance platforms; IP and platform-based designs;
HW/SW codesign; Modeling and performance analysis; Support for
security, languages and operating systems; Real-time systems;
Application-specific and embedded software optimization; Compiler
support for multithreaded and multi-core designs; Memory system and
network system optimization; On-chip and system-area networks; Support
for communication and synchronization.

Microarchitecture design techniques for uni- and multi-core
processors: instruction-level parallelism, pipelining, caching, branch
prediction, multithreading; Techniques for low-power, secure, and
reliable processors; Embedded, network, graphic, system-on-chip,
application-specific and digital signal processor design; Hardware
support for processor virtualization; Real-life design challenges:
case studies, tradeoffs, post-mortems.

Circuits and design techniques for digital, memory, analog and
mixed-signal systems; Circuits and design techniques for high
performance and low power; Circuits and design techniques for
robustness under process variability and radiation; Design techniques
for emerging process technologies (MEMs, spintronics nano, quantum);
Asynchronous circuits; Signal processing, graphic processor and
arithmetic circuits.

High-level, logic and physical synthesis; Physical planning, design
and early estimation for large circuits; Automatic analysis and
optimization of timing, power and noise; Tools for multiple-clock
domains, asynchronous and mixed timing methodologies; CAD support for
FPGAs, ASSPs, structured ASICs, platform-based design and NOC; DfM and
OPC methodologies; System-level design and synthesis; Tools and design
methods for emerging technologies (MEMs, spintronics, nano, quantum).

Design error debug and diagnosis; Fault modeling; Fault simulation and
ATPG; Fault tolerance; DFT and BIST. Functional, transaction-level,
RTL, and gate-level modeling and verification of hardware designs;
Equivalence checking, property checking, and theorem proving;
Constrained-random test generation; High-level design and SoC
validation. Hardware security primitives; Side channel analysis; Logic
and microarchitectural countermeasures; Interaction between VLSI test
and trust.

ICCD 2013 Organizing Committee

General Chairs
Greg Byrd, NC State Univ., USA
Klaus Schneider, Univ. of Kaiserslautern, Germany
Past Chair
Sofiene Tahar, Concordia Univ., Canada
Technical Program Chairs
Pradip Bose, IBM, USA
Naehyuck Chang, Seoul National Univ., Korea
Special Sessions Chair
Omer Khan, Univ. of Connecticut, USA
Finance Chairs
Carlo Galuzzi, TU Delft, The Netherlands
Andrew Hilton, Duke Univ., USA
Local Arrangements Chair
James Tuck, NC State Univ., USA
Publication Chair
Sung Woo Chung, Korea Univ., Korea
Web Chair
John Kim, KAIST, Korea
Publicity Chairs
Rainer Buchty, TU Braunschweig, Germany
Yukuen Lai, Chung Yuan Christian Univ., Taiwan
Guru Prasadh Venkataramani, GWU, USA

ICCD 2013 Track Chairs

Computer Systems and Applications
Luc Claesen, Hasselt Univ., Belgium
Natalie Enright Jerger, Univ. of Toronto, Canada
Processor Architecture
Ben Juurlink, TU Berlin, Germany
Sung Woo Chung, Korea Univ., Korea
Logic and Circuit Design
Massimo Alioto, Univ. of Siena, Italy
William Hung, Synopsys, USA
Electronic Design Automation
David Pan, Univ. of Texas, USA
Donatella Sciuto, Politecnico di Milano, Italy
Test, Verification, and Security
Ozgur Sinanoglu, NYU Abu Dhabi, UAE
Dominik Stoffel, Univ. Kaiserslautern, Germany

ICCD Steering Committee

Kee-Sup Kim, Samsung, Korea (Chair)
Peter-Michael Seidel, Univ. of Hawaii, USA
Sandip Kundu, Univ. of Massachusetts, USA
Georgi Gaydadjiev, Chalmers Univ., Sweden