Call for Papers: WDDD 2013

Submitted by Natalie Enright Jerger
https://sites.google.com/site/wddd2013/
June 23, 2013 at 08:00

Submitted by Natalie Enright Jerger
https://sites.google.com/site/wddd2013/
Important Dates:
Submission: March 29, 2013
Acceptance: April 26, 2013

Workshop Overview

WDDD provides the computer systems research community a forum for
work that validates or duplicates earlier results; deconstructs prior findings
by providing greater, in-depth insight into causal relationships or
correlations; or debunks earlier findings by describing precisely how and
why proposed techniques fail where earlier successes were claimed, or
succeed where failure was reported.

Traditionally, computer systems research conferences have focused almost
exclusively on novelty and performance, neglecting an abundance of
interesting work that lacks one or both of these attributes. A significant
part of research–in fact, the backbone of the scientific method–involves
independent validation of existing work and the exploration of strange ideas
that never pan out. This workshop provides a venue for disseminating such
work in our community. Published validation experiments strengthen
existing work, while thorough comparisons provide new dimensions and
perspectives. Studies that refute or correct existing work also strengthen
the research community, by ensuring that published material is technically
correct and has sound assumptions. Publishing negative or strange or
unexpected results will allow future researchers to learn the hard lessons
of others, without repeating their effort.

This workshop will set a high scientific standard for such experiments, and
will require insightful analysis to justify all conclusions. The workshop will
favor submissions that provide meaningful insights, and identify underlying
root causes for the failure or success of the investigated technique.
Acceptable work must thoroughly investigate and communicate why the
proposed technique performs as the results indicate. WDDD has a unique
tradition of asking the original paper authors to provide a follow-up
comment after the WDDD paper has been presented, where appropriate.
The follow-up comment may take the form of a rebuttal or additional
insight from the original authors.

Submission Topics

–Independent validation of earlier results with meaningful analysis
–In-depth analysis and sensitivity studies that provide further insight into
earlier findings, or identify key parameters or assumptions that affect the
results
–Studies that refute earlier findings, with clear justification and explanation
–Negative results for ideas that intuitively make sense and should work,
along with explanations for why they do not
–Validation/refutation of controversial advertising claims by industrial
competitors

Workshop Scope

Computer Architecture
–Processor architecture/microarchitecture
–Memory hierarchy
–Multiprocessor systems
–Power-efficient architecture
–Dependable architectures
–Compiler/architecture interaction
–Application-specific, reconfigurable and embedded architecture

Code Generation and Optimization
–Feedback-driven optimization
–Phase-based optimization
–Dynamic compilation, adaptive/continuous optimization
–Modulo/trace scheduling
–Efficient profiling techniques
–Binary translation/optimization
–Compilation support for thread level speculation

Submission Guidelines

Submit a manuscript of up to 10 pages in two-column format by March 29, 2013
using the submission website
(https://www.easychair.org/conferences/?conf=wddd2013)

Organizers
Murali Annavaram, USC
Natalie Enright Jerger, University of Toronto
Gabriel Loh, AMD

Call for Papers: WIVOSCA 2013

Submitted by Girish Venkatasubramanian
http://www.ideal.ece.ufl.edu/wivosca/
June 23 to June 24, 2013

Submitted by Girish Venkatasubramanian
http://www.ideal.ece.ufl.edu/wivosca/

Seventh Annual
Workshop on the Interaction amongst
Virtualization, Operating Systems, and Computer Architecture
( WIVOSCA 2013 )

http://www.ideal.ece.ufl.edu/wivosca

Held in Conjunction with the
40th Annual International Symposium on Computer Architecture
( ISCA – 40 )

Workshop Overview and Topics
~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Operating systems (OS) constitute a major software component
and are essential to any computing system. Commercial and
server workloads such as online transaction processing,
database, file/e-mail servers involve significant OS-level
activity. The interactions between OS and emerging
architectures (e.g. homogeneous and heterogeneous chip
multiprocessors, simultaneous multithreading systems) /
technology (e.g. hardware-assisted virtualization) are
projected to continuously increase. In addition, the use of a
wide variety of virtualization techniques, ranging from
application-level virtualization to full-system virtualization,
for providing application portability, managing power and
performance, providing QoS guarantees and to effectively use the
power of emerging architectures, has become prominent.

To optimize system
performance/power/reliability/security, it is important to
facilitate efficient interaction and cooperation amongst the
three constantly evolving components – OS, virtualization and
computer architecture.

This workshop focuses on characterizing, modeling, and
optimizing the interaction between OS and hardware in the
light of emerging architecture paradigms, workloads, and
computing technology. Topics of particular interest include,
but are not limited to:

* Architectural support for OS functionality and services
* Architectural support for virtual machines and hypervisors
* Hardware acceleration of OS and Virtualization services
* OS and Virtualization support for emerging computer architectures
* Implications of virtualization on OS design
* Effect of OS/Virtualization on emerging architectures
* System software-aware microarchitecture design
* Leveraging OS/Virtualization to optimize reliability/thermal/power
* Frameworks and tools for full-system simulation
* Characterization of OS/Virtualization activity in emerging workloads
* Performance, power, dependability, and security in OS/Virtualization
* OS/Virtualization -intensive benchmark suites
* Evaluation of the interaction/interference among OS/user
* Mitigation of OS and Virtualization related execution bottlenecks
* Architecture and Virtualization issues in data centers
* Architecture and Virtualization support for cloud computing

Furthermore, the workshop aims at providing a forum for
researchers, engineers, and students from academia and
industry to discuss their latest research in
virtualization, computer architecture and OS, to bring
their ideas and research problems to the attention of
others, and to obtain valuable and instant feedback from
fellow researchers.

Workshop Co-Organizers
~~~~~~~~~~~~~~~~~~~~~~
Tao Li, University of Florida (taoli@ece.ufl.edu)
James Poe, Miami Dade College (jpoe@mdc.edu)
Girish Venkatasubramanian, Intel (girish.venkatasubramanian@intel.com)

Important Dates
~~~~~~~~~~~~~~~

* Abstract Submission: April 12, 2013
* Paper Submission: April 19, 2013
* Author Notification: May 10, 2013
* Camera-ready Version: May 17, 2013

Please feel free to visit our website for more information
as well as links to previous WIOSCA workshops:

http://www.ideal.ece.ufl.edu/wivosca

Call for Papers: HEART2013

Submitted by Yoshiki Yamaguchi
http://www.isheart.org/
June 13 to June 14, 2013

Submitted by Yoshiki Yamaguchi
http://www.isheart.org/
The 4th International Symposium on Highly Efficient Accelerators and
Reconfigurable Technologies (HEART) is a forum to present and discuss
the latest research on accelerators including FPGAs and multi/many
core technologies for high-performance and power-efficient computing.

Important Dates (all 23:59 GMT)
– Paper submission: March 15, 2013
– Author notification: April 15, 2013
– Camera-ready due: April 30, 2013
– Symposium Dates: June 13 – 14, 2013

Submissions are solicited on a wide variety of topics related to
acceleration for high-performance and power-efficient computing,
including but not limited to:

Architectures and systems:
– Novel systems/platforms for efficient acceleration based
on FPGA, GPU, and other devices
– Heterogeneous processors/systems for scalable, high-performance,
high-reliability and/or low-power computation
– Reconfigurable/configurable hardware and systems including IP-cores,
embedded systems, SoCs and cluster/grid/cloud computing systems
for scalable, high-performance and/or low-power processing
– High-performance custom-computing processors/systems
– Novel architectures and device technologies that can be applied
to efficient acceleration, including many-core architectures,
NoC architectures, 3D-stacking technologies and optical devices

Software and applications:
– Novel applications for efficient acceleration systems/platforms,
and custom computing
– Compiler techniques and programming languages for efficient
acceleration systems/platforms, including many-core processors,
GPUs, FPGAs and other reconfigurable/custom processors
– Run-time techniques for acceleration, including Just-in-Time
compilation and dynamic partial-reconfiguration
– Performance evaluation and analysis for efficient acceleration
– High-level synthesis and design methodologies for heterogeneous,
reconfigurable and/or custom processors/systems

As in previous HEART editions, we plan to publish selected accepted
papers at HEART 2013 in post-proceedings ACM SIGARCH Computer
Architecture News (CAN), which is also available in ACM Digital
Library.

Prospective authors are invited to submit original and unpublished
contributions as 6-page papers to be considered as regular papers
or 4-page papers to be considered as poster papers.
All contributions must be submitted electronically in PDF format
(two columns, US letter size, single-spacing, 10 points for main
body text).

For double-blind review, manuscripts must NOT identify the authors
in any way, so author names, affiliations, e-mail addresses and
self-references should be blanked out. Papers that identify authors
may be rejected without review. You can submit your contribution(s)
by following this easychair submission link.

Each accepted paper MUST have at least one author with a paid
registration for the manuscript to be included and published in
the symposium proceedings and ACM SIGARCH CAN post-proceedings.
Authors are also expected to attend and present their paper(s)
at the symposium.

The HEART2013 paper template can be download here: HEART2013
template in MS-Word, HEART2013 template in Latex.

Important Dates (all 23:59 GMT)
– Paper submission: March 15, 2013
– Author notification: April 15, 2013
– Camera-ready due: April 30, 2013
– Symposium Dates: June 13 – 14, 2013

Call for papers: SYSTOR 2013, deadline extended

Submitted by Ronen Kat
http://systor13.systor.org
June 30 to July 2, 2013

Submitted by Ronen Kat
http://systor13.systor.org
We invite you to submit original and innovative papers to SYSTOR 2013,
the 6th Annual International Systems and Storage Conference.
The conference will take place June 30 – July 2, 2013 in Haifa, Israel,
shortly following the ACM/IEEE International Symposium on Computer
Architecture (ISCA 2013) in Tel Aviv.

Submission deadline was now extended to March 21.

SYSTOR promotes experimental and practical computer systems research including
(but not limited to) the following topics:
* operating systems, computer architecture, and their interactions
* distributed, parallel, and cloud systems
* networked, mobile, wireless, peer-to-peer, and sensor systems
* runtime systems and compiler/programming-language support
* energy/power management
* file and storage systems
* security, privacy, and trust
* virtualization
* embedded and real-time systems
* fault tolerance, reliability, and availability
* deployment, usage, and experience
* performance evaluation and workload characterization

Call for Papers: IEEE NAS deadline extended

Submitted by Chao Li
http://www.nas-conference.org/
July 17 to July 19, 2013

Submitted by Chao Li
http://www.nas-conference.org/
The submission deadline of IEEE NAS Conference has been extended.
The new deadline is: March 18th (hard deadline).
Please consider submitting your papers.

Topics of interest include but are not limited to the list as follow:

– Network security and privacy
– Virtual and overlay networks
– Network applications and services
– Ad hoc and sensor networks
– Networks and protocols
– Network architectures
– Processor architectures
– Cache and memory systems
– Parallel and multi-core systems
– Impact of (emerging) technologies on architectures
– Network information theory & network coding
– Power and energy efficient architectures and techniques
– Storage management
– Storage performance and scalability
– File systems, object-based storage, and block storage
– Energy-aware storage
– Architecture and applications of solid state disks
– Cloud Storage
– Storage Virtualization
– HW/SW tradeoffs

Call For Papers: ISLPED 2013, Beijing, China, Deadline Extension

Submitted by Yuan Xie
http://www.islped.org
September 4 to September 6, 2013

Submitted by Yuan Xie
http://www.islped.org

INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN
Beijing, China
Sept. 4 – Sept. 6, 2013

http://www.islped.org

Deadline Extension:
Abstract Registration deadline extended from March 8 to March 22, 2013;
Full Paper deadline extended from March 15 on March 29, 2013;

CALL FOR PAPERS

The International Symposium on Low Power Electronics and Design
(ISLPED) is the premier forum for presentation of recent advances in
all aspects of low power design and technologies, ranging from process
and circuit technologies, simulation and synthesis tools, to system
level design and optimization. Specific topics include, but are not
limited to, the following two main areas, each with three sub-areas:
1.1. Technologies and Digital Circuits : Emerging logic/memory
technologies and applications; Low power device and interconnect
design; Low power low leakage circuits; Memory circuits; 3-D
technologies; Cooling technologies; Battery technologies;
Variation-tolerant design; Temperature-aware and reliable design.
1.2. Logic and Microarchitecture Design: Processor core design; Cache
and register file design; Memory Architectures; Logic and RTL design;
Arithmetic and signal processing circuits; Encryption technologies;
Asynchronous design.
1.3. Analog, MEMS, Mixed Signal and Imaging Electronics: RF circuits;
Wireless; MEMS circuits; AD/DA Converters; I/O circuits; Mixed signal
circuits; Imaging circuits; Circuits to support emerging technologies
and platforms; DC-DC converters.
2.1. CAD & Design Tools: Energy estimation and optimization tools
that operate at the physical, circuit/gate level, RT level, behavioral
level, and algorithmic levels; Links to other metrics: variability,
reliability, temperature.
2.2. System Design and Methodologies: Microprocessor, DSP and
embedded systems design; FPGA and ASIC designs; System-level power-
and thermal-aware design; System-level reliability- and
variability-aware design; Systems for Emerging applications
2.3. Software Design and Optimization: Power- and thermal-aware
software design, scheduling, and management; Application-level
optimizations; Wireless and sensor networks; Software for emerging
applications.

Submissions on new topics: emerging technologies,
architectures/platforms, and applications are particularly encouraged.

IMPORTANT DATES:

Abstract registration: March 22, 2013;
Full paper: March 29, 2013.

Submission Instructions:

Submissions should be full-length papers of up to 6 pages
(double-column, IEEE Transactions/Conference format, available at

http://www.ieee.org/conferences_events/conferences/publishing/templates.html),

including all illustrations, tables, references and an abstract of no more than
100 words. Papers exceeding the six-page limit will not be reviewed. Submission
must be anonymous: papers identifying the authors and/or with explicit
references to their prior work will be automatically rejected. Electronic
submission in pdf format only via the web is required. More information on
electronic submission to ISLPED’13 can be found at http://www.islped.org.

Program Co-Chairs:
Yuan Xie, Penn State/AMD Research yuanxie@cse.psu.edu
Tanay Karnik, Intel Labs tanay.karnik@intel.com

General Co-Chairs:
Pai Chou UC Irvine/NTHU phchou@uci.edu
Ru Huang Peking University huangr@ime.pku.edu.cn

Call for Participation: ACACES 2013

Submitted by Koen De Bosschere
http://www.hipeac.net/summerschool
July 14 to July 20, 2013

Submitted by Koen De Bosschere
http://www.hipeac.net/summerschool

Ninth International Summer School on
Advanced Computer Architecture and Compilation
for High-Performance and Embedded Systems

Fiuggi, Italy
Sunday July 14 – Saturday July 20, 2013

Organized by the HiPEAC Network of Excellence
sponsored by the 7th European framework programme
http://www.hipeac.net/summerschool

The ACACES Summer School is a one week summer school for computer architects
and tool builders working in the field of high performance computer
architecture, compilation and embedded systems. The school aims at the
dissemination of advanced scientific knowledge and the promotion of
international contacts among scientists from academia and industry.
A distinguishing feature of this Summer School is its broad scope ranging
from low level technological issues to advanced compilation techniques. In
the design of modern computer systems one has to be knowledgeable about
architecture as well as about the quality of the code, and how to improve
it. This summer school offers the ideal mix of the two worlds, both at
the entry level and at the most advanced level.

The ACACES Summer School is organized by the HiPEAC Network of Excellence
(http://www.HiPEAC.net), but it is open to everybody. However, previous
training and/or experience in computer science as well as a background in
computer architecture or compilation is indispensable.

The Summer School will take place in Fiuggi, a small town near Rome, Italy.
Students and lecturers will be accommodated in private hotel rooms with
standard hotel accommodation. There will be lots of opportunities for
interaction among the participants, both in and out of the classrooms,
during the meals, at the bar or at the swimming pool, in the fitness room,
in the spa and in the city. Long after-the-lecture discussions are one of
the major assets of this summer school. You will remember this summer
school for a long time.

Scientific program
——————
Sunday July 14: Opening ceremony with a keynote.
Monday July 15: Invited talk.

Starting on Monday 15, 2013:
12 courses spread over two morning slots and two afternoon slots. Per slot
there are three parallel courses of which one can be taken. The topics
of this year’s Summer School will be presented by the following world-class
experts.

Arvind, MIT, USA
Computer architecture: a constructive approach
Emery Berger, University of Massachusetts Amherst, USA
Software fault tolerance and correction
Henrik Berglund, Chalmers University of Technology, Sweden
Creating new business based on innovative technology
Luis Ceze, University of Washington, USA
Approximate computing from programming language to hardware
Samarjit Chakraborty, Technical University of Munich, Germany
Cyber-physical systems
Alex Garthwaite, CloudPhysics, USA
Memory hierarchies and their impact on virtualization
Jesus Labarta, Barcelona Supercomputing Center, Spain
Parallel programming with OmpSs
Hsien-Hsin Lee, Georgia Institute of Technology, USA
2.5D and 3D IC electronic systems
Sam Midkiff, Purdue University, USA
Automatic parallelization for computer architects
Onur Mutlu, Carnegie Mellon University, USA
Scalable many-core memory systems
Lesley Shannon, Simon Fraser University, Canada
Computing system design for reconfigurable platforms
Anand Sivasubramaniam, The Pennsylvania State University, USA
Datacenter power management

Wednesday afternoon: Poster session
Friday evening: Farewell dinner and party

Certificate
———–
All participants will receive a certificate of attendance with a
description of the courses taken. Some universities will accept
this certificate in their PhD program.

Poster Session
————–
The poster session on Wednesday afternoon will provide an ideal
opportunity for students to present their own work in progress
and get feedback from senior researchers and fellow students,
and can be the beginning of future collaboration. A booklet with
a 1 to 4 page abstract per poster will be distributed to all
summer school participants.

Admission
———
To stimulate maximum interaction between lecturers and
participants, the steering committee of the Summer School will
limit the attendance to about 200 participants. The application
form is on the website, and the deadline for application is
March 31, 2013.

Important dates
—————
March 31, 2013: deadline for admission application
April 15, 2013: notification of admission
May 15, 2013: deadline for payment
June 1, 2013: deadline for poster abstract

Registration
————
1000 euro, all inclusive:
– Transfer from Rome FCO airport to Fiuggi by bus on Sunday July 14, 2013.
– 6 nights in private room with bathroom.
– 6 breakfasts
– 5 three course lunches
– 5 three course dinners
– Farewell dinner on Friday evening
– 2 half-hour coffee breaks per day
– Registration for 4 top-quality courses + printed handouts
– Student kit
– Access to the poster session + book of abstracts
– Free Internet during the duration of the summer school
– Free access to the spa
– Free transfer from Fiuggi to Rome FCO airport or to downtown Rome on
Saturday July 20, 2013.

Steering Committee
——————
Koen De Bosschere, Ghent University, Belgium, Chair
Philippe Bonnot, Thales, France
Giuseppe Desoli, ST, Italy
Marc Duranton, CEA, France
Paul Heysters, Recore, The Netherlands
Manolis Katevenis, FORTH, Greece
Rainer Leupers, RWTH Aachen, Germany
Bilha Mendelson, IBM, Haifa
Mike O’Boyle, University of Edinburgh, UK
Emre Ozer, ARM, UK
Per Stenstrom, Chalmers, Sweden
Olivier Temam, INRIA, France
Adras Vajda, Ericsson, Sweden
Mateo Valero, UPC, Barcelona, Spain

Contact information
——————-
Koen De Bosschere
acaces@hipeac.net

Call for Papers: ISLPED 2013, Beijing, China

Submitted by Yuan Xie
http://www.islped.org
September 4 to September 6, 2013

Submitted by Yuan Xie
http://www.islped.org

INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN
Beijing, China
Sept. 4 – Sept. 6, 2013
http://www.islped.org

CALL FOR PAPERS

The International Symposium on Low Power Electronics and Design
(ISLPED) is the premier forum for presentation of recent advances in
all aspects of low power design and technologies, ranging from process
and circuit technologies, simulation and synthesis tools, to system
level design and optimization. Specific topics include, but are not
limited to, the following two main areas, each with three sub-areas:
1.1. Technologies and Digital Circuits : Emerging logic/memory
technologies and applications; Low power device and interconnect
design; Low power low leakage circuits; Memory circuits; 3-D
technologies; Cooling technologies; Battery technologies;
Variation-tolerant design; Temperature-aware and reliable design.
1.2. Logic and Microarchitecture Design: Processor core design; Cache
and register file design; Memory Architectures; Logic and RTL design;
Arithmetic and signal processing circuits; Encryption technologies;
Asynchronous design.
1.3. Analog, MEMS, Mixed Signal and Imaging Electronics: RF circuits;
Wireless; MEMS circuits; AD/DA Converters; I/O circuits; Mixed signal
circuits; Imaging circuits; Circuits to support emerging technologies
and platforms; DC-DC converters.
2.1. CAD & Design Tools: Energy estimation and optimization tools
that operate at the physical, circuit/gate level, RT level, behavioral
level, and algorithmic levels; Links to other metrics: variability,
reliability, temperature.
2.2. System Design and Methodologies: Microprocessor, DSP and
embedded systems design; FPGA and ASIC designs; System-level power-
and thermal-aware design; System-level reliability- and
variability-aware design; Systems for Emerging applications
2.3. Software Design and Optimization: Power- and thermal-aware
software design, scheduling, and management; Application-level
optimizations; Wireless and sensor networks; Software for emerging
applications.

Submissions on new topics: emerging technologies,
architectures/platforms, and applications are particularly encouraged.

IMPORTANT DATES:

Abstract registration: March 8, 2013;
Full paper: March 15, 2013.

Submission Instructions:

Submissions should be full-length papers of up to 6 pages
(double-column, IEEE Transactions/Conference format, available at
http://www.ieee.org/conferences_events/conferences/publishing/templates.html),
including all illustrations, tables, references and an abstract of no more than
100 words. Papers exceeding the six-page limit will not be reviewed. Submission
must be anonymous: papers identifying the authors and/or with explicit
references to their prior work will be automatically rejected. Electronic
submission in pdf format only via the web is required. More information on
electronic submission to ISLPED’13 can be found at http://www.islped.org.

Program Co-Chairs:
Yuan Xie, Penn State/AMD Research yuanxie@cse.psu.edu
Tanay Karnik, Intel Labs tanay.karnik@intel.com

General Co-Chairs:
Pai Chou UC Irvine/NTHU phchou@uci.edu
Ru Huang Peking University huangr@ime.pku.edu.cn