Call for Papers: Languages and Compilers for Parallel Computing

Submitted by Pablo Montesinos
September 25 to September 27, 2013

Submitted by Pablo Montesinos

LCPC 2013
The 26th International Workshop on
Languages and Compilers for Parallel Computing
Qualcomm Research Silicon Valley
September 25-27, 2013

The LCPC workshop is a forum for sharing research on all aspects of
concurrency: parallel languages, parallel programming models,
compilers, runtime systems, and tools. The scope of the workshop spans
foundational results and practical experience, early ideas and
interesting results. LCPC encourages work that goes outside the scope
of scientific computing and enables parallel programming in new areas,
such as mobile computing and data centers.

Specific topics include:
• Parallel programming models
• Parallel programming languages
• Compiling for parallelism and parallel compilers
• Static, dynamic, and adaptive optimization of parallel programs
• Formal analysis and verification of parallel programs
• Parallel runtime systems
• Parallel libraries and parallel application frameworks
• Performance analysis tools for concurrency
• Debugging tools for parallel programs
• Parallel algorithms and concurrent data structures
• Parallel applications
• Synchronization and concurrency control
• Software engineering for parallel programs
• Fault tolerance for parallel systems
• Parallel programming for accelerators

Papers should report on original research, and should include enough
background material to make them accessible to the entire LCPC
research community. Papers describing experiences should indicate how
they illustrate general principles; papers about parallel programming
foundations should indicate how they relate to practice.

All submissions must be made electronically through the conference web
site. LCPC 2013 papers are limited to 15 pages in the Springer LNCS
format. Papers must be submitted in PDF format and must be viewable by
Adobe Acrobat Reader. Papers that are not readable are automatically
rejected. Springer will publish the proceedings. Authors of accepted
papers and posters shall be required to sign the Springer copyright

Call for Papers: The 19th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2013)

Submitted by Jae W. Lee
December 15 to December 18, 2013

Submitted by Jae W. Lee

Call for Papers: ICPADS 2013

The 19th IEEE International Conference on Parallel and Distributed Systems
(ICPADS 2013)
Seoul, Korea
December 15-18, 2013

Established in 1992, ICPADS has been a major international forum in
the parallel and distributed systems area. ICPADS 2013 will be held in
Seoul, December 15-18, 2013. Seoul is a city of various culture and
variation. There is a wide range of modern and fusion culture of the
West and the East, along with cutting edge technology. The conference
venue, COEX convention center is located at Gangnam district that is
famous for a song, Gangnam Style, by Korean singer Psy. The conference
provides an international forum for scientists, engineers, and users
to exchange and share their experiences, ideas, and latest results on
all aspects of parallel and distributed systems. Contributions are
solicited in all areas of parallel and distributed systems research
and applications.

Topics of interest include, but are not limited to:

* Parallel and Distributed Applications and Algorithms
* Cloud OS, Middleware, Toolkits, and Applications
* Data Intensive Computing and Data Center Architectures
* Big Data Platforms
* Web-Based Computing and Service-Oriented Architectures
* Multi-core and Multithreaded Architectures
* Virtualization Techniques
* Resource Provision, Management, and Scheduling
* Security and Privacy
* Cluster and Grid Computing
* Power-Aware and Green Computing
* Internet of Things
* Peer-to-Peer Computing
* Wireless and Mobile Computing
* Ad Hoc and Sensor Networks
* Performance Modeling and Evaluation
* Communication and Networking Systems
* Dependable and Trustworthy Computing and Systems
* Real-Time and Multimedia Systems
* High Performance Computational Biology and Bioinformatics
* Cyber-Physical Systems
* Operating Systems Distributed and Parallel Systems
* Embedded systems


Papers must be unpublished and must not be submitted for publication
elsewhere. All papers will be reviewed by program committee members
and other experts active in the field to ensure high quality and
relevance to the conference. Submissions should include abstract, 5-10
keywords, and the e-mail address of the corresponding author and be in
PDF format. Each submission must not exceed 8 pages in the IEEE 8.5″ x
11″ two-column format with 10-12 point font, including tables and
figures. Each submission should be regarded as an undertaking that,
should the submission be accepted, at least one of the authors must
register the paper and attend the conference to present the work in
order that the accepted paper can be put into digital library. The
final version will be limited to 8 pages in IEEE proceeding format for
conference papers. Up to 2 extra pages may be purchased.


Papers accepted for ICPADS 2013 conference and workshops will be
published by the IEEE Computer Society Press. All accepted papers will
be included in IEEE Xplore and indexed by EI. Best Paper Award will be
presented at the conference. Three papers nominated for the best paper
will appear in the IEEE Transactions on Parallel and Distributed
Systems after another review process.


Deadline for paper submissions: June 17, 2013
Notification of paper acceptance: September 2, 2013
Deadline for author registration: September 30, 2013
Deadline of camera-ready version: October 7, 2013


Jong Kim, POSTECH, Korea

Jaejin Lee, Seoul National University, Korea
Samuel P. Midkiff, Purdue University, USA

Jangwoo Kim, POSTECH, Korea

John Kim, KAIST, Korea

Hyeonsang Eom, Seoul National University, Korea

Jae W. Lee, Sungkyunkwan University, Korea

Jung Ho Ahn, Seoul National University, Korea

**** SPONSORS ****

IEEE Technical Committee on Distributed Processing
IEEE Technical Committee on Parallel Processing

Call for Proprosals: ESSA 2013, Tutorial/Workshop on Energy-Secure System Architectures

Submitted by Augusto Vega
June 23, 2013

Submitted by Augusto Vega

The “power wall” has forced chip and system architects to design
with smaller margins between nominal and worst-case operating
points. Dynamic power and thermal management control loops have
already become an integral part of chip and system design. New
research papers in wearout and general reliability management have
recently been published. These new generation management protocols
have, however, opened up other sources of concern: e.g. control loop
stability and robustness of the management protocols. The potential
security holes exposed by the integrated control loops and system
safety issues triggered by potential violations of power or thermal
limits are other areas of concern. We seek to motivate the research
community into adopting a holistic approach to mitigating the power
wall and the concomitant reliability-security wall.

We have coined the term “Energy-Secure System Architectures” to
cover the range of research being pursued within industry and
academia in order to ensure robust and secure functionality, while
meeting the energy-related constraints of the emerging “green
computing” era. This segmented tutorial/workshop offering, composed
of lectures provided by experts in the areas of power/thermal
management, reliability and security, provides a comprehensive view
of the hardware and software aspects of Energy-Secure System
This is the third year of the offering of this workshop.

Call for Papers: WIVOSCA 2013, extended deadline

Submitted by Girish Venkatasubramanian
June 23, 2013

Submitted by Girish Venkatasubramanian
Seventh Annual
Workshop on the Interaction amongst
Virtualization, Operating Systems, and Computer Architecture
( WIVOSCA 2013 )

Held in Conjunction with the
40th Annual International Symposium on Computer Architecture
( ISCA – 40 )

The new, extended deadlines are
Abstract Submission: April 19, 2013
Paper Submission: April 26, 2013

Workshop Overview and Topics
Operating systems (OS) constitute a major software component
and are essential to any computing system. Commercial and
server workloads such as online transaction processing,
database, file/e-mail servers involve significant OS-level
activity. The interactions between OS and emerging
architectures (e.g. homogeneous and heterogeneous chip
multiprocessors, simultaneous multithreading systems) /
technology (e.g. hardware-assisted virtualization) are
projected to continuously increase. In addition, the use of a
wide variety of virtualization techniques, ranging from
application-level virtualization to full-system virtualization,
for providing application portability, managing power and
performance, providing QoS guarantees and to effectively use the
power of emerging architectures, has become prominent.

To optimize system
performance/power/reliability/security, it is important to
facilitate efficient interaction and cooperation amongst the
three constantly evolving components – OS, virtualization and
computer architecture.

This workshop focuses on characterizing, modeling, and
optimizing the interaction between OS and hardware in the
light of emerging architecture paradigms, workloads, and
computing technology. Topics of particular interest include,
but are not limited to:

* Architectural support for OS functionality and services
* Architectural support for virtual machines and hypervisors
* Hardware acceleration of OS and Virtualization services
* OS and Virtualization support for emerging computer architectures
* Implications of virtualization on OS design
* Effect of OS/Virtualization on emerging architectures
* System software-aware microarchitecture design
* Leveraging OS/Virtualization to optimize reliability/thermal/power
* Frameworks and tools for full-system simulation
* Characterization of OS/Virtualization activity in emerging workloads
* Performance, power, dependability, and security in OS/Virtualization
* OS/Virtualization -intensive benchmark suites
* Evaluation of the interaction/interference among OS/user
* Mitigation of OS and Virtualization related execution bottlenecks
* Architecture and Virtualization issues in data centers
* Architecture and Virtualization support for cloud computing

Furthermore, the workshop aims at providing a forum for
researchers, engineers, and students from academia and
industry to discuss their latest research in
virtualization, computer architecture and OS, to bring
their ideas and research problems to the attention of
others, and to obtain valuable and instant feedback from
fellow researchers.

Workshop Co-Organizers
Tao Li, University of Florida (
James Poe, Miami Dade College (
Girish Venkatasubramanian, Intel (

Important Dates
* Abstract Submission: April 19, 2013
* Paper Submission: April 26, 2013
* Author Notification: May 10, 2013
* Camera-ready Version: May 17, 2013

Please feel free to visit our website for more information
as well as links to previous WIOSCA workshops:

Call For Participation: NOCS-13, Extended Registration Deadline

Submitted by Carole Wu
April 21 to April 24, 2013

Submitted by Carole Wu

The 7th ACM/IEEE International Symposium on Networks-on-Chip

April 21-24, 2013
Tempe, Arizona, USA

The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip and chip-scale communication
technology, architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and applications
from inter-related research communities, including computer architecture,
networking, circuits and systems, embedded systems, and design automation.

Deadline for Advanced Registration is Extended to April 15, 2013.

Scientific program
Sunday April 21: Tutorials on (1) MILLIMETER (mm)-WAVE WIRELESS NoC AS

Monday–Wednesday April 22-24: Conference Technical Sessions
Featured Keynote Talks
Professor Luca Benini (University of Bologna)

Professor Radu Marculescu (Carnegie Mellon University)

Dr. Ravishankar Iyer (Intel)

Organizing Committee
General Co-Chairs:
Karam S. Chatha, Qualcomm Research, USA
Chita R. Das, Penn State University, USA
Finance Chair:
Sudeep Pasricha, Colorado State, USA
Registration Chair:
Mohammed Al Faruque, University of California- Irvine, USA
Publicity Chair:
Carole-Jean Wu, Arizona State University, USA
Program Co-Chairs:
John Bainbridge, Sonics Inc., USA
Natalie Enright Jerger, University of Toronto, CA
Publications Chair:
Paul Gratz, Texas A&M, USA
Tutorials/Demo Chair
Zhonghai Lu, KTH, Sweden
Industrial Chair
Umit Ogras, Intel, USA

Call for Papers: International Workshop on Algorithmic and Application Error Resilience (AER'13)

Submitted by Joseph Sloan
June 11, 2013

Submitted by Joseph Sloan
International Workshop on Algorithmic and Application Error Resilience
AER 2013

Held in conjunction with the
27th International Conference on Supercomputing (ICS 2013)

June 10th, 2013
Eugene, Oregon, USA

Circuit and logic variability from process scaling is leading to significant
reliability problems in future systems. The increasingly stringent power
constraints on system designs are making prior hardware and software-based
fault tolerance approaches impractical due to their heavy reliance on redundant,
worst-case, and conservative designs. Instead, algorithm-based approaches
provide applications the flexibility to adapt to inherent application error
tolerances and leverage the patterns of higher level abstractions.

The AER workshop, to be held as a full-day meeting at the ICS 2013 conference
in Eugene, Oregon, focuses on techniques, approaches, and principles for
algorithmic and application error resilience.

Topics of Interest:
* Algorithm design principles for error resilience
* Algorithmic error resilience implementations
* Techniques for massively parallel resilient applications
* Application fault detection and correction
* Hardware fault and application error models
* Application error resilience analysis and case studies
* Tools for analyzing application vulnerability to errors
* Optimizations for exploiting error resilience
* System design and automation

The AER workshop proceedings will be published electronically along with the
ICS conference proceedings via the ACM Digital Library. Submitted manuscripts
should be formatted using the ACM SIG proceedings alternate format
( The maximum
length is 8 pages. All papers must be in English. Please visit the workshop
website for further instructions and the submission link

Submission deadline: May 1st, 2013
Author notification: May 20th, 2013

Greg Bronevetsky, Lawrence Livermore National Laboratory, USA
Joseph Sloan, University of Illinois at Urbana-Champaign, USA

Rakesh Kumar, UIUC
Zizhong Chen, UC Riverside
John Daly, DoD
Pedro Diniz, University of Southern California
Jack Dongarra, University of Tennessee
Marc Casas-Guix, LLNL
Ganesh Gopalkrishnan, University of Utah
Nathan DeBardeleben, LANL
Mike Heroux, Sandia


Call for Participation: ISPASS 2013

Submitted by Niti Madan
April 21 to April 23, 2013

Submitted by Niti Madan
The IEEE International Symposium on Performance Analysis of Systems
and Software provides a forum for sharing advanced academic and
industrial research work focused on performance analysis in the
design of computer systems and software.

Preliminary Program is available (

ISPASS Registration is setup now(Early registration deadline: March 31, 2013)

ISPASS 2013 will be held at Hilton Garden Inn Austin
Downtown/Convention Center (Special rate cutoff date: March 31, 2013)

Student Travel Grant Information (Due date: March 31, 2013)

Call for Participation: ISPASS 2013 – Tutorial on Modeling Exascale Applications with SST/macro and Eiger

Submitted by Eric Anger
April 21, 2013 at 01:30

Submitted by Eric Anger
Tutorial on Modeling Exascale Applications with SST/macro and Eiger

Held in conjunction with the ISPASS 2013 Conference
Sunday, April 21 2013 1:30 PM to 5:30 PM.

This tutorial will present attendees with the techniques and methodologies to
leverage the SST/macro simulator and the Eiger performance modeling framework
for modeling large scale applications on upcoming supercomputer hardware.

In high performance computing (HPC), the importance of fast, accurate models
that can be used at large scales is increasing as we move towards the next
frontier of exascale. The SST/macro simulator provides HPC engineers the ability
to explore current and future machine architectures and programming models with
coarse grain on-line simulation that executes real application code to reproduce
communication behavior, a vital part of the hardware/software codesign process.
Instead of using cycle-accurate simulation of instructions executing on
processors, SST/macro relies on analytical models for computation performance.
The Eiger Performance Modeling Framework enables the generation of performance
models by applying statistical techniques from the field of machine learning on
empirically acquired performance data. While macro-scale simulation can provide
a reasonable overview of system wide phenomena, Eiger can leverage data acquired
from micro-scale sources to create models that form elements of large scale
simulations in SST/macro. The Eiger methodology constructs models from
aggregated data from micro-scale sources such as simulators, emulators, and
runtime instrumentation.

This presentation is geared towards domain experts and HPC hardware designers,
as well as students and researchers whose work requires exploration of
programming models, interaction between computation and communication, and
data-driven modeling techniques for large scale systems. These tools are geared
toward ease of use and rapid iteration, allowing area experts to generate
verbose performance models without requiring intricate knowledge of every facet
of the computing environment. This tutorial will require only a basic level of
programming skill.

More details about the tutorial can be found at the tutorial website.

Call for Papers: ASBD 2013

Submitted by Yi Zhang
June 23, 2013 at 09:00

Submitted by Yi Zhang
Third Workshop on Architectures and Systems for Big Data (ASBD 2013)

June 23, 2013 * Co-located with ISCA 2013 * Tel-Aviv, Israel
Preliminary results of interesting ideas and work-in-progress are welcome.

The term “Big Data” refers to the continuing massive expansion in the data
volume and diversity as well as the speed sand complexity of data processing.
The use of big data underpins critical activities in all sectors of our society.
Achieving the full transformative potential of big data in this increasingly
digital world requires both new data analysis algorithms and a new class of
systems to handle the dramatic data growth, the demand to integrate structured
and unstructured data analytics, and the increasing computing needs of massive-
scale analytics.

We are pleased to request papers for presentation at the upcoming Third Workshop
on Architectures and Systems for Big Data (ASBD 2013) held in conjunction with
ISCA-40. The workshop will provide a forum to exchange research ideas related to
all critical aspects of emerging analytics systems for big data, including
architectural support, benchmarks and metrics, data management software,
operating systems, and emerging challenges and opportunities. We hope to attract
a group of interdisciplinary researchers from academia, industry and government
research labs. To encourage discussion between participants, the workshop will
include significant time for interactions between the presenters and the
audience. We also plan to have a keynote speaker and/or panel session.

Topics of interest include but are not limited to:

-Processor,memory, and system architectures for data analysis
-Benchmarks, metrics, and workload characterization for big data
-Debugging and performance analysis tools for analytics and data-intensive
-Accelerators for analytics and data-intensive computing
-Implications of data analytics to mobile and embedded systems
-Energy efficiency and energy-efficient designs for analytics
-Availability, fault tolerance and recovery issues
-Scalable system and network designs for high concurrency or high bandwidth data
-Data management and analytics for vast amounts of unstructured data
-Evaluation tools, methodologies and workload synthesis
-OS, distributed systems and system management support
-MapReduce and other processing paradigms for analytics

We encourage both industry and academic researchers to submit their research.
Preliminary results of interesting ideas and work-in-progress are welcome.
Submissions that are likely to generate vigorous discussion will be favored!

Submission format: All papers should be submitted in PDF format, using 10 point
or larger font for text (8 points or larger for figures and tables), total
length not to exceed 6 pages.
Submission website:

Important Dates
Submission site open: March 15, 2013
Submission deadline: May 1, 2013
Author notification: May 18, 2013

Workshop Co-Organizers:
Jichuan Chang, HP Labs
Jian Li, IBM Research
Evan Speight, IBM Research

Program Committee
Lixin Zhang, ICT/CAS China
Wu Zhou, Huawei