Call for Papers: VEE 2014

Submitted by Dan Tsafrir
http://vee2014.org
March 1 to March 2, 2014

Submitted by Dan Tsafrir
http://vee2014.org
VEE’14: 10th ACM international conference on Virtual Execution Environments

http://vee2014.org

Co-located with ASPLOS 2014
March 1-2, 2014,
Salt Lake City, UT

SUBMISSION DEADLINE: Nov 14, 2013 (11:59pm, PST)

VEE’14, co-located with ASPLOS’14, invites authors to submit original
papers related to virtualization, encompassing all layers from the
microarchitectural level and throughout the entire software stack.
Topics of interest include: virtualization support for programs and
programmers; architecture support for virtualization; operating system
support for virtualization; compiler and programming language support
for virtualization; runtime system support for virtualization; virtual
I/O, storage, and networking; memory management; management
technologies for virtual environments; performance analysis and
debugging for virtual environments; and virtualization technologies
applied to specific problem domains such as cloud, HPC, realtime,
power management, and security.

General chair:
Martin Hirzel (IBM Research)

Program co-chairs:
Erez Petrank (Technion – Israel Institute of Technology)
Dan Tsafrir (Technion – Israel Institute of Technology)

Call for Papers: CGO 2014

Submitted by Vijay Janapa Reddi
http://cgo.org/cgo2014/
February 15 to February 19, 2014

Submitted by Vijay Janapa Reddi
http://cgo.org/cgo2014/
The International Symposium on Code Generation and Optimization (CGO) provides
a premier venue to bring together researchers and practitioners working at the
interface of hardware and software on a wide range of optimization and code
generation techniques and related issues. The conference spans the spectrum
from purely static to fully dynamic approaches, including techniques ranging
from pure software-based methods to architectural features and support.
Original contributions are solicited on, but not limited to, the following
topics:

== Code Generation and Optimization ==

* Efficient execution of dynamically typed and higher-level languages
* Optimization and code generation for emerging programming models, platforms
* Optimizations for energy efficiency
* Profile-guided, feedback-directed, and machine learning based optimization
* Compiler abstractions and intermediate representations

== Optimization for Parallelism ==

* Runtime systems for parallelism & heterogeneity
* Optimizations for heterogeneous or specialized parallel targets, e.g. GPUs
* Compiler-driven data distribution and synchronization
* Thread extraction

== Static and Dynamic Analysis ==

* Profiling and instrumentation for power, memory, throughput or latency
* Efficient profiling and instrumentation techniques
* Program characterization methods
* Profile-guided optimization
* Novel and efficient tools for power, performance analysis, debugging and
testing

== OS, Architecture and Runtime support ==

* Architectural support for improved profiling, optimization and code
generation
* Integrated system design (HW/OS/VM/SW)
* Memory management and garbage collection

== Security and Reliability ==

* Code analysis and transformations to address security or reliability
concerns

== Practical Experience ==

* Real dynamic optimization and compilation systems for general purpose,
embedded system and HPC platforms

== Applications of above in emerging technology areas ==

* Web programming environments, application runtimes, optimizations SOCs,
heterogeneous platforms hardware/software co-design, analysis and
optimization

== Important Dates

Abstract Submission: September 6, 2013
Paper Submission: September 13, 2013, 12am EST
Author Response Period: October 28-30, 2013
Notification to Authors: November 8, 2013

Call for Papers: IEEE Micro Special Series on Harsh Chips

Submitted by Augusto Vega
http://www.computer.org/portal/web/computingnow/micfp-series
January 17, 2014

Submitted by Augusto Vega
http://www.computer.org/portal/web/computingnow/micfp-series

Guest Editors: Augusto Vega, Alper Buyuktosunoglu, Pradip Bose (IBM)

Submissions due: Jan 17, 2014
Publication date: 2014 – Various

Embedded chips are deployed almost everywhere, from mobile phones to on-board
electronics in automobiles and planetary rovers. Different from conventional
microprocessor designs, the operation conditions of embedded processors are
severely constrained by the environment. For example, Unmanned Aerial Vehicle
(UAV) chips demand significant throughput for real-time processing despite
their tight power budget. To guarantee reliability in such harsh environments,
the design and operation of embedded processors should traverse different
layers, involving firmware, operating system, applications, as well as power
management units and communication interfaces. The goal of this IEEE Micro
series is to seek original papers on topics related to all critical aspects of
new-generation harsh environment-capable embedded processors. This series
will be published over several issues of IEEE Micro.

Areas of interest include, but are not limited to:

– Applications and design issues related to Harsh Chips, e.g.
* AEROSPACE: unmanned aerial vehicles (UAVs), planetary rovers and space
probes, satellites, avionic systems, etc.

* MEDICAL SUPPORT: lifesaving monitors, portable medical devices,
high-end imaging systems, etc.

* OIL AND GAS EXPLORATION & EXTRACTION: unmanned underwater vehicles (UUVs),
measurement while drilling (MWD), logging while drilling (LWD), etc.

* AERIAL SURVEILLANCE

* DISASTER search, rescue, and relief

* NOVEL APPLICATIONS for highly-reliable low-power embedded chips

– Architectural approaches for reliability assurance under low power budgets.
– Availability, soft-error tolerance and recovery issues.
– Highly-reliable cache/memory hierarchies.
– Massive heterogeneous processing capabilities.
– Power management techniques.
– Very-low power, reliable real-time processing.
– Specialized accelerator architectures and unique designs.
– Reusable and/or reconfigurable embedded designs.
– Packaging and cooling.
– Algorithm, application and software-based fault tolerance.
– Cross-stack hardware/software techniques for reliability assurance.

SUBMISSION PROCEDURE:
Log onto IEEE CS Manuscript Central (
https://mc.manuscriptcentral.com/micro-cs) and submit your manuscript.
Please direct questions to the IEEE Micro magazine assistant
(micro-ma@computer.org). For the manuscript submission, acceptable
file formats include Microsoft Word and PDF. Manuscripts should not
exceed 5,000 words including references, with each average-size figure
counting as 150 words toward this limit. Please include all figures
and tables, as well as a cover page with author contact information
(name, postal address, phone, fax, and mail address) and a 200-word
abstract. Submitted manuscripts must not have been previously
published or currently submitted for publication elsewhere, and all
manuscripts must be cleared for publication. All previously published
papers must have at least 30% new content compared to any conference
(or other) publication. Accepted articles will be edited for
structure, style, clarity, and readability. For more information,
please visit the IEEE Micro Author Center
(http://www2.computer.org/portal/web/peerreviewmagazines/acmicro)

QUESTIONS?
Contact Guest editor, Augusto Vega (ajvega@us.ibm.com)