Call for Papers: Workshop on Near-Data Processing

Submitted by Rajeev Balasubramonian
December 8, 2013 at 13:00

Submitted by Rajeev Balasubramonian
WoNDP: 1st Workshop on Near-Data Processing
in conjunction with MICRO-46
Sunday, December 8th, 2013
Davis, California


Computing in large-scale systems is shifting away from the traditional
compute-centric model successfully used for many decades into one that is much
more data-centric. This transition is driven by the evolving nature of what
computing comprises, no longer dominated by the execution of arithmetic and
logic calculations but instead becoming dominated by large data volume and the
cost of moving data to the locations where computations are performed. Data
movement impacts performance, power efficiency and reliability, three
fundamental components of a system. These trends are leading to changes in the
computing paradigm, in particular the notion of moving computation to the data
in a so-called Near-Data Processing approach, which seeks to perform
computations in the most appropriate location depending on where data resides
and what needs to be extracted from that data. Examples already exist in
systems that perform some computations closer to disk storage, leveraging the
data streaming coming from the disks, filtering the data so that only useful
items are transferred for processing in other parts of the system.
Conceptually, the same principle can be applied throughout a system, by placing
computing resources close to where data is located, and decomposing
applications so that they can leverage such a distributed and potentially
heterogeneous computing infrastructure. This workshop is intended to bring
together experts from academia and industry to share advances in the
development of Near-Data Processing systems principles, with emphasis on
large-scale systems. We expect this workshop to be the first one in an emerging
area of computer architecture. The workshop will consist of submitted papers
and invited talks.

Topics of interest include but are not limited to:

– Analysis of applications illustrating the potential for Near-Data Processing
– System and software architectures for Near-Data Processing
– Programming models for distributed and heterogeneous infrastructures,
driven by location of the data
– Processing/Memory/Storage architectures and microarchitectures for
Near-Data Processing
– Performance evaluation of Near-Data Processing systems and subsystems
– Power-efficiency and reliability analysis and evaluation of Near-Data

Call for Papers:
Two kinds of papers are invited:
– Technical papers (4-6 pages) with preliminary results.
– Position papers (3 pages max) on directions for research and development.

Please submit an electronic copy of your paper (in PDF) in two column
format with at least 10pt font.

The selected papers will be made available online. However, publication in
WoNDP does not preclude later publication at regular conferences or journals.

Important Dates:
Paper submissions due: Monday October 14, 2013
Notification: Monday November 4th, 2013
Final Paper Due: Monday December 2nd, 2013

Jaime Moreno, IBM TJ Watson Research Center
Ravi Nair, IBM TJ Watson Research Center
Rajeev Balasubramonian, University of Utah

Program Committee:
Rajeev Balasubramonian, University of Utah
Jichuan Chang, HP Labs
Jeff Draper, USC/ISI
David Lilja, University of Minnesota
Jaime Moreno, IBM TJ Watson Research Center
Richard Murphy, Micron
Ravi Nair, IBM TJ Watson Research Center

Call for Papers: SiPhotonics'2014

Submitted by Jose M. Garcia
January 21, 2014

Submitted by Jose M. Garcia
1st International Workshop on Exploiting Silicon Photonics for
energy-efficient heterogeneous parallel architectures (SiPhotonics’2014)
in Vienna, Austria, 21 January 2014

associated with the 9th HiPEAC conference on High Performance and
Embedded Architecture and Compilers (

Goal of the Workshop:

The main purpose of this workshop is to promote further research interests and
activities on Silicon Photonics and related topics in the perspective of its
adoption in future computer systems. In fact Silicon Photonics poses in itself
crucial challenges and interesting design tradeoffs for being deployed in
future computer systems effectively, also in integration with other
technologies. Furthermore, the unique features of photonics (e.g. extreme
low-latency, end-to-end transmission, high bandwidth density) have the
potential to constitute a discontinuity element able to modify the expected
shape of future computer systems from the design point of view and also from
the programmability and/or runtime management perspectives.

Summarizing, silicon photonics can bring innovations and benefits into current
and foreseeable computing systems directly, due to their intrinsic features,
but also indirectly enabling the evolution towards architectures, runtime and
resource management approaches that maximize the photonic raw technological
opportunities and lead to more efficient overall designs, otherwise impossible.

This workshop aims to increase the synergy from a complete range of
perspectives, from raw technology issues and solutions up to studies at the
overall system level of modern multi-/many-core systems, both from academic and
industrial researchers working in this area. We are interested in experimental,
systems-related, and work-in-progress papers in all aspects of the Silicon
Photonics technology at all levels of development.

Topics of interest:

The topics of interest include, but are not limited to:

– Integration of positive features of both electronic and photonic
interconnection technology.
– Low-level technological improvements and implications (e.g. integrated
lasers, modulation and detection technologies, microring resonators).
– Fabrication issues (e.g. precision) and new tools (e.g. design, place and
route, ecc) to easy the topological exploration.
– Emerging challenges and solutions for on-chip interconnections, cache
coherence protocols, runtime and OS scheduling, and programmability, for future
homogeneous/heterogeneous energy-aware CMPs
– Simulation, validation and verification
– Photonics in the memory hierarchy and I/O of computing systems
– QoS management and performance analysis
– Programming languages and compilers for thermal-, energy-, and power-aware
– Solving the requirements of multiple heterogeneous parallel applications.
– Interaction between photonic features and current computer design issues.
– Industrial practices and case studies

Submission guidelines:

Prospective authors should submit electronically a full paper in English in PDF
format. Submitted papers must represent original unpublished research that is
not currently under review for any other conference or journal.

All manuscripts will be reviewed and will be judged on correctness,
originality, technical strength, significance, quality of presentation, and
interest and relevance to the workshop attendees.

They should be formatted according to double-column ACM format pages, including
figures and references. Please use the following template when preparing your
exceeding 6 pages.

Submissions can be made through the submission web site at


Informal proceedings will be provided in an USB stick to all participants
including all material relevant to the conference and the related events.

To confirm the publication, at least one author of each accepted paper is
expected to register for the workshop and present the papers at
the workshop itself.

After the conference, authors of selected papers will be invited to submit
an extended version of their contribution for a special issue of the
journal “Concurrency and Computation: Practice and Experience” from Wiley,
scheduled to be published for June 2014.

Important dates:

Paper submission deadline: October 24, 2013
Notification of acceptance: November 30, 2013
Camera-ready paper due: December 13, 2013
Workshop: 21st Jan 2014


José M. García, University of Murcia, Spain.
Sandro Bartolini, University of Siena, Italy

Program committee:

Keren Bergman Columbia University
Giovanna Calo’ Politecnico di Bari
José M. Cecilia Catholic University of Murcia
Yawen Chen Otago University
Sylvain Collange INRIA/IRISA
Ricardo Fernández-Pascual University of Murcia
Paolo Grani University of Siena
Timothy Jones University of Cambridge
Wolfgang Karl Karlsruhe Institute of Technology (KIT)
Kostas Katrinis IBM
Sébastien Le Beux Lyon Institute of Nanotechnology (INL)
Oliver Mattes Karlsruhe Institute of Technology (KIT)
Gokhan Memik Northwestern University
Sergei Mingaleev VPIphotonics
Lasse Natvig Norwegian University of Science and Technology
Sudeep Pasricha Colorado State University
Luca Ramini University of Ferrara
Laurent Schares IBM TJ Watson


Prof. José M. García
Departamento de Ingeniería y Tecnología de Computadores
University of Murcia, Spain.
email: jmgarcia[at]
Tel.: +34 868 884819 Fax: +34 868 884151

Ing. Sandro Bartolini, PhD
Dipartimento di Ingegneria dell’Informazione e Scienze Matematiche
University of Siena, Italy
E-mail: bartolini[at]
Tel: +39 0577 234850 Fax: +39 0577 233609

Call for Papers: ISPASS 2014

Submitted by Byeong Kil Lee
March 23 to March 25, 2014

Submitted by Byeong Kil Lee
2014 IEEE International Symposium on Performance Analysis of Systems
and Software (ISPASS 2014)
March 23-25, 2014
Monterey, CA

Call for Papers:
The IEEE International Symposium on Performance Analysis of Systems
and Software provides a forum for sharing advanced academic and
industrial research work focused on performance analysis in the design
of computer systems and software. Authors are invited to submit
previously unpublished work for possible presentation at the
conference. Papers are solicited in fields that include the following:

* Performance and power evaluation methodologies
– Analytical modeling
– Statistical approaches
– Tracing and profiling tools
– Simulation techniques
– Hardware (e.g., FPGA) accelerated simulation
– Hardware performance counter architectures
– Power/Temperature/Variability/Reliability models for computer systems
– Micro-benchmark based hardware analysis techniques

* Performance and power analysis
– Metrics
– Bottleneck identification and analysis
– Visualization

* Power/Performance analysis of commercial and experimental hardware
– General-purpose microprocessors
– Multi-threaded, multi-core and many-core architectures
– Accelerators and graphics processing units
– Embedded and mobile systems
– Enterprise systems and data centers
– Supercomputers
– Computer networks

* Power/Performance analysis of emerging workloads and software
– Software written in managed languages
– Virtualization and consolidation workloads
– Internet-sector workloads
– Embedded, multimedia, games, telepresence
– Bioinformatics, life sciences, security, biometrics

* Application and system code tuning and optimization
* Confirmations or refutations of important prior results

In addition to research papers, we also welcome tool papers. The
conference is an ideal forum to publicize new tools to the
community. Tool papers will be judged primarily on their potentially
wide impact and use than on their research contribution. Tools in any
of the above fields of interest are eligible.

See for submission details.

Paper abstract submission: September 20, 2013
Full submission: September 27, 2013 (No extensions)
Rebuttal: November 27-29, 2013
Notification: December 11, 2013
Final paper due: January 31, 2014

Tor M. Aamodt, University of British Columbia

Benjamin C. Lee, Duke

Alaa Alameldeen, Intel
Abhishek Bhattacharjee, Rutgers
Ramon Canal, UPC Barcelona
Fred Chong, UC Santa Barbara
Bronis de Supinski, LLNL
Stijn Eyerman, Ghent
Andrew Hilton, Duke
Nuwan Jayasena, AMD
Xiaoyao Liang, Shanghai Jiaotong
Kevin Lim, HP
Albert Meixner, NVIDIA
Karthick Rajamani, IBM
Jose Renau, UC Santa Cruz
Ali Saidi, ARM
Karu Sankaralingam, Wisconsin
Arrvindh Shriraman, Simon Fraser
Ravi Soundararajan, VMWare
Lingjia Tang, Michigan
Devesh Tiwari, ORNL
Mohit Tiwari, Texas
David Wentzlaff, Princeton
Qiang Wu, Facebook
Hongzhong Zheng, Samsung

Byeong Kil Lee, Samsung

Nadeem Malik, IBM

Mike Ferdman, Stonybrook

Mark Hempstead, Drexel

Jason Mars, University of Michigan

Suzanne Rivoire, Sonoma State University

Carole-Jean Wu, Arizona State University

Call for Proposals: Creating Visions for Computing Research

Submitted by Mark Hill
December 1, 2013

Submitted by Mark Hill
As a CCC Council Member, I am forwarding CCC blog post by staffer Ann Drobnis:

The Computing Research Association’s Computing Community Consortium (CCC)
recently issued a call for proposals for workshops that will create exciting
visions and agendas for research at the frontiers of computing. “Proposals are
encouraged across the full spectrum of theoretical and applied work related to
the creation and application of information technologies as well as their use
in addressing important scientific or societal challenges,” according to the
solicitation. Past visioning activities funded by the CCC include Online
Education, Health IT, Spatial Computing, and Disaster Management. The
solicitation notes that many of the past visioning activities have had a
significant impact on the national research agenda. “Successful workshops will
articulate new research visions, galvanize community interest in those visions,
and mobilize support for those visions from the computing research community,
government leaders, and funding agencies,” the solicitation says. Budgets for
the proposals can range from $10,000 to $200,000, and the proposals should be
submitted by Dec. 1, 2013, with start dates no later than September 2014.

Call for Papers: Micro's Top Picks from the Computer Architecture Conferences 2014

Submitted by Mithuna Thottethodi—top-picks-2014
September 9, 2013 at 12:00

Submitted by Mithuna Thottethodi—top-picks-2014
Call for Papers – Special Issue of IEEE Micro:

Micro’s TOP PICKS from the Computer Architecture Conferences
May/June 2014

Deadlines: Abstract: October 11th, 2013, 4:59:59 pm EDT
Final Paper: October 18th, 2013, 4:59:59 pm EDT

Publication Date: May/June 2014

IEEE Micro will publish its yearly “Micro’s Top Picks from the Computer
Architecture Conferences” as its May / June 2014 issue. This issue collects
some of this year’s most significant research papers in computer
architecture based on novelty and long-term impact. Any computer
architecture paper (not a combination of papers) published in the top
conferences of 2013 (including MICRO-46) is eligible.

Top Picks will attempt to recognize those significant and insightful papers
that have the potential to influence the work of computer architects for
years to come. To simplify reviewing, there is a mandatory format for
submissions. The submission website allows uploading two documents per
submission. Please upload the following two documents separately as a single

1. A three-page, two-column document using 10-point type. The first two
pages should summarize the paper. The third page should argue for the
potential for the work to have long-term impact.

2. The final version of the original conference paper.

Submissions that do not follow this format will not be reviewed. The first
document should contain the names of the authors with a footnote that
contains the title of the original conference paper, with the full name of
the conference, page numbers, and date of publication. Authors will receive
further instructions upon acceptance.


INFO SITE:—top-picks-2014

Paper / Abstract Registration Deadline: October 11th, 2013 4:59:59 pm EDT
Final Submission Deadline: October 18th, 2013 4:59:59 pm EDT
Author notification: January 18th, 2014
Final papers due: February 14th, 2014
Publication date: May/June 2014

SPECIAL ISSUE GUEST EDITORS (and Co-Chairs of the Selection Committee):
Shubu Mukherjee, Cavium
Mithuna Thottethodi, Purdue University


Tor Aamodt, University of British Columbia
David Albonesi, Cornell University
David August, Princeton University
Rajiv Balasubramaniam, University of Utah
Pradip Bose, IBM
Doug Burger, Microsoft
John Carter, IBM
Joel Emer, Intel/MIT
Babak Falsafi, EPFL
Antonio Gonzalez, Intel
Sudhanva Gurumurthi, Univ of Virginia/AMD
Dan Jimenez, Texas A&M University
Toni Juan, Intel
David Kaeli, Northeastern University
Alvin Lebeck, Duke University
Hsien-Hsin Lee, Georgia Tech
Gabriel Loh, AMD
Margaret Martonosi, Princeton University
Kathryn McKinley, Microsoft/U-Texas, Austin
Milo Martin, University of Pennsylvania
Trevor Mudge, University of Michigan
Satish Narayanaswamy, Univ of Michigan
Eric Rotenberg, NCSU
Karu Sankaralingam, U-Wisconsin, Madison
Yanos Sazeides, University of Cyprus
Simha Sethumadhavan, Columbia Univ
Andre Seznec, INRIA
Dan Sorin, Duke University
Dean Tullsen, UCSD
T. N. Vijaykumar, Purdue University
Sudhakar Yalamanchili, Georgia Tech

Ahmed H. Abdel-Gawad, Tim Pritchett, Eric Villasenor (Purdue University)

Call for Papers: IEEE Micro Special Issue on Big Data

Submitted by Boris Grot

Submitted by Boris Grot
Call for Papers: IEEE Micro Special Issue on Big Data
Guest Editors: Babak Falsafi (EPFL) and Boris Grot (University of Edinburgh)

Submissions due: Jan 8, 2014
Author notification: March 5, 2014
Publication date: July­/Aug 2014

Big data is transforming our lives, but it is also placing an unprecedented
burden on our compute infrastructure. As data expansion rates outpace Moore’s
law and supply voltage scaling grinds to a halt, the IT industry is being
challenged in its ability to effectively store, process, and serve the growing
volumes of data. Delivering on the premise of big data in the post­-Dennard
era calls for specialization and tight integration across the system stack,
with the aim of maximizing energy efficiency, performance scalability,
resilience, and security. This IEEE Micro special issue seeks original papers
on a range of topics related to big data computing.

Areas of interest include, but are not limited to:
– Processor, memory systems, storage, and network architectures for big data
– Integrated systems for big data: blades, racks, and datacenters
– Custom accelerators for the big data domain
– Big data systems and workloads in the wild: case studies and bottleneck
– Software support for big data processing: programming languages, operating
systems, runtime environments
– Energy efficiency in big data systems through vertical integration,
specialization, and approximation
– Emerging compute, storage, and communication technologies for big data
– Architectural support for security in the context of big data

Submission procedure:

Log onto IEEE CS Manuscript Central
( and submit your manuscript. Please
direct questions to the IEEE Micro magazine assistant (
For the manuscript submission, acceptable file formats include Microsoft Word
and PDF. Manuscripts should not exceed 5,000 words including references, with
each average-­size figure counting as 150 words toward this limit. Please
include all figures and tables, as well as a cover page with author contact
information (name, address, phone, and e­mail) and a 200­-word abstract.
Submitted manuscripts must not have been previously published or currently
submitted for publication elsewhere, and all manuscripts must be cleared for
publication. All previously published papers must have at least 30% new content
compared to any conference (or other) publication. Accepted articles will be
edited for structure, style, clarity, and readability. For more information,
please visit the IEEE Micro Author Center

Call for Papers: IEEE D&T Special Issue on Silicon Nanophotonics for Future Multicore Architectures

Submitted by Yi Xu
December 1, 2013

Submitted by Yi Xu
The need for high performance and energy-efficient communication between
processing cores has never been more critical. Rapidly increasing application
complexity and limited computing power budgets have led to more and more
lightweight cores replacing fewer bulky cores in emerging processor chips. The
increase in core counts has put more pressure on the communication fabric which
must now support many more streams of higher bandwidth data transfers than ever
before. A direct consequence of this trend is that chip power and performance
are now dominated not by processor cores but by the need to transport data
between processors and to memory. Unfortunately, traditional electrical wires
that make up the backbone of communication fabrics on computing chips today are
facing unprecedented challenges in ultra-deep nanoscale CMOS fabrication
technologies. These wires are becoming slower, more power hungry, and less
reliable. We are thus at a critical juncture where the power, bandwidth, and
latency of communication must scale favorably to meet the needs of processing
chips in the near future. Silicon nanophotonics represents one of the more
promising solutions to overcome the challenge of worsening communication
performance with electrical wires. Such a solution also promises to pair well
with existing board-to-board and chip-to-chip photonics offerings that are
rapidly being adopted today.

IEEE Design and Test of Computers seeks original manuscripts for a special
issue on “Silicon Nanophotonics for Future Multicore Architectures”
scheduled for publication in Sep/Oct 2014. The topics of interest include,
but are not limited to:

– Emerging silicon nanophotonic devices, circuits, technological innovations,
and challenges
– Novel architectures that integrate silicon nanophotonics with compute,
storage, and wiring resources
– CAD tools for the design and analysis of silicon nanophotonic based systems
– Runtime techniques to adapt silicon nanophotonic components and related
chip resources
– Mechanisms to model, quantify, and cope with variations, uncertainty,
and failure for silicon nanophotonic components
– Impact of silicon nanophotonics on the spectrum of applications from
the embedded to the HPC domain.

Submission and review procedures:
Prospective authors should follow the submission guidelines for IEEE
Design & Test. All manuscripts must be submitted electronically to the IEEE
Manuscript Central Web site at Indicate
that you are submitting your article to the special issue on “Silicon
Nanophotonics for Future Multicore Architectures.” All papers will undergo
the standard IEEE Design & Test review process. Submitted manuscripts must
not have been previously published or currently submitted for publication
elsewhere. Manuscripts must not exceed 5,000 words, including figures
(with each average – size figure counting as 200 words) and a maximum of 12
references (30 for surveys). This amounts to about 4,000 words of text and
a maximum of five small to medium figures.

Important Dates:
– Submission Deadline: 1 December 2013
– Reviews Complete: 1 March 2014
– Revisions Due: 15 April 2014
– Notification of final acceptance: 1 June 2014
– Submission of final version: 1 July 2014
– Publication date: September/October 2014

Guest Editors:
– Sudeep Pasricha (Colorado State University,
– Yi Xu (AMD Research,,