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Call for Papers: IEEE D&T Special Issue on Silicon Nanophotonics for Future Multicore Architectures

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December 1, 2013

Submitted by Yi Xu
The need for high performance and energy-efficient communication between
processing cores has never been more critical. Rapidly increasing application
complexity and limited computing power budgets have led to more and more
lightweight cores replacing fewer bulky cores in emerging processor chips. The
increase in core counts has put more pressure on the communication fabric which
must now support many more streams of higher bandwidth data transfers than ever
before. A direct consequence of this trend is that chip power and performance
are now dominated not by processor cores but by the need to transport data
between processors and to memory. Unfortunately, traditional electrical wires
that make up the backbone of communication fabrics on computing chips today are
facing unprecedented challenges in ultra-deep nanoscale CMOS fabrication
technologies. These wires are becoming slower, more power hungry, and less
reliable. We are thus at a critical juncture where the power, bandwidth, and
latency of communication must scale favorably to meet the needs of processing
chips in the near future. Silicon nanophotonics represents one of the more
promising solutions to overcome the challenge of worsening communication
performance with electrical wires. Such a solution also promises to pair well
with existing board-to-board and chip-to-chip photonics offerings that are
rapidly being adopted today.

IEEE Design and Test of Computers seeks original manuscripts for a special
issue on “Silicon Nanophotonics for Future Multicore Architectures”
scheduled for publication in Sep/Oct 2014. The topics of interest include,
but are not limited to:

- Emerging silicon nanophotonic devices, circuits, technological innovations,
and challenges
- Novel architectures that integrate silicon nanophotonics with compute,
storage, and wiring resources
- CAD tools for the design and analysis of silicon nanophotonic based systems
- Runtime techniques to adapt silicon nanophotonic components and related
chip resources
- Mechanisms to model, quantify, and cope with variations, uncertainty,
and failure for silicon nanophotonic components
- Impact of silicon nanophotonics on the spectrum of applications from
the embedded to the HPC domain.

Submission and review procedures:
Prospective authors should follow the submission guidelines for IEEE
Design & Test. All manuscripts must be submitted electronically to the IEEE
Manuscript Central Web site at http://www.manuscriptcentral.com/dandt. Indicate
that you are submitting your article to the special issue on “Silicon
Nanophotonics for Future Multicore Architectures.” All papers will undergo
the standard IEEE Design & Test review process. Submitted manuscripts must
not have been previously published or currently submitted for publication
elsewhere. Manuscripts must not exceed 5,000 words, including figures
(with each average – size figure counting as 200 words) and a maximum of 12
references (30 for surveys). This amounts to about 4,000 words of text and
a maximum of five small to medium figures.

Important Dates:
- Submission Deadline: 1 December 2013
- Reviews Complete: 1 March 2014
- Revisions Due: 15 April 2014
- Notification of final acceptance: 1 June 2014
- Submission of final version: 1 July 2014
- Publication date: September/October 2014

Guest Editors:
- Sudeep Pasricha (Colorado State University, sudeep@colostate.edu)
- Yi Xu (AMD Research, yi1.xu@amd.com, yi.xu.2000@gmail.com)