Submitted by Jose M. Garcia
1st International Workshop on Exploiting Silicon Photonics for
energy-efficient heterogeneous parallel architectures (SiPhotonics’2014)
in Vienna, Austria, 21 January 2014
associated with the 9th HiPEAC conference on High Performance and
Embedded Architecture and Compilers (http://www.hipeac.net/conference/vienna).
Goal of the Workshop:
The main purpose of this workshop is to promote further research interests and
activities on Silicon Photonics and related topics in the perspective of its
adoption in future computer systems. In fact Silicon Photonics poses in itself
crucial challenges and interesting design tradeoffs for being deployed in
future computer systems effectively, also in integration with other
technologies. Furthermore, the unique features of photonics (e.g. extreme
low-latency, end-to-end transmission, high bandwidth density) have the
potential to constitute a discontinuity element able to modify the expected
shape of future computer systems from the design point of view and also from
the programmability and/or runtime management perspectives.
Summarizing, silicon photonics can bring innovations and benefits into current
and foreseeable computing systems directly, due to their intrinsic features,
but also indirectly enabling the evolution towards architectures, runtime and
resource management approaches that maximize the photonic raw technological
opportunities and lead to more efficient overall designs, otherwise impossible.
This workshop aims to increase the synergy from a complete range of
perspectives, from raw technology issues and solutions up to studies at the
overall system level of modern multi-/many-core systems, both from academic and
industrial researchers working in this area. We are interested in experimental,
systems-related, and work-in-progress papers in all aspects of the Silicon
Photonics technology at all levels of development.
Topics of interest:
The topics of interest include, but are not limited to:
- Integration of positive features of both electronic and photonic
- Low-level technological improvements and implications (e.g. integrated
lasers, modulation and detection technologies, microring resonators).
- Fabrication issues (e.g. precision) and new tools (e.g. design, place and
route, ecc) to easy the topological exploration.
- Emerging challenges and solutions for on-chip interconnections, cache
coherence protocols, runtime and OS scheduling, and programmability, for future
homogeneous/heterogeneous energy-aware CMPs
- Simulation, validation and verification
- Photonics in the memory hierarchy and I/O of computing systems
- QoS management and performance analysis
- Programming languages and compilers for thermal-, energy-, and power-aware
- Solving the requirements of multiple heterogeneous parallel applications.
- Interaction between photonic features and current computer design issues.
- Industrial practices and case studies
Prospective authors should submit electronically a full paper in English in PDF
format. Submitted papers must represent original unpublished research that is
not currently under review for any other conference or journal.
All manuscripts will be reviewed and will be judged on correctness,
originality, technical strength, significance, quality of presentation, and
interest and relevance to the workshop attendees.
They should be formatted according to double-column ACM format pages, including
figures and references. Please use the following template when preparing your
exceeding 6 pages.
Submissions can be made through the submission web site at
Informal proceedings will be provided in an USB stick to all participants
including all material relevant to the conference and the related events.
To confirm the publication, at least one author of each accepted paper is
expected to register for the workshop and present the papers at
the workshop itself.
After the conference, authors of selected papers will be invited to submit
an extended version of their contribution for a special issue of the
journal “Concurrency and Computation: Practice and Experience” from Wiley,
scheduled to be published for June 2014.
Paper submission deadline: October 24, 2013
Notification of acceptance: November 30, 2013
Camera-ready paper due: December 13, 2013
Workshop: 21st Jan 2014
José M. García, University of Murcia, Spain.
Sandro Bartolini, University of Siena, Italy
Keren Bergman Columbia University
Giovanna Calo’ Politecnico di Bari
José M. Cecilia Catholic University of Murcia
Yawen Chen Otago University
Sylvain Collange INRIA/IRISA
Ricardo Fernández-Pascual University of Murcia
Paolo Grani University of Siena
Timothy Jones University of Cambridge
Wolfgang Karl Karlsruhe Institute of Technology (KIT)
Kostas Katrinis IBM
Sébastien Le Beux Lyon Institute of Nanotechnology (INL)
Oliver Mattes Karlsruhe Institute of Technology (KIT)
Gokhan Memik Northwestern University
Sergei Mingaleev VPIphotonics
Lasse Natvig Norwegian University of Science and Technology
Sudeep Pasricha Colorado State University
Luca Ramini University of Ferrara
Laurent Schares IBM TJ Watson
Prof. José M. García
Departamento de Ingeniería y Tecnología de Computadores
University of Murcia, Spain.
Tel.: +34 868 884819 Fax: +34 868 884151
Ing. Sandro Bartolini, PhD
Dipartimento di Ingegneria dell’Informazione e Scienze Matematiche
University of Siena, Italy
Tel: +39 0577 234850 Fax: +39 0577 233609