Call for Papers: MULTIPROG7 workshop at Hipeac 2014

Submitted by Osman Unsal
January 22, 2014

Submitted by Osman Unsal
Seventh Workshop on Programmability Issues for Heterogeneous Multicores
Submission Deadline: 18 October 2013

Held in conjunction with the 9th International Conference on High-Performance
and Embedded Architectures and Compilers (HiPEAC)
Vienna, Austria, January 22, 2014
Workshop website:

Goal of the Workshop
Computer manufacturers have already embarked on the multi-core roadmap,
promising to add more and more cores/hardware threads on a chip:
many-cores are on the horizon. This shift to an increasing number of
cores and heterogeneous architectures has placed new burdens on the
programming community. Until now, software has been developed with a single
processor in mind and it needs to be parallelized and optimized for
accelerators such as GPUs to take advantage of the new breed of
multi-/many-core computers. As a result, progress in how to easily
harness the computing power of multi-core architectures is in great

The seventh edition of the MULTIPROG workshop aims to bring together,
and cause fruitful interaction between, researchers interested in
programming models and their implementation and in computer architecture,
with special emphases on heterogeneous architectures. A wide spectrum
of issues are central themes for this workshop such as what the future
programming models should look like to accelerate software productivity,
how compilers, run-times and architectures should support these new
programming models, innovative algorithm and data structure development,
and heterogeneous embedded, accelerated systems.

MULTIPROG is intended for quick publication of early results,
work-in-progress, etc, and is not intended to prevent later publication
of extended papers. We will prioritize papers addressing cross-cutting
issues and that provide thought-provoking insights into the main themes.
Informal proceedings with accepted papers will be made available at the

Topics of interest
Papers are sought on topics including, but not limited to:
* Multi-core architectures
o Architectural support for compilers/programming models
o Processor (core) architecture and accelerators, in particular GPUs
o Memory system architecture
o Performance, power, temperature, and reliability issues
* Heterogeneous computing
o Algorithms and data structures for heterogeneous systems
o Applications for heterogeneous computing and real-time graphics
* Programming models for multi-core architectures
o Language extensions
o Run-time systems
o Compiler optimizations and techniques
o Tools for discovering and understanding parallelism
* Benchmarking of multi-/many-core architectures
o Tools for understanding performance and debugging
o Case studies and performance evaluation

Eduard Ayguade UPC and BSC Spain (eduard[at]
Benedict R. Gaster Qualcomm USA (bgaster[at]
Lee Howes Qualcomm USA (lhowes[at]
Per Stenstrom Chalmers University of Technology Sweden (pers[at]
Osman S. Unsal BSC-Microsoft Research Centre Spain (osman.unsal[at]

Important dates
Submission: October 18, 2013
Notification: November 26, 2013

Paper submission
Submitted papers should use the LNCS format and should be 12 pages
maximum. Manuscript preparation guidelines can be found at the LNCS
web site. Please check that (i) pages are numbered, and (ii) graphs
etc. remain legible when printed in black and white.
Submit your paper here:

Program committee
Mats Brorsson KTH Sweden
Pascal Felber U. of Neuchatel Switzerland
Roberto Giorgi U. of Siena Italy
Hakan Grahn Blekinge Institute of Technology Sweden
Tim Harris Oracle UK
Paul Kelly Imperial College of London UK
Mikel Lujan U. of Manchester UK
Tim Mattson Intel Research USA
Simon McIntosh-Smith U. of Bristol UK
Avi Mendelson Technion Israel
Dimitris Nikolopoulos Queens U. UK
Andy Pimentel U. of Amsterdam Netherlands
Oscar Plata U. of Malaga Spain
Yanos Sazeides U. of Cyprus Cyprus
David Black-Schaffer Uppsala U. Sweden
Nir Shavit MIT USA
Dongping Zhang AMD USA