Call for Papers: HARSH 2014

Submitted by Augusto Vega
February 15 to February 16, 2014

Submitted by Augusto Vega
HARSH-2014 will provide a unique forum for the discussion of the
challenges in the design and operation of harsh environment-capable
embedded processors.

Nowadays, embedded chips are deployed almost everywhere, from mobile
phones to on-board electronics in automobiles and satellites.
Different from conventional microprocessor designs, the operation
conditions of embedded processors are severely constrained by the
environment. For example, in aerospace applications, the computer
installed on Mars rover “Curiosity” has to tolerate extreme space
radiation and temperatures, operate at low power, and provide enough
computation capability to perform mission-critical tasks. Embedded
designs for Unmanned Aerial Vehicles (UAVs) also encounter extremely
challenging design requirements. Despite their tight power budget,
UAV chips demand significant throughput for real-time high-speed
image processing. In the context of oil and gas exploration and
extraction, embedded processors can be found even on the drill string
itself, to process sensor inputs in real time while withstanding high
temperatures and humidity levels.

To guarantee reliability across these drastically diverse
environments, the design and operation of embedded processors should
not be solely confined to the chip but traverse different layers in
the computing system, involving firmware, operating system,
applications, as well as power management units and communication
interfaces. The goal of HARSH-2014 is to facilitate the exchange of
the latest ideas, insights, and knowledge related to all critical
aspects of new-generation harsh environment-capable embedded
processors, including micro-architectural approaches, cross-stack
hardware/software techniques, and emerging challenges and
opportunities. We hope to attract a group of interdisciplinary
researchers from academia, industry, and government research labs.

In addition to the presentation of selected paper submissions,
keynote speakers will be invited to kick-off the workshop sessions
and a “Best Paper” award will be presented at the conclusion of the
workshop. To encourage discussion between participants, HARSH-2014
will organize dedicated programs for discussion between presenters
and the audience.


Topics of interest include but are not limited to:

(1) Architecture design and implementation for highly-reliable
power-efficient embedded processors:
– Architectural approaches for reliability assurance under
very-low power budgets.
– Availability, soft-error tolerance and recovery issues.
– Highly-reliable cache/memory hierarchies.
– Massive heterogeneous processing capabilities.
– Power management techniques.
– Very-low power, reliable real-time processing.
– Specialized accelerator architectures and unique designs.
– Reusable and/or reconfigurable embedded designs.
– Packaging and cooling.

(2) Cross-stack hardware/software techniques:
– Cross-stack approaches for reliability assurance under
very-low power budgets.
– Reliability- and power-aware operating systems, compilers,
workload managers, firmware and other software.
– Workload analysis and optimization for reliable low-power
embedded systems.

(3) Applications:
– Aerospace: unmanned aerial vehicles (UAVs), planetary rovers
and space probes, satellites, avionic systems, etc.
– Medical support: lifesaving monitors, portable medical devices,
high-end imaging systems, etc.
– Oil and gas exploration and extraction: unmanned underwater
vehicles (UUVs), measurement while drilling (MWD), logging
while drilling (LWD), etc.
– Aerial surveillance.
– Disaster search, rescue, and relief.
– Novel applications for highly-reliable low-power embedded


Papers reporting original research results pertaining to the above
and related topics are solicited. Full paper manuscripts must be in
English of up to 6 pages (using the IEEE two-column format). The
online submission site is EasyChair. If web submission is not
possible, please contact the program co-chairs for alternate

To submit regular papers to the workshop, please visit:

If you have questions regarding submission, please contact us:

Important Dates:

– Dec 23, 2013: Submission deadline
– Jan 17, 2014: Notification of acceptance
– Jan 31, 2014: Final paper submission
– Feb 16, 2014: Workshop date


– Augusto Vega (IBM)
– Xuan Zhang (Harvard University)
– David Brooks (Harvard University)
– Alper Buyuktosunoglu (IBM)
– Pradip Bose (IBM)

Call for Participation: IEEE ICPADS 2013

Submitted by Jae W. Lee
December 15 to December 18, 2013

Submitted by Jae W. Lee
The 19th IEEE International Conference on Parallel and Distributed Systems
(ICPADS 2013)
Seoul, Korea
December 15-18, 2013

Established in 1992, ICPADS has been a major international forum
in the parallel and distributed systems area. ICPADS 2013 will be
held in Seoul, December 15-18, 2013. Seoul is a city of various
culture and variation. There is a wide range of modern and fusion
culture of the West and the East, along with cutting edge
technology. The conference venue, COEX convention center is
located at Gangnam district that is famous for a song, Gangnam
Style, by Korean singer Psy. The conference provides an
international forum for scientists, engineers, and users to
exchange and share their experiences, ideas, and latest results
on all aspects of parallel and distributed systems.


Early registration deadline: November 15, 2013


December 15: Workshop and Tutorials

December 16-18: Main Conference


Kang G. Shin, University of Michigan
Joseph Curley, Intel


Conference Program:
Conference Registration:
Venue and Hotel Reservation:


IEEE Technical Committee on Distributed Processing
IEEE Technical Committee on Parallel Processing
Korean Institute of Information Scientists and Engineers (KIISE)


Platinum: Intel
Gold: HP
Silver: Samsung and Nvidia
Bronze: POSTECH CMEST and ManyCoreSoft

Call for Papers: IEEE JETCAS Special Issue on "Robust and Energy-Secure Systems"

Submitted by Augusto Vega
January 31, 2014

Submitted by Augusto Vega
Corresponding Guest Editor: Augusto Vega (IBM Research)
Other Guest Editors: Simha Sethumadhavan (Columbia University)
Subhasish Mitra (Stanford University)

Submissions due: Jan 31, 2014
Publication date: June 2014

The “power wall” has forced chip designers and system architects to
integrate novel power and thermal management control loops into
systems to enable smaller margins between nominal and worst-case
operating points. These management protocols create new challenges for
chip and system designers. Examples include control loop stability,
robustness of the management protocols, potential security
vulnerabilities in integrated control loops and management firmware,
and system security and safety challenges triggered by violations of
energy, reliability, power or thermal limits.

We have coined the term “robust and energy-secure systems” to cover
the broad range of research being pursued within industry and academia
to ensure reliable and secure operation of systems with integrated
power, reliability, and thermal management control loops.

Through this JETCAS special issue, we seek novel research papers on
holistic approaches to designing emerging on-chip control systems.
We solicit papers in the areas of energy/power/thermal management,
reliability, and security to provide a comprehensive view of the
hardware and software aspects of Robust and Energy-Secure Systems.

Areas of interest include, but are not limited to:

o Holistic cross-layer energy, power, thermal and reliability
management solutions
o Robustness of system energy/power/thermal/reliability management:
verification, validation and design for verification
o Reliability and security holes exposed by energy/power/thermal
management protocols
o Guarded, two-level management protocols for safety, security and
low verification complexity
o Architectural implications of and system software support for
robust energy/power/thermal management
o Reliability and security issues in emerging low-power memory
o Power- and thermal-based side-channel attacks

Prospective authors should submit PDF versions of their papers
following the instructions provided on the JETCAS web-site: Submitted manuscripts should
not have been previously published nor should they be currently under
consideration for publication elsewhere. Manuscripts will undergo a
peer review process according to the standard IEEE publication policy.

Important Dates

o Paper submission: January 31, 2014
o First round of reviews completed: February 21, 2014
o Revised manuscripts due: March 4, 2014
o Notification of acceptance: March 25, 2014
o Final manuscripts due date: April 1, 2014

Supporting Committee

o Dimitris Gizopoulos, University of Athens (Greece)
o Ramon Canal, UPC Barcelona (Spain)
o Hiroshi Nakamura, University of Tokyo (Japan)
o Pradip Bose, IBM Research (United States)
o Alper Buyuktosunoglu, IBM Research (United States)
o Hiroshi Sasaki, Kyushu University (Japan)


Contact Guest Editor: Augusto Vega (

Call for Papers: IEEE Micro Special Issue on Big Data

Submitted by Boris Grot
January 8, 2014

Submitted by Boris Grot
Call for Papers: IEEE Micro Special Issue on Big Data
Guest Editors: Babak Falsafi (EPFL) and Boris Grot (University of Edinburgh)

Submissions due: Jan 8, 2014
Author notification: March 5, 2014
Publication date: July­/Aug 2014

Big data is transforming our lives, but it is also placing an unprecedented
burden on our compute infrastructure. As data expansion rates outpace Moore’s
law and supply voltage scaling grinds to a halt, the IT industry is being
challenged in its ability to effectively store, process, and serve the growing
volumes of data. Delivering on the premise of big data in the post­-Dennard
era calls for specialization and tight integration across the system stack,
with the aim of maximizing energy efficiency, performance scalability,
resilience, and security. This IEEE Micro special issue seeks original papers
on a range of topics related to big data computing.

Areas of interest include, but are not limited to:
– Processor, memory systems, storage, and network architectures for big data
– Integrated systems for big data: blades, racks, and datacenters
– Custom accelerators for the big data domain
– Big data systems and workloads in the wild: case studies and bottleneck
– Software support for big data processing: programming languages, operating
systems, runtime environments
– Energy efficiency in big data systems through vertical integration,
specialization, and approximation
– Emerging compute, storage, and communication technologies for big data
– Architectural support for security in the context of big data

Submission procedure:

Log onto IEEE CS Manuscript Central
( and submit your manuscript. Please
direct questions to the IEEE Micro magazine assistant (
For the manuscript submission, acceptable file formats include Microsoft Word
and PDF. Manuscripts should not exceed 5,000 words including references, with
each average-­size figure counting as 150 words toward this limit. Please
include all figures and tables, as well as a cover page with author contact
information (name, address, phone, and e­mail) and a 200­-word abstract.
Submitted manuscripts must not have been previously published or currently
submitted for publication elsewhere, and all manuscripts must be cleared for
publication. All previously published papers must have at least 30% new content
compared to any conference (or other) publication. Accepted articles will be
edited for structure, style, clarity, and readability. For more information,
please visit the IEEE Micro Author Center

Call for Abstracts: Non-Volatile Memories Workshop 2014

Submitted by Steven Swanson
March 9 to March 11, 2014

Submitted by Steven Swanson
The 5th Annual Non-Volatile Memories Workshop (NVMW 2014) provides a unique
showcase for outstanding research on solid state, non-volatile memories. It
features a “vertically integrated” program that includes presentations on
devices, data encoding, systems architecture, and applications related to these
exciting new data storage technologies. Last year’s workshop (NVMW 2013)
included 32 speakers from top universities, industrial research labs, and
device manufacturers and attracted nearly 200 attendees. (The website for NVMW
2013 can be found at NVMW 2013 will build on this

The organizing committee is soliciting presentations on any topic related to
non-volatile, solid state memories, including:

• Advances in memory devices or memory cell design.

• Characterization of commercial or experimental memory devices.

• Error correction and data encoding schemes for non-volatile memories.

• Advances in non-volatile memory-based storage systems.

• Operating system and file system designs for non-volatile memories.

• Security and reliability of solid-state storage systems.

• Applications of non-volatile memories to scientific, “big data”, and
high-performance workloads.

• Implications of non-volatile memories for applications such as
databases and NoSQL systems.

The goal is to facilitate the exchange of the latest ideas, insights, and
knowledge that can propel future progress. To that end, presentations may
include new results or work that has already been published during the 18
months prior to the submission deadline. In lieu of printed proceedings, we
will post the slides and extended abstracts of the presentations
online. Presentation of new work at the workshop does not preclude future

Workshop submissions should be in the form of a 2-page presentation
abstract. Submissions will be evaluated on the basis of impact, novelty, and
general interest.

The submission deadline is November 25, 2013, with notification of acceptance
by January 31, 2014.

Further details on abstract submission, technical program, tutorials, travel,
social program, and travel grant will be provided at

Call for Participation: MICRO 2013

Submitted by Ajay Joshi
December 7 to December 11, 2013

Submitted by Ajay Joshi
The 46th Annual IEEE/ACM International Symposium on
Microarchitecture, 2013

December 7 – 11, 2013

The International Symposium on Microarchitecture (MICRO) is the premier forum
for the presentation and discussion of new ideas in microarchitecture,
compilers, hardware/software interfaces, and design of advanced computing and
communication systems. The goal of MICRO is to bring together researchers in the
fields of microarchitecture, compilers, and systems for technical exchange. The
MICRO community has enjoyed having close interaction between academic
researchers and industrial designers — we aim to continue and strengthen this
longstanding tradition at the 46th MICRO in Davis.

Conference Program, Registration Information and Hotel/Travel Information can
be found at

Early registration ends on November 8th, 2013


General Chair:
Matthew Farrens, UC Davis

Program Chair:
Christos Kozyrakis, Stanford University

Program Committee:
Ali Adl-Tabatabai, Google
Jung Ho Ahn, SNU
Valeria Bertacco, University of Michigan
Pradip Bose, IBM Research
David Brooks, Harvard
John Carter, IBM Research
Jichuan Chang, HP
Jason Cong, UCLA
Tom Conte, Georgia Tech
John Davis, Microsoft Research
Greg Diamos, NVIDIA
Lieven Eeckhout, Ghent University
Mattan Erez, University of Texas at Austin
Antonio Gonzalez, Intel & UPC
Boris Grot, EPFL
Ron Ho, Oracle Labs
James Hoe, CMU
Chris Hughes, Intel
Hillery Hunter, IBM Research
Wen-Mei Hwu, University of Illinois at Urbana-Champaign
Engin Ipek, University of Rochester
Ravi Iyer, Intel
Nuwan Jayasena, AMD Research
Stefanos Kaxiras, Uppsala University
Hyesoon Kim, Georgia Tech
Benjamin Lee, Duke
Scott Mahlke, University of Michigan
Jason Mars, UCSD
Kathryn McKinley, Microsoft Research
Andreas Moshovos, University of Toronto
Satish Narayanasamy, University of Michigan
Milos Prvulovic, Georgia Tech
Vijay Janapa Reddi, University of Texas at Austin
Daniel Sanchez, MIT
Karu Sankaralingam, University of Wisconsin
Yannos Sazeides, University of Cyprus
Simha Sethumadhavan, Columbia
Steve Swanson, UCSD
Olivier Temam, INRIA
Kees Vissers, Xilinx

Tutorials and Workshops Chair:
Mark Oskin, University of Washington

Finance Chair:
Venkatesh Akella, UC Davis

Publicity Chair
Ajay Joshi, Boston University

Local Arrangements Chair
Christopher Nitta, UC Davis

Web and Submissions Chairs:
Christina Delimitrou, Stanford University
David Lo, Stanford University

Steering Committee
Richard Belgard (Chair), Consultant
David Albonesi, Cornell
Tom Conte, Georgia Tech
Kemal Ebcioglu, Global Supercomp.
Paolo Faraboschi, HP Labs
Wen-mei Hwu, University of Illinois
Scott Mahlke, University of Michigan
Bill Mangione-Smith, Consultant
Margaret Martonosi, Princeton
Yale Patt, University of Texas at Austin
Milos Prvulovic, Georgia Tech

Call for Papers: ISCA 2014

Submitted by Natalie Enright Jerger
June 14 to June 18, 2014

Submitted by Natalie Enright Jerger
The International Symposium on Computer Architecture is the premier forum
for new ideas and experimental results in computer architecture. The conference
specifically seeks particularly forward-looking and novel submissions. Papers
are solicited on a broad range of topics, including (but not limited to):

Processor, memory, and storage systems architecture
Parallel and multicore systems
Data-center scale computing
Architectures for handheld and mobile devices
Application-specific, reconfigurable, or embedded architectures
Accelerator-based architectures
Architectures for security and virtualization
Power and energy efficient architectures
Interconnection networks
Instruction, thread, and data-level parallelism
Dependable architectures
Architectural support for programming productivity
Network processor and router architectures
Architectures for emerging technologies and applications
Effect of circuits and technology on architecture
Architecture modeling and simulation methodology
Performance evaluation and measurement of real systems

Abstract Deadline: November 14, 2013, 11:59PM EST
Final Paper Deadline: November 21, 2013, 11:59PM EST
Rebuttal Period: February 11-14, 2014
Author Notification: March 7, 2014

** Program Chair:

Steve Keckler, NVIDIA/University of Texas at Austin

** Program Committee:

David Albonesi Cornell
David I. August Princeton University
Todd Austin University of Michigan
David Brooks Harvard
Doug Burger Microsoft
Doug Carmean Intel
John Carter IBM Research
Derek Chiou Microsoft/UT-Austin
Fred Chong UC-Santa Barbara
Al Davis University of Utah
Pradeep Dubey Intel
Sandhya Dwarkadas University of Rochester
Yoav Etsion Technion
Boris Grot University of Edinburgh
Rajiv Gupta UC-Riverside
David Hansquine Qualcomm
Mark D. Hill University of Wisconsin-Madison
Wen-mei Hwu University of Illinois
Stefanos Kaxiras Uppsala University
Hyesoon Kim Georgia Tech
John Kim KAIST
Martha Kim Columbia
Ronny Krashinsky NVIDIA
James Laudon Google
Alvin Lebeck Duke
Hsien-Hsin Lee Georgia Tech
Srilatha Manne AMD
Nacho Navarro U. Politecnica de Catalunya
Scott Rixner Rice
Simha Sethumadhavan Columbia
Ed Suh Cornell
Olivier Temam INRIA
Mohit Tiwari UT-Austin
Brian Towles DE Shaw Research
Dean Tullsen UC San Diego
Uri Weiser Technion
David Wentzlaff Princeton University
Carole-Jean Wu Arizona State University
Yuan Xie Pennsylvania State University
Sudhakar Yalamanchili Georgia Tech
Lixin Zhang Chinese Academy of Sciences
Craig Zilles University of Illinois

Organizing Committee:

** General Co-Chairs
Pen-Chung Yew, University of Minnesota
Antonia Zhai, University of Minnesota

** Workshop Co-Chairs
David Wentzlaff, Princeton University
Nuwan Jayasena, AMD Research

** Tutorial Co-Chairs
Martha Kim, Columbia University
Debbie Marr, Intel

** Finance Chair
Yuan Xie, Pennsylvania State University

** Industry Liaison Co-Chairs
Hyesoon Kim, Georgia Institute of Technology
Samantika Subramaniam, Intel

** Local Arrangements Chair
John Sartori, University of Minnesota

** Web Chair
Omer Khan, University of Connecticut

** Publicity Co-Chairs
Chia-Lin Yang, National Taiwan University
Natalie Enright Jerger, University of Toronto
Lieven Eeckhout, Ghent University

** Registration Chair
Ulya Karpuzcu, University of Minnesota

** Proceedings Chair
Eric Chung, Microsoft Research

** Travel Award Chair
James Tuck, NC State University

** Submission Chair
Paul Gratz, Texas A&M University

** Steering Committee
Mark Horowitz, Stanford University
David Kaeli, Northeastern University
Shih-Lien Lu, Intel
Avi Mendelson, Technion
Margaret Martonosi, Princeton University
Yale Patt, University of Texas at Austin
Joseph Torrellas, University of Illinois
David Wood, University of Wisconsin

Call for Papers: SiPhotonics '14 – Deadline extension

Submitted by Sandro Bartolini
November 7, 2013

Submitted by Sandro Bartolini
Due to a number of requests, we are *extending the submission deadline to
November 7th*.

In case you are interested, please, submit a title and abstract by October 31st
(not mandatory) so that we can start working on the review assignments

Please, check the updated important dates.

HiPEAC 1st International Workshop on Exploiting Silicon Photonics for
energy-efficient heterogeneous parallel architectures (SiPhotonics’2014)
in Vienna, Austria, 21 January 2014

associated with the 9th HiPEAC conference on High Performance and Embedded
Architecture and Compilers


The main purpose of this workshop is to promote further research interests and
activities on Silicon Photonics and related topics in the perspective of its
adoption in future computer systems. In fact Silicon Photonics poses in itself
crucial challenges and interesting design tradeoffs for being deployed in
future computer systems effectively, also in integration with other
technologies. Furthermore, the unique features of photonics (e.g. extreme
low-latency, end-to-end transmission, high bandwidth density) have the
potential to constitute a discontinuity element able to modify the expected
shape of future computer systems from the design point of view and also from
the programmability and/or runtime management perspectives.

Summarizing, silicon photonics can bring innovations and benefits into current
and foreseeable computing systems directly, due to their intrinsic features,
but also indirectly enabling the evolution towards architectures, runtime and
resource management approaches that maximize the photonic raw technological
opportunities and lead to more efficient overall designs, otherwise impossible.

This workshop aims to increase the synergy from a complete range of
perspectives, from raw technology issues and solutions up to studies at the
overall system level of modern multi-/many-core systems, both from academic and
industrial researchers working in this area. We are interested in experimental,
systems-related, and work-in-progress papers in all aspects of the Silicon
Photonics technology at all levels of development.


The topics of interest include, but are not limited to:

– Integration of positive features of both electronic and photonic
interconnection technology;
– Low-level technological improvements and implications (e.g. integrated
lasers, modulation and detection technologies, microring resonators);
– Fabrication issues (e.g. precision) and new tools (e.g. design, place and
route, ecc) to ease the topological exploration and design in general;
– Emerging challenges and solutions for on-chip interconnections, cache
coherence protocols, runtime and OS scheduling, and programmability, for future
homogeneous/heterogeneous energy-aware CMPs;
– Simulation, validation and verification;
– Photonics in the memory hierarchy and I/O of computing systems;
– QoS management and performance analysis;
– Programming languages and compilers for thermal-, energy-, and power-aware
– Solving the requirements of multiple heterogeneous parallel applications;
– Interaction between photonic features and current computer design issues;
– Industrial practices and case studies;


Prospective authors should submit electronically a full paper in English in PDF
format. Submitted papers must represent original unpublished research that is
not currently under review for any other conference or journal.

All manuscripts will be reviewed and will be judged on correctness,
originality, technical strength, significance, quality of presentation, and
interest and relevance to the workshop attendees.

They should be formatted according to double-column ACM format pages, including
figures and references. Please use the following template when preparing your
preferably, _not exceeding 6 pages (8 pages absolute maximum)_.
Please, feel free to adopt a blind submission process (not mandatory). In case,
ensure to remove the author names and affiliation from the submitted paper as
well as any explicit indication that could immediately reveal them (e.g. if
needed, refer to your previous works in third person).

Submissions can be made through the submission web site at


Informal proceedings will be provided in an USB stick to all participants
including all material relevant to the conference and the related events.

To confirm the publication, at least one author of each accepted paper is
expected to register for the workshop and present the papers at the workshop

After the conference, authors of _selected papers will be invited to submit an
extended version_ of their contribution for a _special issue of the journal
“Concurrency and Computation: Practice and Experience” from Wiley_, scheduled
to be published for June 2014.


Title+Abstract deadline (*not mandatory*): October 31, 2013
Extended paper submission deadline: November 7, 2013
Notification of acceptance: December 2, 2013
Camera ready papers due: December 13, 2013
Workshop: Jan 21, 2014

(*) Abstract submission is not mandatory but can help us to pre-organize
the review assignments.


José M. García, University of Murcia, Spain.
Sandro Bartolini, University of Siena, Italy


Keren Bergman, Columbia University
Giovanna Calò, Politecnico di Bari
José M. Cecilia, Catholic University of Murcia
Yawen Chen, Otago University
Sylvain Collange, INRIA/IRISA
Ricardo Fernández-Pascual, University of Murcia
Paolo Grani, University of Siena
Timothy Jones,University of Cambridge
Wolfgang Karl, Karlsruhe Institute of Technology
Kostas Katrinis, IBM
Sébastien Le Beux, Lyon Institute of Nanotechnology
Oliver Mattes, Karlsruhe Institute of Technology
GokhanMemik, Northwestern University
Sergei Mingaleev, VPIphotonics
Lasse Natvig, Norwegian University of Science and Technology
Sudeep Pasricha, Colorado State University
Luca Ramini, University of Ferrara
Marco Romagnoli, CNIT
Laurent Schares, IBM TJ Watson
Yvain Thonnart, CEA-Leti


Prof. José M. García
Departamento de Ingeniería y Tecnología de Computadores
University of Murcia, Spain.
email: jmgarcia[at]
Tel.: +34 868 884819 Fax: +34 868 884151

Ing. Sandro Bartolini, PhD
Dipartimento di Ingegneria dell’Informazione e Scienze Matematiche
University of Siena, Italy
E-mail: Bartolini[at]
Tel: +39 0577 234850 Fax: +39 0577 233609

Call for Papers: DMTM Workshop at HiPEAC 2014

Submitted by Osman Unsal
January 22, 2014

Submitted by Osman Unsal
Joint Euro-TM/MEDIAN Workshop on Dependable Multicore and
Transactional Memory Systems (DMTM)
Submission Deadline: November 23, 2013
Held in conjunction with the 9th International Conference on
High-Performance and Embedded Architectures and Compilers
(HiPEAC). Vienna, Austria, January 22, 2014
Workshop website:

The shift to multi-core computing has increased the relevance
of parallel programming paradigms such as transactional memory.
On the other hand, semiconductor technology scaling is getting
close to atomic scale, causing reliability issues and making
dependability a first-class design constraint. The DMTM workshop,
co-organized by the COST Actions Euro-TM(
and MEDIAN (, aims to bring together
these two relevant and timely topics. We welcome papers in one
of the two topics as well.

Topic of Interest
Hardware and software techniques to enhance dependability
of multi-core systems and parallel applications
Transactional Memory (TM) and its applications for failure-
isolation, failure-atomicity and real-time systems
Methodologies and tools for the development of concurrent
applications for embedded systems
Correctness, performance, testing and debugging of TM and
multi-core applications
Hardware, OS and language supports for TM and other programming
paradigms for concurrent programming
Energy/reliability/performance tradeoffs
Fault-Tolerant micro-architectures and parallel system architectures
Compiler/architecture/OS methodologies and strategies for reliability
Error modeling, detection, correction, and tolerance for transient and
permanent errors in multi-core architectures
Reliable on-chip communications

Important Dates
Abstracts’ submission: November 8th
Author notification: November 23h 2013

Submission Instructions
The workshop will consist of short presentations. To facilitate later
submission to other venues, DMTM will not have published proceedings.

Please submit a two pages maximum describing your research-in-progress
at EasyChair:

Program Committee
Gilles Muller, LIP6
Heiko Falk . Ulm University
Luis Rodrigues, IST Lisbon
Marc Shapiro, LIP6
Maria Michael, University of Cyprus
Marco Ottavi, University of Rome “Tor Vergata”
Oğuz Ergin, TOBB University of Economics and Technology
Osman Unsal, Barcelona Supercomputing Center
Pascal Felber, University of Neuchatel
Pedro Reviriego, Universidad Antonio de Nebrija
Ruben Titos, Chalmers University of Technology
Salvatore Pontarelli, University of Rome “Tor Vergata”
Theocharis Theocharides, University of Cyprus
Yiannakis Sazeides, University of Cyprus
Wolfgang Karl, Karlsruhe Institute of Technology (KIT)

Program Chair
Adrián Cristal, Barcelona Supercomputing Center

Call for Papers: ICDCS-2014

Submitted by Ernesto Jiménez
June 30 to July 3, 2014

Submitted by Ernesto Jiménez
ICDCS 2014
34th Int. Conf. on Distributed Computing Systems
30th June-3rd July 2014
Madrid, Spain


The conference provides a forum for engineers and scientists in academia,
industry and government to present their latest research findings
in any aspects of distributed computing.
Topics of particular interest include, but are not limited to:

– Big Data, Data Management and Analytics
– Cloud Computing and Data Center Systems
– Distributed OS and Middleware
– Algorithms and Theory
– Fault Tolerance and Dependability
– Security and Privacy
– Social Networks, Crowdsourcing, and P2P systems
– Energy Management and Green Computing
– Sensor Networks and Systems
– Mobile and Wireless Computing
– File and Storage Systems

NOTE: To build a broad program and to encourage a diverse set of
submissions, a limited number of papers will be accepted within each
topic area, and every topic area will accept a minimum quota of papers.

Workshops will be held in conjunction with the conference.
Workshop proposals should be submitted to Workshops Co-Chairs
Prof. Roberto Baldoni (
and Prof. Jason Gu( by September 30th, 2013.
Notification of acceptance will be made by October 10th, 2013. Please
see the conference web page for details.

Form of Manuscript: All paper submissions should follow the IEEE 8.5” x 11”
Two-Column Format.
Each submission can have 10 pages. If the paper is accepted for publication,
up to 2 overlength pages may be purchased for the final camera-ready
version. Submitted papers should NOT be blinded for review.

Electronic Submission: Submissions will be handled via the conference
web page.


Abstract registration 22nd November 2013
Paper Submission 29th November 2013
Author Notification 17th March 2014
Final Manuscript Due 7th April 2014

For further information, please contact General Chair,
Prof. Marta Patiño-Martínez ( or
Program Co-Chair, Prof. Ricardo Jimenez-Peris (


General Chair
Marta Patiño-Martínez (Univ. Politécnica de Madrid, Spain)

Program Co-Chairs
Ricardo Jimenez-Peris (Univ. Politécnica de Madrid, Spain)
Hui Lei (IBM Watson, US)

Program Vice Chairs
Big Data, Data Management and Analytics
Phillip Gibbons (Intel Labs, US)

Cloud Computing and Data Center Systems
Flavio Junqueira (MSR-Cambridge, UK)

Distributed OS and Middleware
Gustavo Alonso (ETH Zurich, Switzerland)

Algorithms and Theory
Antonio Fernandez-Anta (IMDEA, Spain)

Fault Tolerance and Dependability
Bettina Kemme (McGill Univ., Canada)

Security and Privacy
Elisa Bertino (Purdue, US)

Social Networks, Crowdsourcing, and P2P systems
Alberto Montresor (Trento Univ., Italy)

Energy Management and Green Computing
Tarek F. Abdelzaher (UIUC, US)

Sensor Networks and Systems
Tian He (University of Minnesota, US)

Mobile and Wireless Computing
Guohong Cao ( Pennsylvania State Univ, US)

File and Storage Systems
André Brinkmann (Meinz Univ., Germany)

Program Committee Members

Workshops Co-Chairs
Roberto Baldoni (Univ. Sapienza, Italy)
Jason Gu (Singapore Univ., Singapore)

Publicity Chair
Ernesto Jimenez (Univ. Politecnica Madrid, Spain)

Publication Chair
Mikel Larra (Univ. Pais Vasco, Spain)

TCDP Chair
Jiannong Cao,(Hong Kong Polyt. Univ., HK)

Steering Committee Chair
Xiaodong Zhang (Ohio State Univ., USA)

Microsoft Research Cambridge