Call for Participation: ASPLOS 2014

Submitted by Niti Madan
https://www.cs.utah.edu/asplos14/
March 1 to March 5, 2014

Submitted by Niti Madan
https://www.cs.utah.edu/asplos14/
ASPLOS is the premier forum for multidisciplinary systems research
spanning computer architecture and hardware, programming languages
and compilers, and operating systems and networking. The program
covers cross-cutting research spanning mobile systems to data
centers, targeting diverse goals such as performance,
energy efficiency, resiliency, and security.

The conference program (March 3rd-5th) features:

– 49 technical papers
– Two keynotes
– Inside Windows Azure: The Challenges and Opportunities
of a Cloud Operating System by
Brad Calder, Microsoft
– Neuromorphic Processing: A New Frontier in Scaling
Computer Architecture by
Jeff Gehlhaar, Qualcomm
– A debate
– Resolved: Specialized architectures, languages, and
system software should largely supplant general-purpose
alternatives within the next decade
Moderator: David Wood, University of Wisconsin-Madison
Debators:
Pro: Edouard Bugnion (EPFL),
Christos Kozyrakis (Stanford University),
Kunle Olukotun (Stanford University)
Con: Chris Hughes (Intel),
Keshav Pingali (Univ of Texas at Austin),
Emmett Witchel (Univ of Texas at Austin)

– A Wild and Crazy Ideas (WACI) session featuring
– WACInote: RF-powered computing and communication
Josh Smith, University of Washington
– A poster session and lightning talk session for all accepted papers

ASPLOS Co-Located Events:

Saturday March 1st 2014
– ACM SIGPLAN/SIGOPS International Conference on Virtual
Execution Environments (VEE)
– Workshop on Managing Overprovisioned Systems (W-MOS)
– 7th Workshop on General Purpose Processing Using
GPUs (GPGPU-7)
– 4th Workshop on Big Data Benchmarks, Performance
Optimization, and Emerging Hardware (BPOE-4)
– Tutorial: Towards Database Virtualization for Database as
a Service
– Tutorial: Pin Binary Instrumentation Tutorial
– Tutorial: Accelerating Big Data Processing with Hadoop and
MemCached on Datacenters with Modern Networking and Storage
Architecture
– Tutorial: Analyzing Analytics for Parallelism

Sunday March 2nd 2014
– ACM SIGPLAN/SIGOPS International Conference on
Virtual Execution Environments (VEE)
– 5th Workshop on Determinism and Correctness for
Parallel Programs (WODET)
– 9th Workshop on Transactional Computing (TRANSACT)
– 1st Workshop on Approximate Computing Across the
System Stack (WACAS)
– Tutorial: System Analytics in the Cloud
– Tutorial: Concord: Homogeneous Programming for Heterogeneous
Platforms
– Tutorial: Rigorous and Practical Server Design Evaluation
– Tutorial: Machine Learning on Big Data
– Tutorial: Multi2Sim – A Compilation and Simulation Framework
for Heterogeneous Computing

Call for Papers: FastPath, Extended Deadline

Submitted by Mark Hempstead
http://researcher.watson.ibm.com/researcher/view_project.php?id=4338
February 1 to February 28, 2014

Submitted by Mark Hempstead
http://researcher.watson.ibm.com/researcher/view_project.php?id=4338
FASTPATH 2014

3rd International Workshop on Performance Analysis of Workload Optimized Systems

To be held with ISPASS 2014, March 23, 2014.

MOTIVATION

The goal of FastPath is to bring together researchers and practitioners
involved in cross-stack hardware/software performance analysis, modeling,
and evaluation of workload optimized systems.

The goal is increasingly important as the slowdown in Moore’s Law makes it
increasingly important to optimize systems around specific workloads. Such
workload optimized systems have hardware and/or software specifically
designed to run well for a particular application or application class.
Such systems include, but are not limited to traditional CPUs assisted with
accelerators (ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators,
hybrid systems, and IT appliances. This workload optimized system approach
contrasts to the broad general purpose direction of computing over many
decades. However, the workload optimized systems approach is growing in
importance, as we see in systems from cellphones to tablets to routers to
game machines to Top500 supercomputers, and IT appliances such as IBM’s
DataPower and Netezza, and Oracle’s Exadata.

TOPICS

FastPath seeks to facilitate the exchange of ideas on performance analysis
and evaluation of workload optimized systems and seeks papers on a wide
range of topics including, but not limited to:

o Workloads
o Simulators
o Industrial Experiences
o GPUs, FPGAs, ASIC Accelerators
o Game Consoles and their Sensors
o RDMA and Infiniband
o Measurements on accelerated systems
o Analytical Techniques
o Programming Models
o MapReduce, Hadoop
o Runtime Management Systems

SUBMISSIONS

FastPath is focused on presentations and will not have a proceedings. Thus
early ideas can be presented. For submissions, please provide a 1 or 2-page
extended abstract by February 17, 2014:

https://www.easychair.org/conferences/?conf=fastpath2014

HISTORY:

FastPath 2012: https://sites.google.com/site/fastpath2012
Half-day with 1 keynote speaker and 3 invited speakers.

FastPath 2013: http://ispass.org/ispass2013/fastpath2013
Full-day with 1 keynote speaker, 6 invited speakers, and 1 Regular speaker.

FASTPATH 2014 DEADLINES

Submission: February 28, 2014
Author Notification: March 10, 2014
Workshop March 23, 2014 (Monterey, California)

ORGANIZING COMMITTEE

General Chair: Erik Altman (IBM)

Program Chairs: Parijat Dube (IBM)
Lizy John (University of Texas, Austin)

Web Augusto Vega (IBM)

Publicity Mark Hempstead (Drexel)

Call for Papers: ASBD 2014

Submitted by Yungang Bao
http://acs.ict.ac.cn/asbd2014/
March 31, 2014

Submitted by Yungang Bao
http://acs.ict.ac.cn/asbd2014/
We are pleased to request papers for presentation at the upcoming Fourth
Workshop on Architectures and Systems for Big Data (ASBD 2014) held in
conjunction with ISCA-41. The workshop will provide a forum to exchange
research ideas related to all critical aspects of emerging analytics
systems for big data, including architectural support, benchmarks and
metrics, data management software, operating systems, and emerging
challenges and opportunities. We hope to attract a group of interdisciplinary
researchers from academia, industry and government research labs.
To encourage discussion between participants, the workshop will include
significant time for interactions between the presenters and the audience.
We also plan to have a keynote speaker and/or panel session.

Call for Papers: HASH @ ISCA 2014

Submitted by Mohamed Zahran
https://sites.google.com/site/hashworkshop/
June 14, 2014

Submitted by Mohamed Zahran
https://sites.google.com/site/hashworkshop/
The First Annual Workshop on Heterogeneous Architectures:
Software and Hardware (HASH)

June 14, 2014, Minneapolis, MN, USA
(co-located with ISCA 2014)

The architecture and microarchitecture of multicore/manycore
processors is moving rapidly toward heterogeneity. Heterogeneous
multicore/manycore processors provide a promising opportunity to
achieve better performance together with power efficiency. However,
the complexity of the architecture, microarchitecture, software
applications, and system software presents a challenging problem. The
varying requirements of the different applications running on a single
machine, the changing behavior of a single application during its
lifetime, as well as the ever-changing characteristics of
multiprogramming environment make the design and programming of
heterogeneous architectures a big challenge.

The Heterogeneous Architecture: Software and Hardware workshop
provides a high-quality forum for computer scientists and engineers to
present their latest research findings in the rapidly evolving field of
heterogeneous architecture where the
heterogeneouity can be in the form of cores of different strength,
general purpose cores and GPUs, cores with different memory
hierarchies, accelerators, etc; as well as their interconnect. The
interaction among the different layers of the stack is part of the
objectives, which involves compilers, OS, and programming models.

KEY DATES
Submissions deadline: March 10, 2014
Notification: April 10, 2014
Camera-Copy Papers Due: April 30, 2014

TOPICS OF INTEREST
Topics of interest include, but are not limited to:

*Memory hierarchy for heterogeneous multicores

*Power efficiency of heterogeneous architectures

Programming models for heterogeneous architectures

* The effect of heterogeneity on NoC

* Compilation techniques for heterogeneous architectures

* GPGPUs

* Reliability issues in heterogeneous computing

* OS management of heterogeneous architecture

SUBMISSION
The Program Committee invites authors to submit papers up to 8 pages
(11pt font) double-column describing original, unpublished recent
work, or work in progress related to the workshop theme.

Submission must be in pdf format and emailed to:

hash.workshop@gmail.com

PROGRAM COMMITTEE
Trey Cain
(Qualcomm )
John Cavazos
(U. Delaware)
Aamer Jaleel
(Intel)
Pierre Michaud
(INRIA)
Vijay Janapa Reddi
(UT Austin)
Aaron Smith
(Microsoft Research)
Jessica Tseng
( IBM Research )
Dong Ping Zhang
(AMD)

ORGANIZERS
Mohamed Zahran, (NYU)
Hubertus Franke (IBM T. J. Watson)

Call for Participation: ISPASS 2014 — Early Registration Deadline: 3/1

Submitted by Byeong Kil Lee
http://ispass.org
March 23 to March 25, 2014

Submitted by Byeong Kil Lee
http://ispass.org
2014 IEEE International Symposium on Performance Analysis of Systems and
Software (ISPASS 2014)
March 23-25, 2014
Monterey, CA

Call for Participation:
The 2014 IEEE International Symposium on Performance Analysis of Systems and
Software is sponsored by the IEEE Computer Society’s Technical Committee on
Internet, Technical Committee on Computer Architecture,
and Technical Committee on Microprogramming and Microarchitecture.

***** Early Registration deadline is March 1st, 2014 at 5PM Pacific *****

[ Keynotes ]
Keynote I. Bridging the Energy-Efficiency Gap in a Future of Massive Data
Prof. Fred Chong (University of California, Santa Barbara)

Keynote II. Life Lessons and Datacenter Performance Analysis
Dr. Amer Diwan (Google)

[ Program ]
Session 1: Best Paper Nominees
BarrierPoint: Sampled Simulation of Multi-threaded Applications
Sources of Error in Full-System Simulation
Exploiting Spatial Architectures for Edit Distance Algorithms
A Top Down Method for Performance Analysis and Counters Architecture

Session 2: Applications and Benchmarks
Moby: A Mobile Benchmark Suite for Architectural Simulators
The Design Space of Ultra-low Energy Asymmetric Cryptography
Optimized Hardware for Suboptimal Software: The Case for SIMD-aware Benchmarks

Session 3: Analytical and Statistical Models
Applying the Roofline Model
Extending Statistical Cache Models to Support Detailed Pipeline Simulators
Modeling Cache Coherence Misses on Multicore

Session 4: Simulators
Manifold: A Parallel Simulation Framework for Multicore Systems
PriME: A Parallel and Distributed Simulator for Thousand-Core Chips

Poster Session
A Study on Mobile Device Utilizations
Steps Towards Wider Use of Concurrency Code Patterns
ParTejas: A Parallel Simulator for Multicore Processors
Diamond: An Integrated Performance and Power Simulator for Large Scale Multicores
Weighted-Tuple Synchronization for Parallel Architecture Simulators
Accelerating Network-on-Chip Simulation via Sampling
A Case for Resource Efficient Prefetching in Multicores
Evaluating Trace Aggregation through Entropy Measures for Performance
Visualization of Large Distributed Systems
Reverse Engineering of Cache Replacement Policies in Intel Microprocessors and
Their Evaluation
Energy Introspector: A Parallel, Composable Framework for Integrated
Power-Reliability-Thermal Modeling for Multicore Architectures
Characterizing the Latency Hiding Ability of GPUs

Session 5: Online Profiling
A Software Based Profiling Method for Obtaining Speedup Stacks on Commodity
Multi-Cores
MIAMI: A Framework for Application Performance Diagnosis
Quality Time: A Simple Online Technique for Quantifying Multicore Execution
Efficiency
Variability of Data Dependences and Control Flow

Session 6: Cache and Memory Systems
NDC: Analyzing the Impact of 3D-Stacked Memory+Logic Devices on MapReduce
Workloads
Simulating DRAM controllers for future system architecture exploration
Energy-Efficient Reconfigurable Cache Architectures for Accelerator-Enabled
Embedded Systems

Session 7: GPUs
GPU-Qin: A Methodology for Evaluating the Error Resilience of GPGPU Applications
Understanding the Tradeoffs between Software-Managed vs. Hardware-Managed Caches
in GPUs

[ Tutorial ]
GPUWattch (morning)
CloudSuite (afternoon)

[ Workshop ]
Fastpath ( full day workshop)

[ Registration ]
Online Registration: http://www.regonline.com/ispass14
Early Registration deadline is March 1st, 2014 at 5PM Pacific.

[ Hotel Information ]
ISPASS 2014 will be held at the Hyatt Regency Hotel in Monterey, California
Please use the following link to register for the hotel:
https://resweb.passkey.com/go/2014IEEEHQ
Note: The hotel registration cutoff is March 1st at 5PM (Pacific).

[ NSF Travel Support for Eligible Students ]
The deadline for submitting travel funding applications is March 1st. Please
send them by email to the Student Travel Grant Chair, Carole-Jean Wu
(carole-jean.wu@asu.edu). Use the subject line “ISPASS 2014 Student Travel Grant
Application.”

[ Visas for Travel to U.S. ]
If you require an invitation letter for purposes of a visa application, please
send an email with your name, email address, mailing address, IEEE member number
(if any), the ID of the paper you are presenting (if any) and a copy of your
registration confirmation to Suzanne Rivoire, the Registration Chair at
registration@ispass.org.

For more details, please see http://www.ispass.org

Call for Papers: FastPath

Submitted by Mark Hempstead
http://researcher.ibm.com/project/4338
February 24, 2014

Submitted by Mark Hempstead
http://researcher.ibm.com/project/4338
FASTPATH 2014

3rd International Workshop on Performance Analysis of Workload Optimized Systems

To be held with ISPASS 2014, March 23, 2014.

MOTIVATION

The goal of FastPath is to bring together researchers and practitioners
involved in cross-stack hardware/software performance analysis, modeling,
and evaluation of workload optimized systems.

The goal is increasingly important as the slowdown in Moore’s Law makes it
increasingly important to optimize systems around specific workloads. Such
workload optimized systems have hardware and/or software specifically
designed to run well for a particular application or application class.
Such systems include, but are not limited to traditional CPUs assisted with
accelerators (ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators,
hybrid systems, and IT appliances. This workload optimized system approach
contrasts to the broad general purpose direction of computing over many
decades. However, the workload optimized systems approach is growing in
importance, as we see in systems from cellphones to tablets to routers to
game machines to Top500 supercomputers, and IT appliances such as IBM’s
DataPower and Netezza, and Oracle’s Exadata.

TOPICS

FastPath seeks to facilitate the exchange of ideas on performance analysis
and evaluation of workload optimized systems and seeks papers on a wide
range of topics including, but not limited to:

o Workloads
o Simulators
o Industrial Experiences
o GPUs, FPGAs, ASIC Accelerators
o Game Consoles and their Sensors
o RDMA and Infiniband
o Measurements on accelerated systems
o Analytical Techniques
o Programming Models
o MapReduce, Hadoop
o Runtime Management Systems

SUBMISSIONS

FastPath is focused on presentations and will not have a proceedings. Thus
early ideas can be presented. For submissions, please provide a 1 or 2-page
extended abstract by February 17, 2014:

https://www.easychair.org/conferences/?conf=fastpath2014

HISTORY:

FastPath 2012: https://sites.google.com/site/fastpath2012
Half-day with 1 keynote speaker and 3 invited speakers.

FastPath 2013: http://ispass.org/ispass2013/fastpath2013
Full-day with 1 keynote speaker, 6 invited speakers, and 1 Regular speaker.

FASTPATH 2014 DEADLINES

Submission: February 24, 2014
Author Notification: March 10, 2014
Workshop March 23, 2014 (Monterey, California)

ORGANIZING COMMITTEE

General Chair: Erik Altman (IBM)

Program Chairs: Parijat Dube (IBM)
Lizy John (University of Texas, Austin)

Web Augusto Vega (IBM)

Publicity Mark Hempstead (Drexel)

Call for Papers: ASAP 2014, extended deadline

Submitted by Kubilay Atasu
http://www.zurich.ibm.com/asap2014/
June 18 to June 20, 2014

Submitted by Kubilay Atasu
http://www.zurich.ibm.com/asap2014/
25th IEEE International Conference on
Application-specific Systems, Architectures and Processors
18-20 June 2014, IBM Research – Zurich, Switzerland
http://www.asap-conference.org

Important Dates

– Abstract Due 21 February 2014
– Paper Submission 28 February 2014
– Notification of Acceptance 11 April 2014
– Conference 18-20 June 2014

Quick Links

– Conference http://www.zurich.ibm.com/asap2014/
– Call for Papers http://www.zurich.ibm.com/asap2014/asap2014-cfp.pdf
– Submission site: https://www.easychair.org/conferences/?conf=asap2014

The ASAP 2014 conference is organized by IBM Research – Zurich and
the Swiss Federal Institute of Technology Zurich (ETH). The conference
will cover the theory and practice of application-specific systems,
architectures and processors. The 2014 conference will build upon
traditional strengths in areas such as computer arithmetic, cryptography,
compression, signal and image processing, network processing,
reconfigurable computing, and all types of hardware accelerators.
We especially encourage submissions in the following areas:

– Big data analytics: extracting and correlating information
from large-scale semi-structured and unstructured data
using application-specific systems.

– Scientific computing: architectures and algorithms that
address scientific applications requiring significant
computing power and design customization (bioinformatics,
climate modeling, astrophysics, seismology, etc.).

– Industrial computing: systems and architectures for
providing high-throughput or low latency in various
industrial computing applications.

– System security: cryptographic hardware architectures,
security processors, countermeasures against side-channel
attacks, and secure cloud computing.

– Heterogeneous systems: applications and platforms that
exploit heterogeneous computing resources, including
FPGAs, GPUs, or CGRAs.

– Design space exploration: methods for customizing and
tuning application-specific architectures to improve
efficiency and productivity.

– Platform-specific architectures: novel architectures for
exploiting specific compute domains such as smartphones,
tablets, and data centers, particularly in the context of
energy efficiency.

Conference Venue

The conference is hosted at
IBM Research – Zurich
Säumerstrasse 4
CH-8803 Rüschlikon (Switzerland)
http://www.zurich.ibm.com/asap2014/venue.html

Conference Organization

General Chair:
Kubilay Atasu, IBM Research – Zurich, Switzerland

General Co-Chair:
Melissa Smith, Clemson University, USA

Program Co-Chairs:
Haohuan Fu, Tsinghua University, China
David Thomas, Imperial College London, UK

Call for Papers: The First International Workshop on Rack Scale Computing (WRSC 2014)

Submitted by Paolo Costa
http://research.microsoft.com/en-us/events/wrsc2014
April 13, 2014

Submitted by Paolo Costa
http://research.microsoft.com/en-us/events/wrsc2014
The First International Workshop on Rack Scale Computing (WRSC 2014)

http://research.microsoft.com/en-us/events/wrsc2014

WRSC will be a venue to discuss the impact of game-changing
technologies such as SoCs, integrated fabrics, low-latency RDMA,
silicon photonics, on the design of data center hardware and
software. These technologies and implications span different
areas, so as a unifying theme we are using the term “rack-scale
computing” because many of these changes are happening at the
scale of a rack. We are already seeing early platforms from
companies like AMD SeaMicro, HP and Intel.

However, fully unleashing their potential requires a deep and
cross-layer rethinking of the way the hardware, OS and network
stacks, and applications are built and interact. While some of
these ideas have already started being discussed in various
research communities, we believe it’s important to have a common
forum for researchers and practitioners from different
areas (hardware architectures, networking, operating systems,
storage, distributed systems, and HPC) to discuss new ideas on
how to design next-generation rack-scale systems. We hope that
this workshop will help shaping the research agenda in the field.
– Submission deadline: Sunday Feb 16, 2014

– Notification to the authors: Saturday, Mar 8, 2014

– Workshop: Sunday April 13, 2014 in Amsterdam (co-located with Eurosys 2014).

= Organization =

Paolo Costa, Microsoft Research (Program Chair)

Dushyanth Narayanan, Microsoft Research (General Chair)

= Program Committee=

Gustavo Alonso, ETH Zurich
Edouard Bugnion, EPFL
Luis Ceze, U. Washington
Paolo Costa, Microsoft Research
Leendert van Doorn, AMD
Babak Falsafi, EPFL
Blake Fitch, IBM Research
Nathan Farrington, Facebook
Tim Harris, Oracle Labs
Michael Kaminsky, Intel Labs
Dushyanth Narayanan, Microsoft Research
Parthasarathy (Partha) Ranganathan, Google
Luigi Rizzo, U. Pisa
Thomas Wenisch, U. Michigan
Bernard Wong, U. Waterloo

Call for Papers: Workshop on Neuromorphic Architectures (NeuroArch) @ ISCA 2014

Submitted by Hadi Esmaeilzadeh
http://www.cs.utsa.edu/~muzahid/neuroarch.html
June 14, 2014

Submitted by Hadi Esmaeilzadeh
http://www.cs.utsa.edu/~muzahid/neuroarch.html
Workshop on Neuromorphic Architectures (NeuroArch)

Saturday, June 14th, 2014
(held in conjunction with ISCA 2014)
Minneapolis, MN, USA

http://www.cs.utsa.edu/~muzahid/neuroarch.html

PRESENTATION

The first workshop on Neuromorphic Architectures (NeuroArch) aims at exploring
novel ideas and research opportunities in design, programming, and application
of neuromorphic and brain-inspired accelerators. In the current realm of
processor design, where energy and power constraint has shifted the designs
toward heterogeneity, hardware neural networks are emerging as candidate
accelerators with attractive characteristics and broad application scope.

In addition to the power-efficiency and fault tolerance of neural accelerators,
we are at the junction of time where: As technology scales down to the atomic
levels, the increasing process variability causes the designers to pay a high
tax in performance and efficiency to provide fault-free designs; the intrinsic
robustness of neural networks may lead to fault-tolerant accelerators. Novel
neural network algorithms such as Deep Belief Networks outperform many
alternative machine learning algorithms across a broad set of applications.
Significant progress in neuroscience sheds light on the operating principles of
biological neural networks, which can thus be partially replicated in hardware.
The landscape of computing has changed toward providing a more personalized and
more targeted experience for the users, thus increasing the importance of
applications that require learning.

Therefore, we believe it is imperative and timely for the computer architecture
community and the design of next generation computing systems to explore and
research neural models of computing.

TOPICS

To this end, NeuroArch invites research papers and talks on topics including
but not limited to: Hardware design for biologically or mathematically inspired
neural networks Applications of hardware neural networks Advanced technologies
and devices for neural hardware design (3D, memristors, …) Programming models
and environments for neural accelerators

NeuroArch 2014 will include both invited talks and peer-reviewed papers.
Peer-reviewed papers will not be published in a proceedings; therefore,
submitting to NeuroArch will not preclude future publication opportunities.
However, papers and presentation slides will be made available online with the
authors’ approval.

IMPORTANT DATES

Paper Submission: April 1st, 2014
Author Notification: April 15th, 2014

SUBMISSION

Paper submissions are limited to two-page extended abstracts. Please use the
formatting guidelines from the main conference (see
http://cag.engr.uconn.edu/isca2014/submission.html).

Please send a PDF version of your paper to hadi@cc.gatech.edu and
daniel.ben-dayan.rubin@intel.com.

Submissions may optionally be blind (authors can choose whether to include
names on the submitted PDF; this option will be relevant if the organizing
committee decides to query the opinion of an external reviewer).

ORGANIZERS

Daniel Ben Dayan-Rubin, Intel Labs, ICRI, Israel
Hadi Esmaeilzadeh, Georgia Tech
Abdullah Muzahid, University of Texas at San Antonio
Emre Neftci, UCSD
Olivier Temam, Inria

CONTACT
For any question related to the workshop organization, please contact
abdullah.muzahid@utsa.edu and olivier.temam@inria.fr.

Call for Nominations: ACM-IEEE CS Eckert-Mauchly Award, ACM SIGARCH Maurice Wilkes Award, ACM SIGARCH Distinguished Service Award

Submitted by Kevin Lim

Submitted by Kevin Lim
The nomination process is open for multiple ACM SIGARCH associated
awards. These include:
* ACM-IEEE CS Eckert-Mauchly Award: Deadline March 30, 2014
http://www.sigarch.org/awards/acm-eckert-mauchly-award/

* ACM SIGARCH Maurice Wilkes Award: Deadline March 1, 2014
http://www.sigarch.org/awards/acm-sigarch-maurice-wilkes-award/

* ACM SIGARCH Distinguished Service Award: Deadline March 1, 2014
http://www.sigarch.org/awards/acm-sigarch-distinguished-service-award/

Please see the websites and the general SIGARCH award page
(http://www.sigarch.org/awards) for additional information on the
nomination processes. Past winners of all awards can also be found on
the site.