Call for Participation: ISCA-41

Submitted by Natalie Enright Jerger
June 14 to June 18, 2014

Submitted by Natalie Enright Jerger

The 41st International Symposium on Computer Architecture
Minneapolis, MN, USA
June 14-18, 2014

The 41st International Symposium on Computer Architecture is the premier forum
for new ideas and experimental results in computer architecture.


** Early registration deadline: May 15, 2014
** Registration Link:

** Hotel reservation cut-off date: May 24, 2014
** Hotel reservation link:

** Travel grant deadline: May 2, 2014

General Co-Chairs

• Pen-Chung Yew, University of Minnesota

• Antonia Zhai, University of Minnesota

Program Chair

• Steve Keckler, NVIDIA/University of Texas at Austin

Program Committee:

David Albonesi Cornell

David I. August Princeton University

Todd Austin University of Michigan

David Brooks Harvard

Doug Burger Microsoft

Doug Carmean Intel

John Carter IBM Research

Derek Chiou Microsoft/UT-Austin

Fred Chong UC-Santa Barbara

Al Davis University of Utah

Pradeep Dubey Intel

Sandhya Dwarkadas University of Rochester

Yoav Etsion Technion

Boris Grot University of Edinburgh

Rajiv Gupta UC-Riverside

David Hansquine Qualcomm

Mark D. Hill University of Wisconsin-Madison

Wen-mei Hwu University of Illinois

Stefanos Kaxiras Uppsala University

Hyesoon Kim Georgia Tech

John Kim KAIST

Martha Kim Columbia

Ronny Krashinsky NVIDIA

James Laudon Google

Alvin Lebeck Duke

Hsien-Hsin Lee Georgia Tech

Srilatha Manne AMD

Nacho Navarro U. Politecnica de Catalunya

Scott Rixner Rice

Simha Sethumadhavan Columbia

Ed Suh Cornell

Olivier Temam INRIA

Mohit Tiwari UT-Austin

Brian Towles DE Shaw Research

Dean Tullsen UC San Diego

Uri Weiser Technion

David Wentzlaff Princeton University

Carole-Jean Wu Arizona State University

Yuan Xie Pennsylvania State University

Sudhakar Yalamanchili Georgia Tech

Lixin Zhang Chinese Academy of Sciences

Craig Zilles University of Illinois

Workshop Co-Chairs

• David Wentzlaff, Princeton University

• Nuwan Jayasena, AMD Research

Tutorial Co-Chairs

• Martha Kim, Columbia University

• Debbie Marr, Intel

Finance Chair

• Yuan Xie, Pennsylvania State University

Industry Liaison Co-Chairs

• Hyesoon Kim, Georgia Institute of Technology

• Samantika Subramaniam, Intel

Local Arrangements Chair

• John Sartori, University of Minnesota

Web Chair

• Omer Khan, University of Connecticut

Publicity Co-Chairs

• Chia-Lin Yang, National Taiwan University

• Natalie Enright Jerger, University of Toronto

• Lieven Eeckhout, Ghent University

Registration Chair

• Ulya Karpuzcu, University of Minnesota

Proceedings Chair

• Eric Chung, Microsoft Research

Travel Award Chair

• James Tuck, NC State University

Submission Chair

• Paul Gratz, Texas A&M University

Steering Committee

• Mark Horowitz, Stanford University

• David Kaeli, Northeastern University

• Shih-Lien Lu, Intel

• Avi Mendelson, Technion

• Margaret Martonosi, Princeton University

• Yale Patt, University of Texas at Austin

• Joseph Torrellas, University of Illinois

• David Wood, University of Wisconsin

Call for Papers: ASBD @ ISCA 2014

Submitted by Yungang Bao
April 10 to April 11, 2014

Submitted by Yungang Bao
Paper Due April 11th

We are pleased to request papers for presentation at the upcoming Fourth
Workshop on Architectures and Systems for Big Data (ASBD 2014) held in
conjunction with ISCA-41. The workshop will provide a forum to exchange
research ideas related to all critical aspects of emerging analytics
systems for big data, including architectural support, benchmarks and
metrics, data management software, operating systems, and emerging
challenges and opportunities. We hope to attract a group of interdisciplinary
researchers from academia, industry and government research labs.
To encourage discussion between participants, the workshop will include
significant time for interactions between the presenters and the audience.
We also plan to have a keynote speaker and/or panel session.

Call for Papers: 2nd Workshop on on Near-threshold Computing (WNTC@ISCA 2014)

Submitted by Radu Teodorescu
June 14, 2014

Submitted by Radu Teodorescu
Second Workshop on Near-threshold Computing (WNTC),
in conjunction with the International Symposium on Computer Architecture
(ISCA) 2014.

June 14, 2014, Minneapolis, MN, USA

Near-threshold computing (NTC) has emerged as a promising approach
to achieving an order of magnitude improvement in energy efficiency
of microprocessors. The key feature of NTC is to lower the supply voltage
of chips to a value only slightly higher than the threshold voltage.
NTC lowers power consumption by an order of magnitude or more. The reduction
in power however comes with associated costs and challenges that include
low operating frequency, less reliable operation of both logic and memory
and much higher sensitivity to parameter variability. Industry is
actively investigating the technology and has produced prototypes
that show promising initial results. However, many challenges remain
before NTC can become mainstream.

This workshop seeks original contributions on topics that include,
but are not limited to:

*Software/Architecture/Circuit solutions for addressing
performance, reliability or variability challenges in NTC.
*Approximate computing techniques that gracefully
tolerate reliability issues at low voltages.
*Novel applications of NTC in mobile systems,
high-performance/high-parallelism environments.
*Tradeoff analyses and performance/energy studies that help
identify new application domains for NTC.
*Other low-voltage techniques, designs, architectures.

Important dates:
Paper submission: April 18, 2014.
Acceptance notifications: May 2, 2014.
Camera-ready due: June 1, 2014.
Workshop: Saturday, June 14, 2014.

Program Committee:
Alaa Alameldeen, Intel
Yasuko Eckert, AMD
Ron Dreslinski, University of Michigan
Ulya Karpuzcu, University of Minnesota
Nam Sung Kim, University of Wisconsin
Srilatha Manne, AMD
Timothy Miller, Binghamton University
Trevor Mudge, University of Michigan
Radu Teodorescu, Ohio State
Josep Torrellas, University of Illinois
Sungjoo Yoo, POSTECH

Radu Teodorescu (The Ohio State University)
Nam Sung Kim (University of Wisconsin)
Ulya Karpuzcu (University of Minnesota)

Call for Papers: The Memory Forum

Submitted by Rajeev Balasubramonian
June 14, 2014

Submitted by Rajeev Balasubramonian
The Memory Forum

A Workshop in conjunction with ISCA 2014
Saturday June 14th 2014, Minneapolis, MN

Call for Papers:

We invite short 4-page papers along the lines of IEEE Computer
Architecture Letters. Papers should focus on the key new ideas and
preliminary evaluations are fine. Accepted papers will be posted on
the workshop webpage and should not preclude later publication at
other conferences and journals.

Important Dates:

Paper submissions due: Friday April 11th, 2014
Notification: Friday April 25th, 2014
Final Paper Due: Monday June 9th, 2014

Workshop Scope:

In recent years, the memory bottleneck has grown and new memory
technologies are emerging to challenge the traditional dominance
of DRAM. DRAM itself has also been evolving, through the development
of 3DS, HBM, HMC, and Wide IO. All of these factors demand novel
memory architectures and organizations, methods of scheduling and
managing memory, and algorithms for maintaining reliable data
storage with unreliable bits. The Memory Forum will bring together
researchers from both academia and industry to discuss advances in
memory architecture, organization, and management. The workshop will
include a few invited talks to educate the audience about upcoming
technologies. The rest of the program will include short
presentations based on submitted papers — the goal is to provide
feedback to authors on early-stage and exciting ideas. Approaches
to memory management that rely on programming language techniques
may be better suited to the SIGPLAN-sponsored MSPC workshop that is
co-located with PLDI.


Rajeev Balasubramonian, University of Utah
Michael Healy, IBM TJ Watson Research Center
Onur Mutlu, Carnegie Mellon University

Program Committee:

Jung Ho Ahn, Seoul National University
Rajeev Balasubramonian, University of Utah
Ricardo Bianchini, Rutgers University
John Carter, IBM
Mattan Erez, UT Austin
Babak Falsafi, EPFL
Michael Healy, IBM TJ Watson Research Center
Engin Ipek, University of Rochester
Hyesoon Kim, Georgia Tech
Benjamin Lee, Duke University
Gabriel Loh, AMD
Krishna Teja Malladi, Samsung
Jose Martinez, Cornell University
Naveen Muralimanohar, HP Labs
Onur Mutlu, Carnegie Mellon University
Mike O’Connor, NVIDIA, UT Austin
Jong Hoon Oh, SK Hynix
Churoo Park, Samsung
Yanos Sazeides, University of Cyprus
Andre Seznec, IRISA/INRIA
Jeff Stuecheli, IBM
Aniruddha N. Udipi, ARM
Chris Wilkerson, Intel
Jun Yang, University of Pittsburgh
Lixin Zhang, ICT, CAS

Call for Proposals: NSF 2014 BIG DATA Program Solicitation

Submitted by Hong Jiang

Submitted by Hong Jiang
Dear members of the computer architecture research community,
I would like to alert you the latest NSF funding
opportunity that has great relevance to our community:
Critical Techniques and Technologies for
Advancing Big Data Science & Engineering (BIGDATA), PROGRAM SOLICITATION
NSF 14-543

Thank you for your attention!

Hong Jiang
Program Director
Software and Hardware Foundation
National Science Foundation

New Book: Security Basics for Computer Architects by Ruby Lee

Submitted by Michael Morgan

Submitted by Michael Morgan
Security Basics for Computer Architects
Ruby B. Lee
Princeton University

Synthesis Lectures on Computer Architecture
Morgan & Claypool Publishers
September 2013, 111 pages,

Design for security is an essential aspect of the design of future computers.
However, security is not well understood by the computer architecture
Many important security aspects have evolved over the last several decades in
the cryptography, operating systems, and networking communities. This book
attempts to introduce the computer architecture student, researcher, or
practitioner to the basic concepts of security and threat-based design. Past
work in different security communities can inform our thinking and provide a
rich set of technologies for building architectural support for security into
all future computers and embedded computing devices and appliances. I have
tried to keep the book short, which means that many interesting topics and
applications could not be included. What the book focuses on are the
fundamental security concepts, across different security communities,
that should be understood by any computer architect trying to design
or evaluate security-aware computer architectures.

The book is also written to be accessible to a more general audience interested
in the basic security technologies that can be used to improve cyber security.
By understanding the concepts behind the security terminology, the interested
reader would understand more clearly the frequent security breaches being
reported in the news and be able to critique or even help propose effective
security solutions.

Table of Contents: Preface / Threat-Based Design / Security Policy Models /
Access Control / Cryptography for Confidentiality and Integrity / Public-Key
Cryptography / Security Protocols / Summary / Bibliography / Appendix: Further
Readings / Author’s Biography

Call for Papers: IEEE International Symposium on Workload Characterization

Submitted by Jian Li
October 26 to October 28, 2014

Submitted by Jian Li
October 26 (Sun) – 28 (Tue), 2014
Raleigh, North Carolina, USA


Important Dates

Abstracts Submission : April 18, 2014   
Paper Submission : April 25, 2014   
Acceptance Notification : June 17, 2014 

This symposium is dedicated to the understanding and characterization of
workloads that run on all types of computing systems. New applications and
programming paradigms continue to emerge rapidly as the diversity and
performance of computers increase. On one hand, improvements in computing
technology are usually based on a solid understanding and analysis of existing
workloads. On the other hand, computing workloads evolve and change with
advances in microarchitecture, compilers, programming languages, and networking
communication technologies. Whether they are smart phones and deeply embedded
systems at the low end or massively parallel systems at the high end, the
design of future computing machines can be significantly improved if we
understand the characteristics of the workloads that are expected to run on
them. This symposium will focus on characterizing and understanding emerging
applications in consumer, commercial and scientific computing.

General Chair
  Huiyang Zhou, North Carolina State University
Program Chair 
  Lixin Zhang, Inst of Comp Tech, Chinese Academy of Sciences
  Lingjia Tang, University of Michigan
Workshop/Tutorial Chair
  Lisa Hsu, Qualcomm
Finance Chair
  Carole-Jean Wu, Arizona State University
Local Arrangements Chair
  James Tuck, North Carolina State University
Publications Chair
  Mark Hempstead, Drexel University
Publicity Chair
  Jian Li, IBM Research
Registration Chair
  Xin Fu, University of Kansas
Submissions Chair
Web Chair
  Yi Yang, NEC Laboratories America
Topics of Interest
We solicit papers in all areas related to characterization of computing
system workloads. Topics of interest include (but are not limited to):
Characterization of applications in areas including
o Search engines, e-commerce, web services, databases, file/application servers
o Embedded, mobile, multimedia, real-time, 3D-Graphics, gaming, telepresence
o Life sciences, bioinformatics, scientific computing, finance, forecasting
o Machine Learning, Analytics, Data mining
o Security, reliability, biometrics
o Grid and Cloud computing
o Emerging big data applications
Characterization of OS, Virtual Machine, middleware and library behavior
o Virtual machines, Websphere, .NET, Java VM, databases
o Graphics libraries, scientific libraries
Characterization of system behavior, including
o Operating system and hypervisor effects and overheads
o Hardware accelerators (GPGPU, XML, crypto, etc)
o User behavior and system-user interaction
o Impacts of scale-up and scale-out of systems, applications, and inputs
o Instrumentation methodologies for workload verification and characterization
o Techniques for accurate analysis/measurement of production systems
Implications of workloads in design issues, such as
o Power management, reliability, security, performance
o Processors, memory hierarchy, I/O, and networks
o Design of accelerators, FPGA’s, GPU’s, etc.
o Novel architectures (non-Von-Neumann)
Benchmark creation, analysis, and evaluation issues, including
o Multithreaded benchmarks, benchmark cloning
o Profiling, trace collection, synthetic traces
o Validation of benchmarks
Analytical and abstract modeling of program behavior and systems
Emerging and future workloads
o Transactional memory workloads; workloads for multi/many-core systems
o Stream-based computing workloads; web2.0/internet workloads;
cyber-physical workloads
For further information, please contact the General or Program Chair:
   General Chair
         Huiyang Zhou, NC State University ( )
    Program Chair
         Lixin Zhang, Institute of Computing Technology,
Chinese Academy of Sciences    (
         Lingjia Tang, University of Michigan    (