Call for Tutorials and Workshops: ISPASS 2015

Submitted by Kelly Shaw
January 15, 2015

Submitted by Kelly Shaw
ISPASS 2015 Call for Tutorial and Workshop Proposals

Call for Tutorial Proposals

Tutorial proposals are solicited for ISPASS-2015. Tutorials will be
held on March 29 in Philadelphia, PA.

Proposals for both half- and full-day tutorials are solicited on any
topic that is relevant to the ISPASS audience. Tutorials that focus on
workload characterization and analysis tools and techniques that
enable research across layers of the computational stack are strongly

In previous years, tutorials seeking to achieve any of the following
goals have been particularly successful:
* Describe an important piece of research/experimental infrastructure.
* Educate the community on an emerging topic.

Submission deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

Proposals should provide the following information:
* Title of the tutorial
* Presenter(s) and contact information
* Proposed duration (full day, half day)
* 1-2 paragraph abstract suitable for tutorial publicity
* 1 paragraph biography per presenter suitable for tutorial publicity
* Short description (for evaluation). This should include:
– Tutorial scope and objectives
– Topics to be covered
– Target audience
– If the tutorial has been held previously, the location
(i.e., conference), date, and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton ( with the subject
“ISPASS 2015 Tutorial Proposal”. Submissions will be acknowledged via


Call for Workshop Proposals

Workshop proposals are solicited for ISPASS-2015. Workshops will be
held on March 29 in Philadelphia, PA.

Proposals related to power/performance analysis and workload
characterization as it relates to computer architecture, operating
systems, programming languages/compilers in current and emerging areas
such as datacenters and cloud computing, systems based on non-volatile
memory technologies, mobile technologies, large scale data analysis,
smart infrastructure, and extreme scale computing are encouraged.

Submission Deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

Please include in your proposal:
* Title of the workshop
* Organizers and their affiliations
* Sample call for papers
* Duration – Half-Day or Full Day
* If the workshop was previously held, the location
(conference), date, and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton ( with the subject
“ISPASS 2015 Workshop Proposal”. Submissions will be acknowledged via

New Book: A Primer on Hardware Prefetching

Submitted by Shane Clyburn

Submitted by Shane Clyburn
I am pleased to announce the latest title in Morgan & Claypool’s
series on Computer Architecture:

A Primer on Hardware Prefetching
Babak Falsafi, EPFL, Switzerland
Thomas F. Wenisch, University of Michigan
Paperback ISBN: 9781608459520, $30.00
eBook ISBN: 9781608459537
May 2014, 67 pages

Since the 1970’s, microprocessor-based digital platforms have been
riding Moore’s law, allowing for doubling of density for the same
area roughly every two years. However, whereas microprocessor
fabrication has focused on increasing instruction execution rate,
memory fabrication technologies have focused primarily on an increase
in capacity with negligible increase in speed. This divergent trend
in performance between the processors and memory has led to a
phenomenon referred to as the “Memory Wall.”

To overcome the memory wall, designers have resorted to a hierarchy
of cache memory levels, which rely on the principal of memory access
locality to reduce the observed memory access time and the
performance gap between processors and memory. Unfortunately,
important workload classes exhibit adverse memory access patterns
that baffle the simple policies built into modern cache hierarchies
to move instructions and data across cache levels. As such, processors
often spend much time idling upon a demand fetch of memory blocks
that miss in higher cache levels. Prefetching—predicting future memory
accesses and issuing requests for the corresponding memory blocks in
advance of explicit accesses—is an effective approach to hide memory
access latency. There have been a myriad of proposed prefetching
techniques, and nearly every modern processor includes some hardware
prefetching mechanisms targeting simple and regular memory access
patterns. This primer offers an overview of the various classes of
hardware prefetchers for instructions and data proposed in the
research literature, and presents examples of techniques incorporated
into modern microprocessors.

Call for Papers: PPoPP 2015

Submitted by Antoniu Pop
February 7 to February 11, 2015

Submitted by Antoniu Pop
20th ACM SIGPLAN Symposium on Principles and Practice of Parallel
Programming (PPoPP’15)
February 2015 – San Francisco Bay Area

PPoPP is the forum for leading work on all aspects of parallel
programming, including foundational and theoretical aspects,
techniques, languages, compilers, runtime systems, tools, and
practical experiences. In the context of the symposium, “parallel
programming” encompasses work on concurrent and parallel systems
(multicore, multithreaded, heterogeneous, clustered systems,
distributed systems, grids, clouds, and large scale machines). Given
the rise of parallel architectures into the consumer market (desktops,
laptops, and mobile devices), PPoPP is particularly interested in work
that addresses new parallel workloads, techniques, and tools that
attempt to improve the productivity of parallel programming, and work
towards improved synergy with such emerging architectures. Specific
topics of interest include (but are not limited to):
+ Parallel programming theory and models
+ Formal analysis and verification
+ Parallel programming languages
+ Compilers and runtime systems for parallel and heterogeneous systems
+ Task-parallel libraries
+ Parallel application frameworks
+ Software productivity for parallel programming
+ Middleware for parallel systems
+ Performance analysis, debugging and optimization
+ Development, analysis, or management tools
+ Parallel algorithms
+ Parallel applications
+ Concurrent data structures
+ Synchronization and concurrency control
+ Software engineering for parallel programs
+ Fault tolerance for parallel systems
+ Software for heterogeneous architectures
+ Programming tools for parallel and heterogeneous systems
+ Parallelism in non-scientific workloads: web servers, search,
analytics, cloud computing

Papers should report on original research relevant to parallel
programming, and should contain enough background materials to make
them accessible to the entire parallel programming research community.

Papers describing experiences should indicate how they illustrate
general principles; papers about parallel programming foundations
should indicate how they relate to practice. Poster submissions should
meet similar criteria for originality and relevance, but may present
emerging ideas or results that are not yet sufficiently developed for
a full paper.

All submissions must be made electronically through the conference web
site. Abstracts must include contact information, the full list of
authors and their affiliations, and a description (100-400 words) of
the anticipated content of the paper. Full paper submissions must be
in PDF formatted for US lettersize paper. They must not exceed 10
pages (all inclusive) in standard ACM two-column conference format
(preprint mode, with page number). Templates for ACM format are
available for Microsoft Word, and LaTeX at (use the 9 pt
template). Over-length submissions will not be accepted. Submissions
will be judged on correctness, relevance, originality, significance,
and clarity.

Paper submission is double-blind to reduce reviewer bias against or
for authors or institutions. Thus, the submissions cannot include
author names, institutions or hints based on references to prior
work. If authors are extending their own work, they need to reference
and discuss the past work in third person, as if they were extending
someone else’s research. We realize that for some papers it will still
reveal authorship, but as long as an effort was made to follow these
guidelines, the submission will not be penalized. Authors must
identify any conflicts-of-interest with PC members and external review
committee members, as defined here: (ACM SIGPLAN policy).

Poster submissions must conform to the same format restrictions, but
may not exceed 2 pages in length. Paper submissions that are not
accepted for regular presentations will automatically be considered
for posters; authors who do not want their paper considered for the
poster session should indicate this in their abstract
submission. Two-page summaries of posters will be included in the
conference proceedings.

PPoPP 2015 will be co-located with HPCA 2015 and CGO 2015 in the San
Francisco Bay Area (exact location to be announced shortly). Authors
should carefully consider the difference in focus of the conferences
when deciding where to submit a paper.

Important dates:
Abstract submission: September 5, 2014
Full paper submission: September 12, 2014
Author response period: October 28-30, 2014 (Tentative)
Notification of acceptance: November 10, 2014

General Chair
Albert Cohen, INRIA

Program Chair
David Grove, IBM Research

Call for Papers: ISPASS 2015

Submitted by Kelly Shaw
September 19, 2014 at 24:00

Submitted by Kelly Shaw
2015 IEEE International Symposium on Performance Analysis of Systems and

Philadelphia, PA
March 2015

Abstracts Due: September 19, 2014
Full Submissions Due: September 26, 2014

The IEEE International Symposium on Performance Analysis of Systems and
Software provides a forum for sharing advanced academic and industrial
research work focused on performance analysis in the design of
computer systems and software. Authors are invited to submit
previously unpublished work for possible presentation at the
conference. Papers are solicited in fields that include the

* Performance and power evaluation methodologies
– Analytical modeling
– Statistical approaches
– Tracing and profiling tools
– Simulation techniques
– Hardware (e.g. FPGA) accelerated simulation
– Hardware performance counter architectures
– Power/Temperature/Variability/Reliability models for computer systems
– Micro-benchmark based hardware analysis techniques

* Performance and power analysis
– Metrics
– Bottleneck identification and analysis
– Visualization

* Power/Performance analysis of commercial and experimental hardware
– General-purpose microprocessors
– Multi-threaded, multi-core and many-core architectures
– Accelerators and graphics processing units
– Embedded and mobile systems
– Enterprise systems and data centers
– Supercomputers
– Computer networks

* Power/Performance analysis of emerging workloads and software
– Software written in managed languages
– Virtualization and consolidation workloads
– Internet-sector workloads
– Embedded, multimedia, games, telepresence
– Bioinformatics, life sciences, security, biometrics

* Application and system code tuning and optimization

* Confirmations or refutations of important prior results

In addition to research papers, we also welcome tool papers. The
conference is an ideal forum to publicize new tools to the
community. Tool papers will be judged primarily on their potentially
wide impact and use than on their research contribution. Tools in any
of the above fields of interest are eligible.

See for submission details.

Paper abstract submission: September 19, 2014
Full submission: September 26, 2014
Rebuttal: December 3-4, 2014
Notification: December 11, 2014
Final paper due: January 31, 2015

Benjamin C. Lee, Duke University

Jose Renau, UC Santa Cruz

Alaa Alameldeen
Fred Chong
Stijn Eyerman
Ilya Ganusov
Kanad Ghose
Joseph Greathouse
Andrew Hilton
Michael Huang
Chris Hughes
Russ Joseph
Ulya R. Karpuzcu
Omer Khan
Nam Sung Kim
Jason Mars
Albert Meixner
Ghokan Memik
Andreas Moshovos
David Penry
Vijay Janapa Reddi
Bronis de Supinski
Lingjia Tang
Radu Teodorescu
Devesh Tiwari
David Wentzlaff
Walid Najjar

Kelly Shaw, University of Richmond

Nadeem Malik, IBM

Houman Homayoun, George Mason University

Mike Ferdman, Stonybrook University

Drew Hilton, Duke University

Mark Hempstead, Drexel University

Suzanne Rivoire, Sonoma State University

Rajeev Balasubramonian, University of Utah
Lieven Eeckhout, Ghent University
Craig Chase, University of Texas
David Brooks, Harvard University
Lizy John, University of Texas
Nadeem Malik, IBM
Pradip Bose, IBM Research
Nasr Ullah, Samsung
David Albonesi, Cornell University
Sandhya Dwarkadas, University of Rochester
Vijayalakshmi Srinivasan, IBM Research

Call for Papers: ParCo2015 Edinburgh

Submitted by Mark Sawyer
September 1 to September 4, 2015

Submitted by Mark Sawyer
The University of Edinburgh is hosting the International Conference on Parallel
Computing (ParCo) from 1 – 4 September 2015. This is the latest in the series
of biennial ParCo conferences that started in Berlin, 1983. This makes ParCo
one of the longest running international conferences on parallel computing.
Over the years, the conference has established itself as the foremost platform
for exchanging know-how on the newest parallel computing strategies,
technologies,methods, and tools.

The Call for Papers can be found here:

Aims and Scope
The aim of the conference is to give an overview of the state of the art of the
developments, applications, and future trends in parallel computing for the
whole range of platforms. The conference addresses all aspects of parallel
computing, including applications, hardware and software technologies as well
as languages and development environments.

Topic Areas:

Section 1: Algorithms

Design, analysis, and implementation of parallel algorithms in science and
engineering, focusing on issues such as

– Scalability and speedup
– Efficient utilization of the memory hierarchy
– Communication and synchronization
– Data Management and Exploration
– Energy Efficiency.

The parallel computing aspects should be emphasized.

Section 2: Software and Architectures

Software engineering for developing and maintaining parallel software, including

– Parallel programming languages, compilers, and environments
– Tools and techniques for generating reliable and efficient parallel code
– Testing and debugging techniques and tools
– Best practices of parallel computing on multicore, manycore, and stream

Software, architectures and operating systems for all types of parallel
computers may be considered, including multicores, GPU accelerators, FPGA
reconfigurable systems, high-end machines and cloud computing.

Section 3: Applications

The application of parallel computing to solve all types of business,
industrial, scientific, and engineering problems using high-performance
computing technologies, in particular:

– Applications of high-end computers, including exascale
– Applications of multicore / manycore processors
– Applications for heterogeneous systems, including FPGAs, GPUs, etc.
– Cloud and Grid computing applications
– Data intensive (Big Data) analytics and applications.


The scientific programme consists of invited and contributed papers as well as
mini-symposia covering special topics.Papers are presented in parallel sessions
with 20 minutes available per presentation, with an additional five minutes for
discussion.A special session for young researchers as well as an industrial
session and an exhibition are planned.

Contributions :


Contributed papers in English are called for. Extended abstracts of at least
two pages should be submitted in electronic form by 28 February 2015.
Proposals are to be submitted in .pdf-format.

Abstracts should clearly describe the contents of the proposed paper. The
relevance and originality of the contribution must be described and the most
important references included.

At most five relevant keywords must be supplied. Also indicate the preferred
topic area (section 1, 2 or 3) from the list given above.

Submission of paper proposals:

Paper proposals can be submitted using ConfTool at Authors are required to register with the
system before they can enter their proposals.

Full (draft) papers of accepted proposals are due by 31 July 2015.


Proposals for organising a mini-symposium are called for. Such proposals should

– The proposed title of the symposium
– The name and affiliation(s) of the organiser(s)
– A short outline of the contents
– The planned number of papers.

Proposals for organising a mini-symposium can be submitted by 31 March 2015
to the conference office. For any questions about the organisation of a
mini-symposium please contact the conference office.


Extended abstracts of papers: 28 Feb 2015
Proposals for mini-symposia: 31 Mar 2015
Notification of acceptance for presentation at conference: 15 May 2015
Submission of full (draft) papers: 31 Jul 2015
Notification of inclusion of full papers in the proceedings: 30 Sep 2015


The conference proceedings will be published after the conference.

An invitation to authors to present a paper at the conference is based on an
extended abstract or draft paper. Thus, the presentation of a paper at the
conference does not imply an automatic acceptance of the presented paper for
publication in the conference proceedings. All papers presented at the
conference will be refereed at or after the conference. Only accepted papers
will be published.

All papers presented as part of mini-symposia will be considered for
publication in the proceedings. This will be done in liaison with
the organiser(s) of the respective mini-symposium.

Conference Organisation:

ParCo2015 is organised by the non-profit foundation ParCo Conferences in
cooperation with The University of Edinburgh, Scotland, UK.

Conference Committee Chair Gerhard Joubert (Germany/Netherlands)
Program Committee Chair: Mark Parsons (UK)
Organising Committee Chairs: Hugh Leather (UK), Mark Sawyer (UK)
Finance Chair: Frans Peters (Netherlands)


Call for Workshops: CGO 2015

Submitted by Christophe Dubach
February 7 to February 11, 2015

Submitted by Christophe Dubach
CGO 2015

*** Call for Workshops and Tutorials ***

February 7-11, 2015 – San Francisco Bay Area

The 2015 ACM/IEEE International Symposium on Code Generation and
Optimization (CGO), located in San Francisco Bay Area, is looking for proposals
for co-located workshops and tutorials that will run before the main
conference. Please see the CGO web site for more details:

The deadline for submitting a workshop or tutorial proposal is
September 15, 2014 but interested parties are encouraged to contact the
workshops and tutorial chair as soon as possible.

==== Proposal Submission Guidelines ====

If you wish to organize a workshop or tutorial (1/2 or 1 day), please e-mail a
proposal to with the following details :

* Title of the workshop or tutorial
* Organizers and their affiliations
* Brief description of topics to be covered
* Expected duration; i.e., 1/2 day or full day
* Expected attendance (stats from previous years are ideal)
* URL of workshop/tutorial information (if available)
* Any special requirements the workshop or tutorial may have

One free registration will be made available per workshop/tutorial accepted
(could be used for one of the organizers or for one invited speaker)

==== Important Dates ====

* Proposal Submission : September 15, 2014
* Notification : October 1, 2014
* Workshop/Tutorial date : February 7-8, 2015

==== Workshop and Tutorial Chair ====

Christophe Dubach,

Call for Nominations: MICRO Test of Time Award 2014

Submitted by Onur Mutlu
September 15, 2014

Submitted by Onur Mutlu
MICRO Test of Time Award — Call for Nominations (deadline: September 15, 2014)

PDF link:
Eligible papers:

The Micro Test-of-Time (ToT) Award Committee is soliciting nominations
for the first Micro ToT Award to be given at the International
Symposium on Microarchitecture in December 2014, to be held in
Cambridge, United Kingdom. This is a new award that is established to
recognize the most influential papers published in past Micro
conferences that have had significant impact in the field.

For this special first year when the award is to be given the first
time (2014), the award will recognize at most ten papers that were
published at Micro conferences held between 1968-1992 (1968 and 1992
inclusive). After this “bootstrapping” year, at steady state, the
award will recognize an influential Micro paper whose influence is
still felt 18-22 years after its initial publication. In other words,
in each future year N (where N >= 2015), the award will be given to
one paper that was published at Micro conferences in any of the years
N-22, N-21, N-20, N-19, or N-18. Paper nominations will not carry over.
That is, a paper nominated in 2015 (e.g.) will not be carried-over
for nomination in 2016 or later — it must be renominated while

We invite anyone to submit a nomination by the deadline of September 15,
2014. Only papers published at the Micro conferences held between
1968-1992 (1968 and 1992 inclusive) will be considered for this year’s
award. Please submit your nomination to The following describes
the nomination criteria, how to submit a nomination and the selection

Which papers are eligible for the 2014 Micro ToT (Test of Time) Award?
Only papers published at Micro conferences that happened between
1968-1992 (1968 and 1992 inclusive).

An almost-complete list of eligible papers is at:

Who can nominate a paper?
Anyone can nominate a paper except for the author or co-author of the
nominated paper.

Is there a limit on the number of papers one person can nominate?
Yes. One can nominate up to 5 papers from all eligible papers. These
five papers can be published at any eligible year.

When is the last day to submit a nomination?
Nominations must be received by September 15, 2014.

How should a nomination be submitted?
Nominations must be submitted via email to

What should be included in the nomination email?
All of the following must be included in the nomination email. Only
one paper can be nominated in a single email.

1. The title of the nominated paper
2. The author list of the nominated paper
3. Which Micro the nominated paper appeared in? (It must be a Micro in
between 1968-1992, inclusive)
4. A 100-word (maximum) nomination statement, describing why the paper
deserves the Test-of-Time Award
5. The name of the nominator
6. The title of the nominator
7. The affiliation(s) of the nominator
8. The relationship of the nominator to the authors (please describe
any relationship in any way)

Selection process
Micro ToT Award committee will evaluate all submitted nominations to
select at most ten papers for the 2014 Micro ToT (Test of Time) Award.
The committee will produce an award citation for each selected paper.
A strict conflict of interest policy will be followed. If a ToT Award
Committee Member has a conflict of interest with a paper that is
nominated, the member will recuse himself/herself from the discussion
process and a substitute is placed in.

Who are the current Micro ToT Award committee members?
Rich Belgard, Chair
Pradip Bose
Bill Mangione-Smith
Onur Mutlu
Uri Weiser

When will the award be announced and given?
The award will be presented to the authors of the selected paper(s) at
the Awards Ceremony during the International Symposium on
Microarchitecture in December 2014, to be held in Cambridge, United
Kingdom. The Awards Ceremony will be a dedicated half-hour.
Awardees are not expected to make a presentation.

What does the award consist of?
An award certificate and peer recognition.

Call for Papers: ASPLOS 2015

Submitted by Engin Ipek
March 14 to March 18, 2015

Submitted by Engin Ipek
20th International Conference on
Architectural Support for Programming Languages and Operating Systems

Istanbul, Turkey, March 14-18, 2015

ASPLOS is the premier forum for multidisciplinary systems research spanning
computer architecture and hardware, programming languages and compilers,
operating systems and networking, as well as applications and user interfaces.
The 2015 conference will be held in Istanbul, Turkey, a city where two
continents meet on the blue waters of the Bosphorus to offer an abundance of
unique natural, historical, cultural, and culinary experiences.

Like its predecessors, ASPLOS 2015 invites papers on ground-breaking research
at the intersection of at least two ASPLOS disciplines:
architecture, programming languages, operating systems, and related areas.
Non-traditional topics are especially encouraged.
The importance of cross-cutting
research continues to grow as we grapple with the end of Dennard scaling,
the explosion of big data, scales ranging from ultra-low power wearable devices
to exascale parallel and cloud computers, the need for sustainability, and
increasingly human-centered applications.

ASPLOS embraces systems research that directly targets these new problems
in innovative ways.
The research may target diverse goals such as performance, energy and thermal
efficiency, resiliency, security, and sustainability.
The review process will be sensitive to the challenges of
multidisciplinary work in emerging areas.

Areas of interest include, but are not limited to:
-Emerging platforms at all scales, from embedded to cloud
-Heterogeneous multicore architectures and accelerators
-Systems for enabling parallelism at an extreme scale
-Non-traditional computing systems
-Systems that address social, educational, and environmental challenges
-Programming models and compilation for existing and emerging platforms
-Managing, storing, and computing on big data
-Memory and storage technologies and architectures
-Power, energy, and thermal management
-Security, reliability, and availability
-Verification and testing, and their impact on design

Papers should be submitted for double-blind review
following the submission guidelines available at the conference website –

Important dates:

Abstracts July 31, 2014
Full Paper Submissions Aug 7, 2014
Author Response Period Oct 20-22, 2014
Notification Nov 10, 2014
Final Copy Deadline Jan 14, 2015*

*Proceedings will be available in the
ACM DL up to two weeks prior to the conference

General Co-Chairs: Kemal Ebcioglu, Global Supercomputing Corporation
Ozcan Ozturk, Bilkent University

Program Chair: Sandhya Dwarkadas, University of Rochester

Program Committee:
Rajeev Balasubramonian, U. Utah / HP Labs
Andrew Baumann, Microsoft
Ricardo Bianchini, Rutgers U. / Microsoft
Hans Boehm, Google
John Carter, IBM Research
Calin Cascaval, Qualcomm
Yunji Chen, ICT, Chinese Academy of Sciences
Andrew Chien, U. Chicago / Argonne
Alan Cox, Rice U.
John Criswell, U. Rochester
Angela Demke, Brown U. Toronto
Peter Druschel, Max Planck Inst. for Software Systems (MPI-SWS)
Sandhya Dwarkadas, U. Rochester (chair)
Jason Flinn, U. Michigan
Antonio Gonzalez, UPC Barcelona
R. Govindarajan, IISc, India
Dan Grossman, U. Washington
Boris Grot, U. Edinburgh
Erik Hagersten, Uppsala U.
Mary Hall, U. Utah
Kim Hazelwood, Google
Gernot Heiser, NICTA / UNSW, Australia
Hillery Hunter, IBM Research
Alvin Lebeck, Duke U.
David Meisner, Facebook
Jason Nieh, Columbia U.
Mark Oskin, U. Washington
Steve Reinhardt, AMD
Jennifer Sartor, Ghent U.
Xipeng Shen, College of William and Mary
Tatiana Shpeisman, Intel
Asia Slowinska, Vrije U. Amsterdam
Serdar Tasiran, Koc U., Turkey
Dan Tsafrir, Technion
Jeffrey Vetter, Oak Ridge National Lab / Georgia Tech.
Yuanyuan Zhou, UC San Diego

Publicity Chairs:
Onur Mutlu, Carnegie Mellon University
Engin Ipek, University of Rochester
Atakan Dogan, Anadolu University

Registration Chair:
Ulya Karpuzcu, University of Minnesota, Twin Cities

Finance Chair:
Smail Niar, University of Valenciennes

Industry Chairs:
Emre Ozer, ARM
Bugra Gedik, Bilkent University

Workshop Chairs:
Alper Buyuktosunoglu, IBM
Augusto Vega, IBM
Haluk Topcuoglu, Marmara University

Publication Chair:
Seda Ogrenci Memik, Northwestern University

Poster/Lightning Session Chair:
Arrvindh Shriraman, Simon Fraser University

Local Arrangements Chair:
Alper Sen, Bogazici University

Travel Grant Chair:
Suleyman Tosun, Ankara University

Web Chair:
Oguz Ergin, TOBB University

Tutorial Chairs:
Osman Unsal, Barcelona Supercomputing Center
Serdar Tasiran, Koc University

Student Advocates:
Gurhan Kucuk, Yeditepe University

Steering Committee:
Sarita Adve, UIUC
Rajeev Balasubramonian, U. Utah
Ras Bodik, UC Berkeley
Doug Burger, Microsoft
George Candea, EPFL
Al Davis, U. Utah
Jeremy Gibbons, Oxford University
Vivek Sarkar, Rice University
David Wood, U. Wisconsin

Call for Papers: HPCA 2015

Submitted by Lingjia Tang
February 7 to February 11, 2015

Submitted by Lingjia Tang
The 21st IEEE International Symposium on High Performance Computer Architecture

Feb 2015 — Bay Area, CA
[HPCA 2015 will be co-located with CGO-2015 and PPoPP-2015]

The IEEE International Symposium on High Performance Computer Architecture
(HPCA) provides a high-quality forum for scientists and engineers to
present their latest research findings in this rapidly changing field.
Authors are invited to submit papers on all aspects of high-performance
computer architecture. Topics of interest include, but are not limited to:

• Processor, cache, and memory architectures
• Parallel computer architectures
• Multicore architectures
• Impact of technology on architecture
• Power-efficient architectures and techniques
• Dependable/secure architectures
• High-performance I/O systems
• Embedded and reconfigurable architectures
• Interconnect and network interface architectures
• Architectures for cloud-based HPC and data centers
• Innovative hardware/software trade-offs
• Impact of compilers and system software on architecture
• Performance modeling and evaluation
• Architectures for emerging technology and applications

Regular papers.
Authors should submit an abstract by Friday, September 5, 2014, 11:59 PM CET.
They should submit the full version of the paper by
Friday, September 12, 2014, 11:59 PM CET. No extensions will be granted.
The full version should be a PDF file that follows the submission guidelines
available at the conference website. Papers should be submitted for
double-blind review. We anticipate selecting a Best Paper award.
All papers will be evaluated based on their novelty, fundamental insight,
experimental evaluation, and potential for long-term impact; new-idea papers
are encouraged. Submission issues should be directed to the
program chair at

Industry track papers.
HPCA has the tradition of hosting an Industrial Paper Session presenting
novel results and insights from industry. Industry track papers go through
a separate review process. Questions about the industry track should be
directed to the industrial session chair at

Accepted regular and industry track papers will be published in the
conference proceedings distributed to conference attendees.
Papers will also be uploaded to IEEE Xplore.

Workshops and tutorials.
Workshop and tutorial submissions should be directed to the
workshop and tutorial chair at

Important dates
Regular papers
• Abstract deadline: September 5, 2014, 11:59 PM CET
• Paper deadline: September 12, 2014, 11:59 PM CET
• Rebuttal: October 27-29, 2014
• Notification of paper outcome: November 10, 2014
• Final reviews and comments sent out: November 13, 2014
Industry track papers
• Paper deadline: October 1, 2014, 11:59 PM CET
• Author notification: November 10, 2014
Workshops and tutorials
• Workshop and tutorial proposals due: October 3, 2014

Sponsored by the IEEE Computer Society TC on Computer Architecture (TCCA).

General Chair
Michael Taylor, UCSD

Program Chair
Lieven Eeckhout, Ghent University

Program Committee
Erik Altman, IBM
Abhishek Bhattacharjee, Rutgers
David Black-Schaffer, Uppsala
Pradip Bose, IBM
David Brooks, Harvard
Fred Chong, UCSB
John Demme, Columbia
Natalie Enright Jerger, Toronto
Hadi Esmaeilzadeh, GATech
Stijn Eyerman, Ghent
Babak Falsafi, EPFL
Paolo Faraboschi, HP
Wilson Fung, UBC
Antonio Gonzalez, Intel/UPC
Boris Grot, Edinburgh
Engin Ipek, Rochester
Aamer Jaleel, Intel
John Kim, KAIST
James Laudon, Google
Benjamin Lee, Duke
Mikko Lipasti, Wisconsin
Gabriel Loh, AMD
José Martinez, Cornell
Jason Mars, Michigan
Margaret Martonosi, Princeton
Andreas Moshovos, Toronto
Onur Mutlu, CMU
Satish Narayanasamy, Michigan
Mike O’Connor, NVidia
Moin Qureshi, GATech
Ravi Rajwar, Intel
Vijay Janapa Reddi, UTAustin
Daniel Sanchez, MIT
Jack Sampson, Penn State
Arrvindh Shriraman, Simon Fraser
André Seznec, INRIA
Dan Sorin, Duke
Viji Srinivasan, IBM
Samantika Subramaniam, Intel
Mohit Tiwari, UTAustin
Josep Torrellas, UIUC
Dean Tullsen, UCSD
Tom Wenisch, Michigan
Lixin Zhang, ICT

Industrial Session Committee Chair
Sudhanva Gurumurthi, AMD Research/University of Virginia

Finance Chair
Reese Nguyen, Keker & Van Nest LLP

Local Arrangements Chairs
José Renau, UC Santa Cruz
Behnam Robatmili, Qualcomm

Publicity Chair
Lingjia Tang, Michigan

Publications Chair
Henry Hoffmann, University of Chicago

Registration Chair
Joe Devietti, U Penn

Workshop/Tutorial Chair
Jack Sampson, Penn State

Student Travel Grants Chair
Christopher Batten, Cornell

Web Chair
Jason Mars, Michigan

Steering Committee
Laxmi Bhuyan, University of California, Riverside
Natalie Enright Jerger, University of Toronto
David Kaeli, Northeastern University
Tao Li, University of Florida
Yale Patt, University of Texas at Austin
Josep Torrellas, University of Illinois, Urbana-Champaign
Dean Tullsen, University of California, San Diego
Lixin Zhang, ICT/Chinese Academy of Sciences

Call for papers: ACM e-Energy 2015

Submitted by Vincenzo Mancuso
July 14 to July 17, 2015

Submitted by Vincenzo Mancuso
Preliminary Call for Papers

ACM e-Energy 2015

Bangalore, India

June 2015 (Exact date TBC)

As countries round the world rally to reduce their carbon emissions
in the face of rising energy costs, there is a growing need to
research computing and communication technologies that will support
smarter and more sustainable energy solutions (e.g., Smart Grid).
Such technologies, measure, monitor and control energy systems
(e.g., micro-grids and electric vehicles); inform and shape human
demand; aid in the prediction, deployment, storage and control
of energy resources; and determine how utilities, generators,
regulators, and consumers measure, analyze, and collectively control
system elements. In turn, the exponential growth in the deployment
of communication and computing technologies has made them large-scale
energy consumers. Therefore, new architectures, technologies and
systems are being developed and deployed to make computing and
networked system more energy efficient.

The Sixth International Conference on Future Energy Systems
(ACM e-Energy), to be held in Bangalore, India in June 2015,
aims to be the premier venue for researchers working in the
broad areas of computing and communication for smart energy
systems (including the smart grid), and in energy efficient
computing and communication systems. By bringing together
researchers from a range of disciplines in a high-quality
single-track conference with significant opportunities for
individual and small-group interaction, it will serve as a major
forum for presentations and discussions that will shape the
future of this area.

We solicit high-quality papers in the areas of computing and
communication for the Smart Grid and energy-efficient computing
and communications. We welcome submissions describing theoretical
advances as well as system design, implementation and
experimentation. ACM e-Energy is committed to a fair, timely, and
thorough review process providing authors of submitted papers with
sound and detailed feedback.

Topics covered:


. Advances in monitoring and control of smart homes and buildings

. Sensing, monitoring, control, and management of energy systems

. Energy-efficient computing and communication, including
energy-efficient data centers

. The impact of storage integration on the smart grid

. Electric Vehicle monitoring and control

. Distribution and transmission network control techniques

. Microgrid and distributed generation management and control

. Modeling, control, and architectures for renewable energy
generation resources

. Smart grid communication architectures and protocols

. Privacy and security of smart grid infrastructure

. Innovative pricing and incentives for demand-side management

. Novel technologies to enhance reliability and robustness of
energy systems

. HCI for energy monitoring, management, and awareness

. User studies and behavioral change enabled by computing and
communication technologies

. Data analytics for the smart grid and energy-efficient systems



Two type of contributions are solicited:

. Full papers, up to 12 pages in ACM double-column format, should
present original theoretical and/or experimental research in any of
the areas listed above that has not been previously published,
accepted for publication, or is not currently under review by
another conference or journal.

.. Poster/demo descriptions, up to 2 pages in ACM double-column
format showcasing works-in-progress; accepted posters/demos will
be presented at the conference. Topics of interest are the same
as research topics listed above. Preference will be given to
posters/demos where the primary contribution is from one or
more students.

Papers will be judged in terms of technical quality and originality.

Important Dates: (TBC)


Submission Deadline: January 2015

Reviews and Notification: March-April 2015

Conference: June 2015

General Co-Chairs:


Shivkumar Kalyanaraman (IBM Research, AUS)

Deva P. Seetharam (IBM Research, INDIA)

TPC Co-chairs:


Mani Srivastava (UCLA)

Sarvapali (Gopal) Ramchurn ( U. Southampton)