Call for Papers: Workshop on Near-Data Processing

Submitted by Boris Grot
December 13, 2014

Submitted by Boris Grot

Co-located with MICRO-47
Cambridge, UK

Paper submissions due: Friday October 17, 2014
Notification: Tuesday November 4th, 2014
Final Paper Due: Monday December 8th, 2014

Computing in large-scale systems is shifting away from the traditional
compute-centric model to a much more data-centric one. This transition is
driven by the evolving nature of what computing comprises, no longer dominated
by the execution of arithmetic and logic calculations but instead dominated by
large data volume and the cost of moving data to the locations where
computations are performed. Data movement impacts performance,
energy-efficiency and reliability. These trends are leading to changes in the
computing paradigm driven by the notion of moving computation to the data in a
so-called Near-Data Processing approach, which seeks to perform computations
in the most appropriate location based on where data resides and what needs to
be done with it.

This workshop is intended to bring together experts from academia and industry
to share advances in the development of Near-Data Processing systems
principles, with emphasis on large-scale systems. Topics of interest include
but are not limited to:
– Analysis of applications illustrating the potential for Near-Data Processing
– System and software architectures for Near-Data Processing
– Programming models for distributed and heterogeneous infrastructures
driven by location of the data
– Processing/Memory/Storage architectures and microarchitectures for Near-Data
– Performance evaluation of Near-Data Processing systems and subsystems
– Energy-efficiency and reliability analysis and evaluation of Near-Data

Two kinds of papers are invited:
– Technical papers (4-6 pages) with preliminary results.
– Position papers (3 pages maximum) on directions for research and development.


Rajeev Balasubramonian , University of Utah
Boris Grot , University of Edinburgh
Jaime Moreno , IBM TJ Watson Research Center
Ravi Nair , IBM TJ Watson Research Center


Rajeev Balasubramonian , University of Utah
Boris Grot , University of Edinburgh
Jeff Draper , USC/ISI
Ron Dreslinski, University of Michigan
Maya Gokhale , Lawrence Livermore National Laboratory
Nuwan Jayasena, AMD Research
Jaime Moreno , IBM TJ Watson Research Center
Arrvindh Shriraman , Simon Fraser University

Further details and submission instructions available at

Call for Papers: ASPLOS SRC 2015

Submitted by Onur Mutlu
November 14, 2014

Submitted by Onur Mutlu
ACM Student Research Competition

Important Dates
Abstract submission: 11:59pm CST Friday November 14, 2014
Acceptance notification: 11:59pm CST Friday January 16, 2015
Poster Session for Accepts: Monday March 16, 2015
Presentations for Finalists: Monday March 16, 2015

ASPLOS is the premier forum for multidisciplinary systems research
spanning computer architecture and hardware, programming languages and
compilers, operating systems and networking, as well as applications
and user interfaces. The 2015 conference will be held in Istanbul,
Turkey, a city where two continents meet on the blue waters of the
Bosphorus to offer an abundance of unique natural, historical,
cultural, and culinary experiences.

The 20th International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS) invites
participation in the ACM Student Research Competition (SRC). Sponsored
by ACM and Microsoft Research, the SRC is a forum for undergraduates
and graduate students to share their research results, exchange ideas,
and improve their communication skills while competing for
prizes. Students accepted to participate in the SRC are entitled to a
travel grant (up to $500) to help cover travel expenses. The top 3
undergraduate and graduate winners will receive all of the following

1. Monetary prizes of $500, $300, and $200, respectively.

2. An award medal (gold, silver or bronze) and a two-year
complimentary ACM membership with a subscription to ACM’s Digital

3. The names of the winners and their placement will be posted on the
ACM SRC web site.

4. In addition, the first place winner in each category
(undergraduate, graduate) will receive an invitation to participate in
the SRC Grand Finals, an on-line round of competitions among the first
place winners of individual conference-hosted SRCs. The top three
graduate and undergraduate Grand Finalists will receive an additional
$500, $300, and $200, respectively, along with Grand Finalist medals
(gold, silver, bronze). Grand Finalists and their advisors will be
invited to the Annual ACM Awards Banquet for an all-expenses-paid
trip, where they will be recognized for their accomplishments, along
with other prestigious ACM award winners, including the winner of the
Turing Award.

The SRC consists of two rounds: a poster session and a presentation
session. A panel of judges will select a number of finalists from the
poster session, who will be invited to the presentation session at
ASPLOS 2015 and compete for the prizes. The evaluation will be
concentrated on the quality of both visual and oral presentation, the
research methods, and the significance of contribution. You can find
more information on the ACM Student Research Competition site

A participant in the SRC must meet all following conditions:

* The participant must submit an up to 800-word abstract outlining the
content of a poster that is going to be presented during the

* The abstract must include the poster title, author names,
affiliations, and the name of the academic advisor.

* It should describe the research problem, motivation and background,
techniques and results, and the prospect for clearly and concisely
conveying the work in a poster format.

* It should state the novelty and contributions of the work

* The submission deadline is November 14th, 2014 at 23:59 CST.

* The abstract must have not appeared before. Novelty is one of the
criteria for selection.

* The abstract and the poster must be authored solely by the

* The participant can be from anywhere in the world, but must be an
ACM student member, and must maintain an undergraduate or graduate
student status as of November 14, 2014.

* In your submission, please indicate whether you are an undergraduate
or a graduate student.

* You may join ACM prior to entering. Basic student membership is $19
per year or less

For each accepted SRC poster, a one-page extended abstract in the ACM
format will be included in the ASPLOS 2015 conference proceedings. The
content, however, can be included in a future submission to other
conferences or journals.

For questions regarding the submission process, or for additional
information, clarifications, or questions, please contact the ACM
Student Research Competition Co-chairs, Eren Kursun
( and Gurhan Kucuk (

The ACM Student Research Competition at ASPLOS 2015 is sponsored by
the ACM and Microsoft Research.

Call for Papers: ACM SIGMETRICS 2015

Submitted by Niklas Carlsson
June 15 to June 19, 2015

Submitted by Niklas Carlsson
June 15-19, 2015
Portland, Oregon, USA


Abstract Registration: November 17, 2014 (11:59pm EST)
Paper Submission: November 24, 2014 (11:59pm EST)
Notification: February 17, 2015
Conference: June 15-19, 2015


ACM SIGMETRICS 2015 solicits papers on the development and application
of state-of-the-art, broadly applicable analytic, simulation and
measurement-based performance evaluation techniques. Of particular
interest is work that presents new performance evaluation methods or
that creatively applies previously developed methods to make
predictions about, or gain insights into key design trade-offs in,
computer and networked systems. The main conference will be held from
June 16-18, 2015. There will be workshops and tutorials on June 15,
2015. There will also be workshops on June 19, 2015. Submission details
will be published shortly on this Web site. All accepted regular papers
will include oral (short or long time slot, single track)
presentations. We foresee a continuation in the recent organic growth
of the size of ACM SIGMETRICS, while still keeping it a single track
venue. All regular papers will be allocated 12 pages in the conference
proceedings. In addition, poster papers will be accepted (2 pages in
proceedings, no oral presentation).

The notion of performance is broadly construed including considerations
of speed and scalability as well as reliability, availability,
sustainability and manageability of systems. We encourage both
theoretical contributions and also submissions relating to real world
empirical studies or focusing on implementation and experimental

Quantitative design and evaluation studies of:

* Computer and communication networks, protocols and algorithms
* Wireless, mobile, ad-hoc and sensor networks
* Computer architectures, multi-core processors, memory systems and
storage systems/networks
* Operating systems, file systems and databases
* Virtualization, data centers, distributed and cloud computing
* Social networks, multimedia systems, service-oriented architectures
and Web services
* Energy-efficient computing systems
* Real-time and fault-tolerant systems
* Mobile and personal computing systems
* Large-scale operational systems
* Software systems and enterprise applications
* Smart power grids
* Emerging technologies
* Data processing

Methodologies, formalisms, solution techniques and algorithms for:

* Performance, scalability, power and reliability analysis
* Sustainability analysis and power management
* Capacity planning, resource allocation, run time management and
* Anomaly detection, system measurement, monitoring and forecasting
* Analytical modeling techniques and model validation
* System measurement, monitoring and forecasting
* Workload characterization and benchmarking
* Quality of service, total cost of ownership and pricing
* Experimental design, statistical analysis, simulation
* Performance-oriented applications of game theory, economics and
control theory
* Big data, machine learning and signal processing


Papers should not exceed 12 pages double column including figures,
tables, and references in standard ACM format. In addition, a 2-page
appendix is permitted, where the appendix does not count towards the
original 12 pages. Papers must be submitted electronically in printable
pdf form. Templates for the standard ACM format can be found at this

Both strict and alternate styles are acceptable for submission. No
changes to margins, spacing, or font sizes are allowed from those
specified by the style files. Papers violating the formatting
guidelines will be returned without review.

All submissions will be reviewed using a double-blind review process.
The identity of authors and referees will not be revealed to each
other. To ensure blind reviewing, author names and affiliations should
not appear in the paper; bibliographic references should be made in
such a way as to preserve author anonymity. Accepted papers will appear
in the conference proceedings published in the ACM Performance
Evaluation Review.

Warning: It is ACM policy not to allow double submissions, where the
same paper is submitted to more than one conference/journal
concurrently. Any double submissions detected will be immediately
rejected from all conferences/journals involved.

Bill Lin, UCSD
Jun (Jim) Xu, Georgia Tech

Sudipta Sengupta, Microsoft Research
Devavrat Shah, Massachusetts Institute of Technology

Mohammad Alizadeh Insieme Networks
Lakshmi Bairavasundaram Datrium
Randall Berry Northwestern University
Sem Borst Eindhoven U. of Technology and
Alcatel-Lucent Bell Labs
Ana Busic INRIA
John C S Lui CUHK
Y Charlie Hu Purdue University
Mark Crovella Boston University
Peter Desnoyers Northeastern University
Ayalvadi Ganesh University of Bristol
Javad Ghaderi Columbia University
Philip Gibbons Intel Research Pittsburgh
Leana Golubcik University of Southern California
Varun Gupta University of Chicago
Bruce Hajek UIUC
Mor Harchol-Balter CMU
John Hasenbein UT Austin
Kyomin Jung Seoul National University
Ramana Kompella Purdue University
Peter Marbach University of Toronto
Athina Markopoulou UC Irvine
Vishal Misra Columbia University
Eytan Modiano MIT
Jason Nieh Columbia University
Sewoong Oh UIUC
Alexandre Proutiere France Telecom
Konstantinos Psounis University of Southern California
Kavita Ramanan Brown University
Rhonda Righter UC Berkeley
Dan Rubenstein Columbia University
Saswati Sarkar University of Pennsylvania
Srinivas Shakkottai Texas A&M University
Mayank Sharma IBM T. J. Watson Research Center
Jinwoo Shin KAIST
Evgenia Smirni College of William and Mary
Alex Snoeren UCSD
Mark Squillante IBM T. J. Watson Research Center
Alexander (Sasha) Stolyar Alcatel-Lucent Bell Labs
Ryan Stutsman Microsoft Research
Lakshmi Subramanian NYU
Vijay Subramanian Northwestern University
Y C Tay National University of Singapore
Don Towsley University of Massachusetts Amherst
Milan Vojnovic Microsoft Research
Neil Walton University of Amsterdam
Jia Wang AT&T Research
Adam Wierman California Institute of Technology
Lau Wing-Cheong CUHK
Cathy Xia Ohio State University
Kuang Xu Stanford
Tauhid Zaman MIT
Li Zhang IBM T. J. Watson Research Center
Zhi-Li Zhang University of Minnesota
Yuan Zhong Columbia University
Gil Zussman Columbia University
Bert Zwart CWI

New Book: FPGA-Accelerated Simulation of Computer Systems

Submitted by David Schlangen

Submitted by David Schlangen
I am pleased to announce the latest title in Morgan & Claypool’s
series on Computer Architecture:

FPGA-Accelerated Simulation of Computer Systems
Hari Angepat, The University of Texas and Microsoft
Derek Chiou, Microsoft and The University of Texas
Eric S. Chung, Microsoft
James C. Hoe, Carnegie Mellon University
Paperback ISBN: 9781627052139, $35.00
eBook ISBN: 9781627052146
August 2014, 80 pages
To date, the most common form of simulators of computer systems are
software-based running on standard computers. One promising approach
to improve simulation performance is to apply hardware, specifically
reconfigurable hardware in the form of field programmable gate arrays
(FPGAs). This manuscript describes various approaches of using FPGAs
to accelerate software-implemented simulation of computer systems and
selected simulators that incorporate those techniques. More precisely,
we describe a simulation architecture taxonomy that incorporates a
simulation architecture specifically designed for FPGA accelerated
simulation, survey the state-of-the-art in FPGA-accelerated simulation,
and describe in detail selected instances of the described techniques.

Series: Synthesis Lectures on Computer Architecture
Series Editor: Margaret Martonosi, Princeton University
Founding Editor Emeritus: Mark D. Hill, University of Wisconsin, Madison

Use of this book as a course text is encouraged, and the texts may be
downloaded without restriction by members of institutions that have
licensed accessed to the Synthesis Digital Library of Engineering and
Computer Science or after a one-time fee of $30.00.

This book can also be purchased in print from Amazon and other
booksellers worldwide.

Amazon URL:

Available titles and subject areas in the Synthesis Digital Library:

Information for librarians, including pricing and license:

Please contact to request your desk copy.

New Book: Adiabatic Quantum Computation and Quantum Annealing, by

Submitted by David Schlangen

Submitted by David Schlangen
I am pleased to announce the latest title in Morgan & Claypool’s
series on Quantum Computing:

Adiabatic Quantum Computation and Quantum Annealing: Theory and Practice
Catherine C. McGeoch, Amherst College
Paperback ISBN: 9781627053358, $40.00
eBook ISBN: 9781627053365
July 2014, 93 pages

Adiabatic quantum computation (AQC) is an alternative to
the better-known gate model of quantum computation. The
two models are polynomially equivalent, but otherwise
quite dissimilar: one property that distinguishes AQC
from the gate model is its analog nature. Quantum
annealing (QA) describes a type of heuristic search
algorithm that can be implemented to run in the “native
instruction set” of an AQC platform. D-Wave Systems Inc.
manufactures {quantum annealing processor chips} that
exploit quantum properties to realize QA computations in
hardware. The chips form the centerpiece of a novel
computing platform designed to solve NP-hard optimization
problems. Starting with a 16-qubit prototype announced in
2007, the company has launched and sold increasingly larger
models: the 128-qubit D-Wave One system was announced in
2010 and the 512-qubit D-Wave Two system arrived on the
scene in 2013. A 1,000-qubit model is expected to be
available in 2014. This monograph presents an introductory
overview of this unusual and rapidly developing approach
to computation. We start with a survey of basic principles
of quantum computation and what is known about the AQC
model and the QA algorithm paradigm. Next we review the
D-Wave technology stack and discuss some challenges to
building and using quantum computing systems at a
commercial scale. The last chapter reviews some
experimental efforts to understand the properties and
capabilities of these unusual platforms. The discussion
throughout is aimed at an audience of computer scientists
with little background in quantum computation or in physics.

Series: Synthesis Lectures on Quantum Computing
Series Editor: Marco Lanzagorta, U.S. Naval Research Labs
Jeffrey Uhlmann, University of Missouri-Columbia

Use of this book as a course text is encouraged, and the texts may be
downloaded without restriction by members of institutions that have licensed
accessed to the Synthesis Digital Library of Engineering and Computer Science
or after a one-time fee of $30.00.

This book can also be purchased in print from Amazon and other booksellers
Amazon URL:

Available titles and subject areas in the Synthesis Digital Library:

Information for librarians, including pricing and license:

Please contact to request your desk copy.

Call for Papers: ISCA-42

Submitted by Lisa Wu
June 13 to June 17, 2015

Submitted by Lisa Wu
Call for Papers – ISCA-42
The 42nd Annual International Symposium on Computer Architecture
Portland, OR, USA June 13-17, 2015

*** Important Dates:

Abstract Deadline: November 18, 2014, 11:59:59PM EST
Final Paper Deadline: November 25, 2014, 11:59:59PM EST
Rebuttal Period: February 10-13, 2015
Author Notification: March 6, 2015

The International Symposium on Computer Architecture is the premier forum for
new ideas and experimental results in computer architecture. The
conference specifically seeks particularly forward-looking and novel
submissions. Papers are solicited on a broad range of topics, including (but
not limited to):
• Processor, memory, and storage systems architecture
• Parallel and multi-core systems
• Data-center scale computing
• Architectures for handheld and mobile devices
• Application-specific, reconfigurable, or embedded architectures
• Accelerator-based architectures
• Architectures for security and virtualization
• Power and energy efficient architectures
• Interconnection networks
• Instruction, thread, and data-level parallelism
• Dependable architectures
• Architectural support for programming productivity
• Network processor and router architectures
• Architectures for emerging technologies and applications
• Effect of circuits and technology on architecture
• Architecture modeling and simulation methodology
• Performance evaluation and measurement of real systems

*** Sponsored by ACM SIGARCH IEEE TCCA
General Chair
Debbie Marr, Intel

Program Chair
 David Albonesi, Cornell University

Steering Committee
Mark Horowitz, Stanford University
David Kaeli, Northeastern University
Steve Keckler, Nvidia, University of Texas Austin
Avi Mendelson, Technion
Margaret Martonosi, Princeton University
Josep Torrellas, University of Illinois at Urbana-Champaign
David A. Wood, University of Wisconsin-Madison
Pen-Chung Yew, University of Minnesota
Antonia Zhai, University of Minnesota

Call for Papers: ISPASS 2015

Submitted by Kelly Shaw
September 19, 2014

Submitted by Kelly Shaw
2015 IEEE International Symposium on Performance Analysis of Systems and

Philadelphia, PA
March 29-31, 2015

Abstracts Due: September 19, 2014
Full Submissions Due: September 26, 2014

The IEEE International Symposium on Performance Analysis of Systems and
Software provides a forum for sharing advanced academic and industrial
research work focused on performance analysis in the design of
computer systems and software. Authors are invited to submit
previously unpublished work for possible presentation at the
conference. Papers are solicited in fields that include the

* Performance and power evaluation methodologies
– Analytical modeling
– Statistical approaches
– Tracing and profiling tools
– Simulation techniques
– Hardware (e.g. FPGA) accelerated simulation
– Hardware performance counter architectures
– Power/Temperature/Variability/Reliability models for computer systems
– Micro-benchmark based hardware analysis techniques

* Performance and power analysis
– Metrics
– Bottleneck identification and analysis
– Visualization

* Power/Performance analysis of commercial and experimental hardware
– General-purpose microprocessors
– Multi-threaded, multi-core and many-core architectures
– Accelerators and graphics processing units
– Embedded and mobile systems
– Enterprise systems and data centers
– Supercomputers
– Computer networks

* Power/Performance analysis of emerging workloads and software
– Software written in managed languages
– Virtualization and consolidation workloads
– Internet-sector workloads
– Embedded, multimedia, games, telepresence
– Bioinformatics, life sciences, security, biometrics

* Application and system code tuning and optimization

* Confirmations or refutations of important prior results

In addition to research papers, we also welcome tool papers. The
conference is an ideal forum to publicize new tools to the
community. Tool papers will be judged primarily on their potentially
wide impact and use than on their research contribution. Tools in any
of the above fields of interest are eligible.

See for submission details.

Paper abstract submission: September 19, 2014
Full submission: September 26, 2014
Rebuttal: December 3-4, 2014
Notification: December 11, 2014
Final paper due: January 31, 2015

Benjamin C. Lee, Duke University

Jose Renau, UC Santa Cruz

Alaa Alameldeen, Intel
Fred Chong, University of California – Santa Barbara
Stijn Eyerman, Ghent University
Ilya Ganusov, Xilinx
Kanad Ghose, Binghamton University
Joseph Greathouse, AMD
Andrew Hilton, Duke University
Michael Huang, Rochester University
Chris Hughes, Intel
Russ Joseph, Northwestern University
Ulya R. Karpuzcu, University of Minnesota
Omer Khan, University of Connecticut
Nam Sung Kim, University of Wisconsin – Madison
Krishna Malladi, Samsung
Jason Mars, University of Michigan
Albert Meixner, Google
Gokhan Memik, Northwestern University
Andreas Moshovos, University of Toronto
David Penry, Brigham Young University
Vijay Janapa Reddi, University of Texas – Austin
Bronis de Supinski, Lawrence Livermore National Laboratory
Lingjia Tang, University of Michigan
Radu Teodorescu, Ohio State University
Devesh Tiwari, Oak Ridge National Laboratory
David Wentzlaff, Princeton University
Walid Najjar, University of California – Riverside

Kelly Shaw, University of Richmond

Nadeem Malik, IBM

Houman Homayoun, George Mason University

Mike Ferdman, Stonybrook University

Drew Hilton, Duke University

Mark Hempstead, Drexel University

Suzanne Rivoire, Sonoma State University

Rajeev Balasubramonian, University of Utah
Lieven Eeckhout, Ghent University
Craig Chase, University of Texas
David Brooks, Harvard University
Lizy John, University of Texas
Nadeem Malik, IBM
Pradip Bose, IBM Research
Nasr Ullah, Samsung
David Albonesi, Cornell University
Sandhya Dwarkadas, University of Rochester
Vijayalakshmi Srinivasan, IBM Research