Call for Participation: MICRO-47

Submitted by Ronald Dreslinski
http://www.microarch.org/micro47/
December 13 to December 17, 2014

Submitted by Ronald Dreslinski
http://www.microarch.org/micro47/

The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47)
December 13-17, 2014
Cambridge, UK

Micro-47 registration portal is live NOW.
You can take advantage of early bird registration until Nov. 12!

The International Symposium on Microarchitecture (MICRO) is the premier forum
for the presentation and discussion of new ideas in microarchitecture,
compilers, hardware/software interfaces, and design of advanced computing
and communication systems. The goal of MICRO is to bring together researchers
in the fields of microarchitecture, compilers, and systems for technical
exchange. The MICRO community has enjoyed having close interaction between
academic researchers and industrial designers ­ we aim to continue and
strengthen this longstanding tradition at the 47th MICRO in Cambridge, England.

On behalf of the Micro47 organization team, we look forward to seeing you
in Cambridge.

Tool Release: MIAOW Opensource GPU Hardware RTL and FPGA

Submitted by Karu Sankaralingam
http://www.miaowgpu.org

Submitted by Karu Sankaralingam
http://www.miaowgpu.org

MIAOW (pronounced “me-ow”) [Many-core Integrated Accelerator Of
Waterdeep/Wisconsin] is an open source GPU created by the Vertical
Research Group at the University of Wisconsin-Madison led by Professor
Karu Sankaralingam. Based on the publicly released Southern
Islands ISA by AMD, MIAOW implements a compute unit suitable for
performing architecture analysis and experimentation with GPGPU
workloads. In addition to the Verilog HDL composing the compute unit,
MIAOW also includes a suite of unit tests and benchmarks for
regression testing.

A primary motivator for MIAOW’s creation is the belief that software
simulators of hardware such as CPUs and GPUs often miss many subtle
aspects that can skew the performance, power, and other quantitative
results that they produce. As an actual implementation of a GPU’s
logic, the Vertical Research Group believes that MIAOW can be a useful
tool in producing not only more accurate quantitative results when
benchmarking GPGPU workloads but also provide context for the
architectural complexities of actually implementing newly proposed
algorithms and designs that are intended to improve performance or
other desired characteristics.

It must be emphasized that MIAOW represents a GPU’s compute unit. It
does not possess the auxiliary logic required to produce actual
graphical output nor does it have logic to connect it to a specific
memory interface or system bus. These extensions can be developed and
we would welcome outside contributors for such efforts, but as MIAOW
was created as a research tool their presence was not an absolute
necessity in running benchmarks and experiments.

MIAOW is licensed under the 3-clause BSD license.

MIAOW developers:
Raghuraman Balasubramanian
Mario Paulo Drumond
Vinay Gangadhar
Ziliang Guo
Chen-Han Ho
Cherin Joseph
Jaikrishnan Menon
Robin Paul
Sharath Prasad
Pradip Vallathol

Call for Papers: IEEE Transactions on Computers Special Issue on Transparent Computing

Submitted by Jimmy Cuo
http://www.computer.org/cms/Computer.org/transactions/cfps/cfp_tcsi_tc.pdf
October 1 to November 30, 2014

Submitted by Jimmy Cuo
http://www.computer.org/cms/Computer.org/transactions/cfps/cfp_tcsi_tc.pdf

Call for Papers: Special Issue in IEEE Transactions on Computers on “Transparent Computing”

At 2012 Intel Developer Forum, San Francisco, Renee James, senior Vice
President and General Manager of Intels Software Services Group, delivered a
keynote speech “Next Era of Computing: Transparent Computing”, in which she
pointed out that “(transparent computing) represents for us the direction
that we believe we need to go as an industry. And it’s the next step really
beyond ubiquitous computing.”

The basic idea behind transparent computing is simple: give developers just
one basic platform on which to develop their applications, and make it
possible for these applications to run on any other platform. A formal model
of transparent computing has been proposed, which is a cloud-style paradigm.
As described by James, transparent computing “is really about allowing
experiences to seamlessly cross across different platforms, both
architectures and operating system platform boundaries”. The key idea of
transparent computing is to logically separate hardware and software
(including operating systems) and to separate computation and memory.
Specifically, all the required software and data are centralized on central
servers, and streamed to the clients on demand to carry out the computing
tasks leveraging the local CPU and memory resources. Compared with other
cloud computing models, transparent computing has the following desired
features: (1) user and application transparency; (2) heterogeneous OS
support; (3) streaming delivery; (4) supports of various devices; and (5)
enhanced security.

Transparent computing has proposed new challenges in the research of
computer software and systems:

From user’s perspectives:
_ user transparency (in paradigms, systems, applications, and services);
_ user machine’s efficiency and security;
_ privacy protection and system reliability; and
_ local resource scheduling and management.

From system’s perspectives:
_ standardized software-hardware interface;
_ device and user virtualization;
_ data consistence and security;
_ multiple-user system performance; and
_ operating system modularization.

This journal Special Issue in the IEEE Transaction on Computers will provide
the scientific community a dedicated forum for discussing new research and
development in transparent computing. The Special Issue invites original
research papers that make significant contributions to the state-of-the-art
that advance the fundamental understanding, technologies, concepts, and
applications in transparent computing.

IMPORTANT DATES:
Open for Submissions in ScholarOne Manuscripts: October 31, 2014
Closed for Submission: November 30, 2014
Results of First Round of Review: January 25, 2015
Submission of Revised Manuscripts: February 20, 2015
Results of Second Round of Review: March 15, 2015
Publication Materials Due: March 31, 2015

SUBMISSION GUIDELINES:
Prospective authors are invited to submit their manuscripts electronically
after the open for submissions date, adhering to the IEEE Transactions on
Computers guidelines at

http://www.computer.org/portal/web/tc/author

Please submit your papers through the online system
(https://mc.manuscriptcentral.com/tc-cs) and be sure to select the special
issue or special section name. Manuscripts should not be published or
currently submitted for publication elsewhere. Please submit only full
papers intended for review, not abstracts, to the ScholarOne portal. If
requested, abstracts should be sent by e-mail to the Guest Editors directly.

GUEST EDITORS:
Jianer Chen, Texas A&M University, USA, chen@cse.tamu.edu
Yaoxue Zhang, Central South University, P.R. China, zyx@csu.edu.cn

Call for Papers: IEEE Micro Special Issue on Heterogeneous Computing

Submitted by jayvant anantpur

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/heterogeneous-computing–july-august-2015

Call for Papers: IEEE Micro Special Issue on Heterogeneous Computing

Guest Co-Editors:
Dean Tullsen (UCSD)
Ravishankar Iyer (Intel)

Submissions due: Jan 16, 2015
Publication date: July-August 2015

Heterogeneity is widely accepted as a fruitful avenue to improve performance
and power/energy/thermal-efficiency in the face of continued technology
miniaturization (Moore’s Law) and slowed supply voltage reduction (end of
Dennard scaling). Heterogeneity comes in many flavors ranging from Systems-
on-Chip (SoCs) with specialized hardware accelerators, to hybrid CPU/GPU
architectures, to single-ISA heterogeneous multi-cores with different core
types, to multi-ISA heterogeneous multi-cores in which different core types
implement different Instruction-Set Architectures (ISA). Architects have
explored and built heterogeneous architectures across a broad spectrum of
computing devices including embedded systems, mobile devices, datacenters,
and High-Performance Computing (HPC) supercomputers. While the performance
and power/energy opportunities have been outlined, important challenges are
yet to be studied regarding architecture, accelerators, hardware/software
interface, run-time support, compilation, programming models, and performance
evaluation. The goal of this Special Issue is to present the latest state-of-the-art
results in the broad area of heterogeneous computing systems.

Areas of interest include, but are not limited to:
-Heterogeneous architectures, including:
   o System-on-Chip (SoC) with accelerators
   o CPU/GPU systems
   o Single-ISA heterogeneous multi-cores
   o Multi-ISA heterogeneous multi-cores
-Roadmaps and commercial trends in heterogeneous architectures
-Trade-offs in performance, power, energy, thermal, reliability, code
portability and programmability due to heterogeneity
-Case studies of heterogeneous architectures in embedded system design, mobile
computing, HPC, data centers, etc.
-Accelerator architectures and interfaces
-Platform support for heterogeneous and accelerator architectures
-Hardware/software interactions on heterogeneous architectures, including OS
scheduling and compilation
-Programming models and runtime support for heterogeneous architectures
-Workloads particularly suited for heterogeneity
-Performance evaluation of heterogeneous architectures
-Experiences with real heterogeneous platforms

Submission procedure:
Log onto IEEE CS Manuscript Central ( https://mc.manuscriptcentral.com
/micro-cs) and submit your manuscript. Please direct questions to the IEEE
Micro magazine assistant (micro­ma@computer.org) regarding the submission
site. For the manuscript submission, acceptable file formats include
Microsoft Word and PDF. Manuscripts should not exceed 5,000 words including
references, with each average­size figure counting as 150 words toward this
limit. Please include all figures and tables, as well as a cover page with
author contact information (name, postal address, phone, fax, and e­mail
address) and a 200­word abstract. Submitted manuscripts must not have been
previously published or currently submitted for publication elsewhere, and all
manuscripts must be cleared for publication. All previously published papers
must have at least 30% new content compared to any conference (or other)
publication. Accepted articles will be edited for structure, style, clarity,
and readability. For more information, please visit the IEEE Micro Author
Center (http://www2.computer.org/portal/web/peerreviewmagazines/acmicro).

Important dates:
Initial submissions due: Jan 16, 2015
Author notification: March 2, 2015
Revised papers due: March 20, 2015
Final version due: April 23, 2015
Publication timeframe: July-August 2015

Questions?
Contact the Guest Co-Editors Dean Tullsen (tullsen@ucsd.edu) and Ravi Iyer
(ravishankar.iyer@intel.com), or the Editor-in-Chief Lieven Eeckhout
(lieven.eeckhout@ugent.be)

Call for Papers: IEEE Micro General Interest 2015

Submitted by jayvant anantpur

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/2015-cfp—general-interest

Call for Papers: IEEE Micro General Interest 2015

IEEE Micro seeks general-interest submissions for publication in upcoming 2015
issues. The submissions should present the design, performance, or application
of microcomputer and microprocessor systems. Summaries of work in progress
and descriptions of recently completed work are most welcome, as are tutorials
and position statements.

IEEE Micro is a bimonthly magazine of the IEEE Computer Society that reaches an
international audience of computer designers, system integrators, and users.
IEEE Micro publishes 6 to 8-page papers that are slightly less technical and
less quantitative than top-conference and archival journal papers, while being
insightful, slightly more qualitative, with a high tutorial value, and up to
date with current trends. IEEE Micro attracts a broad readership among both
academics and practitioners who want to keep up with new results and trends in
the field of computer architecture.

Areas of interest include, but are not limited to:
-Processor, memory, and storage systems architecture
-Parallel and multicore systems
-Data-center scale computing
-Architectures for handheld and mobile devices
-Application-specific, reconfigurable, or embedded architectures
-Heterogeneous and accelerator-based architectures
-Neuromorphic computing architectures
-Architectures for security and virtualization
-Power and energy efficient architectures
-Interconnection networks
-Instruction, thread, and data-level parallelism
-Dependable architectures
-Architectural support for programming productivity
-Network processor and router architectures
-Architectures for emerging technologies and applications
-Effect of circuits and technology on architecture
-Architecture modeling and simulation methodology
-Performance evaluation and measurement of real systems
-Design of high-performance and low-power chips

Submission procedure:
Log onto IEEE CS Manuscript Central (https://mc.manuscriptcentral.com/micro-
cs) and submit your manuscript. Please direct questions to the IEEE Micro
magazine assistant (micro-ma@computer.org) regarding the submission site.
For the manuscript submission, acceptable file formats include Microsoft Word
and PDF. Manuscripts should not exceed 5,000 words including references, with
each average¬size figure counting as 150 words toward this limit. Please
include all figures and tables, as well as a cover page with author contact
information (name, postal address, phone, fax, and e¬mail address) and a
200¬-word abstract. Submitted manuscripts must not have been previously
published or currently submitted for publication elsewhere, and all manuscripts
must be cleared for publication. All previously published papers must have at
least 30% new content compared to any conference (or other) publication.
Accepted articles will be edited for structure, style, clarity, and
readability. For more information, please visit the IEEE Micro Author Center
(http://www2.computer.org/portal/web/peerreviewmagazines/acmicro).

The submission site is continuously open. Papers of general interest appear in
upcoming issues as space allows, or are grouped in the Nov/Dec 2015 issue.

Questions?
Contact the Editor-in-Chief, Lieven Eeckhout, at lieven.eeckhout@ugent.be.

Call for Papers: Special Issue on Optimization of Parallel Scientific Applications with Accelerated HPC

Submitted by Javier Garcia
http://www.journals.elsevier.com/computers-and-electrical-engineering/call-for-papers/cfp-optimization-of-parallel-scientific-applications-with-ac
November 7, 2014

Submitted by Javier Garcia
http://www.journals.elsevier.com/computers-and-electrical-engineering/call-for-papers/cfp-optimization-of-parallel-scientific-applications-with-ac

Call for Papers: Special Issue on Optimization of Parallel Scientific
Applications with Accelerated HPC
International Journal of Computers & Electrical Engineering

GENERAL SCOPE:

Since 2011, the most powerful supercomputers systems
ranked in the Top500 list have been hybrid systems composed
of thousands of nodes that includes CPUs and accelerators,
as Xeon Phi and GPUs. Programming and deploying applications
on those systems is still a challenge due to complexity of the
system and the need to mix several programming interfaces
(MPI, CUDA, Intel Xeon Phi) in the same application. This special
issue is aimed at exploring the state of the art of developing applications
in accelerated massive HPC architectures, including practical issues
of hybrid usage models with MPI, OpenMP, and other accelerators
programming models. The idea is to publish novel work on the use
of available programming interfaces (MPI, CUDA, Intel Xeon Phi)
and tools for code development, application performance optimizations,
application deployment on accelerated systems, as well as the
advantages and limitations of accelerated HPC systems. Experiences
with real-world applications, including scientific computing, numerical
simulations, healthcare, energy, data-analysis, etc. are also encouraged.

The topics of specific interest for this Special Issue include the following:

– Hybrid and heterogeneous programming with MPI and accelerators
– Performance evaluation of scientific applications based on accelerators
– Automatic performance tuning of scientific applications with accelerators
– Integrating accelerators on existing HPC run-times and middlewares
– Energy efficient HPC solutions based on accelerators
– Storage cache solutions based on SSD accelerators
– Real-world scientific and engineering applications using accelerated HPC

SUBMISSION INFORMATION:

Submitted papers must be written in English and must describe
original research that has not been published, and is not currently
under review by other journals or for conferences. The papers should
be submitted via journal’s submission website and should adhere to
standard formatting requirements. The author guidelines for preparation
of manuscripts are available online. Manuscripts should be no longer
than 20 pages, including the title page, abstract, or references. All
manuscripts and any supplementary material should be submitted
through the Elsevier Editorial System (EES) at the location indicated.
The authors must choose the Article Type “SI-hpc” at the time of
submission.

The special issue will invite extended versions of the best papers
of ESAA 2014, “International Workshop on Enhancing Parallel
Scientific Applications with Accelerated HPC” at the EuropMPI/Asia
2014 on September 2014 in Kyoto, but it is also open to other authors.
For work that has been published previously in the workshop or conference,
it is required that submissions to the special issue have at least 30%
new content/contribution. Each submission will be peer-reviewed to
ensure a very high quality of papers selected for the Special Issue.

IMPORTANT DATES:

Submission of papers: November 1st 2014
Communication of first round of review results: January 15th 2015
Submission of revised manuscript: February 15th 2015
Notification of acceptance: April 1st 2015
Final paper due: May 1st 2015
Publication date: August 2015

GUEST EDITORS:

Jesus Carretero,
Universidad Carlos III de Madrid, Spain
Email: Jesus.carretero@uc3m.es

Javier Garcia-Blas,
Universidad Carlos III de Madrid, Spain
E-mail: fjblas@arcos.inf.uc3m.es

Maya Neytcheva,
Uppsala University, Sweden
E-mail: Maya.Neytcheva@it.uu.se

Call for Papers: VEE 2015

Submitted by Angela Demke Brown
http://vee.sigops.org/vee15
November 25, 2014

Submitted by Angela Demke Brown
http://vee.sigops.org/vee15

VEE’15: 11th ACM international conference on Virtual Execution Environments
Co-located with ASPLOS 2015
March 14-15, 2015
Istanbul, Turkey

SUBMISSION DEADLINE:
Tuesday, November 25, 2014 (11:59pm, PST)

The 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution
Environments (VEE’15) brings together researchers and practitioners from
different computer systems domains to interact and share ideas in order to
advance the state of the art of virtualization and broaden its applicability.

VEE’15 accepts both full-length and short papers. Both types of submissions are
reviewed to the same standards and differ primarily in the scope of the ideas
expressed. Short papers are limited to half the space of full-length papers.
The program committee will not accept a full paper on the condition that it is
cut down to fit in a short paper slot, nor will it invite short papers to be
extended to full length. Submissions will be considered only in the category
in which they are submitted.

We invite authors to submit original papers related to virtualization across
all layers of the software stack down to the microarchitectural level.
Topics of interest include (but are not limited to):
– virtualization support for programs and programmers;
– architecture support for virtualization;
– operating system support for virtualization;
– compiler and programming language support for virtualization;
– runtime system support for virtualization;
– virtual I/O, storage, and networking;
– memory management;
– management technologies for virtual environments;
– performance analysis and debugging for virtual environments;
– virtualization technologies applied to specific problem domains such as
cloud, HPC, realtime, power management, and security.

IMPORTANT DATES:
Submission Deadline: Tuesday, November 25, 2014 (11:59pm, PST)
Author Rebuttal: Friday – Saturday, January 23 – 24, 2015
Author Notification: Wednesday, January 28, 2015
Camera-ready Deadline: Thursday, February 12, 2015 (11:59pm, PST)

GENERAL CHAIR:
Ada Gavrilovska (Georgia Institute of Technology)

PROGRAM CO-CHAIRS:
Angela Demke Brown (University of Toronto)
Bjarne Steensgaard (Microsoft Research)

PROGRAM COMMITTEE:
Jonathan Appavoo (Boston University)
Haibo Chen (Shanghai Jiao Tong University)
Dilma Da Silva (Texas A&M University)
Amer Diwan (Google)
Daniel Frampton (Microsoft Research)
David Gregg (Trinity College Dublin)
David Grove (IBM Research)
Vishakha Gupta (Intel)
Tomas Kalibera (Purdue University)
Kenichi Kourai (Kyushu Institute of Technology)
Priya Nagpurkar (IBM Research)
Donald Porter (Stony Brook University)
Jennifer Sartor (Ghent University)
Ravi Soundararajan (VMWare)
Gael Thomas (LIP6)
Timothy Wood (GWU)

Call For Papers: ISCA 2015

Submitted by Lisa Wu
http://www.isca2015.org
June 13 to June 17, 2015

Submitted by Lisa Wu
http://www.isca2015.org

Call for Papers : ISCA 2015
The 42nd Annual International Symposium On Computer Architecture
Portland, OR, USA
June 13-17, 2015

IMPORTANT DATES:
Abstract Deadline: November 18, 2014, 11:59:59PM EST
Final Paper Deadline: November 25, 2014, 11:59:59PM EST
Rebuttal Period: February 10-13, 2015
Author Notification: March 6, 2015

The International Symposium on Computer Architecture is the premier forum for
new ideas and experimental results in computer architecture. The
conference specifically seeks particularly forward-looking and novel
submissions. Papers are solicited on a broad range of topics, including (but
not limited to):

•Processor, memory, and storage systems architecture
•Parallel and multi-core systems
•Data-center scale computing
•Architectures for handheld and mobile devices
•Application-specific, reconfigurable, or embedded architectures
•Accelerator-based architectures
•Architectures for security and virtualization
•Power and energy efficient architectures
•Interconnection networks
•Instruction, thread, and data-level parallelism
•Dependable architectures
•Architectural support for programming productivity
•Network processor and router architectures
•Architectures for emerging technologies and applications
•Effect of circuits and technology on architecture
•Architecture modeling and simulation methodology
•Performance evaluation and measurement of real systems

Sponsored by ACM SIGARCH IEEE Computer Society TCCA

General Chair
Debbie Marr, Intel

Program Chair
David Albonesi, Cornell University

Steering Committee
Mark Horowitz, Stanford University
David Kaeli, Northeastern University
Steve Keckler, Nvidia, University of Texas Austin
Avi Mendelson, Technion
Margaret Martonosi, Princeton University
Josep Torrellas, University of Illinois at Urbana-Champaign
David A. Wood, University of Wisconsin-Madison
Pen-Chung Yew, University of Minnesota
Antonia Zhai, University of Minnesota

Program Committee
Murali Annavaram, University of Southern California
Rajeev Balasubramonian, University of Utah / HP Labs
Christopher Batten, Cornell University
Ricardo Bianchini, Microsoft / Rutgers University
David Brooks, Harvard University
Doug Burger, Microsoft
Alper Buyuktosunoglu, IBM Research
John Carter, IBM Research
Luis Ceze, University of Washington
Derek Chiou, Microsoft / University of Texas at Austin
Fred Chong, University of California at Santa Barbara
Robert Colwell, Consultant
Bill Dally, NVIDIA / Stanford University
Lieven Eeckout, Ghent University
Mattan Erez, University of Texas at Austin
Babak Falsafi, EPFL
Michael Ferdman, Stony Brook University
Antonio Gonzalez, Universitat Politècnica de Catalunya
Sudhanva Gurumurthi, AMD / University of Virginia
James Hoe, Carnegie Mellon University
Wen-mei Hwu, University of Illinois at Urbana-Champaign
Engin Ipek, University of Rochester
Ravi Iyer, Intel
Natalie Enright Jerger, University of Toronto
Lizy John, University of Texas at Austin
David Kaeli, Northeastern University
Hsien-Hsin Lee, TSMC
Scott Mahlke, University of Michigan
Jason Mars, University of Michigan
José Martínez, Cornell University
Margaret Martonosi, Princeton University
Shubu Mukherjee, Cavium Networks
Parthasarathy (Partha) Ranganathan, Google
Scott Rixner, Rice University
Ronny Ronen, Intel
Eric Rotenberg, North Carolina State University
Karthikeyan Sankaralingam, University of Wisconsin-Madison
Simha Sethumadhavan, Columbia University
Yanos Sezeides, University of Cyprus
Tim Sherwood, University of California at Santa Barbara
Daniel Sorin, Duke University
Karin Strauss, Microsoft

Call for Papers: Workshop on Programmability Issues for Heterogeneous Multicores

Submitted by Oscar Palomar
http://research.ac.upc.edu/multiprog/
January 20, 2015

Submitted by Oscar Palomar
http://research.ac.upc.edu/multiprog/


Call for Papers: Eight Workshop on Programmability Issues for Heterogeneous
Multicores (MULTIPROG-2015)
Held in conjunction with the 10th International Conference on High-Performance
and Embedded Architectures and Compilers (HiPEAC)
Amsterdam, The Netherlands
January 20, 2015

GOAL OF THE WORKSHOP
Computer manufacturers have embarked on the many-core roadmap, promising to
add more and more cores/hardware threads on their chips. The ever-increasing
number of cores and heterogeneity in architectures has placed new burdens on
the programming community. Software needs to be parallelized and optimized for
accelerators such as GPUs in order to take advantage of the new breed of
multi-/many-core computers. As a result, progress in how to easily harness the
computing power of multi-core architectures is in great demand.

The eighth edition of the MULTIPROG workshop aims to bring together
researchers interested in programming models, runtimes, and computer
architecture. The workshop’s emphasis is on heterogeneous architectures and
covers issues such as:
– How can future parallel programming models improve software productivity?
– How should compilers, runtimes and architectures support programming
models and emerging applications?
– How to design efficient data structures and innovative algorithms?

MULTIPROG is intended for quick publication of early results, work-in-progress,
etc., and is not intended to prevent later publication of extended papers.
Informal proceedings with accepted papers will be made available at the
workshop.

TOPICS OF INTEREST
Papers are sought on topics including, but not limited to:
– Multi-core architectures
   o Architectural support for compilers/programming models
   o Processor (core) architecture and accelerators
   o Memory system architecture
   o Performance, power, temperature, and reliability issues
– Heterogeneous computing
   o Algorithms and data structures for heterogeneous systems
   o Applications for heterogeneous computing and real-time graphics
– Programming models for multi-core architectures
   o Language extensions
   o Run-time systems
   o Compiler optimizations and techniques
– Benchmarking of multi-/many-core architectures
   o Tools for discovering and understanding parallelism
   o Tools for understanding performance and debugging
   o Case studies and performance evaluation

IMPORTANT DATES
Final submission: October 24, 2014
Author notification: November 28, 2014

PAPER SUBMISSION
Submissions should not exceed 12 pages and should be formatted according to the
LNCS format for CS Proceedings. This limit includes text, figures, tables and
references.

Please use one of the templates below:
– Latex template:
ftp://ftp.springer.de/pub/tex/latex/llncs/latex2e/llncs2e.zip
– Word template:
ftp://ftp.springer.de/pub/tex/latex/llncs/word/splnproc1110.zip

Submission link: https://easychair.org/conferences/?conf=multiprog2015

ORGANIZERS
Miquel Pericàs, Chalmers University of Technology, Sweden
Vassilis Papaefstathiou, Chalmers University of Technology, Sweden
Oscar Palomar, Barcelona Supercomputing Center, Spain
Ferad Zyulkyarov, Barcelona Supercomputing Center, Spain

STEERING COMMITTEE
Eduard Ayguade, UPC/Barcelona Supercomputing Center, Spain
Benedict R. Gaster, Qualcomm, USA
Lee Howes, Qualcomm, USA
Per Stenstrom, Chalmers University of Technology, Sweden
Osman Unsal, Barcelona Supercomputing Center, Spain

PROGRAM COMMITTEE
Mats Brorsson, KTH Royal Institute of Technology, Sweden
Pascal Felber, University of Neuchatel, Switzerland
Roberto Giorgi, University of Siena, Italy
Hakan Grahn, Blekinge Institute of Technology, Sweden
Ali Jannesari, RWTH Aachen University, Germany
Paul Kelly, Imperial College of London, UK
Mikel Lujan, University of Manchester, UK
Vladimir Marjanovic, High Performance Computing Center Stuttgart, Germany
Tim Mattson, Intel, USA
Simon McIntosh-Smith, University of Bristol, UK
Avi Mendelson, Technion, Israel
Dimitris Nikolopoulos, Queen’s University of Belfast, UK
Andy Pimentel, University of Amsterdam, Netherlands
Oscar Plata, University of Malaga, Spain
Yanos Sazeides, University of Cyprus, Cyprus
Ruben Titos, Barcelona Supercomputing Center, Spain
Dongping Zhang, AMD, USA

Call for Papers: Workshop on Multi-Objective Many-Core Design

Submitted by Stefan Wildermann
https://www12.cs.fau.de/momac/
March 24, 2015

Submitted by Stefan Wildermann
https://www12.cs.fau.de/momac/

Call for Papers: Second International Workshop on Multi-Objective Many-Core Design (MOMAC)
in conjunction with International Conference on Architecture of Computing Systems (ARCS 2015)
Porto, Portugal, March 24, 2015

IMPORTANT DATES
Paper submission deadline: December 1, 2014
Notification of acceptance: January 16, 2015
Final version: February 16, 2015

ABOUT MOMAC
Semiconductor industry is hitting the utilization wall, resulting in
parallel and heterogeneous many-core architectures. Applications have
to exploit the available parallelism and heterogeneity to meet their
functional and non-functional requirements and to gain performance
improvements. A main challenge originates from many-cores promoting
highly dynamic usage scenarios as already observable in today’s “smart
devices”, where multiple and varying numbers of applications are
running at different points in time. As a consequence, providing
mapping of applications to processor cores which is optimal and
predictable with respect to performance, timing, energy consumption,
safety, security, etc. may not be guaranteed by static design-time
optimization alone. At the same time, pure run-time optimization may
result in unpredictable and non-optimal system states. This workshop
investigates this field of tension of run-time, design-time, and
hybrid design methodologies for the mapping of applications on
many-core systems, particularly addressing the aspect of multiple
conflicting objectives that drive the design.

This field of research includes numerous intermeshed aspects:
– Languages, Models, and Compilers: How to specify, analyze,
parallelize, and compile programs which support dynamic usage
scenarios in many-cores?
– Formal methods, Test, and Verification: How to analyze and verify
predictable execution of applications despite unforeseeable
run-time events?
– Optimization Techniques: Which design-time and run-time techniques
as well as combinations of them provide optimized and predictable
application mapping for many-cores?
– Architecture: Which architectural concepts are required to support
predictability, run-time management and (self-)optimization?

TOPICS OF INTEREST
Topics of interest include, but are not limited to:

Multiple Objectives and Predictability
– Performance
– Hard & Soft Real-time
– Energy Efficiency
– Fault Tolerance & Reliability
– Safety
– Security
– Scalability
– Flexibility

Specification
– Programming
– Modelling
– Parallelization
– Resource awareness

Design-time Optimization
– Multi-Objective Optimization
– Design Space Exploration
– Verification
– Profiling
– Performance Analysis

Run-time Optimization
– Resource Management
– Temperature and Power Management
– Decentralized vs Centralized Management
– Reconfigurable Computing
– Operating System
– Online Verification
– Auto-tuning
– Machine Learning

Architecture
– Architectural Predictability
– Reconfiguration
– Power Management
– Benchmarking
– Monitoring

SUBMISSION
Paper can be submitted as regular papers or as position papers.
Formats requirements:

– up to 8 pages (regular paper) IEEE style
– 4 pages (position paper) IEEE style: Preliminary and exploratory
work are welcome in this category, including wild & crazy ideas.
Authors submitting papers in this category must prepend
“Position Paper:” to the title of the submitted paper.

Papers are required to be in English using the IEEE style in A4 paper
size.

Full Paper submission until December 01, 2014 via EasyChair:
https://easychair.org/conferences/?conf=momac2015

All papers undergo a blind review process. Authors will be notified
until January 16, 2015. Final version is due to February 16, 2015.
All accepted papers will be published in the ARCS Workshop Proceedings
and are expected to be published online under IEEE Xplore.

LOCATION
MOMAC will be held conjunction with the 28th International Conference
on Architecture of Computing Systems (ARCS 2015), March 24-27,
2015 in Porto, Portugal.

ORGANIZERS
Stefan Wildermann (FAU, Germany, stefan.wildermann@fau.de)
Michael Glaß (FAU, Germany, michael.glass@fau.de)

PROGRAM COMMITTEE
Lars Bauer (Karlsruhe Institute of Technology (KIT), Germany)
Jens Gladigau (Robert Bosch GmbH, Germany)
Omar Hammami (ENSTA, France)
Markus Happe (ETH Zurich, Switzerland)
Christian Haubelt (University of Rostock, Germany)
Akash Kumar (National University of Singapore, Singapore)
Martin Lukasiewycz (TUM CREATE, Singapore)
Sanaz Mostaghim (Otto von Guericke University of Magdeburg, Germany)
Mathias Pacher (University of Hannover, Germany)
Gianluca Palermo (Politecnico Di Milano, Italy)
Marco Domenico Santambrogio (Politecnico di Milano, Italy)
Muhammad Shafique (Karlsruhe Institute of Technology (KIT), Germany)
Lucian Vintan (Lucian Blaga University of Sibiu, Romania)
Sebastian Voss (fortiss GmbH, Germany)