Call for Papers: Transact 2015

Submitted by Victor Luchangco
June 15 to June 16, 2015

Submitted by Victor Luchangco

10th ACM SIGPLAN Workshop on Transactional Computing (Transact 2015)
Portland, Oregon, USA
15-16 June 2015

This year, Transact will be part of the Federated Computing Research
Conference (FCRC).
General FCRC information is available at
Also note Transact will two days this year rather than just one.

Submission Deadline: 19 February 2015 (Thursday)
Author Notification: 24 April 2015 (Friday)
Workshop: 15-16 June 2015 (Monday-Tuesday)

The past decade has seen an explosion of interest in programming languages,
systems, and hardware to support transactions, speculation, and related
alternatives to classical lock-based concurrency. Recently, transactional
memory has crossed two new thresholds. First, IBM and Intel are now shipping
processors with hardware support for transactional memory. Second, the C++
Standard Committee has begun investigation into transactional memory as a
new language feature. These developments highlight the demand for continued
high quality TM research.

Transact 2015 will provide a forum to present and discuss the latest research
on all aspects of transactional computing. The tenth in the series, it will
extend over two days (rather than the usual one) during the Federated
Computing Research Conference (FCRC). The scope of the workshop is
intentionally broad, with the goal of encouraging interaction across the
languages, architecture, systems, database, and theory communities. Papers
may address implementation techniques, foundational results, applications and
workloads, or experience with working systems. Environments of interest
include the full range from multithreaded or multicore processors to high-end
parallel computing.

Transact seeks papers on topics related to all areas of software and hardware
for transactional computing. Specific topics of interest include but are not
limited to:

– Run-time systems
– Hardware support
– Applications, workloads, and test suites
– Experience reports
– Language mechanisms and semantics
– Memory models
– Formal verification
– Speculative concurrency
– Conflict detection and contention management
– Debugging and tools
– Static analysis and compiler optimizations
– Checkpointing and failure atomicity
– Persistence and I/O
– Nesting and exceptions

Papers should present original research. As transactional memory spans many
disciplines, papers should provide sufficient background material to make them
accessible to the broader community. Papers focused on foundations should
indicate how the work can be used to advance practice; papers on experiences
and applications should indicate how the experiments reinforce or reflect principles.

Papers must be submitted in PDF, and be no more than 8 pages in standard
two-column SIGPLAN conference format including figures and tables but not
including references. Shorter submissions are welcome. Submissions will be
judged based on the merit of the ideas rather than the length. Submissions
must be made through the on-line submission site. Final papers will be
available to participants electronically at the meeting, but to facilitate
resubmission to more formal venues, no archival proceedings will be published,
and papers will not be sent to the ACM Digital Library.

Authors will have the option of having their final paper accessible from the
workshop website. Authors must be familiar with and abide by SIGPLAN’s
republication policy, which forbids simultaneous submission to multiple venues
and requires disclosing prior publication of closely related work. At the
discretion of the program committee and with the consent of the authors,
particularly worthy papers may be recommended for a special journal issue.

Cristiana Amza, University of Toronto
Annette Bieniusa, Universitat Kaiserslautern
Luke Dalessandro, Indiana University
Dave Dice, Oracle Labs
Stephan Diestelhorst, ARM
Pascal Felber, Universite de Neuchatel
Justin Gottschlich, Intel Labs
Victor Luchangco, Oracle Labs (chair)
Alessia Milani, Bordeaux Institute of Technology
Binoy Ravindran, Virginia Tech
Torvald Riegel, Red Hat
Paolo Romano, University of Lisbon
Michael Scott, University of Rochester
Michael Spear, Lehigh University
Osman Unsal, BSC-Microsoft Research Centre

General Chair:
Justin Gottschlich, Intel Labs

Program Chair:
Victor Luchangco, Oracle Labs

Web Chair:
Michael Spear, Lehigh University

Steering Committee:
Pascal Felber, University de Neuchatel
Justin Gottschlich, Intel Labs
Dan Grossman, University of Washington
Rachid Guerraoui, EPFL
Tim Harris, Oracle Labs
Maurice Herlihy, Brown University
Eliot Moss, UMass
Jan Vitek, Purdue University
Michael Scott, University of Rochester
Tatiana Shpeisman, Intel Labs
Michael Spear, Lehigh University


Call for Papers: IJPP Special Issue on Workload Optimized Systems

Submitted by Parijat Dube
November 1 to October 1, 2015

Submitted by Parijat Dube

Springer International Journal of Parallel Programming (IJPP)
Special Issue on Workload Optimized Systems


The slowdown in Moore’s Law makes it increasingly important to optimize
systems around specific workloads. Such workload optimized systems have
hardware and/or software specifically designed to run well for a particular
workload or workload class. Such systems include, but are not limited to
traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory
accelerators, I/O accelerators, hybrid systems, and IT appliances. This
workload optimized system approach contrasts to the broad general purpose
direction of computing over many decades. The workload optimized systems
approach is growing in importance, as we see in systems from cellphones to
tablets to routers to game machines to Top500 supercomputers, and IT
appliances such as IBM’s DataPower and Netezza, and Oracle’s Exadata. The
goal of this special issue is to foster awareness in industry and academic
community on workload optimized systems and to expose cross hw/sw stack
unique systems and software research challenges associated with such
systems. All submitted papers are subject to the same review process as those
papers accepted for publication in the regular issues. The special issue seeks
original papers on a range of topics related to workload optimized systems
including, but not limited to

– GPUs, FPGAs, ASIC Accelerators
– Memory and I/O accelerators
– Network accelerators
– Storage optimized systems
– System level accelerators
– IT Appliances
– Systems in specific domains like analytics, cloud, cognitive, mobile etc.
– Converged/Hybrid/Heterogeneous systems
– Cross hardware/software stack design and optimization
– Programming models for workload optimized systems
– Measurements and Experimentation
– Workload characterization and profiling
– Performance modeling and optimization
– Workload scheduling and orchestration
– Runtime management systems
– Industrial Experiences

Manuscript due: March 27, 2015
First decision notification: June 5, 2015
Revision due: July 10, 2015
Final decision notification: August 14, 2015
Final version due: September 11, 2015

Authors are encouraged to submit high-quality, original work that
has neither appeared in, nor is under consideration by, other
journals. All papers will be reviewed following standard reviewing
procedures for the Journal.
Papers must be prepared in accordance with the Journal guidelines:
Manuscripts must be submitted to:
Choose “S.I.: Workload Optimized Systems” as the article type.

Erik Altman, IBM Research, Yorktown Heights, NY.
Parijat Dube, IBM Research, Yorktown Heights, NY.


Call for Papers: RAW 2015

Submitted by Joao MP Cardoso
May 25, 2015

Submitted by Joao MP Cardoso

22nd Reconfigurable Architectures Workshop (RAW 2015)
Hyderabad, India
May 25, 2015

The 22nd Reconfigurable Architectures Workshop (RAW 2015)
will be held in Hyderabad, India in May 2015. RAW 2015 is
associated with the 29th Annual International Parallel &
Distributed Processing Symposium (IPDPS 2015) and is
sponsored by the IEEE Computer Society Technical Committee
on Parallel Processing. The workshop is one of the
major meetings for researchers to present ideas, results,
and on-going research on both theoretical and practical
advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized
by the ability of underlying hardware architectures or
devices to rapidly alter (often on the fly) the functionalities
of their components and the interconnection between them
to suit the problem at hand. The area has a rich theoretical
tradition and wide practical applicability. There are several
commercially available reconfigurable platforms
(FPGAs and coarse-grained devices) and many modern
applications (including embedded systems and HPC) use
reconfigurable subsystems. An appropriate mix of theoretical
foundations and practical considerations, including algorithms,
architectures, applications, technologies and tools,
is essential to fully exploit the possibilities offered
by reconfigurable computing. The Reconfigurable Architectures
Workshop aims to provide a forum for creative and productive
interaction for researchers and practitioners in the area.

Authors are invited to submit manuscripts of original
unpublished research in all areas of reconfigurable systems,
including architectures, algorithms, applications,
software and cross-cutting areas. Topics of interest include,
but are not limited to:

Architectures & Algorithms
– Theoretical Interconnect and Computation Models
– Algorithmic Techniques and Mapping
– Run-Time Reconfiguration Models and Architectures
– Emerging Technologies (optical models, 3D Interconnects, devices)
– Bounds and Complexity Issues
– Analog Arrays

Reconfigurable Systems & Applications
– Reconfigurable accelerators (HPC, Bioinformatics, Multicore environments)
– Embedded systems and Domain-Specific solutions
(Digital Media, Gaming, Automotive applications)
– Distributed Systems & Networks
– Wireless and Mobile Systems
– Emerging applications (Organic Computing, Biology-Inspired Solutions)
– Critical issues (Security, Energy efficiency, Fault-Tolerance)

Software & Tools
– High-Level Design Methods (Hardware/Software co-design, Compilers)
– System Support (Soft processor programming)
– Runtime Support
– Reconfiguration Techniques (reusable artifacts)
– Simulations and Prototyping (performance analysis, verification tools)

All manuscripts will be reviewed by at least three members
of the program committee. Submissions should be a complete
manuscript or, in special cases, may be a summary of relevant
work. The manuscript should be not exceed 8 single-spaced,
double-column pages using 10-point size font on
8.5X11 inch pages (IEEE conference style) including
references, figures and tables. A submission link will be
provided on this site by November 2014. Submitted papers
should not have appeared in or be under consideration
for a different workshop, conference or journal.
It is also expected that all accepted papers (regular or poster)
will be presented at the workshop by one of the authors.

IEEE CS Press will publish the IPDPS symposium and workshop
abstracts as a printed volume.
The complete symposium and workshop proceedings will also be published
by IEEE CS Press as a CD-ROM disk and be available
in the IEEE Digital Library.

Submission deadline: January 6, 2015
Decision notification: February 1, 2015
Camera-Ready papers due: February 14, 2015

Call for Papers: ISCA 2015 – Abstract deadline 11/18

Submitted by Lisa Wu
June 13 to June 17, 2015

Submitted by Lisa Wu

The 42nd Annual International Symposium On Computer
Architecture (ISCA 2015)

June 13-17, 2015
Portland, OR, USA

Abstract Deadline: November 18, 2014, 11:59:59PM EST
Final Paper Deadline: November 25, 2014, 11:59:59PM EST
Rebuttal Period: February 10-13, 2015
Author Notification: March 6, 2015

The International Symposium on Computer Architecture is the premier forum
for new ideas and experimental results in computer architecture. The
conference specifically seeks particularly forward-looking and novel
submissions. Papers are solicited on a broad range of topics, including (but
not limited to):

– Processor, memory, and storage systems architecture
– Parallel and multi-core systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Accelerator-based architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems

Sponsored by ACM SIGARCH IEEE Computer Society TCCA

General Chair: Debbie Marr, Intel

Program Chair: David Albonesi, Cornell University

Steering Committee:
Mark Horowitz, Stanford University
David Kaeli, Northeastern University
Steve Keckler, Nvidia, University of Texas Austin
Avi Mendelson, Technion
Margaret Martonosi, Princeton University
Josep Torrellas, University of Illinois at Urbana-Champaign
David A. Wood, University of Wisconsin-Madison
Pen-Chung Yew, University of Minnesota
Antonia Zhai, University of Minnesota

Program Committee:
Murali Annavaram, University of Southern California
Rajeev Balasubramonian, University of Utah / HP Labs
Christopher Batten, Cornell University
Ricardo Bianchini, Microsoft / Rutgers University
David Brooks, Harvard University
Doug Burger, Microsoft
Alper Buyuktosunoglu, IBM Research
John Carter, IBM Research
Luis Ceze, University of Washington
Derek Chiou, Microsoft / University of Texas at Austin
Fred Chong, University of California at Santa Barbara
Robert Colwell, Consultant
Bill Dally, NVIDIA / Stanford University
Lieven Eeckout, Ghent University
Mattan Erez, University of Texas at Austin
Babak Falsafi, EPFL
Michael Ferdman, Stony Brook University
Antonio Gonzalez, Universitat Politècnica de Catalunya
Sudhanva Gurumurthi, AMD / University of Virginia
James Hoe, Carnegie Mellon University
Wen-mei Hwu, University of Illinois at Urbana-Champaign
Engin Ipek, University of Rochester
Ravi Iyer, Intel
Natalie Enright Jerger, University of Toronto
Lizy John, University of Texas at Austin
David Kaeli, Northeastern University
Hsien-Hsin Lee, TSMC
Scott Mahlke, University of Michigan
Jason Mars, University of Michigan
José Martínez, Cornell University
Margaret Martonosi, Princeton University
Shubu Mukherjee, Cavium Networks
Parthasarathy (Partha) Ranganathan, Google
Scott Rixner, Rice University
Ronny Ronen, Intel
Eric Rotenberg, North Carolina State University
Karthikeyan Sankaralingam, University of Wisconsin-Madison
Simha Sethumadhavan, Columbia University
Yanos Sazeides, University of Cyprus
Tim Sherwood, University of California at Santa Barbara
Daniel Sorin, Duke University
Karin Strauss, Microsoft
Radu Teodorescu, Ohio State University
Mohit Tiwari, University of Texas at Austin
Dean Tullsen, University of California, San Diego
Tom Wenisch, University of Michigan
Carole-Jean Wu, Arizona State University
Yuan Xie, University of California at Santa Barbara
Lixin Zhang, Chinese Academy of Sciences

Call for Papers: Tiny ToCS Volume 3

Submitted by Yuhao Zhu
March 5, 2015

Submitted by Yuhao Zhu

Tiny Transactions on Computer Science (Tiny ToCS)

Tiny ToCS seeks papers describing significant research contributions to the
field of computer science. Tiny ToCS is the premier venue for computer science
research of 140 characters or less.

Tiny ToCS is a forum for high-quality scholarly discourse
that challenges researchers to engage with their work in new
capacities. Not only does the restricted format require a concise
distillation of scholarly results, but the short format will be
more accessible to the Computer Science community at large. Tiny ToCS
favors accessible, carefully crafted, creative research, and
invites submissions both about novel ideas as well as summaries or
distillations of existing work.

We invite submissions on a wide range of computer science research, including,
but not limited to:

– Artificial Intelligence
– Computer Architecture
– Computer Networking
– Computer Systems
– Computer Security
– Databases and Data Management
– Graphics
– Human-Computer Interaction
– Machine Learning
– Programming Languages
– Theory of Computation

Submissions to Tiny ToCS can be up to 140 characters in length,
with an abstract of no more than 250 words and a title of no
more than 118 characters.

Alternate (video) format: Videos of up to 120 seconds may also be
submitted. Authors should be careful to maintain anonymity in the
video. The attached video description must fit within 118 characters
so that it may be tweeted alongside the video. Videos should be
submitted directly to the PC via email: Heidy Khlaaf.

The primary content of submissions should fit into 140 characters.
The abstract is not intended to expound upon your finding but instead
to provide context for your work. What is the background for your
research? Concisely, how does this work improve on related research?
Submissions which violate this requirement will be rejected without

You may use three references in your submission. References will count as one
word when used in the abstract section and three letters in the body
section (“[1]”).

Your submission may not contain any non-text figures or special formatting.
Plain-text only. ASCII art okay.

Reviewing will be double-blind and serve primarily to ensure basic quality
of accepted papers. Submissions that are unverifiable or purely humorous will be
rejected; submissions that highlight nuggets in or concisely summarize existing
work are acceptable.

For inspiration, we have provided a sample submission, or refer to Tiny ToCS
Volume I.

Please validate your submission before submitting.

If possible, please format your submission(s) using the Tiny ToCS LaTeX
class file. We’ve provided a sample skeleton file for you. At the least,
please submit in PDF format (required by our conference software). And
remember, leave names and affiliations off of your PDF.

Final submission: January 15, 2015, 11:59 PM PST
Notification: February 15, 2015
Camera Ready Due: March 1, 2015
Publication: March 5, 2015

The proceedings of Tiny ToCS Volume 3 will be posted to the arXiv under a
Creative Commons Attribution-NonCommercial-ShareAlike license. Authors will
retain all future publishing rights.

Program Chair:
Heidy Khlaaf, University College London

Program Committee:
Peter Bailis, University of California, Berkeley
Yonatan Bisk, University of Illinois Urbana-Champaign
Sarah Deisburg, University of Northern Iowa
Mike Dodds, University of York
Andrew Ferguson, Google
Mital Kinderkhedia, University College London
Zachary Kincaid, University of Toronto
Lindsey Kuper, Intel
Katie Kuksenok, University of Washington
Jinna Lei, University of Washington
Igore Mordatch, University of Washington
Faisal Nawab, University of California Santa Barbara
Sunil Pedapudi, Google
Malte Schwarzkopf, University of Cambridge
Divya Sharma, Carnegie Mellon University
Stephen Strowes, Yahoo
Yuhao Zhu, The University of Texas at Austin

Call for Papers: Symposium on Architectures for Networking and Communications Systems (ANCS)

Submitted by Eric Keller
May 7 to May 8, 2014

Submitted by Eric Keller

The 11th ACM/IEEE Symposium on Architectures for Networking
and Communications Systems (ANCS 2015)

Oakland, California, USA
May 7-8, 2015

Co-located with NSDI 2015

ACM Special Interest Group on Computer Architecture (SIGARCH)
ACM Special Interest Group on Communications (SIGCOMM)
IEEE Computer Society Tech. Committee on Computer Architecture (TCCA)

ANCS is a systems-oriented research conference, presenting original work
that explores the relationship between the algorithms and architectures of
data communication networks and the hardware and software elements from
which these networks are built. This includes both experimental and
theoretical analysis. To recognize and foster the increasing importance of
research into the co-design of computer and network systems, the conference
also places an emphasis on systems issues arising from the interaction of
computer and network architectures.

ANCS 2015 will be co-located with the 12th USENIX Symposium on Networked
Systems Design and Implementation (NSDI ’15), which will be held May 4–6.

Papers – Abstract submission deadline: January 7, 2015
Papers – Full paper submission deadline: January 14, 2015
Papers – Author notification: March 16, 2015
Conference: May 7-8, 2015

– System design for future network architectures
– Router and switch architectures
– High-speed networking algorithms and mechanisms
– Software Defined Networking systems
– Network Functions Virtualization architectures
– Virtualized infrastructure architectures and systems
– Architectures for data centers
– Converged router, server, and storage platforms
– Host-network interface issues
– Techniques and systems for large-scale data analysis
– Wireless network hardware and related software, including software radios
– Mesh, ad hoc and sensor network hardware and related software
– Information-centric network architectures, platforms, and mechanisms
– Network security architectures and security anchor/enhancement devices
– Network measurement techniques, architectures, and devices
– Scalable programming and application frameworks
– High-performance and high-function network processing platforms
– Power- and size-optimized computer and communications platforms
– Hardware accelerators and offload engines
– Single-chip networking elements, e.g., multicore, NPU, FPGA, TCAM, ASIC
– Network-on-Chip architectures and applications
– Memory architectures and technologies for packet, state and table storage.

General Chair: Gordon Brebner (Xilinx, USA)
Program Chairs:
– Alex Bachmutsky (Ericsson, USA),
– Chita Das (Penn State University, USA)


Call for Papers: Architecture, Languages, Compilation and Hardware support for Emerging ManYcore systems

Submitted by Loïc CUDENNEC
June 1 to June 3, 2015

Submitted by Loïc CUDENNEC

ALCHEMY Workshop 2015: Architecture, Languages, Compilation and
Hardware support for Emerging ManYcore systems

Held in conjunction with the International Conference on
Computational Science (ICCS 2015)
Reykjavik, Iceland
1-3 June 2015

Important dates are synchronized with the ICCS meeting

The International Conference on Computational Science is an annual
conference that brings together researchers and scientists from mathematics
and computer science as basic computing disciplines, researchers from various
application areas who are pioneering computational methods in sciences such
as physics, chemistry, life sciences, and engineering, as well as in arts and
humanitarian fields, to discuss problems and solutions in the area,
to identify new issues, and to shape future directions for research.

Massively parallel processors have entered high performance computing
architectures, as well as embedded systems. In June 2014, the TOP500
number one system (Tianhe-2) features the 57-core Intel Xeon Phi
processor. The increase of the number of cores on a chip is expected
to rise in the next years, as shown by the ITRS trends: other examples
include the Kalray MPPA 256-core chip, the 63-core Tilera GX processor
and even the crowd-funded 64-core Parallella Epiphany chip. In this
context, developers of parallel applications, including heavy
simulations and scientific calculations will undoubtedly have to cope
with many-core processors at the early design steps.

In the two past sessions of the Alchemy workshop, held together with
the ICCS meeting, we have presented significant contributions on the
design of many-core processors, both in the hardware and the software
programming environment sides, as well as some industrial-grade
application case studies. In this 2015 session, we seek academic
and industrial works that contribute to the design and the
programmability of many-core processors.

Topics include, but are not limited to:
* Programming models and languages for many-cores
* Compilers for programming languages
* Runtime generation for parallel programming on manycores
* Architecture support for massive parallelism management
* Enhanced communications for CMP/manycores
* Shared memory, data consistency models and protocols
* New operating systems, or dedicated OS
* User feedback on existing manycore architectures
(experiments with Adapteva Epiphany, Intel Phi, Kalray MPPA, ST
STHorm, Tilera Gx, TSAR..etc)

This year, there will be two formats for the presentation at the
workshop. The usual full-length paper is 10 pages according to the ICCS
format, and the short-paper format well fitted for works in progress,
with a maximum of 2 pages. The accepted papers for full-length paper
will be published alongside with the ICCS proceedings in Procedia
Computer Science, whereas the short-papers will be presentation and
poster only at the conference (with proceedings and presentations
available from the workshop website).

Akram BEN AHMED, University of Aizu, Fukushima, Japan
Camille COTI, Université de Paris-Nord, France
Stephan DIESTELHORST, ARM Ltd; Cambridge, UK
Aleksandar DRAGOJEVIC, Microsoft Research Cambridge, UK
Daniel ETIEMBLE, Université de Paris-Sud, France
Bernard GOOSSENS, Université de Perpignan, France
Vincent GRAMOLI, NICTA / University of Sydney, Australia
Jorn W. JANNECK, Lund University, Sweden
Vianney LAPOTRE, Université de Bretagne-Sud, France
Eric LENORMAND, Thales TRT, France
Stéphane LOUISE, CEA, LIST, France
Vania MARANGOZOVA-MARTIN, Université Joseph-Fourier Grenoble, France
Eric PETIT, Université de Versailles Saint Quentin-en-Yvelines, France
Erwan PIRIOU, CEA, LIST, France
Antoniu POP, University of Manchester, UK
Jason RIEDY, Georgia Institute of Technology, USA
Etienne RIVIERE, Université de Neuchâtel, Switzerland
Thomas ROPARS, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Martha JOHANNA SEPULVEDA, INRIA, École Centrale de Lyon, France
(to be extended)

Call for Papers: ICS 2015

Submitted by Arun Kejariwal
June 8 to June 11, 2015

Submitted by Arun Kejariwal

ACM 29th International Conference on Supercomputing

ICS is the premier international forum for the presentation of research results
in high-performance computing systems. In 2015, the conference will be
held in Newport Beach, California. Papers are solicited on all aspects of the
research, development, and application of large-scale, high-performance
experimental and commercial systems, including:

– Computer architecture and hardware, including multicore and multiprocessor
systems,accelerators, memory, interconnection network and storage and file

– High-performance computational and programming models, including new
languages and middleware for high performance computing, auto-tuning
and function-specific code generators;

– High performance system software, including compilers, runtime systems,
programming and development tools, performance tools, and operating

– Hardware and software solutions for heterogeneity, reliability, and power

– Languages, runtimes, and hardware for “big data” scenarios with a focus
on high-performance data analytics, including scalable data structures,
dealing with large quantities of unstructured data, online monitoring and
I/O, and parallel visualization;

– Computationally challenging scientific and commercial applications,
particularly studies and experiences on large-scale systems, and
supercomputing on big data problems;

– Large scale installations, including case studies to guide the design of
future systems and solutions for efficiently scaling power, performance,
reliability and sustainability;

– Novel infrastructures for internet, grid and cloud computing;

– Performance evaluation studies and theoretical underpinnings of any of the
above topics.

Of particular interest are papers on any aspects of extreme-scale and
heterogeneous supercomputing systems, integrated HPC software stacks, and
supercomputing applications in science and engineering. Papers should not
exceed 10 pages in the ACM format.

The review process will include a rebuttal period. The important dates are given

Abstract submission: January 9, 2015 (Friday) AOE
Paper submission: January 16, 2015 (Friday) AOE
Workshop/Tutorial proposals: January 23, 2015 (Friday) AOE
Workshop/Tutorial notification: January 28, 2015 (Wednesday) AOE
Author rebuttal period: March 2-4, 2015
Author notification: March 16, 2015 (Monday)
Early registration deadline: March 27, 2015 (Monday)
Final papers: March 30, 2015 (Monday) AOE

AOE (Anywhere on Earth) dates shown above mean the deadlines are at 11:59pm
UTC-12:00 of the days. The above dates are tentative and subject to change.
Consult the conference website for the most up-to-date scheduling information.

For more information: please visit

Call for Papers: Computing Frontiers 2015

Submitted by Kaoutar El Maghraoui
May 18 to May 21, 2015

Submitted by Kaoutar El Maghraoui

ACM International Conference on Computing Frontiers 2015 (CF’15)
Ischia, Italy
May 18 – 21, 2015

Computing Frontiers represents an engaged, collaborative community
of researchers who are excited about transformational technologies
in the field of computing. We are presently on the cusp of several
revolutions, including new memory technologies, networking
technologies, algorithms for handling large-scale data, power-saving
and energy-efficient solutions for data centers, systems solutions
for cloud computing, new application domains that affect every day
life and many, many more. Boundaries between the state-of-the-art
and revolutionary innovation constitute the computing frontiers that
must be pushed forward to advance science, engineering, and
information technology. Before revolutionary materials, devices,
and systems enter the mainstream, early research must be performed
using far-reaching projections of the future state of technologies.

Computing Frontiers is a gathering for people to share and discuss
such work, focusing on a wide spectrum of advanced technologies and
radically new solutions relevant to the development of the whole
spectrum of computer systems, from embedded to high-performance

This year we are adding Industry Sessions and Workshops that focus
on special topics. These sessions should have a special computing
frontiers focus and can run between 1/2 and a full day.

Workshop / Industry Sessions Proposal Deadline: November 1, 2014
(Extended from October 3, 2014)
Submissions deadline: January 16, 2015
Notification: February 20, 2015
Camera-Copy Papers Due: March 20, 2015

We seek contributions that push the envelope in a wide range of
computing topics, ranging from more traditional research in
architecture and systems to new technologies and devices. We seek
contributions on novel computing paradigms, computational models,
algorithms, application paradigms, development environments,
compilers, operating environments, computer architecture, hardware
substrates, memory technologies and smarter life applications. We
are also interested in emerging fields that may not fit within
traditional categories.

– Algorithms and Models of Computing
approximate and inexact computing, quantum and probabilistic

– Biological Computing Models
brain computing, neural computing, computational neuroscience,
biologically-inspired architectures

– Big Data
analytics, machine learning, search and representation, system

– System Complexity Management
cloud systems, datacenters, exa-scale computing

– Computers and Society
education, health and cost/energy-efficient design, smart cities,
emerging markets

– Security
architecture and systems support for protection against malicious

– Limits on Technology Scaling and Moore’s Law
defect- and variability-tolerant designs, graphene and other
novel materials, nanoscale design, optoelectronics, dark silicon

– Uses of Technology Scaling
3D stacked technology, challenges of manycore designs,
PCM’s, novel memory architectures, mobile devices

– Compiler technologies
novel techniques to push the envelope on new technologies,
applications, hardware/software integrated solutions, advanced

– Networking
technology and protocols, bandwidth management, social networks,
internet of things

– Interdisciplinary Applications
applications that bridge multiple disciplines in interesting ways

– Position Papers, Trend Papers and Crazy Ideas

– Industry Sessions and Workshops
Sessions should have a special computing frontiers focus and can
run between 1/2 and full day. Proposals for Industry Sessions and
Workshops should be sent by e-mail to fpalumbo (AT) by
filling out the form that can be found on the Computing Frontiers

Authors are invited to submit full papers or posters to the main
conference. Full papers and poster abstracts must be submitted
through the conference paper submission site. Full papers should
not exceed 8 double-column pages in standard ACM conference format.
Poster abstracts should not exceed two pages in the same format.
These limits include figures, tables, and references. Our review
process is double-blind. Thus, please remove all identifying
information from the paper submission (also if citing own work).
Abstracts for accepted posters will be published in the proceedings
and in the ACM Digital Library (note that authors of these works
retain their copyright rights to publish more complete versions
later). The best papers from the Computer Frontiers Conference and
Workshops will be invited to be published in special issues of IJPP
or PARCO. As per ACM guidelines, at least one of the authors of
accepted papers is required to register for the conference. Industry
Session and Workshop proposals should be submitted to
fpalumbo (AT) by filling out the form that can be found
on the Computing Frontiers website.

General Chairs:
Claudia Di Napoli, ICAR-CNR, IT
Valentina Salapura, IBM, USA

Program Chairs:
Hubertus Franke, IBM Research, USA
Rui Hou, Institute for Computing Technology,
Chinese Academy of Sciences, PRC

Finance Chair:
Jens Breitbart, TU Munich, DE

Local Arrangements Chair:
Silvia Rossi, Universite degli Studi di Napoli “Federico II”, IT

Poster Chair:
Alexander Heinecke, Intel Parallel Computing Lab, US

Publicity Chairs:
Kun Wang, Microsoft, PRC
Raymond Namyst, University of Bordeaux, FR

Publication Chair:
Michela Taufer, University of Delaware, US

Web Chair:
Kristian Rietveld, Leiden University, NL

Steering Committee:
Monica Alderighi, INAF, IT
Claudia Di Napoli, ICAR-CNR, IT
Hubertus Franke, IBM, US
Diana Franklin, University of California at Santa Barbara, US
Georgi Gaydadijev, Chalmers University, SE
Alexander Heinecke, Intel Parallel Computing Lab, US
Paul Kelly, Imperial College, GB
Sally A. McKee, Chalmers University of Technology, SE
Krishna Palem, Rice University, US / Nanyang Technological University, SG
Francesca Palumbo, University of Cagliari, IT
Valentina Salapura, IBM, US
Pedro Trancoso, University of Cyprus, CY
Carsten Trinitis, TU Munich, DE
Eli Upfal, Brown University, US
Josef Weidendorfer, TU Munich, DE

Call for Papers: ISLPED 2015

Submitted by Andreas Burg
July 22 to July 24, 2015

Submitted by Andreas Burg

International Symposium on Low Power Electronics and Design
July 22 – July 24, 2015
Rome, Italy

Technical Paper Submission Deadline:
– Abstract registration by Feb 22, 2015
– Full paper by March 1, 2015
Invited Talk, Panel, and Embedded Tutorial Proposals Deadline: April 1, 2015
Notification of Paper Acceptance: May 1, 2015
Submission of Camera-Ready Papers: June 1, 2015

For more information or general queries, please email
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Sponsored by the IEEE Circuits and Systems Society (CASS) and the ACM Special
Interest Group on Design Automation (SIGDA).

The International Symposium on Low Power Electronics and Design (ISLPED) is
the premier forum for presentation of innovative research in all aspects of
low power electronics and design, ranging from process technologies and
analog/digital circuits, simulation and synthesis tools, system-level
design and optimization, to system software and applications. Specific
topics include, but are not limited to, the following three main tracks
and sub-areas:

1. Technology, Circuits, and Architecture

1.1. Technologies
Low-power technologies for Device, Interconnect, Logic, Memory,
2.5/3D, Cooling, Harvesting, Sensors, Optical, Printable, Biomedical,
Battery, and Alternative energy storage devices.

1.2. Circuits
Low-power digital circuits for Logic, Memory, Reliability, Clocking,
Power gating, Resiliency, Near-threshold and Sub-threshold,
Variability, and Digital assist schemes; Low-power analog/mixed-signal
circuits for Wireless, RF, MEMS, AD/DA Converters, I/O, PLLs/DLLS,
Imaging, DC-DC converters, and Analog assist schemes.

1.3. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, Processor cores
(compute, graphics and other special purpose cores), Cache, Memory,
Arithmetic/Signal processing, Cryptography, Variability, Asynchronous
design, and Nonconventional computing.

2. CAD, Systems, and Software

2.1. CAD Tools and Methodologies
CAD tools and methodologies for low-power and thermal-aware design
addressing power estimation, optimization, reliability and variation impact
on power, and power-down approaches at all levels of design abstraction:
physical, circuit, gate, register transfer, behavioral, and algorithm.

2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design and platforms
for microprocessors, DSPs, embedded systems, FPGAs, ASICs, SoCs,
heterogeneous computing, data-center power delivery and cooling, and
system-level power implications due to reliability and variability.

2.3. Software and Applications
Energy-efficient, energy-aware, and thermal-aware system software and
application design including scheduling and management, power
optimizations through HW/SW interactions, and emerging low power
applications such as approximate and brain-inspired computing, the
Internet-of-Things (IoT), wearable computing, body-area/in-body networks,
and wireless sensor networks.

3. Industrial Design Track (New Initiative for 2015)

3.1. Industry Perspectives
For the first time, ISLPED’15 solicits papers for an “Industrial Design” track
to reinforce interaction between the academic research community and
industry. Industrial Design track papers have the same submission deadline
as regular papers and should focus on similar topics, but are expected to
provide a complementary perspective to academic research by focusing on
challenges, solutions, and lessons learnt while implementing industrial-
scale designs. In addition to purely hardware-focused papers, papers
describing power optimizations through an interaction of hardware and
software are also welcome.

Submissions should be full-length papers of up to 6 pages (PDF format,
double-column, US letter size, using the IEEE Conference format, available at,
including all illustrations, tables, references, and an abstract of no more
than 250 words. Submissions must be anonymous. Submissions exceeding 6 pages
or identifying the authors, either directly or through explicit references to
their prior work, will be automatically rejected. More information on paper
submission can be found at

Submitted papers must describe original work that has not been
published/accepted or currently under review by another journal, conference,
symposium, or workshop at the same time. Accepted papers will be published in
the Symposium Proceedings and included in IEEE Xplore and the ACM Digital
Library. ISLPED’15 will present two Best Paper Awards based on the ratings of
reviewers and a panel of judges.

There will be several invited talks by industry and academic thought leaders
on key issues in low power electronics and design. The Symposium may also
include embedded tutorials to provide attendees with the necessary background
to follow recent research results, as well as panel discussions on future
directions in low power electronics and design.

Proposals for invited talks, embedded tutorials, and panels should be sent by
email to the ISLPED’15 Technical Program Co-Chairs, Vijay Raghunathan
( and Ruchir Puri ( by the deadline listed


General Co-Chairs:
Luca Benini, Univ. of Bologna,
Renu Mehra, Synopsys,
Mauro Olivieri, Sapienza Univ.,

Program Co-Chairs:
Ruchir Puri, IBM,
Vijay Raghunathan, Purdue Univ.,

Local Arrangement Chair:
Alessandro Trifiletti, Sapienza Univ.,

Industry Liaison:
David Garrett, Broadcom,

Publicity Co-Chairs:
Andreas Burg, EPFL,
Deming Chen, UIUC,

Publication Chair:
Paul Wesling, IEEE,

Industrial Design Track Co-Chairs:
Edith Beigne, CEA-Leti,
Juergen Karmann, Infineon,

Design Contest Co-Chairs:
Alberto Macii, Politecnico di Torino,
Hiroki Matsutani, Keio University,

Yu Wang, Tsinghua University,

Web Chair:
Theo Theocharides, Univ. of Cyprus,

Local Staff:
Francesco Menichelli, Sapienza Univ.
Antonio Mastrandrea, Sapienza Univ.
Zia Abbas Zaidi, Sapienza Univ.
Usman Khalid, Sapienza Univ.
Monica Coppola, FREEnergy