Call for Proposals: 2015 Fellowships in ACM History

Submitted by Boris Grot

Submitted by Boris Grot

2015 Fellowships in ACM History

The Association for Computing Machinery, founded in 1947, is the oldest and
largest educational and scientific society dedicated to the computing
profession, and today has more than 100,000 members around the world.
The ACM History Committee is preparing groundwork for a special history
workshop in mid-October 2015. Aiming at the workshop, we will support research
projects related to ACM’s professional and educational activities and/or to ACM’s
rich institutional history including its organization, publications, SIG
activities, and conferences. See list of past supported projects.

We will support up to four projects with awards of up to $4,000 each.
Successful candidates may be of any rank, from graduate students through
senior researchers. All awardees must be willing to present a paper to the ACM
history workshop held in conjunction with the SHOT and SIGCIS annual meeting
in Albuquerque, New Mexico during 8-11 October 2015. A supplement for
workshop travel, lodging, and meals will be provided—in addition to this research
project award. Previous ACM HC awardees will be invited to the workshop and
similarly supported.

We especially invite research projects that relate to the following 2015
workshop themes:
– Public policy, government relations, and computing
– Public policy, government relations, and computing
– Computing education and professionalization
– Organizational innovation: special-interest groups, conferences, and
publications in computing

Applicants should send a 2-page CV as well as a 750-word project
description that [a] describes the proposed research; [b] identifies the
importance of specific ACM historical materials, whether traditional archival
collections or online historical materials (oral histories, digitized
conference papers, ACM organizational records, etc.); [c] discusses any
project outcome besides the ACM history workshop (e.g. journal article, book
or dissertation chapter, teaching resource, museum exhibit, website); and [d]
outlines a timeline for completing the project —- including, specifically,
your willingness to contribute a 10-page (2500-word) paper to the mid-October
2015 ACM history workshop. Workshop papers will be pre-circulated to workshop
attendees; revised papers may be published.

In preparing a proposal, applicants should examine the document “ACM Research
Materials” posted at as well as
“Sources for ACM History,” CACM 50 #5 (May 2007): 36-41 Other research materials relating
to ACM may also be used. Applicants should include a letter of endorsement
from their home institution or an external scholarly reference.

Proposals are due by 1 February 2015. Proposals should be submitted as a
single pdf-format document to Notification of
awards will be made within 6 weeks.

The current and past winners of the fellowship can be found at

Call for Participation: CGO 2015

Submitted by Aaron Smith
February 7 to February 11, 2015

Submitted by Aaron Smith

2015 IEEE/ACM International Symposium on Code Generation and
Optimization (CGO)

San Francisco Airport Marriott Waterfront
Feb 7-11, 2015

CGO brings together researchers and practitioners working at the interface of
hardware and software on a wide range of optimization and code generation
techniques and related issues.

CGO 2015 is located with ACM PPoPP and IEEE HPCA in the San Francisco Bay Area.

There are 24 full papers and over 30 co-located workshops and tutorials.

Travel grants are available for all students. Apply now!

Conference Dates: February 9-11, 2015
Workshops and Tutorials: February 7-8, 2015
Early Registration Deadline: January 11, 2015

Call for Papers: FCCM 2015

Submitted by David Thomas
January 9, 2015

Submitted by David Thomas

The 23rd IEEE International Symposium on
Field-Programmable Custom Computing Machines (FCCM 2015)

Vancouver, British Columbia, Canada
May 3-5

Title and abstract submission: January 6th, 2015
Full paper submission: January 6th, 2015
Notification of acceptance: March 2nd, 2015
Conference: May 3rd-5th, 2015

The IEEE Symposium on Field Programmable Custom Computing
Machines is the original and premier forum for presenting and
discussing new research related to computing that exploits the
unique features and capabilities of FPGAs and other
reconfigurable hardware. Over the past two decades, FCCM has
been the place to present papers on architectures, tools, and
programming models for field programmable custom computing
machines as well as applications that use such systems.

Papers on the traditional topics of FCCM as described below
are solicited. Novel research in the general area of
reconfigurable computing is also encouraged.

Architectures and Programming Models
– Architectures for high performance and/or low power
configurable computing
– New spatial architectures with immense parallelism but
different basic components than FPGAs
– System-level architectures for reconfigurable computing in
either real-time or non real-time systems
– Heterogeneous architectures that integrate a mix of coarse,
fine, special purpose, and general-purpose hardware
– Implications and effects of new technologies, including
nanotechnology on reconfigurable computing (and vice versa)
– Security enhancements for reconfigurable computing

Languages and Compilers
– New languages and development environments to describe
spatial or heterogeneous applications
– Tools to make run-time reconfiguration more accessible to
application designers
– Compilation and CAD techniques for reconfigurable computing
systems and other spatial computers

Run-Time Systems and Run-Time Reconfiguration
– Operating system techniques to manage run-time
reconfiguration of resources in reconfigurable computing or
spatial computing systems
– Run-time CAD algorithms to support the above techniques or
improve fault tolerance/avoidance
– Use of reconfigurability to build evolvable or adaptable
computing systems
– Novel uses of run-time reconfiguration in
application-specific systems
– Implications of run-time reconfiguration on security

– Applications that use reconfigurability to customize
hardware for scientific computation, mobile communications,
medical image processing, data and communication security,
network infrastructure and other embedded systems. These
papers should describe novel use of some particular attribute
of the reconfigurable device used, or discuss lessons that
will help other users.
– Comparison of application implementations on different
spatial hardware, such as GPUs, multi-core processors, and

General Chair: Lesley Shannon, Simon Fraser University
Program Chair: David Andrews, University of Arkansas
Finance Chair: Ken Eguro, Microsoft Research
Publications Chair: Jason D. Bakos, University of South Carolina
Publicity Chair: David Thomas, Imperial College
Exhibits and Sponsorships Chair: Shep Siegel, Atomic Rules

Call for Participation: Top Picks community input

Submitted by Karin Strauss

Submitted by Karin Strauss

IEEE Micro Top Picks: community input web site now open

IEEE Micro will publish its yearly Micro’s Top Picks from Computer Architecture
Conferences as its May / June 2015 issue. This issue collects some of this
year’s most significant research papers in computer architecture based on
novelty and potential for long-term impact.

The Top Picks committee will recognize those significant and insightful papers
that have the potential to influence the work of computer architects for years
to come. The selection has been traditionally based on reviews by the committee
and a small number of external reviewers. This year we want to experiment with
gathering community input as well. In other words, we would like to have your

The community input website will be open between Dec 18, 2014 and Jan 17,
2015. Reviews will be anonymous to the authors but they will not be anonymous
to the selection committee. We will be checking very closely for conflicts of
interest, therefore we ask that community reviewers do not spend time
submitting reviews of conflicted papers because they will not be considered.
Here are the conflict rules: worked for the same institutions in the last 5
years; co-author on a paper or co-PI on a proposal in the last 5 years; advisor
advisee relationships (forever); family relations by blood or marriage

As pointed out, gathering community input is an experiment for Top Picks. We
would like to make it a successful one so that the selection process in future
years remains open to the community at large. Therefore, we ask those who
choose to review submissions to follow the highest ethics standards and to
provide constructive input. We have a plan on how we are going to use this
input, but we reserve ourselves the right to not use the input at all if we
feel it will not be constructive.

If you would like to provide input, please follow these two simple steps:

1. Create an account at the community input website between Dec 18, 2014 and
Jan 17, 2015. We will only consider reviews from users with an institutional
email (university or company).

2. After creating an account, you will be able to log in, see the submissions
and write reviews for any paper you are not conflicted with.

Please participate! Happy Holidays!

-Luis Ceze and Karin Strauss
IEEE Micro Top Picks 2015 Selection Committee Chairs

Call for Papers: ASAP 2015

Submitted by Vaughn Betz
July 27 to July 29, 2015

Submitted by Vaughn Betz

The 2015 IEEE International Conference on Application-Specific
Architectures, Systems, and Processors (ASAP)

Toronto, Canada
July 27-29, 2015

Abstract Submission: February 27, 2015
Paper Due: March 6, 2015
Notification: May 15, 2015
Conference: July 27-29, 2015

The 26th IEEE International Conference on Application-specific
Systems, Architectures and Processors 2015 (ASAP 2015) takes place
July 27-29, 2015 at the University of Toronto in Toronto, Canada. The
conference will cover the theory and practice of application-specific
systems, architectures and processors. The 2015 conference will build
upon traditional strengths in areas such as computer arithmetic,
cryptography, compression, signal and image processing, network
processing, reconfigurable computing, application-specific
instruction-set processors, and hardware accelerators. We especially
encourage submissions in the following areas:

– Big data analytics: extracting and correlating information from
large-scale semi-structured and unstructured data using
application-specific systems.
– Scientific computing: architectures and algorithms that address
applications requiring significant computing power and customization
(bioinformatics, climate modeling, astrophysics, seismology, etc.).
– Industrial computing: systems and architectures for providing high-
throughput or low latency in various industrial computing
– System security: cryptographic hardware architectures, security
processors, countermeasures against side-channel attacks, and secure
cloud computing.
– Heterogeneous systems: applications and platforms that exploit
heterogeneous computing resources, including FPGAs, GPUs, or CGRAs.
– Design space exploration: methods for customizing and tuning
application- specific architectures to improve efficiency and
– Platform-specific architectures: novel architectures for exploiting
specific compute domains, such as smartphones, tablets, and data
centers, particularly in the context of energy efficiency.

ASAP 2015 will accept 8-page full papers for oral presentations,
4-page short papers for short oral or poster presentations, with a
single-blind review process.

Submissions to ASAP 2015 must use the double-column IEEE conference
proceedings format. The only accepted file format is PDF. An online
submission page will be made available on the ASAP 2015 website and
will include detailed guidelines and links to formatting templates.


General Chair:
Jason Anderson, University of Toronto

Program Co-Chairs:
Deshanandh Singh, Altera Corp.
Hayden So, University of Hong Kong

Finance Chair:
Warren Gross, McGill University

Publicity Chair:
Vaughn Betz, University of Toronto

Web Chair:
Hiren Patel, University of Waterloo

Publications Chair:
Yuko Hara-Azumi, Tokyo Inst. of Tech.

Industry Chair:
Soojung Ryu, Samsung Electronics

Call for Participation: HiPEAC 2015

Submitted by Gennady Pekhimenko
January 19 to January 21, 2015

Submitted by Gennady Pekhimenko

10th International Conference on High-Performance Embedded
Architectures and Compilers (HiPEAC)

Amsterdam, The Netherlands
January 19-21, 2015

Early Registration: December 23, 2014

Call for Papers: NOCS 2015

Submitted by Maurizio Palesi
September 28 to September 30, 2015

Submitted by Maurizio Palesi

9th IEEE/ACM International Symposium on Networks-on-Chip
Vancouver, Canada
September 28 – 30, 2015

The International Symposium on Networks-on-Chip (NOCS) is the premier
event dedicated to interdisciplinary research on on-chip, chip-scale,
and multichip package scale communication technology, architecture,
design methods, applications and systems. NOCS brings together
scientists and engineers working on NoC innovations and applications
from inter-related research communities, including computer
architecture, networking, circuits and systems, packaging, embedded
systems, and design automation.

Topics of interest include, but are not limited to:

NoC Architecture and Implementation
– Network architecture (topology, routing, arbitration)
– NoC Quality of Service
– Timing, synchronous/asynchronous communication
– NoC reliability issues
– Network interface issues
– NoC design methodologies and tools
– Signaling & circuit design for NoC links
NoC Analysis and Verification
– Power, energy & thermal issues(at the NoC, un-core and/or system-level)
– Benchmarking & experience with NoC-based hardware
– Modeling, simulation, and synthesis of NoCs
– Verification, debug & test of NoCs
– Metrics and benchmarks for NoCs
Novel NoC Technologies
– New physical interconnect technologies, e.g., carbon nanotubes,
wireless NoCs, through-silicon, etc.
– Optical, RF, & emerging technologies for on-chip/in-package
– NoCs for 3D and 2.5D packages
– Package-specific NoC design
NoC Application
– Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems, fused CPU-GPU
architectures, etc
– Scalable modeling of NoCs
NoC at the Un-Core and System-level
– Design of memory subsystem (un-core) including memory
controllers, caches, cache coherence protocols & NoCs
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing
and novel programming models
– Issues related to large-scale systems (datacenters, supercomputers)
with NoC-based systems as building blocks
– On-Chip Communication Optimization
– Communication efficient algorithms
– Multi/many-core communication workload characterization & evaluation
– Energy efficient NoCs and energy minimization

Electronic paper submission requires a full paper, up to 8
double-column IEEE format pages, including figures and references. The
program committee in a double-blind review process will evaluate
papers based on scientific merit, innovation, relevance, and
presentation.Submitted papers must describe original work that has
not been published before or is under review by another conference or
journal at the same time. Each submission will be checked for any
significant similarity to previously published works or for
simultaneous submission to other archival venues, and such papers
will be rejected. Please see the paper submission instructions for
details.This year will also include one or more industrial sessions on
the architecture of future NoC platforms. The objective of these
sessions is to provide a forum for industry leaders to share their
experiences and perspectives on the technical challenges facing future
platforms and discuss potential solutions. Check the submission page
for details on submissions to this session. These sessions will
feature a small number of papers (4-6) covering experiences from
industrial design and development.

Proposals for tutorials, special sessions, and panels are also
invited. Please see the detailed submission instructions for paper,
tutorial, special sessions, and panel proposals at the submission

– Abstract registration deadline February, 27th, 2015
– Full paper submission deadline March 6th, 2015
– Notification of acceptance May 5th, 2015
– Final version due June 1st, 2015
– Industry Session submission deadline March 23rd 2015

General Co-Chairs
– Andre Ivanov, University of British Columbia
– Diana Marculescu, Carnegie Mellon University
Program Co-Chairs
– Partha Pratim Pande, Washington State University
– José Flich, Universitat Politècnica de València

Call for Papers: ALCHEMY Workshop (Deadline: Jan 15)

Submitted by Loïc CUDENNEC
June 1 to June 3, 2015

Submitted by Loïc CUDENNEC

Architecture, Languages, Compilation and Hardware support
for Emerging ManYcore systems (ALCHEMY Workshop 2015)

Held in conjunction with ICCS 2015
Reykjavik, Iceland
1-3 June 2015

[1] Submission deadline extended to January 15.
[2] 27 thematic workshops are registered
[3] In addition to the Full Paper submission, we offer a Presentation Only
option (a short abstract is published in a book of abstracts,
but not in proceedings). You may also go for a Poster presentation,
with or without a full paper.

The International Conference on Computational Science (ICCS) is an annual
conference that brings together researchers and scientists from mathematics
and computer science as basic computing disciplines, researchers from various
application areas who are pioneering computational methods in sciences such
as physics, chemistry, life sciences, and engineering, as well as in arts and
humanitarian fields, to discuss problems and solutions in the area,
to identify new issues, and to shape future directions for research.

Massively parallel processors have entered high performance computing
architectures, as well as embedded systems. In June 2014, the TOP500
number one system (Tianhe-2) features the 57-core Intel Xeon Phi
processor. The increase of the number of cores on a chip is expected
to rise in the next years, as shown by the ITRS trends: other examples
include the Kalray MPPA 256-core chip, the 63-core Tilera GX processor
and even the crowd-funded 64-core Parallella Epiphany chip. In this
context, developers of parallel applications, including heavy
simulations and scientific calculations will undoubtedly have to cope
with many-core processors at the early design steps.

In the two past sessions of the Alchemy workshop, held together with
the ICCS meeting, we have presented significant contributions on the
design of many-core processors, both in the hardware and the software
programming environment sides, as well as some industrial-grade
application case studies. In this 2015 session, we seek academic
and industrial works that contribute to the design and the
programmability of many-core processors.

Topics include, but are not limited to:
– Programming models and languages for many-cores
– Compilers for programming languages
– Runtime generation for parallel programming on manycores
– Architecture support for massive parallelism management
– Enhanced communications for CMP/manycores
– Shared memory, data consistency models and protocols
– New operating systems, or dedicated OS
– Security, crypto systems for manycores
– User feedback on existing manycore architectures (e.g., Adapteva
Epiphany, Intel Phi, Kalray MPPA, ST STHorm, Tilera Gx, TSAR, etc)

This year, there will be two formats for the presentation at the
workshop. The usual full-length paper is 10 pages according to the ICCS
format, and the short-paper format well fitted for works in progress,
with a maximum of 2 pages. The accepted papers for full-length paper
will be published alongside with the ICCS proceedings in Procedia
Computer Science, whereas the short-papers will be presentation and
poster only at the conference (with proceedings and presentations
available from the workshop website).

The manuscripts of up to 10 pages, written in English and formatted
according to the EasyChair templates, should be submitted electronically.
Templates are available for download in the Easychair right-hand-side menu
in a “New submission” mode.

Submission Deadline: Jan 15, 2015
Notification Due: Feb 15, 2015
Final Version Due: Mar 15, 2015
Workshop: Jun 1 – 3, 2015

Akram BEN AHMED, University of Aizu, Fukushima, Japan
Jeronimo CASTRILLON, CFAED / TU Dresden, Germany
Camille COTI, Université de Paris-Nord, France
Stephan DIESTELHORST, ARM Ltd; Cambridge, UK
Aleksandar DRAGOJEVIC, Microsoft Research Cambridge, UK
Daniel ETIEMBLE, Université de Paris-Sud, France
Bernard GOOSSENS, Université de Perpignan, France
Vincent GRAMOLI, NICTA / University of Sydney, Australia
Jorn W. JANNECK, Lund University, Sweden
Vianney LAPOTRE, Université de Bretagne-Sud, France
Eric LENORMAND, Thales TRT, France
Stéphane LOUISE, CEA, LIST, France
Vania MARANGOZOVA-MARTIN, Université Joseph-Fourier Grenoble, France
Marco MATTAVELLI, EPFL, Switzerland
Eric PETIT, Université de Versailles Saint Quentin-en-Yvelines, France
Erwan PIRIOU, CEA, LIST, France
Antoniu POP, University of Manchester, UK
Mickaël RAULET, IETR / INSA de Rennes, France
Jason RIEDY, Georgia Institute of Technology, USA
Etienne RIVIERE, Université de Neuchâtel, Switzerland
Thomas ROPARS, EPFL, Switzerland
Martha JOHANNA SEPULVEDA, INRIA, École Centrale de Lyon, France
Osamu TATEBE, AIST / University of Tsukuba, Japan
(to be extended)

Call for Papers: IEEE Micro Special Issue on Alternative Computing Designs & Technologies

Submitted by jayvant anantpur

Submitted by jayvant anantpur

IEEE Micro Special Issue on Alternative Computing Designs & Technologies

Luis Ceze (University of Washington)
Olivier Temam (Google)

SUBMISSIONS DUE: March 5th 2015
PUBLICATION DATE: September-October 2014

As the benefits of Moore’s law progressively diminish and come at a greater
cost, there is a growing urge to consider alternative computing approaches in
order to keep increasing computational capabilities fast enough to continue
spurring innovation. Because it is unlikely that we will find a replacement to
Moore’s law that will provide again decades of sustained growth, we may have
to accept that computing hardware will become multi-faceted, both in terms of
design approaches and implementation technologies. Alternative approaches may
mean breaking away from CPUs with radically different designs using mature
CMOS technologies, and they may also entail radically different fundamental
technologies. In this special edition, we want to be inclusive and contemplate
both types of alternative approaches. We are looking for papers that discuss
ideas that will lead to significant quantitative gains in performance and
efficiency and/or are enabler of new forward-looking applications.

Also breaking away from traditional CFPs, we voluntarily decided not to outline
a set of topics which could only have the effect of narrowing down the scope of
alternative approaches we are willing to consider. If in doubt whether we will
welcome your submission, please do not hesitate to contact us, if possible
(but not necessarily) with an abstract. Please keep in mind that IEEE Micro is
about computing architecture at large, and that it is a very high-quality
publication, two criteria we will diligently enforce.

Please log onto IEEE CS Manuscript Central (
micro-cs) to submit your manuscript to the “Alternative Computing Designs and
Technologies” issue. Please direct questions to the IEEE Micro magazine
assistant ( For the manuscript submission, acceptable
file formats include Microsoft Word and PDF. Manuscripts should not exceed
5,000 words including references, with each average-size figure counting as 150
words toward this limit. Please include all figures and tables, as well as a
cover page with all the relevant author contact information (name, postal
address, phone, fax, and e-mail address) and a 200-word abstract. Submitted
manuscripts must not have been previously published or currently submitted for
publication elsewhere, and all manuscripts must be cleared for publication. All
previously published papers must have at least 30% new content compared to
any conference (or other) publication. Accepted articles will be edited for
structure, style, clarity, and readability. For more information, please visit
the IEEE Micro Author Center(

March 5: Initial submissions due
April 30: First notification
May 21: Revised papers due
June 25: Final notification

For any further information and questions please contact Guest Editors,
Luis Ceze ( and Olivier Temam (

Call for Papers: SYSTOR 2015

Submitted by Doron Chen
May 26 to May 28, 2015

Submitted by Doron Chen

The 8th ACM International Systems and Storage Conference (SYSTOR 2015)
Haifa, Israel
May 26-28, 2015

Paper submission deadline: March 5, 2015

SYSTOR has a broad scope, promoting experimental and practical computer
systems research encompassing the following topics:

– Operating systems, computer architecture, and their interactions
– Distributed, parallel, and cloud systems
– Networked, mobile, wireless, peer-to-peer, and sensor systems
– Runtime systems and compiler/programming-language support
– File and storage systems
– Security, privacy, and trust
– Virtualization
– Embedded and real-time systems
– Fault tolerance, reliability, and availability
– Deployment, usage, and experience
– Performance evaluation and workload characterization

– Full & short paper submission: March 5, 2015
– Highlights paper submission: April 30, 2015
– Paper notification: April 5, 2015
– Camera-ready submission: April 17, 2015
– Poster submission: April 30, 2015
– Poster notification: May 11, 2015

SYSTOR is a home for high-quality international systems research of a
practical nature and welcomes both academic and industrial contributions. We
solicit paper submissions in three separate categories:

– Full papers: should report original, previously unpublished high-
quality research, and be at most 10 pages of content, including everything
except references, which may use additional pages. The program committee
will review all submitted papers. Accepted papers will be presented at the
conference and included in the conference proceedings, to be published by
the ACM.

– Short papers: should report original, previously unpublished work for
which a full paper may not be suitable. Short paper submissions may report
on smaller ideas; unconventional ideas that are still in a preliminary stage
of development; interesting negative results; experimental (in)validation of
previous findings; controversial positions that challenge common wisdom; and
fresh approaches for addressing old problems. Short papers may be at most 5
pages, excluding references. They will undergo the same review process as
full papers. If accepted, short papers will be allocated a shorter talk slot
during the conference and will also be published in the conference

– Highlight papers: should contain exciting research results that have
been accepted to a recent top-tier systems conference or journal. A small
sub-committee will briefly review these submissions and will select the
most suitable ones for SYSTOR. The corresponding presentations will then be
“replayed” at SYSTOR for the benefit of the local community. A highlight
paper submission should include the full citation of the published or
accepted paper and a link to it. Accepted submissions will not be published
in the proceedings.

SYSTOR 2015 will host distinguished keynote speakers, a poster session, and
several social events at the conference. Our goal is to provide an excellent
forum for interaction across the systems community: international, academic,
and industrial, for both students and more established members.

Additional details can be found at:

Gernot Heiser (NICTA and UNSW, Australia)
Idit Keidar (Technion)

Dalit Naor (IBM Research)

David Breitgand (IBM Research)

Michael Factor (IBM Research)

Ethan Miller (University of California Santa Cruz)
Liuba Shrira (Brandeis University)
Dan Tsafrir (Technion)
Yaron Wolfsthal (IBM Research)
Erez Zadok (Stony Brook University)