Call for Proposals: Intel-Altera Heterogeneous Architecture Research Platform Program

Submitted by Nicholas Carter

Submitted by Nicholas Carter

Intel-Altera Heterogeneous Architecture Research
Platform (HARP) Program

 

Intel® Corporation and Altera® Corporation are pleased to announce the
Heterogeneous Architecture Research Platform (HARP) program, which
will provide faculty with computer systems containing Intel
microprocessors and an Altera Stratix® V FPGA module that incorporates
Intel® QuickAssist Technology in order to spur research in programming
tools, operating systems, and innovative applications for
accelerator-based computing systems.

In recent years, accelerators and coprocessors have attracted a great
deal of interest, but the effort required to program heterogeneous
systems has limited their impact. Current programming tools for these
technologies require a great deal of user input to select the portions
of an application that should be executed on the coprocessor or
accelerator, to manage data transfers between the CPU and the other
chip(s), and to tune the application to match the characteristics of
the hardware. Worse yet, performing this work generally results in an
application that only performs well on a particular device, with
little portability to other systems.

Overcoming this drawback will require research into tools that reduce
the amount of effort required to map an application onto a coprocessor
or accelerator, operating systems and schedulers that can
automatically assign tasks to the most efficient hardware in a
heterogeneous system, techniques to make applications portable across
different hardware technologies, and innovative applications that
demonstrate the potential of heterogeneous systems. To support and
encourage this research, the HARP program is making systems available
to researchers that pair a 12-core Intel microprocessor with an Altera
Stratix V FPGA module that incorporates Intel QuickAssist Technology.

We plan to build approximately 20 HARP systems to be donated to
academic researchers based on responses to this call. Researchers
awarded HARP systems may also qualify for a license to use the Altera
Quartus® II Design Software and other Altera software tools free of
charge under the terms of the applicable software license and the
Altera University Program (details of such program are on the Altera
website). Additionally, researchers awarded HARP systems will be
invited to a series of workshops to be held at Intel campuses. The
first workshop, to be held in early 2015, will include tutorials on
the Intel QuickAssist Technology, and will give researchers an
opportunity to discuss ideas for research using the HARP systems.
Later workshops will allow researchers to present the results of their
work and discuss opportunities for technology transfer with Intel
researchers and product designers.

Topics of interest to this CFP include, but are not limited to:
– Compilation techniques to map applications onto accelerator-based systems
– Operating system and scheduler techniques for accelerator-based systems
– Techniques to evaluate the suitability of algorithms to different components
of a heterogeneous architecture and select the most-effective hardware for
different phases of an application
– Languages and libraries for coprocessors and accelerators, including
domain-specific languages
– Novel accelerator-based applications that demonstrate the potential of the
Altera FPGA module with Intel QuickAssist Technology.
– Studies of algorithm/application remapping/tuning to exploit different
aspects of the HARP system
– Analysis of application characteristics that support mapping onto a
heterogeneous platform with coherent communication links
– Approaches that exploit the benefits of low-latency cache-coherent
communication between CPU and accelerators.

ELIGIBILITY:
To be eligible for this program, proposers must be associated with a non-profit
college, university, or research institution. Proposer may not be a resident or
national of any of the following countries: Cuba, Iran, North Korea, Sudan, and
Syria. U.S. export regulations prohibit the export of goods and services to Cuba,
Iran, North Korea, Sudan and Syria. Therefore, residents or nationals of these
countries are not eligible to participate. Proposer and their institution must not
be listed on a denial order published by the U.S. Government or any other
applicable Government. We welcome proposals from individual researchers,
groups, and centers. In most cases, successful proposals will receive a single
HARP system, although we will consider exceptions if the specific project requires
multiple systems to succeed or the size of the requesting group justifies a
multi-system donation.

Proposals will be evaluated on technical merit, potential impact of the proposed
research, the proposer’s ability to carry out the proposed research, and potential
for collaboration with Intel and Altera researchers. Submitters of successful
proposals will be expected to sign an agreement not to resell the donated
equipment for a period of three years, to make results of their work available to
Intel and Altera, and to participate on the program’s web forum by giving
feedback about their experiences with the HARP platforms.

Each Recipient must acknowledge that donated equipment is subject to export
controls under U.S. and other applicable Government laws and regulations.
Recipient will comply with these laws and regulations governing export, re-
export, import, transfer, distribution, use, and servicing of donated equipment,
and agree to obtain all required Government authorizations. Recipient will not
sell or transfer donated equipment to any entity listed on a denial order published
by Government, or a country subject to sanctions, without first obtaining a
license or authorization. Recipient will not use, sell, or transfer donated
equipment for purposes prohibited by Government, including, without limitation,
the development, design, manufacture, or production of nuclear, missile,
chemical or biological weapons, unless authorized by a specific license. For more
details on your export obligations, please visit http://www.intel.com/content/www/us/en/legal/export-compliance.html.

SUBMISSION INSTRUCTIONS:
Interested parties should submit a proposal of at most two 8.5″x11″ pages, in
at least 10pt font, to harp_program@intel.com by midnight Pacific Standard
Time (UTC -8) on March 20, 2015. Proposals should be in PDF format, and
should include the name and institution of the individual(s) requesting the
platform, a description of the research that will be performed using the platform,
and a brief summary of the requestor’s relevant previous work, if any.
 

Call for Papers: Workshop on Large-Scale Parallel Processing

Submitted by Darren J. Kerbyson
http://hpc.pnl.gov/conf/LSPP/
May 25 to May 29, 2015

Submitted by Darren J. Kerbyson
http://hpc.pnl.gov/conf/LSPP/

Workshop on Large-Scale Parallel Processing
to be held in conjunction with
IEEE International Parallel and Distributed Processing Symposium
Hyderabed, India
May 25th, 2015
 

SUBMISSION DEADLINE: January 16th 2015
 

The workshop on Large-Scale Parallel Processing is a forum that
focuses on computer systems that utilize thousands of processors
and beyond. Large-scale systems, referred to by some as
extreme-scale and Ultra-scale, have many important research
aspects that need detailed examination in order for their
effective design, deployment, and utilization to take place.
These include handling the substantial increase in multi-core
on a chip, the ensuing interconnection hierarchy, communication,
and synchronization mechanisms. Increasingly this is becoming an
issue of co-design involving performance, power and reliability
aspects. The workshop aims to bring together researchers from
different communities working on challenging problems in this
area for a dynamic exchange of ideas. Work at early stages of
development as well as work that has been demonstrated in
practice is equally welcome.

Of particular interest are papers that identify and analyze novel
ideas rather than providing incremental advances in the following
areas:

– LARGE-SCALE SYSTEMS : exploiting parallelism at large-scale,
the coordination of large numbers of processing elements,
synchronization and communication at large-scale, programming
models and productivity

– NOVEL ARCHITECTURES AND EXPERIMENTAL SYSTEMS : the design of
novel systems, the use of processors in memory (PIMS),
parallelism in emerging technologies, future trends.

– MULTI-CORE : utilization of increased parallelism on a single
chip (MPP on a chip such as the Cell and GPUs), the possible
integration of these into large-scale systems, and dealing with
the resulting hierarchical connectivity.

– MONITORING, ANALYSIS AND MODELING : tools and techniques for
gathering performance, power, thermal, reliability, and other
data from existing large scale systems, analyzing such data
offline or in real time for system tuning, and modeling of
similar factors in projected system installations.

– ENERGY MANAGEMENT: Techniques, strategies, and experiences
relating to the energy management and optimization of
large-scale systems.

– APPLICATIONS : novel algorithmic and application methods,
experiences in the design and use of applications that scale to
large-scales, overcoming of limitations, performance analysis
and insights gained.

– WAREHOUSE COMPUTING: dealing with the issues in advanced
datacenters that are increasingly moving from co-locating many
servers to having a large number of servers working cohesively,
impact of both software and hardware designs and optimizations
to achieve best cost-performance efficiency.

Results of both theoretical and practical significance will be
considered, as well as work that has demonstrated impact at
small-scale that will also affect large-scale systems. Work may
involve algorithms, languages, various types of models, or
hardware.

SUBMISSION GUIDELINES
Papers should not exceed eight single-space pages (including
figures, tables and references) using a 12-point font on 8.5×11
inch pages. Submissions in PostScript or PDF should be made
using EDAS (www.edas.info). Informal enquiries can be made to
Darren.Kerbyson@pnl.gov. Submissions will be judged on correctness,
originality, technical strength, significance, presentation
quality and appropriateness. Submitted papers should not have
appeared in or under consideration for another venue.

IMPORTANT DATES
Submission deadline: January 16th 2015
Notification of acceptance: February 14th 2015
Camera-Ready Papers due: February 28th 2015

WORKSHOP CHAIRS
Darren J. Kerbyson, Pacific Northwest National Laboratory
Ram Rajamony, IBMa Austin Research Lab
Charles Weems,University of Massachusetts

STEERING COMMITTEE
Johnnie Baker,Kent State University
Alex Jones, University of Pittsburgh
H.J. Siegel, Colorado State University
Guangming Tan, ICT, Chinese Academy of Sciences
Lixin Zhang, ICT, Chinese Academy of Sciences

PROGRAM COMMITTEE
Pavan Balaji, Argonne National Laboratory, USA
Kevin J. Barker, Pacific Northwest National Laboratory
Laura Carrington, San Diego Supercomputer Center, USA
I-Hsin Chung, IBM T.J. Watson Research Lab, USA
Tim German, Los Alamos National Laboratory, USA
Georg Hager, University of Erlangen, Germany
Simon Hammond, Sandia National Laboratory, USA
Martin Herbordt, Boston University, USA
Kalapriya Kannan, IBM Research, India
Daniel Katz, University of Chicago, USA
Celso Mendes, University of Illinois Urbana-Champagne
Bernd Mohr,Forschungszentrum Juelich, Germany
Ankur Narang, IBM Research, India
Phil Roth, Oak Ridge National Laboratory, USA
Jose Sancho, Barcelona Supercomputer Center, USA
Gerhard Wellein, University of Erlangen, Germany
Ulrike Yang, Lawrence Livermore National Laboratory, USA

LOCAL WORKSHOP CHAIR
Ankur Narang, IBM Research India

LOCAL PUBLICITY CHAIR
Kalapriya Kannan, IBM Research India
 

Call for Participation: HPCA 2015

Submitted by Michael Taylor
http://darksilicon.org/hpca
February 7 to February 11, 2015

Submitted by Michael Taylor
http://darksilicon.org/hpca

2015 IEEE International Symposium on High Performance
Computer Architecture (HPCA)

San Francisco Airport Marriott Waterfront Hotel
San Francisco Bay Area, California, USA
Feb 7-11, 20015
 

EARLY REGISTRATION DEADLINE: January 11
Early hotel reservation rate ($179): Expires shortly after reg deadline.
 

HPCA is a premier annual computer architecture conference sponsored
by the Computer Society of the Institute of Electrical and Electronics
Engineers (IEEE CS). It will bring together researchers, academics,
and industrial engineers from all over the world. It provides an
international forum for these experts to promote, share, and discuss
various issues and developments in the growing field of High
Performance Computer Architecture.

We have pulled together a program of 60 talks, almost 30 workshops
and tutorials, co-organized with CGO and PPoPP, and three excellent
keynote speakers.

http://darksilicon.org/hpca