Call for Papers: IEEE Micro Special Issue on Alternative Computing Designs & Technologies

Submitted by jayvant anantpur

Submitted by jayvant anantpur

IEEE Micro Special Issue on Alternative Computing Designs & Technologies

Luis Ceze (University of Washington) and
Olivier Temam (Google)

SUBMISSIONS DUE: March 5, 2015

As the benefits of Moore’s law progressively diminish and come at a greater
cost, there is a growing urge to consider alternative computing approaches
in order to keep increasing computational capabilities fast enough to
continue spurring innovation. Because it is unlikely that we will find a
replacement to Moore’s law that will provide again decades of sustained
growth, we may have to accept that computing hardware will become
multifaceted, both in terms of design approaches and implementation
technologies. Alternative approaches may mean breaking away from CPUs with
radically different designs using mature CMOS technologies, and they may
also entail radically different fundamental technologies. In this special
edition, we want to be inclusive and contemplate both types of alternative
approaches. We are looking for papers that discuss ideas that will lead to
significant quantitative gains in performance and efficiency and/or are
enabler of new forward looking applications.

Also breaking away from traditional CFPs, we voluntarily decided not to
outline a set of topics which could only have the effect of narrowing down
the scope of alternative approaches we are willing to consider. If in doubt
whether we will welcome your submission, please do not hesitate to contact
us, if possible (but not necessarily) with an abstract. Please keep in mind
that IEEE Micro is about computing architecture at large, and that it is a
very high quality publication, two criteria we will diligently enforce.

Please log onto IEEE CS Manuscript Central
( to submit your manuscript to the
“Alternative Computing Designs and Technologies” issue. Please direct
questions to the IEEE Micro magazine assistant ( For
the manuscript submission, acceptable file formats include Microsoft Word
and PDF. Manuscripts should not exceed 5,000 words including references,
with each average size figure counting as 150 words toward this limit.
Please include all figures and tables, as well as a cover page with all the
relevant author contact information (name, postal address, phone, fax, and
email address) and a 200word abstract. Submitted manuscripts must not have
been previously published or currently submitted for publication elsewhere,
and all manuscripts must be cleared for publication. All previously
published papers must have at least 30% new content compared to any
conference (or other) publication. Accepted articles will be edited for
structure, style, clarity, and readability. For more information, please
visit the IEEE Micro Author Center(

March 5: Initial submissions due
April 30: First notification
May 21: Revised papers due
June 25: Final notification

For any further information and questions please contact Guest Editors,
Luis Ceze ( and Olivier Temam (

Call for Papers: IEEE Micro General Interest 2015

Submitted by jayvant anantpur

Submitted by jayvant anantpur

IEEE Micro General Interest 2015

IEEE Micro seeks general-interest submissions for publication in upcoming
2015 issues. The submissions should present the design, performance, or
application of microcomputer and microprocessor systems. Summaries of work
in progress and descriptions of recently completed work are most welcome,
as are tutorials and position statements.

IEEE Micro is a bimonthly magazine of the IEEE Computer Society that
reaches an international audience of computer designers, system
integrators, and users. IEEE Micro publishes 6 to 8-page papers that are
slightly less technical and less quantitative than top-conference and
archival journal papers, while being insightful, slightly more
qualitative, with a high tutorial value, and up to date with current
trends. IEEE Micro attracts a broad readership among both academics and
practitioners who want to keep up with new results and trends in the field
of computer architecture.

Areas of interest include, but are not limited to:
– Processor, memory, and storage systems architecture
– Parallel and multicore systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Heterogeneous and accelerator-based architectures
– Neuromorphic computing architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems
– Design of high-performance and low-power chips

Log onto IEEE CS Manuscript Central
( and submit your manuscript.
Please direct questions to the IEEE Micro magazine assistant
(micro-¬ regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and
PDF. Manuscripts should not exceed 5,000 words including references, with
each average¬size figure counting as 150 words toward this limit. Please
include all figures and tables, as well as a cover page with author
contact information (name, postal address, phone, fax, and e¬mail address)
and a 200¬-word abstract. Submitted manuscripts must not have been
previously published or currently submitted for publication elsewhere, and
all manuscripts must be cleared for publication. All previously published
papers must have at least 30% new content compared to any conference (or
other) publication. Accepted articles will be edited for structure, style,
clarity, and readability. For more information, please visit the IEEE
Micro Author Center
The submission site is continuously open. Papers of general interest
appear in upcoming issues as space allows, or are grouped in the Nov/Dec
2015 issue.

Contact the Editor-in-Chief, Lieven Eeckhout, at

Call for Nominations: ACM SIGARCH Maurice Wilkes Award

Submitted by Per Stenström

Submitted by Per Stenström
ACM SIGARCH Maurice Wilkes Award


The award of $2,500 is given annually for an outstanding contribution to
computer architecture made by an individual whose computer-related
professional career (graduate school or full-time employment, whichever began
first) started no earlier than January 1st of the year that is 20 years prior
to the year of the award (At the discretion of the SIGARCH Executive
Committee, eligibility may be adjusted for documented family-related or
medical leaves from employment. Questions about eligibility should be directed
to the SIGARCH Chair (

The award is presented annually at the International Symposium on Computer
Architecture Awards Banquet. This year’s recipient will be invited to accept
the award at ISCA 2015.

Nominations should consist of:
1) Name, address, and phone number of person making the nomination.
2) Name and address of candidate for whom the award is recommended.
3) A statement (between 200 and 500 words long) as to why the candidate
deserves the award. Note that since the award is for an outstanding
contribution, the statement and supporting letters should address what the
contribution is and why it is both outstanding and significant.
4) The name(s) and email address(es) or telephone number(s) of others who
agree with the recommendation. Supporting letters from such persons are
useful but not required.

Please send nominations (preferably electronically) no later than March 31,
2015 to the Chair of the Nominating Committee (

The recipient of the Maurice Wilkes Award is selected by a vote of the SIGARCH
Executive Committee and Board from a list of nominees submitted by the
SIGARCH Awards Committee.

The SIGARCH Awards Committee consists of three members. Each member of the
committee is selected by the Chair of SIGARCH to serve a three year term, with
one new member added to the committee each year. Each committee member
will serve as the Chair of the Awards Committee during their second year on the
committee. Each year at least one member of the Awards Committee should be a
member of the SIGARCH Executive Committee or Board, and at least one
member should not be a member of the SIGARCH Executive Committee or Board.
The Awards Committee should nominate from one to three candidates for
selection by the SIGARCH Executive Committee and Board. The Awards
Committee should transmit supporting materials for its nominees, along with a
ranking of the nominees if appropriate, to the SIGARCH Chair. When a winner is
selected, the SIGARCH Chair and the Awards Committee Chair will choose a
citation for the Award.

Per Stenstrom (chair)
Department of Computer Science and Engineering
Chalmers University of Technology
S-412 96 Gothenburg, Sweden

Dean Tullsen
Department of Computer Science and Engineering
University of California, San Diego
9500 Gilman Drive
La Jolla, CA 92093-0114

Margaret Martonosi
Department of Computer Science
Princeton University
Princeton, NJ 08540-5233

Tool Release: DESTINY, a 3D SRAM/eDRAM/NVM cache modeling tool

Submitted by Sparsh Mittal

Submitted by Sparsh Mittal

Oak Ridge National Lab, Penn State, and UCSB are pleased to announce the
release of DESTINY (a 3D dEsign-Space exploraTIon tool for SRAM, eDRAM and
Non-volatile memorY). DESTINY is a tool for modeling both 2D and 3D caches
designed with five prominent memory technologies: SRAM, eDRAM (embedded
DRAM), PCM (or PCRAM), STT-RAM (or STT-MRAM) and ReRAM (or RRAM), which
covers both conventional and emerging technologies and both volatile and
non-volatile memory technologies. It can be used to model technology
devices ranging from 22nm to 180nm. DESTINY has been validated against
several commercial prototypes. Thus, DESTINY is intended to be a
comprehensive tool, extending the capabilities of CACTI, CACTI-3DD, and NVSim,
on which DESTINY is based.

The following DATE-2015 paper provides a general introduction of DESTINY:
Matt Poremba, Sparsh Mittal, Dong Li, Jeffrey S Vetter and Yuan Xie,
“DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches”,
DATE, 2015. (Available at

This work was supported by the Office of Advanced Scientific Computing
Research in the U.S. Department of Energy, under the project “Blackcomb –
Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems”

For receiving announcements, or sending questions and comments, please
subscribe to the mailing list by visiting the
following webpage:

Call for Papers: NAS 2015

Submitted by Ramon Bertran
April 3, 2015

Submitted by Ramon Bertran

10th IEEE International Conference on Networking, Architecture and Storage (NAS)
Boston, Massachusetts, USA,
August 6-7, 2015

Sponsored by IEEE Computer Society’s Technical Committees on Computer
Architecture (TCCA), Parallel Processing (TCPP) and Distributed Processing

– Paper Submission: April 3, 2015
– Notification: May 20, 2015
– Camera-Ready Copy: June 29, 2015

The International Conference on Networking, Architecture, and Storage (NAS)
provides a high-quality international forum to bring together researchers and
practitioners from academia and industry to discuss cutting-edge research on
networking, high-performance computer architecture, and parallel and distributed
data storage technologies. NAS 2015 will expose participants to the most recent
developments in the interdisciplinary areas.

Authors are invited to submit previously unpublished work for possible
presentation at the conference. Papers should be submitted for double-blind
review. The program committee will nominate best papers for recognition in
the three conference topic areas. All papers will be evaluated based on their
novelty, fundamental insight, experimental evaluation, and potential for
long-term impact; new-idea papers are encouraged. All accepted papers will
be published in IEEE digital library.

Papers are solicited in fields that include, but are not limited to, the
– Processor, cache, memory system architectures
– Parallel and multi-core architectures
– GPU architecture and programming
– Data-center scale architectures
– Architecture for handheld or mobile devices
– Accelerator-based architectures
– Application-specific, reconfigurable or embedded architectures
– HW/SW co-design and tradeoffs
– Power and energy efficient architectures and techniques
– Effects of circuits and emerging technology on architecture
– Cloud and grid computing
– Architecture, networking or storage modeling and simulation methodologies
– Non-volatile memory technologies
– Software defined networking
– Storage performance and scalability
– File systems, object-based storage
– Energy-aware storage
– SSD architecture and applications
– Parallel I/O
– Cloud storage
– Storage virtualization and security
– Software defined storage
– Big Data infrastructure
– Big Data services and analytics

General Chair
– Resit Sendag (U of Rhode Island)
Program Co-Chairs:
– Jun Wang (U of Central Florida)
– Iris Bahar (Brown U)
Vice Program Chairs:
– Networking: Weikuan Yu (Auburn U) and Haiying Shen (Clemson U)
– Architecture: Martin Herbordt (Boston U) and Tali Moreshet (Boston U)
– Storage: Xiaosong Ma (Qatar Computing Res. Inst. & NC State U) and Ali Butt
(Virginia Tech)
Local Arrangements Chair:
– Ningfang Mi (Northeastern U)
Publications Chair:
– Gus Uht (U of Rhode Island)
Registration Chair:
– Yan Sun (U of Rhode Island)
Finance Chair:
– Yan Luo (U of Massachussetts-Lowell)
Industry Liaison Chair:
– Ming Zhang (EMC)
Publicity Co-chairs:
– Chengsheng Xie (Huazhong U Sci. Tech)
– Andre Brinkmann (Universitat Mainz)
– Ramon Bertran (IBM)
– Alper Buyuktosunoglu (IBM)
Submission Chair:
– Xunchao Chen (U of Central Florida)
Web Chair:
– Ibrahim Burak Karsli (U of Rhode Island)
Steering Committee
– Xubin He (Virginia Commonwealth U)
– Changsheng Xie(Huazhong U of Sci.Tech)
– Andre Brinkmann (U Mainz)
– Jian Li (IBM Austin Research Lab)
– Tao Li (University of Florida)
– Marco D Santambrogio (Politec. Milano)
– Hongbin Sun (Xi’An Jiaotong U)

Networking Track
– Weikuan Yu, Auburn University (co-chair)
– Haiying Shen, Clemson University (co-chair)
– Sarp Oral, Oak Ridge National Lab
– Shane Canon, Lawrence Berkeley National Lab
– Richard Graham, Mellanox
– Amith R Mamidala, IBM
– Jian Tan, IBM
– Ronald Brightwell, Sandia National Lab
– Gerald F II Lofstead, Sandia National Lab
– Wenjun Wu, Beihang University
– Jia Rao, University of Colorado Cold Springs
– Seung-Jong Park, Louisiana State University
– Xin Yuan, Florida State University
– Saad Biaz, Auburn University
– Kang Chen, Clemson University
– Yaohang Li, Old Dominion University
– Shan Lin, Temple University
– Chuan Yue, University of Colorado Colorado Springs
– Mengjun Xie, University of Arkansas at Little Rock
– Lei Yu, Georgia State University
– Yang Guo, Bell Labs
– Yongning Tang, Illinois State University
– Fangzhe Chang, Bell Labs, Alcatel-Lucent
– Feng Deng, Clemson University
– Weichen Liu, Chongqing University
– Zhi Wang, Tsinghua University
– Xiaojun Hei, Huazhong University of Science and Technology
– Yuan He, Hong Kong University of Science and Technology
– Di Wu, Sun Yat-Sen University
– Liudong Xing, University of Massachusetts Dartmouth
– Gang Zhou, College of William and Mary
– Jiangyi Hu, Devry University
– Junwei Cao, Tsinghua University
– Wenzhong Li, Nanjing University
– Surendar Chandra, EMC Data Protection and Availability Division
– Wei Zhang, Hong Kong University of Science and Technology
– Yao Liu, SUNY Binghamton
– Chiu Tan, Temple University
– Kyoungwon Suh, Illinois State University
Architecture Track
– Martin Herbordt, Boston University (co-chair)
– Tali Moreshet, Boston University (co-chair)
– Lide Duan , University of Texas at San Antonio
– Cesare Ferri , Marvel
– Mark Hempstead , Drexel University
– Ajay Joshi , Boston University
– Dong Li , Qualcomm
– Xiaoyao Liang , Shanghai Jiao Tong University
– Yan Luo , University of Massachusetts Lowell
– Vijay Nagarajan , University of Edinburgh
– Gi-Ho Park , Sejong University
– Dmitry Ponomarev , SUNY
– Kelly Shaw , University of Richmond
– Magnus Sjalander, Uppsala University
– Bharat Sukhwani, IBM
– Radu Teodorescu , Ohio-State University
– Jing Wang , Capital Normal University
– Jason Xue , City University of Hong Kong
– Zhibin Yu , Shenzhen Institute of Advanced Technology
– Jidong Zhai , Tsinghua University
– Dongyuan Zhan , AMD
– Chuanjun Zhang , Intel
– Wei Zhang , Virginia Commonwealth University
– Ping Zhou , Intel
– Zhichun Zhu , University of Illinois at Chicago
Storage Track
– Ali Butt, Virginia Tech (co-chair)
– Xiaosong Ma, Qatar Computing Research Institute and North Carolina State
University (co-chair)
– Youngjae Kim, Oak Ridge National Laboratory
– Gary Liu, Oak Ridge National Laboratory
– Fei Meng, North Carolina State University and PureStorage
– Xing Wu, Amazon
– Xuanhua Shi, Huazhong University of Science and Technology
– Zhe Zhang, Cloudera
– Sudharshan Vazhkuda, ORNL
– Shuibing He, IIT
– Yong Chen, TTU
– Suren Byna, LBL
– Medha Bhadkamkar, Symantec Research Labs
– Avani Wildani, Salk Institute
– Min Li, IBM TJ Watson Research Center
– Aayush Gupta, IBM Almaden Research Center
– Lei Tian, Tintri
– Tao Xie, San Diego State University
– Song Jiang, Wayne State University
– Abhishek Chandra, University of Minnesota
– Jay Lofstead, Sandia National Laboratories
– Jinho Hwang, IBM Research
– Yifeng Zhu, University of Maine
– Xiao Qin, Auburn University
– Douglas Thain, University of Notre Dame
– Alan Sussman, University of Maryland
– Peter Varman, Rice University
– Nitin Agrawal, NEC Labs
– Fang Zheng, IBM T.J. Watson Research Center
– Qingdong Wang, University of Central Florida/Huizhou University

Call for Papers: SYSTOR 2015

Submitted by Doron Chen
May 26 to May 28, 2015

Submitted by Doron Chen

8th ACM International Systems and Storage Conference (SYSTOR 2015)
Haifa, Israel
May 26-28, 2015

Paper submission deadline: March 5, 2015

SYSTOR has a broad scope, promoting experimental and practical
computer systems research encompassing the following topics:
– Operating systems, computer architecture, and their interactions
– Distributed, parallel, and cloud systems
– Networked, mobile, wireless, peer-to-peer, and sensor systems
– Runtime systems and compiler/programming-language support
– File and storage systems
– Security, privacy, and trust
– Virtualization
– Embedded and real-time systems
– Fault tolerance, reliability, and availability
– Deployment, usage, and experience
– Performance evaluation and workload characterization

– Full & short paper submission: March 5, 2015
– Highlights paper submission: April 30, 2015
– Paper notification: April 5, 2015
– Camera-ready submission: April 17, 2015
– Poster submission: April 30, 2015
– Poster notification: May 11, 2015

SYSTOR is a home for high-quality international systems
research of a practical nature and welcomes both academic and
industrial contributions. We solicit paper submissions in three
separate categories:

– Full papers: should report original, previously unpublished
high-quality research, and be at most 10 pages of content,
including everything except references, which may use
additional pages. The program committee will review all
submitted papers. Accepted papers will be presented at the
conference and included in the conference proceedings, to be
published by the ACM.

– Short papers: should report original, previously
unpublished work for which a full paper may not be suitable.
Short paper submissions may report on smaller ideas;
unconventional ideas that are still in a preliminary stage of
development; interesting negative results; experimental
(in)validation of previous findings; controversial positions
that challenge common wisdom; and fresh approaches for
addressing old problems. Short papers may be at most 5 pages,
excluding references. They will undergo the same review process
as full papers. If accepted, short papers will be allocated a
shorter talk slot during the conference and will also be
published in the conference proceedings.

– Highlight papers: should contain exciting research results
that have been accepted to a recent top-tier systems conference
or journal. A small sub-committee will briefly review these
submissions and will select the most suitable ones for SYSTOR.
The corresponding presentations will then be “replayed” at
SYSTOR for the benefit of the local community. A highlight
paper submission should include the full citation of the
published or accepted paper and a link to it. Accepted
submissions will not be published in the proceedings.

SYSTOR 2015 will host distinguished keynote speakers, a poster
session, and several social events at the conference. Our goal
is to provide an excellent forum for interaction across the
systems community: international, academic, and industrial, for
both students and more established members.

Additional details can be found at:

– Gernot Heiser (NICTA and UNSW, Australia)
– Idit Keidar (Technion)

– Dalit Naor (IBM Research)

– David Breitgand (IBM Research)

– Michael Factor (IBM Research)

– Ethan Miller (University of California Santa Cruz)
– Liuba Shrira (Brandeis University)
– Dan Tsafrir (Technion)
– Yaron Wolfsthal (IBM Research)
– Erez Zadok (Stony Brook University)

– Doron Chen (IBM Research)

Call for Papers: ISLPED 2015 (Extended Deadline for Abstracts: Mar 1)

Submitted by Andreas Burg
July 22 to July 24, 2015

Submitted by Andreas Burg

International Symposium on Low Power Electronics and Design (ISLPED) Rome, Italy
July 22 – July 24, 2015

Abstract Registration Deadline (extended): March 1st, 2015
Full paper submission Deadline: March 8th, 2015
Invited Talk, Panel, and Embedded Tutorial Proposals Deadline: April 1, 2015
Notification of Paper Acceptance: May 1, 2015
Submission of Camera-Ready Papers: June 1, 2015

Sponsored by the IEEE Circuits and Systems Society (CASS) and the ACM Special
Interest Group on Design Automation (SIGDA).

The International Symposium on Low Power Electronics and Design (ISLPED) is the
premier forum for presentation of innovative research in all aspects of low
power electronics and design, ranging from process technologies and
analog/digital circuits, simulation and synthesis tools, system-level design
and optimization, to system software and applications. Specific topics include,
but are not limited to, the following three main tracks and sub-areas:

1. Technology, Circuits, and Architecture

1.1. Technologies
Low-power technologies for Device, Interconnect, Logic, Memory,
2.5/3D, Cooling, Harvesting, Sensors, Optical, Printable, Biomedical,
Battery, and Alternative energy storage devices.

1.2. Circuits
Low-power digital circuits for Logic, Memory, Reliability, Clocking,
Power gating, Resiliency, Near-threshold and Sub-threshold,
Variability, and Digital assist schemes; Low-power analog/mixed-signal
circuits for Wireless, RF, MEMS, AD/DA Converters, I/O, PLLs/DLLS,
Imaging, DC-DC converters, and Analog assist schemes.

1.3. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, Processor cores
(compute, graphics and other special purpose cores), Cache, Memory,
Arithmetic/Signal processing, Cryptography, Variability, Asynchronous
design, and Nonconventional computing.

2. CAD, Systems, and Software

2.1. CAD Tools and Methodologies
CAD tools and methodologies for low-power and thermal-aware design
addressing power estimation, optimization, reliability and variation impact
on power, and power-down approaches at all levels of design abstraction:
physical, circuit, gate, register transfer, behavioral, and algorithm.

2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design and platforms
for microprocessors, DSPs, embedded systems, FPGAs, ASICs, SoCs,
heterogeneous computing, data-center power delivery and cooling, and
system-level power implications due to reliability and variability.

2.3. Software and Applications
Energy-efficient, energy-aware, and thermal-aware system software and
application design including scheduling and management, power
optimizations through HW/SW interactions, and emerging low power
applications such as approximate and brain-inspired computing, the
Internet-of-Things (IoT), wearable computing, body-area/in-body networks,
and wireless sensor networks.

3. Industrial Design Track (New Initiative for 2015)

3.1. Industry Perspectives
For the first time, ISLPED’15 solicits papers for an “Industrial Design” track
to reinforce interaction between the academic research community and
industry. Industrial Design track papers have the same submission deadline
as regular papers and should focus on similar topics, but are expected to
provide a complementary perspective to academic research by focusing on
challenges, solutions, and lessons learnt while implementing industrial-
scale designs. In addition to purely hardware-focused papers, papers
describing power optimizations through an interaction of hardware and
software are also welcome.

Submissions should be full-length papers of up to 6 pages (PDF format, double-
column, US letter size, using the IEEE Conference format, available at,
including all illustrations, tables, references, and an abstract of no more
than 250 words. Submissions must be anonymous. Submissions exceeding 6
pages or identifying the authors, either directly or through explicit references to
their prior work, will be automatically rejected. More information on paper
submission can be found at

Submitted papers must describe original work that has not been
published/accepted or currently under review by another journal, conference,
symposium, or workshop at the same time. Accepted papers will be submitted to
the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’15 will
present two Best Paper Awards based on the ratings of reviewers and a panel of

There will be several invited talks by industry and academic thought
leaders on key issues in low power electronics and design. The Symposium
may also include embedded tutorials to provide attendees with the necessary
background to follow recent research results, as well as panel discussions
on future directions in low power electronics and design. Proposals for
invited talks, embedded tutorials, and panels should be sent by email to
the ISLPED’15 Technical Program Co-Chairs, Vijay Raghunathan (
and Ruchir Puri ( by the deadline listed above.

General Co-Chairs:
Luca Benini, Univ. of Bologna
Renu Mehra, Synopsys
Mauro Olivieri, Sapienza Univ.

Program Co-Chairs:
Ruchir Puri, IBM,
Vijay Raghunathan, Purdue Univ.

Local Arrangement Chair:
Alessandro Trifiletti, Sapienza Univ.

Industry Liaison:
David Garrett, Broadcom

Publicity Co-Chairs:
Andreas Burg, EPFL
Deming Chen, UIUC
Baris Taskin, Drexel University

Publication Chair:
Paul Wesling, IEEE

Industrial Design Track Co-Chairs:
Edith Beigne, CEA-Leti
Juergen Karmann, Infineon

Design Contest Co-Chairs:
Alberto Macii, Politecnico di Torino
Hiroki Matsutani, Keio University

Yu Wang, Tsinghua University

Web Chair:
Theo Theocharides, Univ. of Cyprus

Local Staff:
Francesco Menichelli, Sapienza Univ.
Antonio Mastrandrea, Sapienza Univ.
Zia Abbas Zaidi, Sapienza Univ.
Usman Khalid, Sapienza Univ.
Monica Coppola, FREEnergy

Call for Participation: ASPLOS 2015

Submitted by Ozcan Ozturk
March 14 to March 18, 2015

Submitted by Ozcan Ozturk

20th International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS 2015)

Istanbul, Turkey
March 14-18, 2015


ASPLOS’15 registration portal is live NOW. You can take advantage of early
bird registration until Feb. 16!

ASPLOS is the premier forum for multidisciplinary systems research
spanning computer architecture and hardware, programming languages and
compilers, operating systems and networking, as well as applications and
user interfaces.

Call for Papers: SBAC-PAD 2015

Submitted by Claudio Amorim
October 18 to October 21, 2015

Submitted by Claudio Amorim

The 27th International Symposium on Computer Architecture and High
Performance Computing (SBAC-PAD 2015)

Florianópolis, SC, Brazil,
October 18-21, 2015

Authors are invited to submit manuscripts on all aspects of computer
architecture and high performance computing. Topics of interest include
(but are not limited to):
– Application-specific systems
– Benchmarking, performance measurements, and analysis
– Cloud, Grid, cluster, and peer-to-peer systems
– Embedded and pervasive systems
– GPUs, FPGAs and other accelerator architectures
– Languages, compilers, and tools for parallel and distributed programming
– Modeling and simulation methodology
– Operating systems and virtualization
– Parallel and distributed systems, algorithms, and applications
– Power and energy-efficient systems
– Processor, cache, memory, storage, and network architecture
– Real-world applications and case studies
– Reconfigurable, resilient and fault-tolerant systems

Submissions must be in English, 8 pages maximum, following the IEEE
conference formatting guidelines. To be published in the SBAC-PAD 2015
Conference Proceedings and to be eligible for publication at the IEEE
Xplore (pending), one of the authors must register at the full rate.
Authors may not use a single registration for multiple papers. Authors of
selected papers will be invited to submit extended versions of their
papers for publication on the Journal of Parallel and Distributed

SBAC-PAD 2015 will be held in Florianópolis, SC, Brazil. Known as “the
Island of Magic”, Florianópolis is the favorite destination for tourism in
the Southern part of Brazil. Florianópolis is known by its 42 beautiful
beaches, special resorts, historical buildings, environmental protected
areas, and by an economy strongly based on information technology.

Workshop proposals: May, 2015
Tutorial proposals: May, 2015
Paper submission deadline: June, 2015
Author notification: July, 2015
Camera ready: August, 2015

General Chair
Mario A. R. Dantas (UFSC, Brazil)

Program Chairs
Edson Borin (Unicamp, Brazil)
Viktor K. Prasanna (USC, USA)

Call for Papers: FastPath 2015

Submitted by Parijat Dube
March 29, 2015

Submitted by Parijat Dube

FastPath 2015: Fourth International Workshop on Performance Analysis of
Workload Optimized Systems

Co-located with ISPASS 2015
Philadelphia, PA USA
March 29, 2015

The goal of FastPath is to bring together researchers and practitioners
involved in cross-stack hardware/software performance analysis, modeling,
and evaluation of workload optimized systems. With microprocessor clock
speeds being held constant, optimizing systems around specific workloads
is an increasingly attractive means to improve performance.
More precisely, workload optimized systems have hardware
and/or software specifically designed to run well for a
particular application or application class. The types and
components of workload optimized systems vary, but a partial list
includes traditional CPUs assisted with accelerators
(ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators,
hybrid systems, converged infrastructure, and IT appliances.

The importance of workload optimized systems is seen
in their ubiquitous deployment in diverse systems from
cellphones to tablets to routers to game machines to
Top500 supercomputers. Prominent commercial examples of
workload optimized systems include IBM DataPower, IBM Purescale
Application System, IBM Watson, Oracle Exadata, and HP Moonshot Servers.
Exploiting CPU savings and speed-ups offered by workload optimized
systems for application level performance improvement poses several
cross stack hardware and software challenges. These include
developing alternate programming models to exploit massive
parallelism offered by accelerators, designing low-latency,
high-throughput H/W-S/W interfaces,developing techniques to
efficiently map processing logic on hardware, and
cross system stack performance optimization and tuning.
Emerging infrastructure supporting big data analytics,
cognitive computing, large-scale machine learning, mobile computing,
and internet-of-things, further exemplify workload optimized design
at large.

FastPath seeks to facilitate the exchange of ideas on performance analysis
and evaluation of workload optimized systems and seeks papers on a wide
range of topics including, but not limited to:
– Workload characterization and profiling
– Industrial experiences
– GPUs, FPGAs, ASIC accelerators
– Memory, I/O, Storage, Network accelerators
– Hardware/Software co-design
– Workload optimized servers
– Hybrid/Heterogeneous systems
– Measurements and Experimentation
– Analytical techniques
– Performance modeling and prediction
– Performance tooling and optimization
– Programming models for workload optimized systems
– Runtime management systems
– Workload scheduling and orchestration
– Workload optimized clusters in Cloud
– Big Data analytics systems
– Large-scale machine learning systems
– Intelligent/Cognitive systems
– Mobile computing systems
– Converged/integrated infrastructure
– Workload optimized systems from specific domains,
e.g., financial, biological, education, commerce, healthcare.

The authors should submit PDF of a 2-4 page extended abstract by the
submission deadline at
The submission should follow standard format (2-column,
10 to 12-point type, single spaced, 1-inch margins).
Abstracts should provide sufficient detail about the work
and its technical contributions.

Authors of selected abstracts will be invited to present their work
at the workshop. Accepted abstracts will be made available through
the workshop website and hard copies will be provided at the
workshop to the attendees. There are no copyright issues with FastPath,
and thus authors retain the copyright of their work with complete
freedom to submit their work elsewhere.

Submission: March 1, 2015
Author Notification: March 10, 2015
Workshop: March 29, 2015

General Chair:
Erik Altman (IBM)

Program Chairs:
Vijay Janapa Reddi (U-Texas, Austin)
Parijat Dube (IBM)

Web Chair: Augusto Vega (IBM)

David Brooks, Harvard University
Trey Cain, Qualcomm Research
Mike Ferdman, Stony Brook University
Sudhanva Gurumurthi, AMD, University of Virginia
Eric Van Hensbergen, ARM Research
Arrvindh Shriraman, Simon Fraser University
Devesh Tiwari, Oak Ridge National Lab
Sudhakar Yalamanchili, Georgia Tech
Chuanjun Zhang, Intel