Call for Papers: Workshop on Architectural Research Prototyping

Submitted by Christopher Batten
June 14, 2015 at 12:00

Submitted by Christopher Batten

WARP: 6th Workshop on Architectural Research Prototyping
Co-located with ISCA’15
Portland, Oregon, USA
Sunday, June 14th, 2015

Building prototype systems can be one of the best ways to validate
assumptions, gain intuition about practical design issues, and
provide platforms for future software research. While the research
ideas behind these prototypes can be published in top-tier
conferences, there are not many venues suitable for focusing on the
actual prototype itself. At the same time, building an FPGA, ASIC, or
full-custom computer architecture prototype is a non-trivial endeavor
and requires a significant financial and time commitment. This
workshop is intended as a forum for the builders in our community to
share their practical on-the-ground experiences, to provide a status
update on their progress, and to convey insights for those
considering prototyping their ideas.

This half-day workshop will be held on Sunday, June 14th, 2015,
co-located with ISCA-42 in Portland, OR. The workshop will primarily
include presentations selected by the technical program committee
based on extended abstract submissions.

We invite submissions on all aspects of building prototype systems
for computer architecture research. Submissions can be based on new
or pending prototypes that have not been discussed in any other
venue, or submissions can focus on the practical prototyping
implications of a previously published research paper. Submissions
more in the spirit of a short position paper are also encouraged.

Topics of particular interest include, but are not limited to:

– Status updates on FPGA, ASIC, or full-custom prototypes
that have been recently constructed or are under construction

– Implementation technology trade-offs (FPGAs, ASICs, full-custom)

– Practical guidance on what works and what doesn’t,
including strategies for:
    o High-level specification
    o Register-transfer-level implementation
    o Pre- and post-construction verification
    o Packaging and board design
    o Managing complex electronic design automation toolflows

– Practical advice on managing the increasing design complexity
inherent in building computer architecture research prototypes
that integrate general-purpose processors and memory systems with
specialized accelerators

– How to balance the often conflicting goals of prototypes as
research vehicles containing novel architectural mechanisms vs.
prototypes as high-performance software development platforms

– How to balance student’s thesis goals vs. engineering work
– How to secure funding for building prototypes

Participation is encouraged for all members of the computer
architecture community, including those considering embarking on a
prototyping effort or those who strongly disagree with the need to
build prototypes.

Participants are invited to submit an extended abstract of up to two
pages (single or double column, 10pt, single spaced). Please include
the authors’ names, affiliations, and clearly reference any previous
publications that were based on the prototype. Submissions must be in
PDF format and submitted according to the instructions posted on the
WARP website.

Participants may also include an appendix of any length. However, we
will not promise to read the appendix, so the extended abstract
should stand alone as a coherent description of what you will discuss
in your talk. The appendix can provide additional details such as
device micrographs or more detailed results.

Extended abstracts and presentation slides will only be posted on the
workshop website with permission of the authors. Authors should feel
free to submit work in progress or work under review (where
permitted) without fear of double publication issues.

– Submission Deadline: April 10, 2015
– Notification of Selection: April 20, 2015
– Final Abstract Submission: May 22, 2015

Workshop chairs:
– Christopher Batten, Cornell University
– Dave Wentzlaff, Princeton University

Program Committee:
– David Brooks, Harvard University
– Steve Keckler, NVIDIA/University of Texas at Austin
– Mark Oskin, University of Washington
– Jose Renau, University of California, Santa Cruz

Call for Papers: Multi-Core SoC

Submitted by Don Draper
September 23 to September 25, 2015

Submitted by Don Draper

IEEE 9th International Symposium on Embedded Multicore/Many-core
Systems-on-Chip (MCSoC-15)

Turin, Italy
September 23-25, 2015

Full Paper Submission: April 30, 2015
Acceptance Notification: May 29, 2015
Camera ready paper: June 30, 2015

The IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-
on-Chip aims at providing the world’s premier forum of leading researchers in the
embedded Multicore/Many-core SoCs software, tools and applications design areas
for Academia and industries. Prospective authors are invited to submit paper of their
works. Submission of a paper implies that at least one of the authors will have a full
registration to the symposium upon acceptance of the paper. The Symposium will
be held in TURIN, Italy — the city of the 2006 Olympic Games!

MCSoC-15 proceedings will be published by IEEE CS Press, which will be included in
the Computer Society Digital Library CSDL and IEEE Xplore.

For more information, visit

For any questions: email:

Call for Papers: IISWC 2015

Submitted by Jaewoong Sim
October 1, 2015

Submitted by Jaewoong Sim

2015 IEEE International Symposium on Workload Characterization (IISWC)
Atlanta, GA, USA
October (Dates: TBD), 2015

– Abstracts Submission: April 10, 2015
– Paper Submission: April 17, 2015
– Acceptance Notification: June 20, 2015

This symposium is dedicated to the understanding and characterization of
workloads that run on all types of computing systems. New applications and
programming paradigms continue to emerge rapidly as the diversity and
performance of computers increase. On one hand, improvements in computing
technology are usually based on a solid understanding and analysis of existing
workloads. On the other hand, computing workloads evolve and change with
advances in microarchitecture, compilers, programming languages, and networking
communication technologies. Whether they are smart phones and deeply embedded
systems at the low end or massively parallel systems at the high end, the
design of future computing machines can be significantly improved if we
understand the characteristics of the workloads that are expected to run on
them. This symposium will focus on characterizing and understanding emerging
applications in consumer, commercial and scientific computing.

We solicit papers in all areas related to characterization of computing system
workloads. Topics of interest include (but are not limited to):

– Characterization of applications in areas including
    o Search engines, e-commerce, web services, databases, application servers
    o Embedded, mobile, multimedia, real-time, 3D-Graphics, gaming, telepresence
    o Life sciences, bioinformatics, scientific computing, finance, forecasting
    o Machine Learning, Analytics, Data mining
    o Security, reliability, biometrics
    o Grid and Cloud computing
    o Emerging big data applications

– Characterization of OS, Virtual Machine, middleware and library behavior
    o Virtual machines, Websphere, .NET, Java VM, databases
    o Graphics libraries, scientific libraries

– Characterization of system behavior, including
    o Operating system and hypervisor effects and overheads
    o Hardware accelerators (GPGPU, XML, crypto, etc)
    o User behavior and system-user interaction
    o Impacts of scale-up and scale-out of systems, applications, and inputs
    o Instrumentation methodologies for workload verification and characterization
    o Techniques for accurate analysis/measurement of production systems

– Implications of workloads in design including issues, such as
    o Power management, reliability, security, performance
    o Processors, memory hierarchy, I/O, and networks
    o Design of accelerators, FPGA’s, GPU’s, etc.
    o Novel architectures (non-Von-Neumann)

– Benchmark creation, analysis, and evaluation issues, including
    o Multithreaded benchmarks, benchmark cloning
    o Profiling, trace collection, synthetic traces
    o Validation of benchmarks

– Analytical and abstract modeling of program behavior and systems

– Emerging and future workloads
    o Transactional memory workloads; workloads for multi/many-core system
    o Stream-based computing workloads; web2.0/internet workloads;
cyber-physical workloads

– Workloads and characterizations for emerging architectures
    o Near data processing architectures
    o Heterogeneous memory hierarchies
    o New memory hierarchies using die stacked DRAM
    o Memory centric architectures with computing in storage, e.g., SSD and disk

General Chair:
– Tom Conte, Georgia Institute of Technology

Program Co-Chairs:
– Hyesoon Kim, Georgia Institute of Technology
– Sudhakar Yalamanchili, Georgia Institute of Technology

Call for Papers: ParaFPGA 2015

Submitted by Erik D’Hollander
September 1 to September 4, 2015

Submitted by Erik D’Hollander

Parallel Computing with FPGAs (ParaFPGA 2015)
A Mini-Symposium held in conjunction with ParCo 2015
Edinburgh, UK

Conference date: 1-4 September 2015
Submission deadline : 1 June 2015

ParaFPGA2015 is a Mini-Symposium organized in conjunction with the
Biennial Parallel Computing conference ParCo2015, to be held in
Edinburgh, Scotland, UK on 1-4 September 2015.


ParaFPGA focuses on parallel techniques for using FPGAs as
accelerator in high performance computing areas such as
supercomputing, embedded systems and big data computing.

Field Programmable Gate Arrays emerge as powerful building blocks for
High Performance Systems. The freedom to build tailored
architectures with extremely low power is one of the key milestones
on the path to exascale computing. Recently the major industrial
players invested heavily in high-level synthesis tools and
established well known programming paradigms to facilitate the march
towards programmable hardware. In addition, the famous memory wall
has been alleviated by incorporating processing cores inside the FPGA

Of special interest are design methods, heterogeneous architectures
and algorithms optimized for execution on FPGAs. Design methods
include optimizing the resource utilization, development time and
high-level synthesis tools. Heterogeneous architectures encompass
multi-FPGAs, FPGAs with CPU cores and systems combining FPGAs, GPUs
and CPUs. Algorithms ready-made for FPGAs range from streaming
applications to fast dynamic reconfiguration and feature a
substantial performance increase.

Researchers and practitioners are invited to submit novel
contributions in the areas of high-level synthesis, dynamic
reconfiguration and high performance applications. Papers are
invited on a wide variety of topics related but not limited to:

– optimizing throughput of streaming applications
– non-uniform memory partitioning and data reuse
– heterogeneous on-chip processor and programmable logic codesign
– scalability of multi-core with multi-FPGA architectures
– OpenCL for FPGA applications
– evaluating performance metrics for high-level synthesis
– high-level synthesis techniques and case studies
– high-level partial and dynamic reconfiguration
– performance-driven resource and area optimization

Authors are invited to submit a full paper of maximum 10 pages or an
extended abstract of minimal 4 pages. The approved contributions
will be presented at the conference and the accepted full papers are
published in the ParCo 2015 proceedings. Details regarding the
format, presentation and paper submission are given on the author
guidelines page.

Submission deadline : 1 June 2015
Notification of acceptance : 15 July 2015
Final papers due : 15 August 2015

Steering committee:
– Gerhard Joubert, Conference Committee Chair
– Frans Peters, Finance Chair

Mini-Symposium committee:
– Dirk Stroobandt, Ghent University, Symposium chair
– Erik D’Hollander, Ghent University, Program committee chair
– Abdellah Touhafi, Brussels University, Program committee co-chair

Program committee:
– Abbes Amira, University of the West of Scotland, UK
– Georgi Gaydadjiev, Chalmers University of Technology
– Mike Hutton, Altera, USA
– Tsutomu Maruyama, University of Tsukuba, Japan
– Dionisios Pnevmatikos, Technical University of Crete, Greece
– Viktor Prasanna, University of Southern California, USA
– Mazen A. R. Saghir, Texas A&M University, Qatar
– Donatella Sciuto, Politecnico di Milano, Italy
– Sascha Uhrig, Technical University of Dortmund, Germany
– Sotirios G. Ziavras, New Jersey Institute of Technology, USA


Call for Participation: Tutorial on IO virtualization

Submitted by Arkaprava Basu

Submitted by Arkaprava Basu

Virtualizing IO through Memory Management Unit (IOMMU):
Use Cases and Internals of IOMMU

Co-located with ISCA’15
Portland, OR, USA

When: Sunday, 14th June 2015 (Afternoon)

Tutorial Overview: Please see tutorial website.

Call for Papers: Workshop on Heterogeneous and Unconventional Cluster Architectures and Applications

Submitted by Holger Froening

Submitted by Holger Froening

4th International Workshop on Heterogeneous and Unconventional
Cluster Architectures and Applications (HUCAA 2015)

In conjunction with IEEE International Conference on Cluster Computing
Chicago, IL, USA
Sept. 8-11, 2015

The workshop on Heterogeneous and Unconventional Cluster Architectures
and Applications gears to gather recent work on heterogeneous and
unconventional cluster architectures and applications, which might
have an impact on future mainstream cluster architectures. This
includes any cluster architecture that is not based on the usual
commodity components and therefore makes use of some special hard- or
software elements, or that is used for special and unconventional
applications. In particular we call for GPUs and other accelerators
(Intel MIC/Xeon Phi, FPGA) used at cluster level. Even though
accelerators are already used pervasively, we still see many
unconventional and even disruptive uses of them.

This year, we especially call for methods, techniques and best
practices to improve the energy efficiency of cluster computing. This
includes for instance specialized hardware and power-/energy-aware
software layers. Power consumption is a hard constraint, and
predictions show that this trend will not revert in the future. For
the nascent field of power- and energy-aware computing, we see a
large need in sharing experiences, best practices and new ideas.

Note that papers submitted to this topic will be preferred given equal
scores with other contributions. However, HUCAA also welcomes
contributions on other topics (examples see below). Also, proposals
may rather be reflective of a broader industry trend; in general
contributions are not only accepted based on their technical merits
but also according to their contribution to the discussion on how
cluster computing might evolve in the future.

This year, HUCAA in particular calls for:

– New methods and techniques for improved energy efficiency

Papers submitted to this topic will be preferred given equal scores
with other contributions. However, HUCAA still welcomes contributions
to other topics, including:

– Clustered GPUs, Xeon Phis or other accelerators
– Runtimes for heterogeneous cluster architectures
– New industry and technology trends and their potential impact
– High-performance, data-intensive, and power-aware computing
– Communication methods for distributed or clustered accelerators
– Application-specific cluster and datacenter architectures
– Emerging programming paradigms for parallel heterogeneous computing
– Software cluster-level virtualization for consolidation purposes
– Hardware techniques for resource aggregation
– New uses of GPUs, FPGAs, and other specialized hardware

Paper submission: June 10, 2015
Notification of acceptance: July 15, 2015
Camera-ready paper: August 1, 2015
Workshop: in between September 8-11, 2015 (final day TBD)

Published papers will appear in the conference proceedings.
Submissions may not exceed 8 pages in PDF format including figures and
references, and must be formatted in the 2-column IEEE format.
Submitted papers must be original work that has not appeared in and is
not under consideration for another conference or journal. Work in
progress is welcome, but first results should be made available as a
proof of concept. Submissions only consisting of a proposal will be
rejected. Please visit the workshop website for additional details.

Templates are available on the main conference website:

– Holger Fröning, U. Heidelberg
– Federico Silla, U. Politécnica Valencia

Steering Committee:
– José Duato, U. Politécnica Valencia
– Sudhakar Yalamanchili, Georgia Tech
– Ulrich Brüning, U. Heidelberg

Technical Program Committee:

HUCAA was previously co-located with ICPP (2012-2014). Due to HUCAA’s
strong focus on cluster architectures we decided to move to IEEE
Cluster for 2015.


or send email to:
– Federico Silla, Technical University of Valencia:
fsilla {at}
– Holger Fröning, Ruprecht-Karls University of Heidelberg:
holger.froening {at}

Call for Posters: ANCS 2015

Submitted by Eric Keller
May 7 to May 8, 2015

Submitted by Eric Keller

The 11th ACM/IEEE Symposium on Architectures for Networking
and Communications Systems (ANCS 2015)

Oakland, CA, USA
May 7-8, 2015

Poster abstract submission deadline: March 23, 2015
Author notification for posters: March 30, 2015
Camera-ready for poster abstract: April 6, 2015

The poster session will provide a forum for researchers to showcase
their exciting early work. Areas of interest are the same as those
listed for regular papers. Posters need not describe complete work,
but they should have at least preliminary results to report so that
feedback on the ongoing work can be obtained from knowledgeable
conference attendees. We especially encourage student poster
submissions where the student is the first author. Posters will be
evaluated based on their technical merit and innovation as well as
their potential to stimulate interesting discussions and exchange of
ideas. Submissions from both industry and universities are
encouraged. Two-page poster abstracts will be published in the
conference proceedings.

Poster submissions must be formatted according to the ACM/SIG
conference paper format using 9pt font and submitted in PDF
format. The style is identical to that used for main conference
submissions ( except that
poster submissions are limited to no more than 2 pages and use 9pt
font instead of 12pt font. Please email poster abstract submissions
as PDF attachments to:
with the subject line: “ANCS 2015 POSTER SUBMISSION.”

ANCS 2015 Poster Chair
Won So:

Call for Papers: SBAC-PAD 2015

Submitted by Claudio Amorim
October 18 to October 21, 2015

Submitted by Claudio Amorim

The 27th International Symposium on Computer Architecture and High
Performance Computing

Florianópolis, SC, Brazil
October 18-21, 2015

Abstract deadline: June 1st
Paper deadline: June 8th
Rebuttal period: July 7th – 9th
Author notification: July 19th
Camera ready: August 14th
Workshop proposals:May
Tutorial proposals: May

Authors are invited to submit manuscripts on all aspects of computer
architecture and high performance computing. Topics of interest include (but
are not limited to):
– Application-specific systems
– Benchmarking, performance measurements, and analysis
– Cloud, Grid, cluster, and peer-to-peer systems
– Embedded and pervasive systems
– GPUs, FPGAs and other accelerator architectures
– Languages, compilers, and tools for parallel and distributed programming
– Modeling and simulation methodology
– Operating systems and virtualization
– Parallel and distributed systems, algorithms, and applications
– Power and energy-efficient systems
– Processor, cache, memory, storage, and network architecture
– Real-world applications and case studies
– Reconfigurable, resilient and fault-tolerant systems

Submissions must be in English, 8 pages maximum, following the IEEE conference
formatting guidelines. To be published in the SBAC-PAD 2015 Conference
Proceedings and to be eligible for publication at the IEEE Xplore (pending),
one of the authors must register at the full rate. Authors may not use a single
registration for multiple papers. Authors of selected papers will be invited to
submit extended versions of their papers for publication on the Journal of
Parallel and Distributed Computing.

SBAC-PAD 2015 will be held in Florianópolis, SC, Brazil. Known as the Island of
Magic, Florianópolis is the favorite destination for tourism in the Southern
part of Brazil. Florianópolis is known by its 42 beautiful beaches, special
resorts, historical buildings, environmental protected areas, and by an economy
strongly based on information technology.

General Chair:
– Mario A. R. Dantas (UFSC, Brazil)

Program Chairs:
– Edson Borin (Unicamp, Brazil)
– Viktor K. Prasanna (USC, USA)

Call for Papers: SC'15

Submitted by Ewa Deelman
November 15 to November 20, 2015

Submitted by Ewa Deelman

Austin, TX, USA
Nov. 15 – 20, 2015

Focus areas this year include:
– Algorithms
– Applications
– Architecture and Networks
– Clouds and Distributed Computing
– Data Analytics, Visualization and Storage
– Performance
– Programming Systems
– State-of-the-Practice
– System Software.

Abstracts due (required): April 3, 2015 (firm deadline)
Full Papers due: April 10, 2015
(a traditional one week extension will be given until April 17,
no further extensions will be granted).

Web Submissions:
More information about the Technical papers:

– Ewa Deelman, University of Southern California Information Sciences Institute
– José Moreira, IBM Corporation

Call for Participation: Workshop on Approximate Computing Across the Stack

Submitted by Luis Ceze
June 13, 2015

Submitted by Luis Ceze

Workshop on Approximate Computing Across the Stack
In conjunction with FCRC
Portland, OR, USA
June 13, 2015

WAX 2015 is a workshop on approximate computing, a research direction that
asks how computer systems can be made better, faster, more efficient, and
less complex by relaxing the requirement that they be exactly correct.
Approximation arises from sources as diverse as sensors, machine learning
algorithms, and big data applications. Approximate systems raise questions
from across the system stack, from circuits to applications. WAX is a
venue for discussion, debate, and brainstorming on all of these topics.

We invite participation in three forms: position papers, lightning talks,
and discussion topics.

For additional details visit the WAX 2015 web site:

– Two page position papers due: (approximately) March 20, 2015
– Position paper notification: (approximately) May 1, 2015
– Lightning talk and discussion topics proposals due: (approximately) June 3, 2015
– Workshop: June 13, 2015 at FCRC in Portland

Emery Berger, University of Massachusetts
Luis Ceze, University of Washington
Kathryn S McKinley, Microsoft Research
Adrian Sampson, University of Washington
Ben Zorn, Microsoft Research