Call for Papers: Mini-Symposium on Energy and Resilience in Parallel Programming

Submitted by Christos D. Antonopoulos
September 3 to September 4, 2015

Submitted by Christos D. Antonopoulos

Mini-Symposium on Energy and Resilience in Parallel Programming (ERPP 2015)
in Conjunction with ParCo 2015
Edinburgh, Scotland, UK
September 3-4 2015

ERPP provides a forum to broadly explore the implications of energy and resilience
on the principles and practice of parallel programming. ERPP aims to present original
research that uses energy and resilience as first-class resources in parallel
programming languages, libraries and models and demonstrates how parallel
programming can improve energy-efficiency and resilience of large-scale
computing systems or many-core embedded systems. The minisymposium also
intends to explore how energy and resilience management in hardware or system
software may affect the performance of existing parallel programming environments.

The topics explored by ERPP include but are not limited to:
– Parallel programming abstractions for energy and resilience
– Compiler and runtime support for energy- and resilience-aware execution
– Parallel libraries and auto-tuning for energy and resilience
– Performance of parallel programming languages, libraries and tools in energy-
constrained environments
– Measurement and characterization of resilience in parallel programming
models, languages and libraries
– Measurement and characterization of energy in parallel programming models,
languages and libraries
– New computing paradigms for improving energy and resilience in parallel
programming, such as approximate computing or near-threshold computing

We call for high-quality, original contributions (in English language) related
to the minisymposium topics. Extended abstracts of at least 4 pages should be
submitted by June 23 2015 and will be published in a book of abstracts. Final,
camera-ready versions of accepted full length papers (up to 10 pages) must be
prepared in October 2015 (after the minisymposium).

June 23, 2015: Submission deadline for extended abstracts
July 17, 2015: Notification of decision
July 31, 2015: Camera-ready of extended abstracts due
October, 2015: Full paper submission

Dimitrios S. Nikolopoulos, Queen’s University of Belfast
Christos D. Antonopoulos, University of Thessaly, Greece

Kevin Barker, PNNL
Costas Bekas, IBM Research – Zurich
Nikolaos Bellas, Universuty of Thessaly
Kirk Cameron, Virginia Tech
Rong Ge, Marquette University
Dimitris Gizopoulos, University of Athens
Nikos Hardavellas, Northwestern University
Georgios Karakonstantis, Queen’s University of Belfast
Spyros Lalis, University of Thessaly
Dong Li, University of California, Merced
David Lowenthal, University of Arizona
Naoya Maruyama, RIKEN AICS
Kathryn Mohror, LLNL
Enrique S. Quintana-Orti, Universidad Jaume I
Pedro Trancoso, University of Cyprus
Zheng Wang, Lancaster University

Call for Participation: Workshop on Computer Architecture Research Directions

Submitted by Joshua J. Yi
June 14, 2015 at 13:30

Submitted by Joshua J. Yi

Fourth Workshop on Computer Architecture Research Directions (CARD 2015)
in conjunction with ISCA 2015
Portland, OR, USA
Sunday, June 14, 2015

CARD 2015 presents three mini-panels consisting of three experts in the field,
two as panelists and the third as a moderator/panelist. The purpose of this
workshop is to serve as a forum in which experts in each field can debate the
state of the field and future directions. The format is designed to quickly
focus on areas of disagreement, rather than expounding on areas of agreement
which, presumably, have ceased to be controversial, at least between the two
panelists. The mini-panels are intended to help clarify the open issues of
each topic and to discuss those open issues. The hope is that the workshop will
be useful to a diverse audience from a graduate student looking for good thesis
topic areas to a senior researcher who wants to hear the opinions of other area

Each 60 minute panel will consist of an opening statement from each panelist
(10 minutes each, 20 minutes total), discussion between the moderator and
panelists (5 to 10 minutes), and questions from the audience (30 to 35 minutes).

CARD 2015 consists of following three mini-panels:

Mini-panel #1: Open-source versus Proprietary ISAs
Moderator: Mark Hill (University of Wisconsin)
Panelist: Dave Patterson (University of California – Berkeley)
Panelist: Dave Christie (AMD)

Mini-panel #2: FPGAs versus GPUs for Datacenters
Moderator: Babak Falsafi (EPFL)
Panelist: Desh Singh (Altera)
Panelist: Bill Dally (Stanford / NVIDIA)

Mini-panel #3: Impact of Future Technologies
Moderator: Trevor Mudge (University of Michigan)
Panelist: Fred Chong (University of Chicago)
Panelist: Igor Markov (University of Michigan)

Descriptions of each panel and the panelists position statement should be
posted on the CARD website shortly.

Derek Chiou, Microsoft/University of Texas at Austin
Resit Sendag, University of Rhode Island
Joshua J. Yi, Dechert LLP

Call for Papers: SBAC-PAD 2015

Submitted by Claudio Amorim
October 18 to October 21, 2015

Submitted by Claudio Amorim

The 27th International Symposium on Computer Architecture and
High Performance Computing (SBAC-PAD)

Florianópolis, SC, Brazil
October 18-21, 2015

Authors are invited to submit manuscripts on all aspects of computer
architecture and high performance computing. Topics of interest include (but
are not limited to):
– Application-specific systems
– Benchmarking, performance measurements, and analysis
– Cloud, Grid, cluster, and peer-to-peer systems
– Embedded and pervasive systems
– GPUs, FPGAs and other accelerator architectures
– Languages, compilers, and tools for parallel and distributed programming
– Modeling and simulation methodology
– Operating systems and virtualization
– Parallel and distributed systems, algorithms, and applications
– Power and energy-efficient systems
– Processor, cache, memory, storage, and network architecture
– Real-world applications and case studies
– Reconfigurable, resilient and fault-tolerant systems

Submissions must be in English, 8 pages maximum, following the IEEE conference
formatting guidelines. To be published in the SBAC-PAD 2015 Conference
Proceedings and to be eligible for publication at the IEEE Xplore (pending),
one of the authors must register at the full rate. Authors may not use a single
registration for multiple papers. Authors of selected papers will be invited to
submit extended versions of their papers for publication on the Journal of
Parallel and Distributed Computing.

Submission link:

Abstract deadline: June 7th (Anywhere on earth)
Paper deadline: June 15th (Anywhere on earth)
Rebuttal: July 9th
Author notification: July 19th
Camera ready: August 14th

Confirmed Keynote Speakers:
Geoffrey Charles Fox (Indiana University, USA)
Satoshi Matsuoka (Tokyo Institute of Technology, Japan)
Onur Mutlu (Carnegie Mellon University, USA)

General Chair:
Mario A. R. Dantas (UFSC, Brazil)

Program Chairs:
Edson Borin (Unicamp, Brazil)
Viktor K. Prasanna (USC, USA)

Track Chairs:
Anne Benoit (ENS Lyon, France) — Applications and Algorithms
David R. Kaeli (Northeastern University, USA) — Architecture
Albert Cohen (Inria, France) — Software
Dilma Da Silva (Texas A&M University, USA) — Distributed Systems and Networks

Publicity Chairs:
Christophe Cérin (Paris 13 University, France) – Europe and Africa
Claudio Amorim (Federal University of Rio de Janeiro, Brazil) – Latin America
Kuan-Ching Li (Providence University, Taiwan) – Asia and Oceania
Miriam Capretz (The University of Western Ontario, Canada) – North America

Publications Chair:
Hermes Senger (Federal University of São Carlos, Brazil)

Workshop Chair:
Alba Melo (University of Brasilia, Brazil)

Financial Chair:
Márcio Castro (Federal University of Santa Catarina, Brazil)

Alfredo Goldman (University of São Paulo, Brazil)
Laércio Lima Pilla (Federal University of Santa Catarina, Brazil)
Philippe Navaux (Federal University of Rio Grande do Sul, Brazil)

Call for Participation: ISLPED 2015 (early registration deadline: June 5)

Submitted by Andreas Burg
July 22 to July 24, 2015

Submitted by Andreas Burg

International Symposium on Low Power Electronics and Design (ISLPED’15)
Rome, Italy
July 22-24, 2015

ISLPED is the world’s premier event on low power design.
It is sponsored by the IEEE Circuits and Systems Society and the
ACM Special Interest Group on Design Automation.

The technical program comprises paper presentations in the areas of:
1.1 Technologies
1.2 Circuits
1.3 Logic & Architecture
2.1 CAD & Methodologies,
2.2 Systems & Platforms,
2.3 Software & Applications,
3.1 Industrial Perspectives

Besides the paper presentations, the program also features three high-profile
keynotes (A. Sangiovanni-Vincentelli — UC Berkeley, USA;
J. Pineda De Givez — NXP, Netherlands; N. Shanbhag — UIUC, USA),
An Industry Reception Dinner (July 22nd),
A Banquet Gala Dinner (July 23rd),
A free Co-Located Workshop and Tutorial (July 24th) on Ultra-Low Power
Environmental Monitoring, Security, and Health (ULPESH)

Early registration is available until June 5, 2015.

For more information and registration, visit:

Call for Papers: Workshop on Heterogeneous and Unconventional Cluster Architectures and Applications

Submitted by Holger Fröning
June 10, 2015

Submitted by Holger Fröning

4th International Workshop on Heterogeneous and Unconventional
Cluster Architectures and Applications (HUCAA 2015)

In conjunction with IEEE CLUSTER 2015
Chicago, IL, USA
Sept. 8-11, 2015


The workshop on Heterogeneous and Unconventional Cluster Architectures
and Applications gears to gather recent work on heterogeneous and
unconventional cluster architectures and applications, which might
have an impact on future mainstream cluster architectures. This
includes any cluster architecture that is not based on the usual
commodity components and therefore makes use of some special hard- or
software elements, or that is used for special and unconventional
applications. In particular we call for GPUs and other accelerators
(Intel MIC/Xeon Phi, FPGA) used at cluster level. Even though
accelerators are already used pervasively, we still see many
unconventional and even disruptive uses of them.

This year, we especially call for methods, techniques and best
practices to improve the energy efficiency of cluster computing. This
includes for instance specialized hardware and power-/energy-aware
software layers. Power consumption is a hard constraint, and
predictions show that this trend will not revert in the future. For
the nascent field of power- and energy-aware computing, we see a
large need in sharing experiences, best practices and new ideas.

This year, HUCAA particularly calls for:
– New methods and techniques for improved energy efficiency

Papers submitted to this topic will be preferred given equal scores
with other contributions. However, HUCAA still welcomes contributions
to other topics, including:
– Clustered GPUs, Xeon Phis or other accelerators
– Runtimes for heterogeneous cluster architectures
– New industry and technology trends and their potential impact
– High-performance, data-intensive, and power-aware computing
– Communication methods for distributed or clustered accelerators
– Application-specific cluster and datacenter architectures
– Emerging programming paradigms for parallel heterogeneous computing
– Software cluster-level virtualization for consolidation purposes
– Hardware techniques for resource aggregation
– New uses of GPUs, FPGAs, and other specialized hardware

Paper submission: June 10th, 2015
Notification of acceptance: July 15th, 2015
Camera-ready paper: August 1st, 2015
Workshop: in between September 8-11, 2015 (final day TBD)

Published papers will appear in the conference proceedings.
Submissions may not exceed 8 pages in PDF format including figures and
references, and must be formatted in the 2-column IEEE format.
Submitted papers must be original work that has not appeared in and is
not under consideration for another conference or journal. Work in
progress is welcome, but first results should be made available as a
proof of concept. Submissions only consisting of a proposal will be
rejected. Please visit the workshop website for additional details.


Workshop Co-chairs:
– Holger Fröning, U. Heidelberg
– Federico Silla, U. Politécnica Valencia

Steering Committee:
– José Duato, U. Politécnica Valencia
– Sudhakar Yalamanchili, Georgia Tech
– Ulrich Brüning, U. Heidelberg

Program Co-chairs:
– Antonio Peña, Argonne National Lab, US

Program Committee:
– Tarek Abdelrahman, U. Toronto, Canada
– José Luis Abellán, Catholic University of Murcia, Spain
– Olivier Aumage, INRIA, France
– José María Cecilia, Catholic University of Murcia, Spain
– Javier Cuenca, U. Murcia, Spain
– Basilio Fraguela, U. Coruna, Spain
– Marc Gonzalez, U. Coruna, Spain
– Sascha Hunold, Technical University of Vienna, Austria
– Christos Kartsaklis, Oak Ridge National Lab, US
– Tomàs Margalef, U. Autonoma Barcelona, Spain
– Thu D. Nguyen, U. Rutgers, US
– Dimitrios S. Nikolopoulos, Queen’s University, Belfast, UK
– Won Ro, Yonsei University, South Korea
– Lena Oden, Argonne National Lab, US
– Dirk Pleiter, Research Center Jülich, Germany
– Antonio Robles, Technical University of Valencia, Spain
– Mingxing Tan, Cornell University, US
– Douglas Thain, U. Notre Dame, US
– Blesson Varghese, U. St Andrews, UK
– Prudence Wong, U. of Liverpool, UK
– Shuangyang Yang, Louisiana State University, US

HUCAA was previously co-located with ICPP (2012-2014). Due to HUCAA’s
strong focus on cluster architectures we decided to move to IEEE
Cluster for 2015.

Call for Submissions: Doctoral Showcase Program @ SC'15

Submitted by Sunita Chandrasekaran
November 15 to November 20, 2015

Submitted by Sunita Chandrasekaran

Doctoral Showcase Program @ SC’15
Austin, TX, USA

Applications for Doctoral Showcase close: July 31, 2015
Notification Sent: September 7, 2015

Submissions will be accepted for the Dissertation Research Showcase track for
Ph.D. students who will be graduating in the next 12 months. This track
provides a venue for Ph.D. students to present a summary of their
latest and systematic dissertation research.

Students are asked to submit a four-page summary of their research (include
research problem statement and major results/contributions), a poster draft,
and list of student’s conference/journal publications for consideration by the
Doctoral Showcase committee. The authors of the accepted submissions will be
invited to give presentations at the SC15 conference. See the website for more

Submissions to this program may also be submitted to the SC15 ACM Student
Research Competition posters track or published in other venues.

Call for Participation: ICS 2015 (Early registration deadline: May 17)

Submitted by Arun Kejariwal
June 8 to June 11, 2015

Submitted by Arun Kejariwal

29th International Conference on Supercomputing (ICS 2015)
Newport Beach, California
8-11 June, 2015

Sponsored by ACM/SIGARCH

EARLY REGISTRATION DEADLINE: May 17, 2015 (extended)

ICS is the premier international forum for the presentation of research
results in high-performance computing systems. This year the conference
will be held at Hyatt Regency, Newport Beach, California.

The technical program features keynote addresses by three leading
authorities in high performance computing:

K1 Datacenter efficiency — What’s next?
Ricardo Bianchini
Professor, Rutgers University and Chief Efficiency Strategist
Microsoft Research

K2 Streaming Task Parallelism
Albert Cohen
Senior Research Scientist, INRIA

K3 Automatically Scalable Computation
Margo Seltzer
Herchel Smith Professor of Computer Science
Harvard College Professor

The conference program is available at:

A Best Paper Award will be given according to the selection made
by the audience among all technical papers.

ICS will also co-host several workshops and tutorials details of
which are given at:

Early Registration May 17, 2015

General Chair:
– Laxmi Bhuyan, UC Riverside

Program Co-Chairs:
– Fred Chong, UC Santa Barbara
– Vivek Sarkar, Rice University

Workshops and Tutorials Co-Chairs:
– Murali Annavaram, University of Southern California

Call for Papers: iNIS 2015

Submitted by Saraju Mohanty
December 21 to December 23, 2015

Submitted by Saraju Mohanty

1st IEEE International Symposium on Nanoelectronic and Information Systems
Indore, India
December 21-23, 2015

iNIS 2015 is to provide a platform for both hardware and software
researchers to interact under one umbrella for further development of
efficient and secure information processing technologies. Efficient and
secure data sensing, storage and processing play pivotal roles in the
current information age. State-of-the-art nanoelectronic technology
based hardware systems cater to the needs of efficient sensing, storage,
and computing. At the same time, efficient algorithms and software used
for faster analysis and retrieval of desired information are becoming
increasingly important. Big data which are large, complex data sets, are
now an integral part of the Internet world. Storing and processing needs
of the enormous amount of structured and unstructured data are getting
increasingly challenging. At the same time, Internet of Things (IoT) and
Cyber-Physical Systems (CPS) have been evolving with the simultaneous
development of hardware and software. The performance and efficiency of
the present as well as the future generation of computing and
information processing systems are largely dependent upon advances in
both hardware and software.

iNIS 2015 is sponsored by IEEE-CS and has technical co-sponsorship of
IEEE-CAS. The iNIS brings together leading scientists and researchers
from academia and industry. Contributions are sought in (but are not
limited to) the following areas: 1) Nanoelectronic VLSI and Sensor
Systems (NVS) 2) Energy-Efficient, Reliable VLSI Systems (ERS) 3)
Hardware/Software Solutions for Big Data (SBD) 4) Hardware/Software for
Internet of Things (IOT) 5) Hardware for Secure Information Processing
(SIP) 6) Cyber Physical Systems and Social Networks (CSN) Detailed
description of the tracks is provided in the iNIS website.

iNIS 2015 proceedings will be published by IEEE-CS. Authors are invited to
submit full-length (6 pages maximum), original, unpublished research
papers with an abstract (200 words maximum). For blind review, author
informations should be omitted from the main document. Papers violating
length and blind-review criteria will be excluded from the review process.
Previously published papers or papers currently under review elsewhere
should not be submitted and will not be considered for publication.
Authors should submit their original work of maximum 6 pages using
double-column IEEE-CS conference format-template
A selected papers from iNIS 2015 will be invited for submission
to a peer-reviewed journal special issue based on reviewer feedback and
quality of conference presentation.

Paper Submission Site:

Submission Deadline: July 20, 2015
Acceptance Notification: September 14, 2015
Submission of Final Version: October 12, 2015

Special Sessions and Panels: iNIS 2015 will consider proposals for
special sessions as well as panels. Special session and panel proposals
can be submitted to the special session chairs by email:
and The submission deadline is the
same as specified for the regular paper submissions.

Student Research Symposium: iNIS 2015 will host a student research
symposium. A single 2-page pdf file for student research symposium paper
can be submitted to the student symposium chairs by email: and The submission deadline
is the same as specified for the regular paper submissions. All the
accepted student research symposium papers will be published in the
conference souvenir. A selected top 10 of these will be published in the
iNIS 2015 proceedings.

General Chairs:
Saraju Mohanty, University of North Texas, USA
Dhruva Ghai, Oriental University, India

Program Chairs:
Ashok Srivastava, Louisiana State University, USA
Shiyan Hu, Michigan Technological University, USA
Prasun Ghosal, IIEST, Shibpur, India

Publication Chair:
Himanshu Thapliyal, University of Kentucky, USA

Web Chair:
Mike Borowczak, Erebus Labs & Consulting LLC, USA

Publicity Chairs:
Sudeep Pasricha, Colorado State University, USA
Aida Todri-Sanial, CNRS-LIRMM, France
Shanq-Jang Ruan, National Taiwan University of Science & Technology
Vaskar Raychoudhury, Indian Institute of Technology Roorkee, India

Local Arrangement Chair:
Rishab Pareek, Oriental University, India

Special Session Chairs:
Xin Li, Carnegie Mellon University, USA
Siva Yellampalli, UTL Technologies, India

Student Symposium Chairs:
Anirban Sengupta, Indian Institute of Technology Indore, India
Bishnu P. Das, Indian Institute of Technology Roorkee, India

Finance Chair:
Garima Ghai, Oriental University, India

Registration Chair:
Hare Ram Singh, Oriental University, India

Technical Program Committee:
The complete list is being made available in the website.
Following are the track chairs.

Nanoelectronic VLSI and Sensor Systems (NVS):
Jawar Singh, IIITDM, Jabalpur, India
Yiyu Shi, Missouri University of Science and Technology, USA

Energy-Efficient, Reliable VLSI Systems (ERS):
Manisha Pattanaik, ABV-IIITM, Gwalior, India
Saket Srivastava, University of Lincoln, UK

Hardware/Software Solutions for Big Data (SBD):
Theocharis Theocharides, University of Cyprus
Rajiv Ranjan, Commonwealth Scientific and Industrial Research Organization

Hardware/Software for Internet of Things (IOT):
Vaskar Raychoudhury, Indian Institute of Technology Roorkee, India
Gustavo Marfia, University of Bologna, Italy, Visiting Scholar, UCLA

Hardware for Secure Information Processing (SIP):
Kailash Chandra Ray, Indian Institute of Technology Patna, India
Kamalakanta Mahapatra, National Institute of Technology, Rourkela, India

Cyber Physical Systems and Social Networks (CSN):
Qi Zhu, University of California, Riverside, USA
Madhavi Ganapathiraju, University of Pittsburgh, USA

Steering Committee:
(1) Saraju Mohanty, University of North Texas, USA (Chair)
(2) Prasun Ghosal, IIEST, Shibpur, India (Vice Chair)
(3) Dhruva Ghai, Oriental University, India (Vice Chair)
(4) Aida Todri-Sanial, CNRS-LIRMM, France
(5) Ashok Srivastava, Louisiana State University, USA
(6) Helen Li, University of Pittsburg, USA
(7) Himanshu Thapliyal, University of Kentucky, USA
(8) Jia Di, University of Arkansas, USA
(9) Nabanita Das, Indian Statistical Institute, India
(10) Sudeep Pasricha, Colorado State University, USA
(11) Xin Li, Carnegie Mellon University, USA

Call for Participation: Workshop on Architectural Research Prototyping

Submitted by David Wentzlaff
June 14, 2015 at 12:30

Submitted by David Wentzlaff

WARP: 6th Workshop on Architectural Research Prototyping
Co-Located with ISCA 2015
Portland, Oregon, USA
Sunday, June 14th, 2015 (Afternoon)

Building prototype systems can be one of the best ways to validate
assumptions, gain intuition about practical design issues, and
provide platforms for future software research. While the research
ideas behind these prototypes can be published in top-tier
conferences, there are not many venues suitable for focusing on the
actual prototype itself. At the same time, building an FPGA, ASIC, or
full-custom computer architecture prototype is a non-trivial endeavor
and requires a significant financial and time commitment. This
workshop is intended as a forum for the builders in our community to
share their practical on-the-ground experiences, to provide a status
update on their progress, and to convey insights for those
considering prototyping their ideas.

This half-day workshop will be held on Sunday, June 14th, 2015,
co-located with ISCA-42 in Portland, OR. The technical program
committee and workshop organizers have selected a particularly strong
program from a record number of submissions. The 11 talks cover a
broad range of exciting prototypes including: millimeter-scale
full-system sensor motes and large-scale ASIC designs with 100’s of
millions of transistors; chip tapeouts in older technologies, chip
tapeouts in a state-of-the-art 28nm process, and chip tapeouts using
3D integration; multicore chip tapeouts with heterogeneous
accelerators; and FPGA prototypes focusing on multicore processors,
network interfaces, and memory systems.

Participation is encouraged for anyone interested in learning about
some of the best prototyping work going on within the computer
architecture research community. Participation is also encouraged for
researchers that have recently constructed or are currently
constructing prototypes, for those considering embarking on a
prototyping effort, or even for those who strongly disagree with the
need to build prototypes.

– “Prototyping Heterogeneous System-on-Chip Architectures:
A System-Level Design Approach”
L. Carloni (Columbia University)

– “Post Mortem on Building 28nm/45nm RISC-V Vector Microprocessors
with Chisel and the Rocket Chip Generator”
Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun,
B. Zimmer, K. Asanovic (University of California, Berkeley)

– “State of the Tinuso Platform and Toolset”
A. Hindborg, N. Jensen, P. Schleuniger, S. Karlsson (Technical
University of Denmark)

– “Designing a Complex 25-Core Academic Processor”
D. Wentzlaff, M. McKeown, Y. Fu, T. Nguyen, Y. Zhou, J. Balkind,
A. Lavrov, M. Shahrad, S. Payne (Princeton University)

– “From PDF to GDS: Designing the RoboBee SoC”
B. Reagen, X. Zhang, D. Brooks, G.-Y. Wei (Harvard University)

– “Lessons from Five Years of Making Michigan Micro Motes”
P. Pannuto, Y. Lee, Z. Foo, G. Kim, D. Blaauw, P. Dutta (University
of Michigan)

– “NVM-Charade: Open-Sourced FPGA-Based NVM Characterization Scheme”
G. Park, M. Shihab, L. Nahar, S. Kang, D. Donofrio, J. Shalf,
M. Jung (UT Dallas and Lawrence Berkeley National Laboratory)

– “Experiences with Two FabScalar-Based Chips”
E. Forbes, R. Chowdhury, B. Dwiel, A. Kannepalli, V. Srinivasan,
Z. Zhang, R. Widialaksono, T. Belanger, S. Lipa, E. Rotenberg,
W.R. Davis, P.D. Franzon (North Carolina State University)

– “Experiences and Lessons from a 3D Integrated Prototype”
R. Dreslinski (University of Michigan)

– “A 10G NetFPGA Prototype for In-network Aggregation”
V.T. Lee, J. Nelson, M. Oskin, L. Ceze (University of Washington)

– “Cymric: A Framework for Prototyping Near-Memory Architectures”
C. Kersey, H. Kim, S. Yalamanchili (Georgia Tech)

– Christopher Batten, Cornell University
– Dave Wentzlaff, Princeton University

– David Brooks, Harvard University
– Steve Keckler, NVIDIA/University of Texas at Austin
– Mark Oskin, University of Washington
– Jose Renau, University of California, Santa Cruz

Call for Participation: ACM SIGMETRICS 2015

Submitted by Niklas Carlsson
June 15 to June 19, 2015

Submitted by Niklas Carlsson

The organizing committee is excited to invite you to take part in
ACM SIGMETRICS 2015 to be held at the Oregon Convention Center in
Portland Oregon during June 15-19, 2015, as part of the Federated
Computer Research Conference (FCRC). ACM SIGMETRICS is the flagship
conference of the ACM special interest group for the computer systems
performance evaluation community.

Conference dates: June 16-18, 2015
Workshops: June 15, 2015
Tutorials: June 19, 2015

Oregon Convention Center in Portland, Oregon, USA

– Early conference registration deadline: May 18, 2015
– Special FCRC hotel rate available at each hotel until May 16, 2015


ACM has blocked sleeping rooms at five hotels all within a short walk
of the Oregon Convention Center with rates ranging from a very
affordable $110/night to $169/night for the higher end properties.

– NetEcon 2015
The 10th Workshop on the Economics of Networks, Systems and Computation
– DCC 2015
The 3rd Workshop on Distributed Cloud Computing
– MAMA 2015
The 17th Workshop on MAthematical performance Modeling and Analysis

We are grateful to the following organizations for sponsoring and
supporting ACM SIGMETRICS 2015.
– Akamai
– Facebook
– Hewlett-Packard (HP)
– Intel
– National Science Foundation (NSF)

General Chairs: Bill Lin (UCSD) and Jun (Jim) Xu (Georgia Tech)
TPC Chairs: Sudipta Sengupta (Microsoft) and Devavrat Shah (MIT)