Call for Nominations: MICRO Test of Time Award

Submitted by Saugata Ghose

Submitted by Saugata Ghose

MICRO Test of Time Award

The MICRO Test of Time (ToT) Award Committee is soliciting nominations
for the second MICRO ToT Award to be given at the International
Symposium on Microarchitecture in December 2015, to be held in
Hawaii. This award recognizes the most influential papers
published in past MICRO conferences that have had significant impact in
the field.

The award will recognize an influential MICRO paper whose influence is
still felt 18-22 years after its initial publication. In other words,
the award will be given to at most one paper that was published at MICRO
conferences in any of the years N-22, N-21, N-20, N-19, or N-18. This
year, N = 2015, so only papers published at MICRO conferences held in
1993, 1994, 1995, 1996, 1997 are eligible. An eligible paper that has
received at least 100 citations (according to Google Scholar) is
automatically nominated, but explicit nominations of such papers are
still encouraged.

Please submit your nomination via email to The following describes the
nomination criteria, how to submit a nomination, and the selection process.

1) Which papers are eligible for the 2015 MICRO ToT (Test of Time) Award?

Only papers published at MICRO conferences that happened between
1993-1997 (1993 and 1997 inclusive).

The list of eligible papers is at:

2) Who can nominate a paper?

Anyone can nominate a paper except for the author or co-author of the
nominated paper.

3) Is there a limit on the number of papers one person can nominate?

Yes. One can nominate up to 5 papers from all eligible papers. These
five papers can be published in any eligible year.

4) When is the last day to submit a nomination?

Nominations must be received by September 15, 2015.

5) How should a nomination be submitted?

Nominations must be submitted via email to

6) What should be included in the nomination email?

1. The title, the author list, and publication year of the nominated paper
2. A 100-word (maximum) nomination statement, describing why the paper
deserves the Test of Time Award
3. The name, title, affiliation of the nominator, and if appropriate, the
relationship of the nominator to the authors

Only one paper can be nominated in a single email.

7) What is the selection process?

The MICRO ToT Award committee will evaluate all submitted nominations after
September 16, 2015 to select at most one paper for the 2015 MICRO ToT (Test
of Time) Award. A strict conflict of interest policy will be followed. If a
ToT Award Committee Member has a conflict of interest with a paper that is
nominated, the member will recuse himself/herself from the discussion process
and a substitute will be placed in.

8.) Who are the current MICRO ToT Award committee members?

Rich Belgard
Pradip Bose
Bill Mangione-Smith
Onur Mutlu, Chair
Andre Seznec
Uri Weiser

9) When will the award be announced and given?

The award will be presented to the authors of the selected paper at the
Awards Ceremony during the International Symposium on Microarchitecture in
December 2015, to be held in Hawaii. Awardees are not expected to make a

10) What does the award consist of?

An award certificate and peer recognition. The authors of the selected paper
are expected to be invited to write a retrospective of the paper in the IEEE
Micro magazine.

11) What papers were previous winners of the award?

A list of the winners of the 2014 MICRO ToT Award is at:

Call for Papers: HotPower’15

Submitted by Christos Kozyrakis
July 26, 2015

Submitted by Christos Kozyrakis

The 7th Workshop on Power-Aware Computing and Systems (HotPower’15)

The 7th Workshop on Power-Aware Computing and Systems will be co-located
with the 25th ACM Symposium on Operating Systems Principles (SOSP) on
October 4, 2015. HotPower’15 is sponsored by USENIX, the Advanced
Computing Systems Association.

HotPower provides a forum to present the latest research and to debate
directions, challenges, and novel ideas about building energy-efficient
systems, including both traditional platforms ranging from smartphones to
datacenters, and emerging platforms such as implantable devices and Internet
of Things (IoT). Researchers and practitioners coming from diverse fields such
as computer architecture, systems and networking, measurement and modeling,
language and compiler design, mobile computing, and embedded systems will
have the opportunity to interact with one another, explore cross-cutting ideas,
and develop new perspectives from the interactions.

The workshop seeks submissions of early-stage research and novel ideas that
will generate interesting discussion, e.g., unconventional, promising ideas
with early results. Submissions about first-hand experience, lessons,
challenges and problems from building and operating real-world systems are
also welcome.

Topics of interest in energy-efficient computing include but are not limited
– Energy-efficiency measurements & benchmarking
– Power-performance trade-offs
– Reliability and power management
– Software optimizations & application design
– Run-time adaptation, scheduling, feedback control
– Power-aware computer architecture
– Energy efficient processors, networks, and storage
– Server & datacenter design
– Mobile and embedded systems, IOTs
– Innovative wearable & mobile devices
– System-level optimization, cross-layer coordination
– Renewable energy sources & energy storage
– Sustainability and life-cycle analysis

Paper Submission Deadline: July 26, 2015
Notification of Paper Acceptance: August 14, 2015
Camera Ready: August 30, 2015

Available Now: 2014 IEEE Micro Top Picks

Submitted by Lieven Eeckhout

Submitted by Lieven Eeckhout

IEEE Micro Top Picks 2014

IEEE Micro Top Picks annually awards the 12 most significant research papers
from computer architecture conferences based on novelty and potential impact.
The IEEE Micro Special Issue includes articles describing the awarded works in
a slightly higher level compared to the conference papers, providing more
context and discussion regarding importance and potential impact. In addition to
these 12 Top Picks, another 12 research papers were recognized as Honorable
Mentions. The selection committee was chaired by Luis Ceze (University of
Washington) and Karin Strauss (Microsoft Research).

Call for Participation: ASAP 2015

Submitted by Vaughn Betz
July 27 to July 29, 2015

Submitted by Vaughn Betz

The 2015 IEEE International Conference on Application-Specific
Architectures, Systems, and Processors (ASAP)

University of Toronto Faculty Club
Toronto, Canada
July 27-29, 2015


The 26th IEEE International Conference on Application-specific
Systems, Architectures and Processors 2015 (ASAP 2015) takes place
July 27-29, 2015 at the University of Toronto in Toronto, Canada.

ASAP is a premiere IEEE conference covering all aspects of
application-specific computing, including systems, architectures,
processors, and design methodologies/tools.

The conference sessions will be held at the University of Toronto
Faculty Club, which is reknown for its collection of Canadian Art.

– Arvind, Massachusetts Institute of Technology
– Derek Chiou, Microsoft and the University of Texas at Austin

The conference will include 21 full and 11 short papers with oral
presentation on topics ranging from customized domain-specific
processor architectures, computer security/cryptography, application
acceleration, design methods and tools, and fault tolerance. The oral
presentations are complemented by 18 poster paper presentations. The
advanced program and information about the keynote speakers
is posted on the conference website.

In addition to the technical program, ASAP 2015 will offer ample
opportunities for professional networking and socializing, including
an opening-day patio wine reception, and a banquet sunset cruise of
the beautiful Toronto islands and harbour.

General Chair:
Jason Anderson, University of Toronto

Program Co-Chairs:
Hayden So, University of Hong Kong
Deshanandh Singh, Altera Corp.

Finance Chair:
Warren Gross, McGill University

Publicity Chair:
Vaughn Betz, University of Toronto

Web Chair:
Hiren Patel, University of Waterloo

Publications Chair:
Yuko Hara-Azumi, Tokyo Inst. of Tech.

Industry Chairs:
Soojung Ryu, Samsung Electronics
Qiang Wang, Huawei America

Call for Papers: Workshop on Energy Efficient Super Computing

Submitted by Andres Marquez
November 15, 2015

Submitted by Andres Marquez

3rd International Workshop on Energy Efficient SuperComputing (E2SC)
in conjunction with SC’15
Austin, Texas, USA
November 15th-20th 2015

In cooperation with SIGHPC

With Exascale systems on the horizon, we will be ushering in an era with power
and energy consumption as a key concern for scalable computing. To achieve
viable high performance, a combination of evolutionary and revolutionary
methods is required with a stronger integration among hardware features,
system software and applications. Equally important are the capabilities for
fine-grained spatial and temporal measurement and control to facilitate energy
efficient computing across all layers. Current approaches for energy efficient
computing rely heavily on power efficient hardware in isolation. However, it
is pivotal for hardware to expose mechanisms for energy efficiency to optimize
power and energy consumption for various workloads and to reduce data motion,
a major component of energy use. At the same time, high fidelity measurement
techniques, typically ignored in data-center level measurement, are of high
importance for scalable and energy efficient inter-play at different layers of
application, system software and hardware.

This workshop seeks to address the important energy efficiency aspects in the
HPC community that have not been previously addressed by aspects covered in
the data center or cloud computing communities. Emphasis is given to an
application’s view related to significant energy efficiency improvements
as well as to the required hardware/software stack that must include
necessary power and performance measurement, and analysis harnesses.

Current tools are often limited by hardware capabilities and their lack of
information about the characteristics of a given workload/application. In the
same manner, hardware techniques, like dynamic voltage frequency scaling, are
often limited by their granularity (very coarse power management) or by their
scope (a very limited system view). More rapid realization of energy savings
will require significant increases in measurement resolution and optimization
techniques. Moreover, the interplay between performance, power and
reliability add another layer of complexity to this already difficult group
of challenges.

We encourage submissions in the following areas:
– Tools for power and energy analysis with different granularities and
scope from hardware (e.g., component, core, node, rack, system) or
software views (e.g., threads, tasks, processes, etc.) or both.
– Tools and techniques for measurement, analysis, and modeling of thermal
effects at different granularities (e.g., component, core, node, rack,
system) for large-scale systems.
– Techniques that enable power and energy optimizations at different
scale levels for HPC systems.
– Integration of power-aware technologies in applications and throughout
the software stack of HPC systems.
– Characterization of current state-of-the-art HPC systems and
applications in terms of power.
– Disruptive infrastructure hardware technologies for energy-efficient
– Analysis of future technologies that will provide improved energy
consumption and management on future HPC systems.

Paper Submission 18th August 2015
Paper Notification 25th September 2015
Final Papers Due 9th October 2015

Papers should not exceed ten single-space pages (including figures, tables and
references) using a 10-point on 8.5×11-inch pages (US Letter). Templates can
be found in:

Submissions will be judged on correctness, originality, technical strength,
significance, presentation quality and appropriateness. Submitted papers
should not have appeared in or should not be under consideration for another
venue. A full peer-review processes will be followed with each paper being
reviewed by at least 3 members of the program committee. Submissions will be
made through EasyChair (

General Chairs:
Kirk Cameron, Virginia Tech, USA
Adolfy Hoisie, PNNL, USA
Darren Kerbyson, PNNL, USA
David Lowenthal, Arizona State University, USA
Dimitrios S. Nikolopoulos, University of Belfast, UK
Sudha Yalamanchili, Georgia Institute of Technology, USA

Program Co-Chairs:
Laura Carrington, San Diego Supercomputing Center, USA
Joseph Manzano, PNNL, USA

Publicity Chair:
Andres Marquez, PNNL, USA

European Liaison:
Michele Weiland, EPCC, UK

Publication Chair:
Abhinav Vishnu, PNNL, USA

Onsite Coordination:
Kevin J. Barker, PNNL, USA

Program Committee:
Jee Choi Georgia Institute of Technology, USA
Pietro Cicotti San Diego Supercomputing Center, USA
Philippe Claus University of Strasbourg, France
Joshua Fryman Intel, USA
Vladimir Getov University of Westminster, UK
Georg Hager Erlangen Regional Computing Center, Germany
Eric Van Hensbergen ARM Research, USA
Torsten Hoefler ETH Zurich, Switzerland
Hillery Hunter IBM Research, USA
Lennart Johnsson University of Houston, USA
Erwin Laure KTH/PDC Royal Institute of Technology, Sweden
Dong Li University of California Merced, USA
Satoshi Matsuoka Tokyo Institute of Technology, Japan
Leonid Oliker Lawrence Berkeley National Laboratory, USA
Scott Pakin Los Alamos National Laboratory, USA
Barry Rountree Lawrence Livermore National Laboratory, USA
Shuaiwen Song Pacific Northwest National Laboratory, USA

Call for Proposals: Workshops and Tutorials at HPCA 2016

Submitted by Carole-Jean Wu
March 12 to March 13, 2016

Submitted by Carole-Jean Wu

Workshops and Tutorials at HPCA 2016
Barcelona, Spain
March 12-13, 2016

The 2016 IEEE International Symposium on High-Performance Computer
Architecture (HPCA 2016) is seeking proposals for workshops and tutorials
to accompany the conference. Workshops and tutorials will be held on
Saturday-Sunday, March 12-13, and may be a half day or a full day in
length. We encourage members of the community to consider submitting
proposals for workshops and tutorials that bring together researchers and
practitioners working on research topics of significant current interest to
the HPCA community.

Prospective workshop and tutorial organizers are invited to submit
proposals in pdf of no more than two pages to the workshop and tutorials
chair Carole-Jean Wu, via email

– Deadline for submission: September 14, 2015, 11:59 PM EDT
– Notification of acceptance: October 14, 2015


For workshops, please include in your proposal:
– Title of the workshop
– Organizers and their affiliations
– Sample call for papers, including the workshop’s main topics and URL
– Expected duration of the workshop: 1/2 day or full day
– For previously held workshops, the number of papers and attendees at
the last workshop.

For tutorials, please include in your proposal:
– Title of the tutorial
– Organizers, presenters, and their affiliations
– Abstract of the tutorial, including objectives, target audience, and
prerequisite knowledge
– List of topics to be covered and URL to the tutorial web page
– Expected duration of the tutorial: 1/2 day or full day
– For previously held tutorials, the location (i.e., which conference), date,
and number of attendees at the last tutorial.

Selection committee:
The workshop proposals will be evaluated by members of the HPCA 2016
organizing committee.

Sponsored by the IEEE Computer Society TC on Computer Architecture.

Call for Papers: CGO 2016

Submitted by Bjoern Franke
March 12 to March 18, 2016

Submitted by Bjoern Franke

2016 IEEE/ACM International Symposium on Code Generation
and Optimization (CGO)

co-located with HPCA, PPoPP, CC, and EuroLLVM
Barcelona, Spain
March 12-18, 2016

The International Symposium on Code Generation and Optimization (CGO) provides
a premier venue to bring together researchers and practitioners working at the
interface of hardware and software on a wide range of optimization and code
generation techniques and related issues. The conference spans the spectrum
from purely static to fully dynamic approaches, and from pure software-based
methods to specific architectural features and support for code generation and

Original contributions are solicited on, but not limited to, the following

Code Generation, Translation, Transformation, and Optimization
– For performance, energy, virtualization, portability, security or reliability
concerns, and architectural support.
– Efficient execution of dynamically typed and higher-level languages.
– Optimization and code generation for emerging programming models, platforms,
domain-specific languages.
– Dynamic/static, profile-guided, feedback-directed, and machine learning based

Static, Dynamic, and Hybrid Analysis
– For performance, energy, memory locality, throughput or latency, security,
reliability, or functional debugging.
– Program characterization methods.
– Efficient profiling and instrumentation techniques; architectural support.
– Novel and efficient tools.

Compiler design, practice and experience
– Compiler abstraction and intermediate representations.
– Vertical integration of language features, representations, optimizations,
and runtime support for parallelism.
– Solutions that involve cross-layer (HW/OS/VM/SW) design and integration.
– Deployed dynamic/static compiler and runtime systems for general purpose,
embedded system and Cloud/HPC platforms.

Parallelism, heterogeneity, and reconfigurable architectures
– Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA.
– Compiler-support for vectorization, thread extraction, task scheduling,
speculation, transaction, memory management, data distribution and

Authors should carefully consider the difference in focus with the co-located
conferences when deciding where to submit a paper. CGO will make the
proceedings freely available via the ACM DL platform during the period from two
weeks before to two weeks after the conference. This option will facilitate
easy access to the proceedings by conference attendees, and it will also enable
the community at large to experience the excitement of learning about the
latest developments being presented in the period surrounding the event itself.

Authors of accepted papers will be invited to formally submit their supporting
materials to the Artifact Evaluation process. The Artifact Evaluation process
is run by a separate committee whose task is to assess how the artifacts
support the work described in the papers. This submission is voluntary and will
not influence the final decision regarding the papers. Papers that go through
the Artifact Evaluation process successfully will receive a seal of approval
printed on the papers themselves. Additional information is available on the
CGO AEC web page.
Authors of accepted papers are encouraged to make these materials publicly
available upon publication of the proceedings, by including them as “source
materials” in the ACM Digital Library.

Abstract Submission: September 12, 2015
Paper Submission: September 18, 2015
Author Response Period: October 28-30, 2015
Notification to Authors: November 8, 2015
Artifact Submission: November 20, 2015
Artifact Decision: December 22, 2015

General Chair:
Björn Franke (U. of Edinburgh)

Programme Chairs:
Fabrice Rastello (Inria)
Youfeng Wu (Intel)

Programme Committee:
Erik Altman (IBM)
Saman Amarasinghe (MIT)
Edson Borin (U. of Campinas)
Florian Brandner (ENSTA)
Derek Bruening (Google)
Vugranam C. Sreedhar (IBM)
Wenguang Chen (Tsinghua U.)
Mila Dalla Preda (U. of Verona)
Evelyn Duesterwald (IBM)
Guang Gao (U. of Delaware)
Antonio Gonzalez (UPC/Intel)
Christophe Guillon (STmicroelectronics)
Sebastian Hack (U. of Saarland)
Ben Hardekopf (UCSB)
Wei-Chung Hsu (National Chiao Tung U.)
Robert Hundt (Google)
Chris J Newburn (Intel)
Vijay Janapa Reddi (U. of Texas)
Alexandra Jimborean (Uppsala)
Alain Ketterlin (U. Louis Pasteur)
Jaejin Lee (Seoul National U.)
Mary Lou Soffa (U. of Virginia)
Scott Mahlke (U. of Michigan)
Vineeth Mekkat (Intel)
John Mellor-Crummey (Rice U.)
Soo-mook Moon (Seoul National U.)
Tipp Moseley (Google)
Dorit Nuzman (Intel)
Michael O’Boyle (U. of Edinburgh)
Ramesh Peri (Intel)
Keshav Pingali (U. of Texas)
Louis-Noel Pouchet (Ohio State U.)
Aaron Smith (Microsoft)
Cheng Wang (Intel)
Chenggang Wu (ICT)
Jingling Xue (U. of New South Wales)
Qing Yi (U. of Colorado)
Antonia Zhai (U. of Minnesota)

Finance Chair:
Christophe Dubach (U. of Edinburgh)

Workshop and Tutorials Chair:
Jeronimo Castrillon (TU Dresden)

Student Travel Chair:
Ronald Mak (San Jose State U.)

Sponsors Chair:
Tobias Edler von Koch (Qualcomm)

Website Chair:
Tom Spink (U. of Edinburgh)

Artifact Evaluation Chairs:
Grigori Fursin (cTuning Foundation)
Bruce Childers (U. of Pittsburgh)

Steering Committee:
Kim Hazelwood (Yahoo Labs)
Robert Hundt (Google)
Scott Mahlke (Michigan)
Jason Mars (Michigan)
Kunle Olukotun (Stanford)
Vijay Janapa Reddi (U. of Texas)
Olivier Temam (Google) — Chair

Call for Papers: JPDC Special Issue on Energy Efficient Multi-Core and Many-Core Systems

Submitted by Amir Rahmani
September 1, 2015

Submitted by Amir Rahmani

Special Issue on Energy Efficient Multicore and Manycore Systems
The Journal of Parallel and Distributed Computing (Elsevier)

Recent trends in the microprocessor industry have important ramifications for
the design of the next generation of high-performance as well as embedded
parallel and network-based systems. By increasing number of cores, it is
possible to improve the performance while keeping the power consumption at the
bay. This trend has reached the deployment stage in parallel and network-based
systems ranging from small ultramobile devices to large telecommunication
servers. It is expected that the number of cores in these systems increases
dramatically in the near future. For such systems, energy efficiency is one of
the primary design constraints. The cessation of Dennard scaling and the dark
silicon phenomenon have limited recent improvements in transistor speed and
energy efficiency, resulting in slowed improvements in multi-core and many-core
systems. Consequently, architectural innovation has become crucial to achieve
performance and efficiency gains. New technologies that combine different types
of cores or similar cores with different computation capabilities can result in
a better match between the workload and the execution hardware improving
overall system energy efficiency. In addition, multi-core and many-core systems
need to be able to reconfigure themselves adaptively by monitoring their own
condition and the surrounding environment in order to adapt themselves to
different scenarios and performance-power requirements. Runtime monitoring
becomes crucial in the near future parallel and distributed multicore systems
due to increase in thermal issues as well as due to the need for various
adaptive managements.

This special issue addresses all aspects of energy-efficient computing in parallel
and distributed multi-core and many-core systems. Topics of interest include:
– Power and thermal estimation, analysis, optimization, and management
techniques for hardware and software systems
– Energy- and thermal aware application mapping and scheduling
– Energy- and thermal-aware dark silicon system design and optimization
– Energy-efficient heterogeneous system architecture
– Programming models, tools, languages and compilers to support energy-
aware computing
– Low-power monitor and sensor circuits
– Energy Efficient defect/fault tolerance, testing, and reliability
– Aging aware design, energy- and thermal-related reliability issues
– Energy-efficient off-chip/on-chip communication architectures including
– 3D architectures, integration and synthesis
– Energy-proportional systems
– Energy-efficient memory architectures and technologies (e.g. coherence
– Formal methods for modeling, design and verification of energy efficient
parallel and network-based systems
– Application analysis and parallelization for energy-efficient design
– Cases studies of parallel and network-based systems demonstrating
energy-efficient implementation as well as emerging applications and design

– Hannu Tenhunen, Royal Institute of Technology, Sweden (
– Alexander V. Veidenbaum, University of California, Irvine, USA (
– Jose L. Ayala, Complutense University of Madrid, Spain (
– Pasi Liljeberg, University of Turku, Finland (
– Amir Rahmani, University of Turku, Finland (

Manuscript due: September 1st, 2015
Acceptance/rejection notification: November 15th, 2015
2nd round check: January 15th, 2016
Final manuscript due: March 15th, 2016

Submitted manuscripts will be reviewed according to the peer review policy of
Information Sciences as available on-line at
Previously published conference papers should be clearly stated by the authors
and an explanation should be provided how such papers have been extended to
be considered for this special issue. Manuscripts should be formatted and be
submitted online according to the instructions for Information Sciences at
Authors should make sure to select the correct special issue by selecting
“SI: E2MC2” in the Article Type step.

Call for Papers: Workshop on Embedded Systems Security

Submitted by Dimitrios Serpanos
October 8, 2015

Submitted by Dimitrios Serpanos

10th Workshop on Embedded Systems Security (WESS 2015)
part of the Embedded Systems Week (ESWEEK 2015)
Amsterdam, The Netherlands
October 8, 2015

Embedded computing systems are continuously adopted in a wide range of
application areas and importantly, they are responsible for a large number of
safety-critical systems as well as for the management of critical information.
The advent of the Internet-of-Things introduces a large number of security
issues: the Internet can be used to attack embedded systems and embedded
systems can be used to attack the Internet. Furthermore, embedded systems are
vulnerable to many attacks not relevant to servers because they are physically
accessible. Inadvertent threats due to bugs, improper system use, etc. can
also have effects that are indistinguishable from malicious attacks.

This workshop will address the range of problems related to embedded system
security. Of particular interest are security topics that are unique to
embedded systems. The workshop will provide proceedings to the participants
and will encourage discussion and debate about embedded systems security.

Topics of Interest:
– Trust models for secure embedded hardware and software
– Isolation techniques for secure embedded hardware, hyperware and software
– System architectures for secure embedded systems
– Hardware security
– Metrics for secure design of embedded hardware and software
– Security concerns for medical and other applications of embedded systems
– Support for intellectual property protection and anti-counterfeiting
– Specialized components for authentication, key storage and key generation
– Support for secure debugging and troubleshooting
– Implementation attacks and countermeasures
– Design tools for secure embedded hardware and software
– Hardware/software co-design for secure embedded systems
– Specialized hardware support for security protocols
– Efficient and secure implementation of cryptographic primitives

The proceedings of the workshop will be published by the ACM. Papers must be
submitted in PDF form through the EASYCHAIR system. Submitted papers should
present original research that is unpublished and not submitted elsewhere.
Papers should be no more than 10 pages 2-column in ACM format. Templates for
the submission of papers can be found at the ACM website. To submit a paper
refer to

Paper submission deadline: July 3, 2015
Author notification: August 18, 2015
Camera ready papers due: September 1, 2015
Copyright forms due: September 1, 2015
Workshop date: October 8, 2015

Program Chairs:
S. Koubias (Univ. of Patras)
T. Sauter (Donau University Krems)

Program Committee:
D. Arora (Intel, USA)
I.C. Bertolotti (PolitecnicoTorino, Italy )
A. Bogdanov (KU Leuven, Belgium)
B. Carbunar (FIU, USA)
K. Dietrich (NXP Semiconductors, Austria)
M. van Dijk (U. Connecticut, USA)
D. Forte (U. Connecticut, USA)
J. Groszschaedl (U. Luxemburg, Luxemburg)
W. Kastner (TU Wien, Austria)
F. Praus (FH Technikum Wien, Austria)
S. Rajagopalan (Honeywell, USA)
P. Schwabe (Radboud U. Nijmegen, Netherlands)
N. Sklavos (TEI Epirus, Greece)
M. Taha (Assiut U., Egypt)
A. Treytl (Donau U. Krems, Austria)
Y. Wang (I2R A*STAR, Singapore)

Steering Committee:
C. Gebotys (U. Waterloo)
D. Serpanos (QCRI)
M. Wolf (Georgia Tech)

Call for Papers: ASPLOS 2016

Submitted by Changhee Jung
April 2 to April 6, 2016

Submitted by Changhee Jung

21th International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS 2016)

Atlanta, GA, USA
Apr 2-6, 2016

Abstracts Due: Aug 5, 2015
Full Papers Due: Aug 12, 2015

ASPLOS is the premier forum for multidisciplinary systems research
spanning computer architecture and hardware, programming languages and
compilers, operating systems and networking, as well as applications
and user interfaces. The 2016 conference will be held in Atlanta,
Georgia, “capital of the new south”, home to the 1996 Summer Olympic
Games, with world-class restaurants and a myriad of cultural
attractions to a hip nightlife and sporting events galore.

Like its predecessors, ASPLOS 2016 invites papers on ground-breaking
research at the intersection of at least two ASPLOS disciplines:
architecture, programming languages, operating systems, and related
areas. Non-traditional topics are especially encouraged. The
importance of cross-cutting research continues to grow as we grapple
with the end of Dennard scaling, the explosion of big data, scales
ranging from ultra-low power wearable devices to exascale parallel and
cloud computers, the need for sustainability, and increasingly
human-centered applications. ASPLOS embraces systems research that
directly targets these new problems in innovative ways. The research
may target diverse goals such as performance, energy and thermal
efficiency, resiliency, security, and sustainability. The review
process will be sensitive to the challenges of multidisciplinary work
in emerging areas.

Areas of interest include, but are not limited to:
– Emerging platforms at all scales, from embedded to cloud
– Heterogeneous multicore architectures and accelerators
– Systems for enabling parallelism at an extreme scale
– Non-traditional computing systems
– Systems that address social, educational, and environmental challenges
– Programming models and compilation for existing and emerging platforms
– Managing, storing, and computing on big data
– Virtualization
– Memory and storage technologies and architectures
– Power, energy, and thermal management
– Security, reliability, and availability
– Verification and testing, and their impact on design

Papers should be submitted for double-blind review following the
submission guidelines available at the conference website.

Abstracts: Aug 5, 2015
Full Paper Submissions: Aug 12, 2015
Author Response Period: Oct 31 – Nov 2, 2015
Notification: Nov 17, 2015
Final Copy Deadline: Jan 30, 2016*

*Proceedings will be available in the ACM DL up to two weeks prior to the

General Chair:
Tom Conte, Georgia Insitute of Technology

Program Chair:
Yuanyuan (YY) Zhou, University of California, San Diego

Program Committee:
Sarita Adve, University of Illinois, Urbana-Champaign
Marcos K. Aguilera, VMware Research Group
Jade Alglave, University College London
Mona Attariyan, Google
Rajeev Balasubramonian, University of Utah and HP-Labs
Yungang Bao, ICT, China
Luiz André Barroso, Google
Ricardo Bianchini, Rutgers University and Microsoft
Angelos Bilas, FORTH and University of Crete, Greece
Steve Blackburn, Australian National University
Calin Cascaval, Qualcomm
Wenguang Chen, Tsinghua University, China
Albert Cohen, INRIA, France
Joe Devietti, University of Pennsylvania
Chen Ding, University of Rochester
Ding Yuan, University of Toronto
Jason Flinn, University of Michigan
Maria Garzaran, Intel and University of Illinois, Urbana-Champaign
Roxana Geambasu, Columbia University
Gernot Heiser, NICTA and UNSW, Australia
Christopher Hughes, Intel
Hillery Hunter, IBM Research
Sanjeev Kumar, Facebook
Katheryn Mckinley, Microsoft Research
Gilles Muller, INRIA, France
Madanlal Musuvathi, Microsoft Research
Onur Mutlu, Carnegie Mellon University
Satish Narayanasamy, University of Michigan
Sam H. Noh, Hongik University, Korea
Santosh Pande, Georgia Tech
Shankar Pasupathy, NetApp
Koushik Sen, University of California, Berkeley
Xipeng Shen, North Carolina State University
Liuba Shrira, Brandeis University
Karin Strauss, Microsoft Research and University of Washington
Lingjia Tang, University of Michigan
Michael Taylor, University of California, San Diego
Dan Tsafrir, Technion, Isreal
Joe Tucek, HP Labs
David Wentzlaff, Princeton University
Emmett Witchel, University of Texas, Austin
David Wood, University of Wisconsin, Madison

Finance Chair:
Hadi Esmaeilzadeh, Georgia Tech

Publicity and Publication Chair:
Changhee Jung, Virginia Tech

Local Arrangements Chair:
Catherine Linder Conte

Web Chair:
Gennady Pekhimenko, Carnegie Mellon University