Call for Submissions: SC'15 Doctoral Showcase Program

Submitted by Sunita Chandrasekaran

Submitted by Sunita Chandrasekaran

Doctoral Showcase Program
Austin, TX, USA

Submissions due: August 7, 2015 (EXTENDED DEADLINE)
Notification Sent: September 7, 2015

As part of the Technical Program, the Doctoral Showcase provides an
important opportunity for students near the end of their Ph.D. to present a
summary of their dissertation research in the form of short talks and posters.
Unlike technical paper and poster presentations, Doctoral Showcase
highlights the entire contents of each dissertation, including previously
published results, to allow for a broad perspective of the work.

Submissions will be accepted for the Dissertation Research Showcase
track for Ph.D. students who will be graduating in the next 12 months.
This track provides a venue for Ph.D. students to present a summary of
their latest and systematic dissertation research. It provides an opportunity
to educate junior graduate students working in high performance
computing areas. This program also provides an ideal opportunity
for prospective employers in academia, research laboratories and
industry to interact with prospective Ph.D.s.

Students are asked to submit a four-page summary of their research
(include research problem statement and major results/contributions),
a poster draft, and list of student’s conference/journal publications for
consideration by the Doctoral Showcase committee. The authors of
the accepted submissions will be invited to give presentations at the
SC15 conference.

Submissions to this program may also be submitted to the SC15 ACM
Student Research Competition posters track or published in other venues.

Everyone attending SC15 is encouraged to attend this program.
Come to see the latest and greatest dissertation work done by
tomorrow’s HPC experts.

OpenFPGA has offered funding/honorarium for student participation,
a priority would be for work that impacts cancer research.

Web Submissions:
Email Contact and Questions:

SC15 Doctoral Showcase Chair:
Melissa C. Smith (Clemson University)

SC15 Doctoral Showcase Vice Chair:
Volodymyr Kindratenko (National Center for Supercomputing Applications)

Call for Participation: Hot Interconnects 2015

Submitted by Torsten Hoefler
August 26 to August 28, 2015

Submitted by Torsten Hoefler

23rd International Symposium on High Performance Interconnects
Oracle Santa Clara Agnews Campus
Santa Clara, California
August 26-28, 2015 (following Hot Chips)

Early Registration: Ends at 11:59 PM (PDT), July 31st, 2015
Last Day for Refunds: 11:59 PM (PDT), August 12, 2015.

Come join us for the 23rd annual IEEE Symposium on High-Performance
Interconnects (Hot Interconnects), to be held August 26-27 (with
tutorials on August 28), 2015, generously hosted by Oracle at the
historic Oracle Agnews Campus, Santa Clara, California.

Hot Interconnects (HotI) is the premier international forum for
researchers and developers of state- of-the-art hardware and
software architectures and implementations for interconnection
networks of all scales, ranging from multi-core on-chip
interconnects to those within systems, clusters, data centers, and
clouds. This yearly conference is attended by leaders in industry
and academia, creating a wealth of opportunities to interact with
individuals at the forefront of this field.

This year’s Hot Interconnects features keynotes from Oracle’s Vice
President of Hardware Development Rick Heatherington, and David
Meyer, the CTO and Chief Scientist of Brocade Communications. There
will be a great lineup of exciting talks, Intel will be discussing
their upcoming OmniPath technology, Facebook will discuss their
efforts in interconnects and VMWare will talk about NFV.

A panel “HPC vs. Datacenter Networks” discussing the intersection
of HPC networking technologies and Data center networking from
experts in both areas from world-leading companies and institutions
will provide a lively debate on what each group can learn from each
other and areas in which they are already converging.

There will be four technical paper sessions covering the cutting
edge in interconnect research and development on cross-cutting
issues spanning computer systems, networking technologies, and
communication protocols for high-performance interconnection
networks. This conference is directed particularly at new and
exciting technology and product innovations in these areas.

Building on last year’s successful technical program comprising
keynotes, technical sessions, and panels on networking for
data centers and high-performance computing, the 2015 edition of Hot
Interconnects will be located at Oracle Agnews Campus in Santa
Clara, CA. This year’s conference focuses on HPC Interconnects and
their use in traditional and non-traditional applications. We hope
you can join us.

A preliminary program and additional conference details are available

Fabrizio Petrini, IBM T.J. Watson

Technical Program Chairs:
Ada Gavrilovska, Georgia Tech
Ryan Grant, Sandia National Laboratories

Tutorial Chair:
Vikram Dham, Kamboi Technologies

Publication Chair:
Luca Valcarenghi, Scuola Superior Sant’Anna

Awards Chair:
Xin Huang, Cyan

Finance Chairs:
Madeleine Glick, University of Arizona
Xinyu Que, IBM T.J. Watson

Registration Chair:
Charlie Perkins, Huawei

Media Chair:
Torsten Hoefler, ETH Zurich

Local Arrangements Chair:
Don Draper, Oracle

Natalia Berezneva

Steering Committee:
Allen Baum, Mill Computing
Keren Bergman, Columbia University
Raj Channa, RBC Capital Markets
Lily Jow, Hewlett Packard
Mark Laubach, Broadcom
John Lockwood, Algo-Logic Systems
Fabrizio Petrini, IBM T.J. Watson
Dan Pitt, Open Networking Foundation

Tool Release: HotSpot 6.0

Submitted by Kevin Skadron

Submitted by Kevin Skadron

HotSpot 6.0

HotSpot version 6.0 introduces several new features that can be useful to
state-of-the-art thermal modeling needs: 1) an upgraded solver based on
SuperLU that significantly speeds up steady-state simulations; 2) an improved
3D model that supports layers with non-uniform thermal resistivity and heat
capacity; 3) an improved secondary heat transfer path model that is compatible
with 3D systems. We want to thank Prof. Ayse K. Coskun’s research team at
Boston University for developing the modeling capability for non-uniform layers.

You can download version 6.0 from

HPCA 2016: Call for Papers, Workshops and Tutorials

Submitted by Augusto Vega
March 12 to March 16, 2016

Submitted by Augusto Vega

22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA 2016)
collocated with PPoPP and CGO
Barcelona, Spain
March 12-16 2016

The IEEE International Symposium on High-Performance Computer Architecture
(HPCA) provides a high-quality forum for scientists and engineers to present
their latest research findings in this rapidly changing field. Authors are
invited to submit papers on all aspects of high-performance computer

Topics of interest include, but are not limited to:
– Processor, cache, and memory architectures
– Parallel computer architectures
– Multicore architectures
– Impact of technology on architecture
– Power-efficient architectures and techniques
– Dependable/secure architectures
– High-performance I/O systems
– Embedded and reconfigurable architectures
– Interconnect and network interface architectures
– Architectures for cloud-based HPC and data centers
– Innovative hardware/software trade-offs
– Impact of compilers and system software on architecture
– Performance modeling and evaluation
– Architectures for emerging technology and applications

Authors should submit an abstract by Friday, September 4, 2015, 5pm EDT. They
should submit the full version of the paper by Friday, September 11, 2015,
5pm EDT. No requests for extensions will be granted. The full version should
be a PDF file that follows the submission guidelines, which will be available
at the submission website. Papers should be submitted for double-blind review.
We anticipate selecting a Best Paper award. All papers will be evaluated based
on their novelty, fundamental insights, experimental evaluation, and potential
for long-term impact.

Abstract submission deadline: 4 September 2015, 5pm EDT
Paper submission deadline: 11 September 2015, 5pm EDT
Rebuttal period: 28-30 October 2015
Paper notification of acceptance: 9 November 2015

The IEEE International Symposium on High-Performance Computer Architecture
(HPCA) is seeking proposals for workshops and tutorials to accompany the
conference. Workshops and tutorials will be held on Saturday-Sunday, March
12-13, and may be a half day or a full day in length. We encourage members of
the community to consider submitting proposals for workshops and tutorials
that bring together researchers and practitioners working on research topics
of significant current interest to the HPCA community. Prospective workshop
and tutorial organizers are invited to submit proposals in PDF of no more
than two pages to the workshop and tutorials chair Carole-Jean Wu, via email

– Deadline for submission: 14 September 2015, 11:59pm EDT
– Notification of acceptance: 14 October 2015

For workshops, please include in your proposal:

– Title of the workshop
– Organizers and their affiliations
– Sample call for papers, including the workshop’s main topics and URL
– Expected duration of the workshop: 1/2 day or full day
– For previously held workshops, the number of papers and attendees at the
last workshop

For tutorials, please include in your proposal:

– Title of the tutorial
– Organizers, presenters, and their affiliations
– Abstract of the tutorial, including objectives, target audience, and
prerequisite knowledge
– List of topics to be covered and URL to the tutorial web page
– Expected duration of the tutorial: 1/2 day or full day
– For previously held tutorials, the location (i.e., which conference),
date, and number of attendees at the last tutorial

Selection committee:

The workshop proposals will be evaluated by members of the HPCA 2016
organizing committee. Sponsored by the IEEE Computer Society TC on Computer

Call for Participation: NAS 2015

Submitted by Ramon Bertran
August 6 to August 7, 2015

Submitted by Ramon Bertran

The IEEE International Conference on Networking, Architecture, and Storage (NAS 2015)
Boston, MA, USA
August 6-7, 2015

NAS provides a high-quality international forum to bring together researchers
and practitioners from academia and industry to discuss cutting-edge research
on networking, high-performance computer architecture, and parallel and
distributed data storage technologies. This year, NAS will be held in the Park
Plaza Hotel in downtown Boston, MA during August 6-7, 2015.

Early registration deadline: July 8th, 2015
Hotel reservation deadline: July 6th, 2015

NAS registration web site:

Hotel Reservation web site:

Conference Program:
Final program for the main conference is ready!

Keynote Speakers:
Scott Klasky, Oak Ridge National Laboratory
David Brooks, Harvard University

Complete details at

Call For Papers: IA^3 2015

Submitted by Antonino Tumeo
July 8 to August 24, 2015

Submitted by Antonino Tumeo

5th Workshop on Irregular Applications: Architectures and Algorithms (IA^3)
in conjunction with SC’15
Austin, TX, USA
November 15, 2015

Irregular applications span a broad range of applications with unpredictable
memory access patterns, control structures, and/or network transfers. They
typically use pointer-based data structures such as graphs and trees, often
present fine-grained synchronization and communication, and generally
operate on very large data sets. They have a significant degree of latent
parallelism, which however is difficult to exploit due to their complex
behavior. Current high performance architectures rely on data locality and
regular computation to tolerate access latencies, and often do not cope
well with the requirements of these applications. Furthermore, irregular
applications are difficult to scale on current supercomputing machines,
due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields,
such as social network analysis, bioinformatics, semantic graph databases,
bioinformatics, Computer Aided Design (CAD) and computer security. Many
of these application areas also process massive sets of unstructured data,
which keep growing exponentially. Addressing the issues of irregular
applications on current and future architectures will become critical to
solve the scientific challenges of the next few years.

This workshop seeks to explore solutions for supporting efficient execution
of irregular applications in the form of new features at the level of the
micro- and system-architecture, network, languages and libraries, runtimes,
compilers, analysis, algorithms. Topics of interest, of both theoretical and
practical significance, include but are not limited to:

– Micro- and System-architectures
– Network and memory architectures
– Heterogeneous, custom and emerging architectures (GPUs, FPGAs,
multi- and many-cores, processors-in-memory)
– Modeling, simulation and evaluation of architectures
– Innovative algorithmic techniques
– Parallelization techniques and data structures
– Approaches for managing massive unstructured datasets
– Languages and programming models
– Library and runtime support
– Compiler and analysis techniques
– High performance data analytics, including graph databases

Besides regular papers, papers describing work-in-progress or incomplete
but sound, innovative ideas related to the workshop theme are also
encouraged. We solicit both 8-page regular papers and 4-page position

Abstract submission: 17 August 2015
Position or full paper submission: 24 August 2015
Notification of acceptance: 2 October 2015
Camera-ready position and full papers: 9 October 2015
Workshop: 15 November 2015

All submissions should be in double-column, single-spaced letter format, using
9-point size fonts, with at least one-inch margins on each side. Submitted manuscripts
may not exceed eight pages in length for regular papers and four pages for position
papers including figures, tables and references.
Submission site:

The proceedings of the workshop will be published in cooperation with ACM SIGHPC.

Workshop chairs:
Antonino Tumeo, Pacific Northwest National Laboratory,
John Feo, Context Relevant,
Oreste Villa, NVIDIA Research,

Program Committee:
Scott Beamer, University of California Berkeley, US
David Brooks, Harvard University, US
Vito Giovanni Castellana, Pacific Northwest National Laboratory, US
Georgi Gaydadjiev, Chalmers University, SWE
Maya Gokhale, Lawrence Livermore National Laboratory, US
John Leidel, Texas Tech University, US
Kamesh Madduri, Penn State University, US
Richard Murphy, Micron, US
Onur Mutlu, Carnegie Mellon University, US
Walid Najjar, University of California Riverside, US
Jacob Nelson, University of Washington, US
Kunle Olukotun, Stanford University, US
Timothy Mattson, Intel, US
Gianluca Palermo, Politecnico di Milano, ITA
Fabrizio Petrini, IBM TJ Watson, US
Keshav Pingali, University of Texas Austin, US
Sébastien Rumley, Columbia University, US
Erik Saule, University of Carolina Charlotte, US
John Shalf, Lawrence Berkeley National Laboratory, US
Michela Taufer, University of Delaware, US
Pedro Trancoso, University of Cyprus, CYP

Call for Workshops and Tutorials: CGO 2016

Submitted by Jeronimo Castrillon

Submitted by Jeronimo Castrillon

International Symposium on Code Generation and Optimization (CGO)
Workshops and Tutorials
Barcelona, Spain
March 12-13, 2016

The 2016 ACM/IEEE International Symposium on Code Generation and
Optimization (CGO), located in Barcelona, is looking for proposals for co-located
workshops and tutorials that will run before the main conference. Please see the
CGO web site for more details:

The deadline for submitting a workshop or tutorial proposal is September 14,
2015 but interested parties are encouraged to contact the workshops and
tutorial chair as soon as possible.

If you wish to organize a workshop or tutorial (1/2 or 1 day), please e-mail a
proposal to with the following details:

– Title of the workshop or tutorial and acronym
– Organizers and their affiliations
– Brief description of topics to be covered
– Expected duration; i.e., 1/2 day or full day
– Expected attendance (stats from previous years are ideal)
– URL of workshop/tutorial information (if available)
– Any special requirements the workshop or tutorial may have

One free registration will be made available per accepted workshop/tutorial
(could be used for one of the organizers or for one invited speaker). To avoid
name clashes we reserve the right to modify the acronym of the event. Please
also note that an event may be cancelled if there are insufficient

Proposal Submission : September 14, 2015
Notification : October 1, 2015
Workshop/Tutorial date : March 12-13, 2016

Jeronimo Castrillon,

Call for Workshops and Tutorials at MICRO 2015 (submission deadline: July 10)

Submitted by Bipin Rajendran
December 5 to December 6, 2015

Submitted by Bipin Rajendran

Workshops and Tutorials at MICRO-48
Waikiki, Hawaii, USA
Dec 5-6, 2015

Submission Deadline: July 10, 2015
Notification Date: July 17, 2015

Proposals should be one to two pages and must include the following
1. Title of the Workshop / Tutorial
2. Organizers and their affiliations (including short bios)
3. Expected duration of the workshop/tutorial; i.e., half day or full day
4. If the workshop/tutorial was previously held, provide the location
(i.e., which conference), date, number of published papers (if any), and
number of attendees at the last event
5. If workshop proposal, provide sample call for papers, including the
workshop main topics
6. If tutorial proposal, provide the abstract of the tutorial

Submit workshop proposal (1 to 2 pages) to Aamer Jaleel
Submit tutorial proposal (1 to 2 pages) to Christopher Hughes

Call for Papers: Workshop on Heterogeneous High-performance Reconfigurable Computing

Submitted by Jason D. Bakos
November 15, 2015

Submitted by Jason D. Bakos

First International Workshop on Heterogeneous High-performance
Reconfigurable Computing (H2RC 2015)

in conjunction with Supercomputing 2015
Austin, TX, USA
Sunday, November 15, 2015

– Submission Deadline: August 15, 2015
– Acceptance Notification: September 15, 2015
– Camera-ready/Author Registration: April 15, 2015
– Workshop Date: November 15, 2015

With Exascale systems on the horizon at the same time that conventional
von-Neumann architectures are suffering from rising power densities, we
are facing an era with power, energy-efficiency, and cooling as
first-class constraints for scalable HPC. FPGAs can tailor the hardware
to the application, avoiding overheads of general-purpose
architectures. Leading FPGA manufacturers have recently made a
concerted effort to provide a range of higher-level, easier to use,
high level programming models for FPGAs, including the OpenCL
framework, which is already widely used by the HPC community for
heterogeneous computing. OpenCL is particularly appealing because it
offers the potential for portability to GPUs and Xeon Phi.

Such initiatives are already stimulating new interest within the HPC
community around the potential advantages of FPGAs over other
architectures in terms of both performance and energy consumption. With
this in mind, this will be the first workshop at SC to bring together
HPC and heterogeneous-computing researchers to demonstrate and share
experiences on how newly-available high-level programming models,
including OpenCL, are already empowering HPC software developers to
directly leverage FPGAs, and to identify future opportunities and needs
for research in this area.

Submissions are solicited which explore the state of the art in the use
of FPGAs in heterogeneous high-performance compute architectures and,
at a system level, in data centers and supercomputers. FPGAs may be
considered from either or both the distributed, parallel and composable
fabric of compute elements or from their dynamic reconfigurability. We
especially encourage submissions which not only consider the
implementation of algorithms and applications in FPGAs but concretely
relate this to the heterogeneous compute model consisting of
differently functioned cooperating compute elements and the overall
impact of such architectures on the compute capacity, cost and power
efficiency, and computational capabilities of data centers and
supercomputers. Submissions may report on theoretical or applied
research, implementation case studies, benchmarks, standards, or any
other area that promises to make a significant contribution to our
understanding of heterogeneous high-performance reconfigurable
computing and will help to shape future research and implementations in
this domain. A non-comprehensive list of potential topics of interest
is given below:

1. FPGAs in the Cloud and Data Center: FPGAs in relation to challenges
to Cloud/Data Center/Supercomputing posed by the end of Dennard scaling

2. Cloud and Data Center Applications: Exploiting FPGA compute fabric to
implement critical cloud/HPC applications

3. Leveraging Reconfigurability: Using reconfigurability for new
approaches to algorithms used in cloud/HPC applications

4. Benchmarks: Compute performance and/or power and cost efficiency for
cloud/HPC with heterogeneous architectures using FPGAs

5. Implementation Studies: Heterogeneous Hardware and Management

6. Programming Languages/Tools/Frameworks for FPGA Heterogeneous

7. Future-gazing: New Applications/The Cloud Enabled by FPGA
Heterogeneous Computing, Evolution of Computer Architecture in
relation to FPGA Heterogeneous Computing

8. Community Building: Standards, consortium activity, open source,
education, initiatives to enable and grow FPGA Heterogeneous

Prospective authors are invited to submit original and unpublished
contributions as 8-page papers. All contributions must be submitted
electronically in ACM SIG Proceedings format via the following link:

All papers selected for this workshop will be peer-reviewed. The
authors of accepted papers will be scheduled to present their work in
one of the two lightning talks sessions. Workshop proceedings will be
made available online and authors will retain their copyright.

Workshop Organizers:
Michaela Blott, Xilinx
Michael Leventhal, Xilinx
Michael Lysaght, ICHEC
Torsten Hoefler, ETH Zurich
Kevin Skadron, University of Virginia
Jason D. Bakos, University of South Carolina

Technical Program Co-Chairs:
Deming Chen, UIUC
Kees Vissers, Xilinx Research

Program Committee:
Junwei Bao, Baidu
Michaela Blott, Xilinx
Paul Chow, University of Toronto
Carl Ebeling, Altera
Hans Eberle, NVIDIA
Tarek El-Ghazawi, George Washington University
Wu Feng, Virginia Tech
Georgi Gaydadjiev, Maxeler
Alan George, University of Florida
Christoph Hagleitner, IBM
Martin Herbordt, Boston University
H. Peter Hofstee, IBM Research, Austin
Miriam Leeser, Northeastern University
Wayne Luk, Imperial College
Walid Najjar, University of California Riverside
Viktor Prasanna, University of Southern California
Desh Singh, Altera
Mitch Wright, HP

Now Available: Videos of the 2015 Workshop on Computer Architecture Research Directions (CARD)

Submitted by Joshua J. Yi

Submitted by Joshua J. Yi

Videos of the mini-panel debates in the fourth Workshop on Computer
Architecture Research Directions are available on YouTube:

Mini-Panel #1 — Open-Source vs. Proprietary ISAs:
Mini-Panel #2 — FPGAs vs. GPUs for Datacenters:
Mini-Panel #3 — Impact of Future Technologies: