Call for Papers: IEEE Micro General Interest 2016

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/2015-cfp—general-interest

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/2015-cfp—general-interest

IEEE Micro General Interest 2015

IEEE Micro seeks general-interest submissions for publication in upcoming
2015 issues. The submissions should present the design, performance, or
application of microcomputer and microprocessor systems. Summaries of work
in progress and descriptions of recently completed work are most welcome,
as are tutorials and position statements.

IEEE Micro is a bimonthly magazine of the IEEE Computer Society that
reaches an international audience of computer designers, system
integrators, and users. IEEE Micro publishes 6 to 8-page papers that are
slightly less technical and less quantitative than top-conference and
archival journal papers, while being insightful, slightly more
qualitative, with a high tutorial value, and up to date with current
trends. IEEE Micro attracts a broad readership among both academics and
practitioners who want to keep up with new results and trends in the field
of computer architecture.

Areas of interest include, but are not limited to:
– Processor, memory, and storage systems architecture
– Parallel and multicore systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Heterogeneous and accelerator-based architectures
– Neuromorphic computing architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems
– Design of high-performance and low-power chips

SUBMISSION PROCEDURE:
Log onto IEEE CS Manuscript Central
(https://mc.manuscriptcentral.com/micro-cs) and submit your manuscript.
Please direct questions to the IEEE Micro magazine assistant
(micro-ma@computer.org) regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and
PDF. Manuscripts should not exceed 5,000 words including references, with
each average-size figure counting as 150 words toward this limit. Please
include all figures and tables, as well as a cover page with author
contact information (name, postal address, phone, fax, and e-mail address)
and a 200-word abstract. Submitted manuscripts must not have been
previously published or currently submitted for publication elsewhere, and
all manuscripts must be cleared for publication. All previously published
papers must have at least 30% new content compared to any conference (or
other) publication. Accepted articles will be edited for structure, style,
clarity, and readability. For more information, please visit the IEEE
Micro Author Center
(http://www2.computer.org/portal/web/peerreviewmagazines/acmicro).
The submission site is continuously open. Papers of general interest
appear in upcoming issues as space allows, or are grouped in the Nov/Dec
2015 issue.

QUESTIONS?
Contact the Editor-in-Chief, Lieven Eeckhout, at lieven.eeckhout@ugent.be.

Call for Papers: IEEE Micro Top Picks 2016

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/top-picks-2016—call-for-papers

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/top-picks-2016—call-for-papers

Micro’s Top Picks from the Computer Architecture Conferences
Special Issue of IEEE Micro
May/June 2016
 

Paper submission deadline: October 16, 2015, 6:00 pm EDT
Submission website: https://toppicks16.egr.duke.edu/

IEEE Micro will publish its yearly “Micro’s Top Picks from the Computer
Architecture Conferences” as its May/June 2016 issue. This issue collects some
of this year’s most significant research papers in computer architecture based
on novelty and potential for long-term impact. Any computer architecture paper
(not a combination of papers) published in the top conferences of 2015
(including MICRO-48) is eligible. IEEE Micro also distinguishes a number of
papers as IEEE Micro Top Pick Honorable Mentions.

The Top Picks committee will attempt to recognize those significant and
insightful papers that have the potential to influence the work of computer
architects for years to come.

SUBMISSION GUIDELINES:
To simplify reviewing, there is a mandatory format for submissions. Please
concatenate the following two documents into a single PDF file that is
submitted.

1. A three-page, two-column document using 10-point type. The first two pages
should summarize the paper. The third page should argue for the potential of
the work to have long-term impact, clearly articulating why and how it will
influence other researchers and/or industry.

2. The final version of the original conference paper.

Submissions that do not follow this format will not be reviewed. The first page
of the submission should contain the names of the authors with a footnote that
contains the title of the original conference paper, with the full name of the
conference and date of publication.

Upon acceptance, authors will receive further instructions on how to prepare
final papers that conform to IEEE Micro’s guidelines (5000 words for the final
paper in IEEE Micro).

IMPORTANT DATES:
Submission Deadline: October 16, 2015 6:00 pm EDT
Author notification: January 29, 2016
Final papers due: February 19, 2016
Publication date: May/June 2016

ORGANIZERS:
Top Picks Guest Editors (and Co-Chairs of the Selection Committee):
Milo Martin, Google
Dan Sorin, Duke University

Program Committee:
Tor Aamodt, University of British Columbia
Sarita Adve, University of Illinois
Murali Annavaram, University of Southern California
Rajeev Balasubramonian, University of Utah
Ramon Canal, Universitat Politecnica de Catalunya
Fred Chong, University of Chicago
Joe Devietti, University of Pennsylvania
Sandhya Dwarkadas, Rochester University
Joel Emer, MIT/Nvidia
Erik Hagersten, Uppsala University
James Hoe, Carnegie Mellon University
Hillery Hunter, IBM Research
Martha Kim, Columbia University
Benjamin Lee, Duke University
Hsien-Hsin Lee, TSMC
Tong Li, Lenovo
Debbie Marr, Intel
Kathryn McKinley, Microsoft Research
Albert Meixner, Google
Trevor Mudge, University of Michigan
Satish Narayanasamy, University of Michigan
Mark Oskin, University of Washington
Ravi Rajwar, Intel
Partha Ranganathan, Google
Vijay Janapa Reddi, University of Texas – Austin
Daniel Sanchez, MIT
Karu Sankaralingam, University of Wisconsin
Karin Strauss, Microsoft Research/University of Washington
Ed Suh, Cornell University
Michael Taylor, University of California, San Diego
Tom Wenisch, University of Michigan
Greg Wright, Qualcomm
Pen-Chung Yew, University of Minnesota

Now Available: XPS Workshop Report

Submitted by Benjamin Lee

Submitted by Benjamin Lee

Information technology is quickly approaching an inflection point at
which previously reliable drivers of computational capability encounter
fundamental challenges. These challenges motivate coordinated
innovation across the hardware stack, re-thinking abstraction layers
for performance, efficiency, and scalability. Investigators from the
National Science Foundation’s program on Exploiting Parallelism and
Scalability (XPS) developed this report to propose strategic research
directions in electrical engineering and computer science.

Report: http://people.duke.edu/~bcl15/workshop/xps15/XPSWorkshopReport.pdf

Workshop details: http://people.duke.edu/~bcl15/workshop/xps15/