Call for Applications: CRA-W Grad Cohort Workshop

Submitted by Kathryn S McKinley

Submitted by Kathryn S McKinley

CRA-W Grad Cohort Workshop
San Diego, CA, USA
April 15-16, 2016

The CRA-W Grad Cohort Workshop was initiated in 2004, and this year is
generously funded by SIGARCH and sponsors from industry, academia, the
National Science Foundation, and the computing community. The Workshop aims
to increase the success and participation women in computing research by
building and mentoring nationwide communities of women through their
graduate studies.

At the Grad Cohort Workshop, CRA-W welcomes new women graduate students
in their first 3 years of graduate school into the community of computing
researchers and professionals by providing them with a broad range of career
strategies and role models.

Students will meet for two days with 20 to 25 senior computing researchers and
professionals, who will share graduate school survival skills, as well as more
personal information and insights about their experiences. The rewards of a
research career will be emphasized. The workshop will include a mix of formal
presentations and informal discussions and social events. Through this
workshop, students will be able to build mentoring relationships and develop
peer networks that will form the basis for ongoing activities during their
graduate careers.

This is a great opportunity for graduate students to be inspired to continue
on their path of computing studies and engage in the research community.

The application deadline is November 30, 2015. To apply visit the Grad Cohort
2016 Event at

If you have any questions or comments regarding our programs or becoming
more involved with our community, please feel free to e-mail

Call for Participation: CWWMCA 2015

Submitted by Min LI
December 6 to December 9, 2015

Submitted by Min LI

Career Workshop for Women and Minorities in Computer Architecture (CWWMCA 2015)
in conjunction with MICRO 2015
Waikiki, Hawaii, USA
December 6, 2015

The CWWMCA Workshop brings together women and under-represented minorities
in academia, industry, and government to promote the recruitment, retention and
progression of women and under-represented groups with research interests in
computer architecture.

The workshop highlights emerging and hot topics in computer architecture, and
provides opportunities for cross-disciplinary research, networking, and career
advice. The program includes a mix of technical presentations and panel
sessions by academic and industry leaders, as well as informal activities to
provide mentoring for students as they get started in their careers. The
workshop also includes a research poster session.

The workshop is generously sponsored by NSF, ACM SIGMICRO, IBM Research
and the MICRO conference.

Thanks to our sponsors, this workshop will be free of charge for the
participating  target demographic of women and minority participants
under-represented in our field, and they will be directly reimbursed for
their registration fees.

Travel grants are available for students and junior faculty/researchers.

For any questions, please contact us at

Call for Papers: FCCM 2016

Submitted by Jason D. Bakos
May 1 to May 3, 2016

Submitted by Jason D. Bakos

24th International IEEE Symposium on Field-Programmable
Custom Computing Machines (FCCM 2016)

Washington D.C., USA
May 1-3, 2016

– Full Paper Submission Deadline: January 5, 2016
– Short Paper Submission Deadline: January 12, 2016
– Notification of Acceptance: March 1, 2016
– Camera-ready Copy: March 29, 2016
– Early Registration Deadline: March 29, 2016

The IEEE Symposium on Field Programmable Custom Computing Machines (FCCM)
is the original and premier forum for presenting and discussing new research
related to computing that exploits the unique features and capabilities of
FPGAs and other reconfigurable hardware. For 24 years, FCCM has been the
place to present papers on architectures, tools, and programming models for
field programmable custom computing machines and applications that use such

Papers are solicited on the following topics related to Field Programmable
Custom Computing Machines (FCCMs):

1) Abstractions, Architectures, and Programming Models:
– Novel architectural abstractions
– Architectures for high performance and/or low power computing
– New spatial architectures built from components different than traditional
– Security enhancements for reconfigurable computing

2) Languages and Compilers:
– New languages and design frameworks for spatial or heterogeneous
– Tools to make run-time reconfiguration more accessible to application
– Compilation and CAD techniques for reconfigurable and spatial
computing systems

3) Run-Time Systems and Run-Time Reconfiguration:
– Techniques for virtualizing reconfigurable hardware
– Run-time management of reconfigurable hardware
– Fault tolerance for reconfigurable hardware
– Use of reconfigurability to build evolvable or adaptable computing systems
– Novel uses of run-time reconfiguration in application-specific systems
– Implications of run-time reconfiguration on security

4) Applications:
– Applications built using new high level synthesis technologies
– Data center applications
– Applications that utilize reconfigurable technology for performance and
– Comparison of application implementations on different spatial hardware

FCCM will accept 8-page papers for oral presentation and 4-page short papers
for short oral and poster presentation. All submissions should be written in
the English language. An online submission link will be available on the FCCM
website in late December. Papers should use the formatting template linked at
the FCCM website.

Later Deadline for Short Paper Submission:
Authors are encouraged to submit preliminary work using the 4-page format.
This category is intended for new projects and early results. These
submissions will be accepted one week later than the 8-page papers.

FCCM uses a double blind reviewing system. Manuscripts must not identify
authors or their affiliations. When referencing their own papers, authors are
encouraged to do so in a way in which they do not identify themselves as
authors. References that clearly identify the authors (for example, “We build
on our previous work…”) should be shown as “Removed for blind review”.
Papers that identify authors will not be considered.

FCCM 2015 will continue the tradition of having a best paper award. We will
also invite the authors of the best papers to extend their work to be
considered for publication in a special section of ACM’s Transactions on
Reconfigurable Technology and Systems (TRETS) for FCCM 2015. Send in your
best work for consideration!

General Chair: Matthew French, University of Southern California ISI
Program Chair: Jason D. Bakos, University of South Carolina
Finance Chair: Ken Eguro, Microsoft Research
Publications Chair: Greg Stitt, University of Florida
Sponsorship Chair: Jan Gray, Gray Research, LLC
Publicity Chair: Kyle Rupnow

Please direct questions about the program and submission of papers to
Jason D. Bakos at

Call for Papers: TRANSACT 2016 (Deadline extended)

Submitted by Stephan Diestelhorst
November 28, 2015

Submitted by Stephan Diestelhorst

11th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2016)

Due to popular demand, we have extended the TRANSACT 2016 paper submission
deadline by two weeks to 28 Nov 2015! TRANSACT 2016 will be held in
conjunction with PPoPP 2016, HPCA 2016, and CGO 2016 in Barcelona, Spain
on Sat, 12th Mar 2016. TRANSACT is _the_ venue to discuss new work on
transactional memory and related technologies across the compute stack,
of course including Computer Architecture.

Additional information along with the full CfP available on the workshop web site.

Call for Papers: Computing Frontiers 2016

Submitted by Jianbo Dong
May 16 to May 18, 2016

Submitted by Jianbo Dong

ACM International Conference on Computing Frontiers 2016 (CF’16)
Como, Italy
May 16 – 18, 2016

Submissions deadline: January 15, 2016
Notification: March 11, 2016
Camera-Copy Papers Due: March 25, 2016

Computing Frontiers is a gathering for people to share and discuss such work,
and it focuses on a wide spectrum of advanced technologies and radically new
solutions relevant to the development of a spectrum of computer systems, from
embedded devices to supercomputers and data centers.

We seek contributions that push the envelope in a wide range of computing
topics, from more traditional research in architecture and systems to new
technologies and devices. We seek contributions on novel computing paradigms,
computational models, algorithms, application paradigms, development
environments, compilers, operating environments, computer architecture,
hardware substrates, memory technologies, and smarter life applications. We are
also interested in emerging fields that may not fit within traditional

– Algorithms and Models of Computing: approximate and inexact computing,
quantum and probabilistic computing

– Biological Computing Models: brain computing, neural computing, computational
neuroscience, biologically-inspired architectures

– Limits on Technology Scaling and Moore’s Law: defect- and variability-
tolerant designs, graphene and other novel materials, nanoscale design,
optoelectronics, dark silicon

– Uses of Technology Scaling: 3D stacked technology, challenges of manycore
designs, accelerators, PCM’s, novel memory architectures, mobile devices

– Embedded and Cyber-Physical systems: design space exploration, ultra-low
power designs, energy scavenging, reactive and realtime systems, reconfigurable
and self-aware systems, sensor networks, internet of things, wearables

– Big Data Analytics: high performance data analytics, machine and deep
learning, data search and representation, architecture and system design

– Large-scale system design: homogeneous and heterogeneous architectures,
runtimes, networking technologies and protocols, Cloud and Grid systems,
datacenters, exa-scale computing, power- and energy management

– Compiler technologies: novel techniques to push the envelope on new
technologies, applications, hardware/software integrated solutions, domain
specific languages, advanced analysis, high-level synthesis

– Security: methods, system support, and hardware for protecting against
malicious code, real-time implementation of security algorithms and protocols,
quantum and post-quantum cryptography, advanced persistent threats, cyber and
physical attacks and countermeasures

– Computers and Society: education, health and cost/energy-efficient design,
smart cities, emerging markets

– Interdisciplinary Applications: applications that bridge multiple disciplines
in interesting ways

Computing Frontiers 2016 also encourages position papers, trend
papers, and poster submissions on topics of interest.

Authors are invited to submit full papers, position papers, trend papers, and
poster abstracts to the main conference. Papers must be submitted through the
conference paper submission site. Authors will declare in advance to which
category they are submitting through the submission site.
Submission site:

Full papers are allowed up to eight (8) double-column pages in standard ACM
conference format. Authors, however, will be able to buy up to two (2) extra
pages at 100 Euro per page. Position and trend papers should be at least two
(2) pages and not exceed four (4) pages in the same format. Poster abstracts
should be at least two (2) pages and not exceed four (4) pages in the same
format. These limits include figures, tables, and references. Our review
process is double-blind. Thus, please remove all identifying information from
the paper submission (and cite your own work in the third person). Authors of
interesting work not mature enough for an oral presentation may be offered the
option of presenting their work as posters.

Position papers, trend papers, and posters will be published in the
proceedings and in the ACM Digital Library (note that authors of these works
retain their copyright rights to publish more complete versions later).

The best papers from the Computer Frontiers Conference and Workshops will be
invited in special issues of IJPP or PARCO.

As per ACM guidelines, at least one author of an accepted paper is required to
register for the conference.

General Chairs:
Gianluca Palermo, Politecnico di Milano, IT

Program Chairs:
Antonino Tumeo, PNNL, US
Hubertus Franke, IBM Research, US

Finance Chair:
Peter Zinterhof, University of Salzburg, AT

Local Arrangements Chair:
Vittorio Zaccaria, Politecnico di Milano, IT

Workshop Chairs:
Francesca Palumbo, University of Sassari, IT
Francesco Regazzoni, ALARI, CH

Publications Chair:
Carlo Galuzzi, Maastricht University, NL

Publicity Chairs:
Maurizio Palesi, KORE University, IT
Jianbo Dong, Chinese Academy of Sciences, CN

Web Chair:
Kristian Rietveld, Leiden University, NL

Steering Committee:
Monica Alderighi, INAF, IT
Claudia Di Napoli, ICAR-CNR, IT
Hubertus Franke, IBM, US
Diana Franklin, University of California at Santa Barbara, US
Georgi Gaydadijev, Maxeler, GB
Alexander Heinecke, Intel Parallel Computing Lab, US
Paul Kelly, Imperial College, GB
Sally A. McKee, Chalmers University of Technology, SE
Krishna Palem, Rice University, US / Nanyang Technological University, SG
Francesca Palumbo, University of Sassari, IT
Valentina Salapura, IBM, US
Pedro Trancoso, University of Cyprus, CY
Carsten Trinitis, Technische Universität München, DE
Eli Upfal, Brown University, US
Josef Weidendorfer, Technische Universität München, DE

Call for Participation: Tutorial on Building Online Power Models from Real Data

Submitted by Stephan Diestelhorst
December 5, 2015

Submitted by Stephan Diestelhorst

Building Online Power Models from Real Data
held at MICRO 2015
Waikiki, Hawaii
December 5, 2015

In this hands-on, interactive tutorial, you will learn how to efficiently
build accurate, run-time power models using real hardware platforms using a
specially built software tool. Starting from the basics of how power is
consumed in a modern system-on-chip through static and dynamic power in the
underlying transistors, we show how activity, voltage and frequency affect the
power consumption.

We will then let you play with a board that we have prepared to be easy to
work with and walk you through practicalities, such as workload selection and
how to get activity information. With the basics from the first section, you
will be able to build your own power model for the test platform quickly.

Once you have built a simple power model for your test board, we will
introduce a surprise workload which we will then use to put the generated
power models through a real-life test: running a workload that was not
anticipated at model construction time. We will even give out prizes for
the ones closest to the real power consumption.

Call for Papers: Sensor to Cloud Architectures Workshop

Submitted by Govind Sreekar Shenoy
March 13, 2016

Submitted by Govind Sreekar Shenoy

Sensor to Cloud Architectures Workshop (SCAW-2016)
in conjunction with HPCA 2016
Barcelona, Spain
March 13, 2016

Paper submission deadline: January 8, 2016 (23:59 PST)
Author notification: January 18, 2016
Final paper submission: February 19, 2016
Workshop: March 13, 2016

The computer industry is witnessing an inflection point – ‘Internet of things
combined with Cloud Analytics’ – which has implications from end (sensor
devices) to end (cloud architectures). Many technologies come together
contributing to this major inflection point: Computing platforms getting
smaller (e.g. handheld devices, wearables), richer (e.g. image and language
understanding) and broader (i.e. reaching the masses via Internet of Things).
Sensors operating in constrained environments connected through intelligent
gateways and cloud backend creates a very complex environment for the
operators, system integrators, and developers of this new emerging technology.
Discovering and managing sensor devices; collecting, cleaning and storing
discoverable data; normalizing, aggregating and analyzing the data for insights
and actions; managing the security and privacy of the data, enforcing the
access privileges and trusted execution environments – all these are required
to make this revolution happen.

The research challenges in IoT platforms are multi-fold:
– providing rich functionality and wider power/performance range for sensor devices
– attempting to cover a broad range of applications that can be migrated
from cloud to gateways and sensor devices
– enabling a scalable and modular cloud architecture that provides the
required real-time and uptime capabilities
– providing a rich software programming environment that eases the challenge
of developing applications on end to end platforms consisting of elements
ranging from sensors to gateways to cloud.

The goal of this workshop is to bring together academic researchers and
industry practitioners to discuss future IoT sensor-to- cloud architectures
including sensors, gateways and cloud architectures.

Topics of interest include, but are not restricted to, the following:

1) Sensors, Actuators, Gateway & Controllers Architectures:
– Architectures for wearable and IOT devices
– Heterogeneity in Cores, Frequency, Cache, Memory
– Power, Performance, Energy optimizations
– SoCs, CPU/GPU, CPU/GPGPU architectures
– Ultra-Low Power Core Micro-architectures
– Fabrics / Network-on-chip, Cache/Memory Hierarchies
– HW Support for Heterogeneity, Programmability, Modularity
– Simulation / Emulation Methodologies
– Protocols and abstraction layers (MQTT, CoAP, REST, …)

2) Cloud Architecture:
– Data Center Architectures for IoT
– Edge/Fog computing, Dynamic Cloud-gateway-device offloads
– Workload partitioning between heterogeneous cores and accelerators
– BigData Frameworks (Hadoop, Spark, Flink, …)
– Heterogeneous Datacenters (FPGA, GPU, Accelerators)
– Machine Learning Algorithms & Applications, Graph processing,
Deep Neural Networks
– Batch, streaming and distributed Analytics
– Design Patterns and Application Programming frameworks

3) Emerging Workloads and Use cases:
– Wearable and IOT use cases and workloads
– Speech/Image recognition and understanding, Cognitive computing
– Personal Assistants, Predictive/Prescriptive Analytics, Robotics
– Workload Analysis for power/performance/energy optimization and
– Performance Monitoring and Simulation, Architecture analysis

4) Novel Accelerator Designs:
– Specialized Accelerator Architectures and Designs
– Machine Learning, Neural Network and Graph Processing accelerators
– Domain-Specific Programmable/Configurable Accelerators
– Accelerator Interfaces for Programmability
– Development Environments for Accelerator Design

Interested authors are encouraged to submit extended abstracts (1-2 pages)
or short papers (6 pages) by email to the organizing chairs. The deadline for
submission is January 8, 2016.

Ramesh Illikkal, Intel
Ravi Iyer, Intel
Murali Emani, University of Edinburgh
Govind Sreekar Shenoy, University of Edinburgh

Call for Papers: HARSH 2016

Submitted by Augusto Vega
March 12, 2016

Submitted by Augusto Vega

Workshop on Highly-Reliable Power-Efficient Embedded Designs (HARSH 2016)
in conjunction with HPCA, CGO, and PPoPP 2016
Barcelona, Spain
March 12, 2016

– Submission deadline: Jan 22, 2016
– Notification of acceptance: Feb 8, 2016
– Final paper submission: Feb 26, 2016
– Workshop date: Mar 12, 2016

HARSH 2016 will provide a unique forum for the discussion of the challenges in
the design and operation of harsh environment-capable embedded processors.

Nowadays, embedded chips are deployed almost everywhere, from mobile phones to
on-board electronics in automobiles and satellites. Different from
conventional microprocessor designs, the operation conditions of embedded
processors are severely constrained by the environment. For example, in
aerospace applications, the computer installed on Mars rover “Curiosity” has
to tolerate extreme space radiation and temperatures, operate at low power,
and provide enough computation capability to perform mission-critical tasks.
Embedded designs for Unmanned Aerial Vehicles (UAVs) also encounter extremely
challenging design requirements. Despite their tight power budget, UAV chips
demand significant throughput for real-time high-speed image processing. In
the context of oil and gas exploration and extraction, embedded processors can
be found even on the drill string itself, to process sensor inputs in real
time while withstanding high temperatures and humidity levels.

To guarantee reliability across these drastically diverse environments, the
design and operation of embedded processors should not be solely confined to
the chip but traverse different layers in the computing system, involving
firmware, operating system, applications, as well as power management units
and communication interfaces. The goal of HARSH 2016 is to facilitate the
exchange of the latest ideas, insights, and knowledge related to all critical
aspects of new-generation harsh environment-capable embedded processors,
including micro-architectural approaches, cross-stack hardware/software
techniques, and emerging challenges and opportunities. We hope to attract a
group of interdisciplinary researchers from academia, industry, and government
research labs.

In addition to the presentation of selected paper submissions, keynote
speakers will be invited to kick-off the workshop sessions and a “Best Paper”
award will be presented at the conclusion of the workshop. To encourage
discussion between participants, HARSH 2016 will organize dedicated programs
for discussion between presenters and the audience.

Topics of interest include but are not limited to:

(1) Architecture design and implementation for highly-reliable power-efficient
embedded processors:
– Architectural approaches for reliability assurance under very-low power
– Availability, soft-error tolerance and recovery issues
– Highly-reliable cache/memory hierarchies
– Massive heterogeneous processing capabilities
– Power management techniques
– Very-low power, reliable real-time processing
– Specialized accelerator architectures and unique designs
– Reusable and/or reconfigurable embedded designs
– Packaging and cooling

(2) Cross-stack hardware/software techniques:
– Cross-stack approaches for reliability assurance under very-low power
– Reliability- and power-aware operating systems, compilers, workload
managers, firmware and other software
– Workload analysis and optimization for reliable low-power embedded

(3) Applications:
– Aerospace: unmanned aerial vehicles (UAVs), planetary rovers and space
probes, satellites, avionic systems, etc.
– Medical support: lifesaving monitors, portable medical devices, high-end
imaging systems, etc.
– Oil and gas exploration and extraction
– Aerial surveillance
– Disaster search, rescue, and relief
– Novel applications for highly-reliable low-power embedded chips

Papers reporting original research results pertaining to the above and related
topics are solicited. Full paper manuscripts must be in English of up to 6
pages (using the IEEE two-column format). The on-line submission site is
EasyChair. If web submission is not possible, please contact the program
co-chairs for alternate arrangements.

– Augusto Vega (IBM Research)
– Xuan (Silvia) Zhang (Washington University in St. Louis)
– David Brooks (Harvard University)
– Alper Buyuktosunoglu (IBM Research)
– Pradip Bose (IBM Research)

Call for Papers: TRANSACT 2016

Submitted by Stephan Diestelhorst
November 14, 2015

Submitted by Stephan Diestelhorst

11th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2016)

The paper deadline for TRANSACT 2016 is approaching: 14 Nov 2015. TRANSACT
2016 will be held in conjunction with PPoPP 2016, HPCA 2016, and CGO 2016 in
Barcelona, Spain on Sat, 12th Mar 2016. TRANSACT is _the_ venue to discuss new
work on transactional memory and related technologies across the compute stack,
of course including Computer Architecture.

Additional information along with the full CfP available at the web site.

Tool Release: SASSI – An Instrumentation Tool for Profiling GPGPU Applications

Submitted by Mark Stephenson

Submitted by Mark Stephenson

SASSI: An Instrumentation Tool for Profiling GPGPU Applications

We at NVIDIA Research have developed and released a compiler-based
instrumentation framework for NVIDIA’s GPUs [Flexible Software Profiling of
GPU Architectures, ISCA 2015]. The tool, which is similar in many ways to its
CPU counterparts such as Pin, allows users to measure or modify GPGPU
programs by injecting instrumentation code at select points in a program.

The tool is called SASSI, which stands for SASS Instrumentor, where SASS is
NVIDIA’s name for its native ISA. SASSI enables the collection of
user-directed, fine-grained data from GPU kernels running at near hardware
speeds. The tool is available on GitHub at

We are also conducting a hands-on tutorial at MICRO-48 to explain SASSI’s
usage and implementation. The tutorial will walk participants through its
usage by designing several targeted instrumentation libraries from scratch.
Participants will run the instrumentation libraries on real-world workloads
and GPUs. This tutorial will be of interest to computer architects exploring
GPGPU architectures and applications as well as those interested in a deeper
understanding of parallel workloads. SASSI can be used across NVIDIA’s most
recent GPU architectures (Fermi, Kepler, and Maxwell) and works on both
Windows and Linux.

We have organized the tutorial into four 1-hour sessions. Each session will
begin with a short lesson and end with interactive exercises. The lesson will
provide background information relevant to completing the exercises. There
are no prerequisites for the tutorial. Bring a laptop with an ssh client
installed if you want to interactively work through the examples.

Tutorial materials are available at: