Call for Papers: Workshop on Cognitive Architectures

Submitted by Karthik Swaminathan
April 2, 2016 at 13:00

Submitted by Karthik Swaminathan

The 2nd Workshop on Cognitive Architectures (CogArch 2016)
co-located with ASPLOS 2016
Atlanta, Georgia, USA
April 2, 2016

Submission deadline: Feb 15, 2016
Notification: Feb 29, 2016
Camera ready deadline: Mar 30, 2016

Recent advances in Cognitive Computing Systems (as evidenced by innovations
like Watson from IBM and self-driving cars from Google), coupled with
neurally-inspired hardware designs (such as the IBM True North chip), have
spawned new research and development activity in machine learning,
neuromorphic and other brain-inspired computing models, and architectures for
efficient support of complex tasks in computer vision, speech recognition and
artificial intelligence. The proliferation of mobile computing platforms, IoT
and cloud support features thereof have opened up exciting new opportunities
for real-time, mobile (distributed or swarm-driven) cognition. This half-day
workshop solicits formative ideas and new product offerings in this general

Topics of interest include (but are not limited to):
– Algorithms in support of cognitive reasoning: recognition, intelligent
search, diagnosis, inference and informed decision-making.
– Swarm intelligence and distributed architectural support; brain-inspired and
neural computing architectures.
– Accelerators and micro-architectural support for cognitive computing.
– Cloud-backed autonomics and mobile cognition: architectural and OS support
– Resilient design of distributed (swarm) mobile cognitive architectures.
– Energy efficiency, battery life extension and endurance in mobile, cognitive
– Case studies and real-life demonstrations/prototypes in specific application
domains: e.g. Smart homes, connected cars and UAV-driven commercial services,
as well as applications of interest to defense and homeland security.

The workshop shall consist of short presentations by authors of selected
submissions. In addition, it will include invited keynotes by eminent
researchers from industry and academia as well as interactive panel
discussions to kindle further interest in these research topics. Submitted
papers will be reviewed by a workshop program committee, in addition to
the organizers. Submissions are limited to 6 pages, including references,
with same formatting guidelines as main conference.

Karthik Swaminathan, Augusto Vega, Alper Buyuktosunoglu, Pradip Bose –
IBM T.J Watson Research Center
Vijaykrishnan Narayanan – Pennsylvania State University

Call For Papers: Workshop on Multicore and Rack-scale Systems

Submitted by Boris Grot
February 5, 2016

Submitted by Boris Grot

Workshop on Multicore and Rack-scale Systems (MARS)
co-located with EuroSys 2016
London, UK
April 18, 2016

Submission deadline: February 5, 2016
Acceptance Notification: March 9, 2016
Workshop date: April 18, 2016

Present and future multi-core architectures pose a variety of challenges for
system developers: non-cache-coherent memory, heterogeneous processing cores
and the exploitation of novel architectural features, such as systems-on-chip
(SoCs), distributed switching fabrics, silicon photonics, and programmable
hardware. In the near future, we expect to see “rack-scale computers” with
1,000s of cores and terabytes of memory, connected with bandwidth and latency
comparable to today’s smaller-scale NUMA servers.

MaRS 2016 is a forum for researchers in the hardware, networking, storage,
operating systems, language runtime and virtual machine communities to present
their experiences with and discuss innovative designs and implementations for
these new architectures.

Topics of interest include, but are not limited to:
– novel multi-core and rack-scale operating system designs,
– System-on-chip (SoC) and Network-on-chip (NoC) designs,
– runtime systems and programming environments for future hardware,
– low-latency and optical networking,
– OS or runtime support for heterogeneous processing cores,
– non-cache-coherent shared memory,
– scheduling on many-core and rack-scale architectures,
– programmable hardware,
– energy efficiency, fault tolerance and resource management on
future multi-core and rack-scale architectures,
– rack-scale storage,
– performance evaluation of emerging hardware,
– architectural support for systems-level software,
– case studies of system-level software design for current or future
multi-core and rack-scale hardware, and
– applications for and experiences with multi-core and rack-scale

Authors are invited to submit original and unpublished work that exposes a
new problem, advocates a specific solution, or reports on actual experience.
Papers should be submitted using the standard two-column ACM SIG proceedings
or SIG alternate template, and are limited to 5 pages (including everything
except references). Additional pages can be used for references if required.
Papers that violate the submission guidelines may be rejected without
consideration of their merit.

Final papers will be made available to participants electronically at the
meeting, but to facilitate resubmission to more formal venues, no archival
proceedings will be published, and papers will not be sent to the ACM Digital
Library. Authors will be given the option of having their final paper
accessible from the workshop website. Authors of accepted papers will be
invited to give a talk at the workshop.

If you are interested in giving a talk at MaRS 2016, please submit a one-page
abstract instead of a full paper. Authors of accepted papers/talks will also
be invited to present a poster and/or demo in the EuroSys ’16 joint poster
session. Student speakers will be eligible to apply for EuroSys travel grants
to attend.

Boris Grot (University of Edinburgh)
Simon Peter (UT Austin)
Chris Rossbach (VMware and UT Austin)

Program Committee:
Mahesh Balakrishnan (Yale)
Antonio Barbalace (Virginia Tech)
Taesoo Kim (Georgia Tech)
Mark Oskin (University of Washington)
Mark Silberstein (Technion)
Cheng-Chun Tu (VMware)
John Wilkes (Google)
Bernard Wong (University of Waterloo)

Call for Papers: Workshop on Heterogeneous and Unconventional Cluster Architectures and Applications

Submitted by Federico Silla
August 16, 2016

Submitted by Federico Silla

5th International Workshop on Heterogeneous and Unconventional
Cluster Architectures and Applications (HUCAA 2016)

in conjunction with ICPP 2016
Philadelphia, PA, USA
August 16, 2016

Paper submission: March 21, 2016
Notification of acceptance: May 13, 2016
Camera-ready paper: June 3, 2016
Workshop: August 16, 2016

The workshop on Heterogeneous and Unconventional Cluster Architectures and
Applications gears to gather recent work on heterogeneous and unconventional
cluster architectures and applications, which might have an impact on future
mainstream cluster architectures. This includes any cluster architecture that
is not based on the usual commodity components and therefore makes use of
some special hard- or software elements, or that is used for special and
unconventional applications. In particular we call for GPUs and other
accelerators (Intel MIC/Xeon Phi, FPGA) used at cluster level. Even though
accelerators are already used pervasively, we still see many unconventional
and even disruptive uses of them.

Other examples of unconventional cluster architectures and applications
include virtualization, in-memory storage, hard- and software interactions,
run-times, databases, and device-to-device communication. We are in
particular encouraging work on disruptive approaches, which may show inferior
performance today but can already point out their performance potential. The
broad scope of the workshop facilitates submissions on unconventional uses of
hardware or software, gearing to gather ideas that are coming to life now and
not limiting them except for their context: clusters. Also, these proposals
may rather be reflective of a broader industry trend.

Topics of interest include any heterogeneous or unconventional cluster
architecture or application. Examples include, but are not limited to:
– Clustered GPUs, Xeon Phis or other accelerators
– Runtimes, resource management and scheduling for heterogeneous cluster
– Communication methods for distributed or clustered accelerators
– Energy-aware data movement techniques
– Energy efficiency at the cluster or node level
– New industry and technology trends and their potential impact
– High-performance, data-intensive, and power-aware computing
– Application-specific cluster and datacenter architectures
– Emerging programming paradigms for parallel heterogeneous computing
– Software cluster-level virtualization for consolidation purposes
– Hardware techniques for resource aggregation
– New uses of GPUs, FPGAs, and other specialized hardware

Submissions may not exceed 8 pages in PDF format including figures and
references, and must be formatted in the 2-column IEEE format. Submitted
papers must be original work that has not appeared in and is not under
consideration for another conference or journal. Work in progress is welcome,
but first results should be made available as a proof of concept. Submissions
only consisting of a proposal will be rejected. Please visit the workshop
website for additional details.

Workshop Co-Chairs:
– Federico Silla, Technical University of Valencia, Spain
– Holger Fröning, U. Heidelberg, Germany

Program Committee:
– Tarek Abdelrahman, U. Toronto, Canada
– José Luis Abellán, Catholic University of Murcia, Spain
– Olivier Aumage, INRIA, France
– José María Cecilia, Catholic University of Murcia, Spain
– Pierfrancesco Foglia, University of Pisa, Italy
– Basilio Fraguela, U. Coruna, Spain
– Efstratios Gallopoulos, University of Patras, Greece
– Marc Gonzalez, Universitat Politecnica de Catalunya, Spain
– Sascha Hunold, Technical University of Vienna, Austria
– Christos Kartsaklis, Oak Ridge National Lab, US
– Christoph Kessler, Linköping University, Sweden
– Tomàs Margalef, U. Autonoma Barcelona, Spain
– Gaspar Mora, Intel, US
– Thu D. Nguyen, U. Rutgers, US
– Dimitrios S. Nikolopoulos, Queen’s University, Belfast, UK
– Lena Oden, Argonne National Labs, US
– Alberto Ros, University of Murcia, Spain
– Dirk Pleiter, Research Center Jülich, Germany
– Alistar Rendell, Australian National University, Australia
– Etienne Riviere, University of Neuchatel, Switzerland
– Won Ro, Yonsei University, South Korea
– Antonio Robles, Technical University of Valencia, Spain
– Douglas Thain, U. Notre Dame, US
– Matthew Jacob Thazhuthaveetil, Indian Institute of Science, India
– Blesson Varghese, U. St Andrews, UK
– Shuangyang Yang, Louisiana State University, US

Steering Committee:
– José Duato, Technical University of Valencia, Spain
– Sudhakar Yalamanchili, Georgia Tech, US
– Ulrich Brüning, U. Heidelberg, Germany

Call for Papers: IEEE Micro Special Issue on Security

Submitted by jayvant anantpur

Submitted by jayvant anantpur

IEEE Micro Special Issue on Security

Guest Co-Editors:
Mohit Tiwari, The University of Texas at Austin
Todd Austin: University of Michigan, Ann Arbor

Submissions due: Feb 26, 2016
Publication date: Sept/Oct 2016

Secure, networked systems are the foundation on which the future
healthcare, finances, automotives, and other intelligent services will rest.
Currently deployed systems, from implanted medical devices to voting
machines to mobile phones and data centers, have all been shown to be
vulnerable, and new architectures are required to construct a trustworthy
computing infrastructure.

This Special Issue on Security seeks papers on a range of topics, including but
not limited to:

– Isolation and Access control, Virtualization
– Capabilities
– Information flow control
– Cryptographic primitives
– Side channel and physical access (power, EM, etc.) attacks and defenses
– Attestation and trusted/tamper-proof execution, enclaves, etc.
– Malware detection
– Network processors and deep packet analysis
– Accelerators for security analytics
– Introspection, debugging, root cause analysis
– Secure storage, e.g. using emerging non-volatile memories
– Programming languages and formal design tools for secure architectures
– Metrics and evaluation methodologies for secure architectures
– Secure architectures for domains such as voting machines, medical devices,
automotives, high assurance embedded systems, data centers, and IoT

Initial submissions due: Feb 26, 2016
Initial notifications: April 29, 2016
Revised papers due: May 20, 2016
Final notifications: June 10, 2016
Final versions due: June 24, 2016
Publication date: Sept/Oct 2016

Log onto IEEE CS Manuscript Central (
and submit your manuscript. Please direct questions to the IEEE Micro magazine
assistant (micro­ regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and PDF.
Manuscripts should not exceed 5,000 words including references, with each
average­-size figure counting as 250 words toward this limit. Please include
all figures and tables, as well as a cover page with author contact information
(name, postal address, phone, fax, and e­mail address) and a 200­-word
abstract. Submitted manuscripts must not have been previously published or
currently submitted for publication elsewhere, and all manuscripts must be
cleared for publication. All previously published papers must have at least 30%
new content compared to any conference (or other) publication. Accepted
articles will be edited for structure, style, clarity, and readability. For
more information, please visit the IEEE Micro Author Center.

Questions: Please contact Guest co-Editors Mohit Tiwari
( and Todd Austin (, or
Editor-in-Chief Lieven Eeckhout (

Call for Contributions: FPL 2016

Submitted by Kubilay Atasu
August 29 to September 2, 2016

Submitted by Kubilay Atasu

26th International Conference on Field-Programmable Logic and
Applications (FPL)

Lausanne, Switzerland
29th Aug – 2nd Sep, 2016

Abstract submission deadline: March 20, 2016
Paper submission deadline: March 27, 2016
Demo night, PhD forum, Workshops, and Tutorial submission deadline: May 8, 2016
Notifications: June 15, 2016 (approximate)
Final manuscript deadline: July 4, 2016

The International Conference on Field-Programmable Logic and Applications
(FPL) was the first and remains the largest conference covering the rapidly
growing area of field-programmable logic and reconfigurable computing.
During the past 25 years, many of the advances in reconfigurable system
architectures, applications, embedded processors, design automation methods
and tools were first published in the proceedings of the FPL conference
series. The conference objective is to bring together researchers and
practitioners from both academia and industry and from around the world.
FPL 2016 looks for contributions in the following areas:

Architectures and Technology
– FPGAs, GPUs and DSPs
– Heterogeneous datacentre/embedded computing
– Low power architectures
– Fault tolerant architectures
– Security and cryptography for FPGA Design
– 2.5D and 3D architectures
– Advanced on-chip interconnect technologies
– Analog and mixed-signal arrays
– Emerging technologies

Applications and Benchmarks
– Aerospace, automotive and industry automation
– Bioinformatics & medical systems
– Communications, software defined networking and Internet-of-Things
– Finance, HPC and database acceleration
– Big data analytics
– Embedded & cyber physical systems
– Signal processing and SDR
– Benchmarks for FPGA designs

Design Methods and Tools
– System-level design tools
– High-level synthesis
– Hardware / software co-design
– Logic optimization and technology mapping
– Optimizations for power efficiency
– Packing, placement and routing
– Rapid prototyping and emulation
– Testing, debugging and verification
– Open-source tools

Self-aware and Adaptive Systems
– Self-awareness in FPGA-based systems
– Self-adaptive architectures and design techniques
– Virtualization of reconfigurable hardware
– Runtime resource management
– Partial reconfiguration

Surveys, Trends, and Education
– Surveys on reconfigurable logic architectures and design techniques
– Deployment of FPGAs in new application domains
– Roadmap of reconfigurable computing platforms
– Teaching courses and tutorials

General Chairs:
Paolo Ienne, EPFL, CH
Walid Najjar, University of California Riverside, US

Programme Chairs:
Jason Anderson, University of Toronto, CA
Philip Brisk, University of California Riverside, US

Workshop and Tutorial Chairs:
Pierre-Emmanuel Gaillardon, University of Utah, US
Michael Huebner, University of Bochum, DE

PhD Forum and Demo Night Chairs:
Mirjana Stojilovic, HEIG-VD, CH
Yann Thoma, HEIG-VD, CH

Proceedings Chair:
Walter Stechele, TU München, DE

Publicity Chair:
Kubilay Atasu, IBM ZRL, CH

Local Arrangements Chair:
Chantal Schneeberger, EPFL, CH

Registration Chair:
Andrew J. Becker, EPFL, CH

Steering Committee:
Jürgen Becker, KIT Karlsruhe, DE
Koen Bertels, TU Delft, NL
Eduardo Boemo, Univ. Autónoma de Madrid, ES
João M. P. Cardoso, Universidade do Porto, PT
Peter Y. K. Cheung, Imperial College London, UK
Martin Danek, Daiteq, CZ
Apostolos Dollas, TU of Crete, GR
Fabrizio Ferrandi, Politecnico di Milano, IT
Manfred Glesner, TU Darmstadt, DE
John Gray, Consultant, UK
Reiner Hartenstein, TU Kaiserslautern, DE
Andreas Herkersdorf, TU München, DE
Udo Kebschull, Goethe University Frankfurt, DE
Wayne Luk, Imperial College London, UK
Patrick Lysaght, Xilinx, Inc., US
Jari Nurmi, Tampere University of Technology, FI
Lionel Torres, University of Montpellier II, FR
Jim Tørresen, University of Oslo, NO

Call for Papers: Workshop on Approximate Computing Across the Stack

Submitted by Adrian Sampson
April 3, 2016

Submitted by Adrian Sampson

Workshop on Approximate Computing Across the Stack (WAX)
co-located with ASPLOS 2016
Atlanta, Georgia, USA
April 3, 2016

WAX is a venue for every aspect of approximate computing, including ideas from
architecture, circuits, devices, system design, compilers, programming
languages, and software-engineering practices. It’s an inherently
interdisciplinary topic, and so is WAX itself.

There are three ways to participate in WAX:
– Peer-reviewed position papers (which will have short talks at the workshop)
– Lightning talks
– Topic suggestions for a debate at WAX

The tentative deadline for position papers is February 10. See the full call
for participation at

Luis Ceze, University of Washington
Hadi Esmaeilzadeh, Georgia Tech
Adrian Sampson, Microsoft Research & Cornell
Ben Zorn, Microsoft Research

Call For Papers: ISLPED 2016

Submitted by Vijay Raghunathan
February 21, 2016 at 24:00

Submitted by Vijay Raghunathan

ACM/IEEE International Symposium on Low Power Electronics and
Design (ISLPED)

San Francisco, CA, USA
August 8-10, 2016

Abstract registration: Feb 21, 2016
Full paper due: Feb 28, 2016
Panel and Embedded Tutorial Proposals Deadline: Apr 16, 2016
Notification of Paper Acceptance: Apr 30, 2016
Camera-ready due: Jun 15, 2016

The International Symposium on Low Power Electronics and Design (ISLPED)
is the premier forum for presentation of innovative research in all aspects of
low power electronics and design, ranging from process technologies and
analog/digital circuits, simulation and synthesis tools, system-level design
and optimization, to system software and applications. Specific topics
include, but are not limited to, the following tracks:

1.1. Technologies
Low-power technologies for Device, Interconnect, Logic, Memory, 2.5/3D,
Cooling, Harvesting, Sensors, Optical, Printable, Biomedical, Battery, and
Alternative energy storage devices.

1.2. Circuits
Low-power digital circuits for Logic, Memory, Reliability, Clocking, Power
gating, Resiliency, Near-threshold and Sub-threshold, Variability, and
Digital assist schemes; Low-power analog/mixed-signal circuits and
Analog assist schemes.

1.3. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, Processor cores
(compute, graphics and other special purpose cores), Cache, Memory, Arithmetic
/Signal processing, Cryptography, Variability, Asynchronous design, and Non-
conventional computing.

2.1. CAD Tools and Methodologies
CAD tools and methodologies for low-power and thermal-aware design
addressing power estimation, optimization, reliability and variation impact
on power, and power-down approaches at all levels of design abstraction:
physical, circuit, gate, register transfer, behavior, and algorithm.

2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design and platforms for
microprocessors, DSPs, embedded systems, FPGAs, ASICs, SoCs, heterogeneous
computing, data-center power delivery and cooling, and system-level power
implications due to reliability and variability.

2.3. Software and Applications
Energy-efficient, energy-aware, and thermal-aware system software and
application design including scheduling and management, power optimizations
through HW/SW interactions, and emerging low power applications such as
approximate and brain-inspired computing, the Internet-of-Things (IoT),
wearable computing, body-area/in-body networks, and wireless sensor networks.

3.1. Industry Perspectives
ISLPED’16 solicits papers for an “Industrial Design” track to reinforce
interaction between the academic research community and industry. Industrial
Design track papers have the same submission deadline as regular papers and
should focus on similar topics, but are expected to provide a complementary
perspective to academic research by focusing on challenges, solutions, and
lessons learnt while implementing industrial-scale designs. Industrial
design papers that focus on any of the topics mentioned in the tracks above
are welcome.

Submissions on new topics: emerging technologies, architectures/platforms,
and applications are particularly encouraged.

Submissions should be full-length papers of up to 6 pages (PDF format, double
-column, US letter size, using the ACM Conference format) including all illustrations,
tables, references, and an abstract of no more than 250 words. Submissions must
be anonymous. Submissions exceeding 6 pages or identifying the authors, either
directly or through explicit references to their prior work, will be automatically
rejected. More information about paper submission can be found at

Submitted papers must describe original work that has not been published/
accepted or currently under review by another journal, conference,
symposium, or workshop at the same time. Accepted papers will be submitted
to the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’16
will present two Best Paper Awards based on the ratings of reviewers and a
panel of judges.

There will be several invited talks by industry and academic thought leaders
on key issues in low power electronics and design. The Symposium may also
include embedded tutorials to provide attendees with the necessary background
to follow recent research results, as well as panel discussions on future
directions in low power electronics and design. Proposals for invited talks,
embedded tutorials, and panels should be sent by email to the ISLPED’16
Technical Program Co-Chairs, David Garrett ( and Chia-
Lin Yang ( by the deadline listed above.

Call for Papers: LCTES 2016 ( Extended Deadline)

Submitted by Che-Wei Chang
June 13 to June 14, 2016

Submitted by Che-Wei Chang

ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools and
Theory for Embedded Systems (LCTES 2016)

Santa Barbara, California, USA
June 13-14, 2016

Submission deadline: Feb 8, 2016 (Extended)
Author notification: Mar 16, 2016
Camera-ready deadline: Mar. 25 2016

Embedded system design faces many challenges both with respect to functional
requirements and nonfunctional requirements, many of which are conflicting.
They are found in areas such as design and developer productivity,
verification, validation, maintainability, and meeting performance goals and
resource constraints. Novel design-time and run-time approaches are needed to
meet the demand of emerging applications and to exploit new hardware
paradigms, and in particular to scale up to multicores (including GPUs and
FPGAs) and distributed systems built from multicores.

LCTES 2016 solicits papers presenting original work on programming languages,
compilers, tools, theory, and architectures that help in overcoming these
challenges. Research papers on innovative techniques are welcome, as well as
experience papers on insights obtained by experimenting with real-world
systems and applications.

Papers are solicited on, but not limited to, the following topics in embedded

Programming language challenges, including:
– Domain-specific languages
– Features to exploit multicore, reconfigurable, and other emerging
– Features for distributed, adaptive, and real-time control embedded systems
– Language features and techniques to enhance reliability, verifiability,
and security
– Virtual machines, concurrency, inter-processor synchronization, and
memory management

Compiler challenges, including:
– Interaction between embedded architectures, OS, and compilers
– Interpreters, binary translation, JIT compilation, and split compilation
– Support for enhanced programmer productivity
– Support for enhanced debugging, profiling, and exception/interrupt handling
– Optimization for low power/energy, code and data size, and best-effort
and real-time performance

Tools for analysis, specification, design, and implementation, including:
– Hardware, system software, application software, and their interfaces
– System integration and testing
– Performance estimation, monitoring, and tuning
– Run-time system support for embedded systems
– Design space exploration tools
– Support for system security and system-level reliability
– Approaches for cross-layer system optimization

Theory and foundations of embedded systems, including:
– Predictability of resource behavior: energy, space, time
– Validation and verification, in particular of concurrent and
distributed systems
– Models of computations for embedded applications

Novel embedded architectures, including:
– Design and implementation of novel architectures
– Workload analysis and performance evaluation
– Architecture support for new language features, virtualization, and
debugging tools
– Achitectural features to improve power, code and data size, and

General Chair: Tei-Wei Kuo, Academia Sinica, Taiwan
Program Chair: David Whalley, Florida State University, USA

Call for Papers: MICRO 2016

Submitted by Vijay Janapa Reddi
October 15 to October 19, 2016

Submitted by Vijay Janapa Reddi

The 49th Annual IEEE/ACM International Symposium on
Microarchitecture (MICRO-49)

Taipei, Taiwan
October 15-19, 2016

Sponsored by IEEE Computer Society, TC-uARCH, and ACM SIGMICRO

Abstracts due : April 3rd, 2016
Papers due : April 10th, 2016
Rebuttal period : June 6th – June 10th, 2016
Notifications : June 25th, 2016

– Processor, memory, interconnect, and storage architectures
– Hardware, software, and hybrid techniques for improving system performance,
energy-efficiency, cost, complexity, predictability, quality of service,
reliability, security, scalability, programmer productivity, etc.
– Processor, memory, storage, interconnect designs
– Architectures for instruction-level, thread-level, and memory-level
parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore,
manycore, etc.
– Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP)
– Low-power, high-performance, and cost/complexity-efficient architectures
– Architectures for emerging platforms, including smartphones, tablets,
cloud/datacenter, etc.
– Architectures and compilers for embedded processors, DSPs, GPUs, ASIPs
(network processors, multimedia, wireless, etc.)
– Advanced software/hardware speculation and prediction schemes
– Microarchitecture techniques to better support system software, programming
languages, programmability, and compilation
– Microarchitecture modeling and simulation methodology
– Insightful experimental and comparative evaluation and analysis of
existing microarchitectures, hardware/software mechanisms and workloads

General Co-Chairs
– Wei-Chung Hsu, Natl. Taiwan U.
– Chia-Lin Yang, Natl. Taiwan U.

Program Co-Chairs
– Mikko Lipasti, Univ. Wisconsin
– Hsien-Hsin Lee, TSMC

Tutorial and Workshops Chair
– David Brooks, Harvard

Local Arrangements
– Shiao-Li Charles Tsao, NCTU
– Pi-Cheng Hsiu, Academia Sinica

Publication Chair
– Bo-Cheng Charles Lai, NCTU

Publicity Co-Chairs
– Koji Inoue, Kyushu Univ.
– Vijay Janapa Reddi, UT Austin
– Albert Cohen, INRIA

Finance Co-Chairs
– Antonia Zhai, U. of Minnesota
– Yi-Jung Chen, NCNU

Web Chair
– Hung-Wei Tseng, UC San Diego

Submission Chair
– Chih-Chen Kao, Natl. Taiwan U.

Registration Chair
– Ren-Shuo Liu, NTHU

Industrial liaison
– Tien-Fu Chen, NCTU
– Mu-Tien Chang, Samsung USA
– Dongrui Fan, ICT

Travel Award Chair
– Carole-Jean Wu, ASU

Steering Committee
– Richard Belgard, Consultant, Chair
– David Albonesi,Cornell
– Tom Conte, Georgia Tech
– Kemal Ebcioglu, Global Supercomputing
– Matthew Farrens, UC Davis
– Scott Mahlke, Univ. of Michigan
– Bill Mangione-Smith, Consultant
– Onur Mutlu, CMU
– Yale Patt, UT Austin
– Milos Prvulovic, Georgia Tech

Call for Participation: HPCA 2016

Submitted by Augusto Vega
March 12 to March 16, 2016

Submitted by Augusto Vega

22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA)
collocated with PPoPP-2016 and CGO-2016
Barcelona, Spain
March 12-16 2016

– Travel grant application deadline: January 31, 2016, 11:59pm (GMT+0)
– Early registration deadline: February 3, 2016

The International Symposium on High-Performance Computer Architecture provides
a high-quality forum for scientists and engineers to present their latest
research findings in this rapidly-changing field. HPCA-22 will be held in
conjunction with the 21st ACM SIGPLAN Symposium on Principles and Practice of
Parallel Programming (PPoPP-2016) and the 14th International Symposium on Code
Generation and Optimization (CGO-2016).

Conference program, workshops and tutorials, registration and lodging
information are all available at the conference website.