Call for Papers: NoCArc 2016

9th International Workshop on Network on Chip Architectures
in conjunction with IEEE/ACM MICRO-49
October 15 or 16, 2016
Taipei, Taiwan

– Abstract submission deadline: July 25, 2016
– Paper submission deadline: August 1, 2016
– Acceptance notification: September 1, 2016
– Camera-ready version due: September 8, 2016

Current multicore architectures formed by tens of processing cores will be soon replaced by the next generation of manycore architectures with hundreds of cores. In fact, the International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a System-on-Chip (SoC) will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on- Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip.

The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis and testing of on-chip networks.

The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation
– Topologies, routing, flow control
– Managing QoS
– Timing, synchronous/asynchronous communication
– Reliability issues
– Design methodologies and tools
– Signaling & circuit design for NoC links
– NoC Analysis and Verification

Power, energy and thermal issues
– Benchmarking and experience with NoC-based systems
– Modeling, simulation, and synthesis
– Verification, debug and test
– Metrics and benchmarks
– NoC Application

Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems
– On-Chip Communication Optimization

Communication efficient algorithms
– Multi/many-core communication workload characterization and evaluation
– Energy efficient NoCs and energy minimization
– NoC at System-level

Design of memory subsystem
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing and novel programming models
– Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks

Emerging NoC Technologies
– Wireless, Optical, and RF
– NoCs for 3D and 2.5D packages

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author. Additional information at

General Co-Chairs
– Maurizio Palesi, Univ. of Enna, KORE, Italy
– Masoud Daneshtalab, Univ. of Turku, Finland and KTH, Sweden
– Xiaohang Wang, South China University of Technology, China

TPC Co-Chairs
– Masoumeh Ebrahimi, Univ. of Turku, Finland
– Davide Patti, Univ. of Catania, Italy

Call for Nominations: Seymour Cray, Sidney Fernbach & ACM/IEEE-CS Ken Kennedy Awards

Call for Nominations: Seymour Cray, Sidney Fernbach & ACM/IEEE-CS Ken Kennedy Awards
Award Presentation: SC16
Salt Lake City, Utah, USA
Nov 14-18, 2016

Nomination Deadline: July 1, 2016

Established in late 1997 in memory of Seymour Cray, the Seymour Cray Award is awarded to recognize innovative contributions to high performance computing systems best exemplify the creative spirit demonstrated by Seymour Cray. The award consists of a crystal memento and honorarium of $10,000. This award requires 3 endorsements.

Established in 1992 by the Board of Governors of the IEEE Computer Society. It honors the memory of the late Dr. Sidney Fernbach, one of the pioneers on the development and application of high performance computers for the solution of large computational problems. The award, which consists of a certificate and a $2,000 honorarium, is presented annually to an individual for “an outstanding contribution in the application of high performance computers using innovative approaches.” This award requires 3 endorsements.

Established in memory of Ken Kennedy, the founder of Rice University’s nationally ranked computer science program and one of the world’s foremost experts on high-performance computing. A certificate and $5,000 honorarium are awarded jointly by the ACM and the IEEE Computer Society for outstanding contributions to programmability or productivity in high- performance computing together with significant community service or mentoring contributions. This award requires 2 endorsements.

For nomination queries, please write to or visit

Call for Papers: HPCA 2017

23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA)
collocated with CGO and PPoPP
Austin, Texas, USA
February 4 – 8, 2017

Abstract submission: July 25, 2016, 11:59 PM CDT
Paper submission: August 1, 2016, 11:59 PM CDT
Notification of paper outcome: October 12, 2016

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture.

Topics of interest include, but are not limited to:
– Processor, cache, and memory architectures
– Parallel computer architectures
– Multicore and multiprocessor architectures
– Impact of technology on architecture
– Power-efficient architectures and techniques
– Dependable/secure architectures
– High-performance I/O systems
– Embedded, reconfigurable, and heterogeneous architectures
– Interconnect and network interface architectures
– Architectures for cloud-based HPC and data centers
– Innovative hardware/software trade-offs
– Impact of compilers and system software on architecture
– Performance modeling and evaluation
– Architectures for emerging technology and applications

Authors should submit an abstract by July 25, 2016 11:59 PM CDT. They should submit the full version of the paper August   1, 2016, 11:59 PM CDT. No extensions will be granted. The full version should be a PDF file following the submission guidelines that will be made available at the submission website.  Papers should be submitted for blind review. We anticipate making a Best Paper award; all papers will be evaluated based on their novelty, fundamental insights, experimental evaluation, and potential for long-term impact.  New-idea papers as well as papers that significantly advance established areas are strongly encouraged. Submission issues should be directed to the program chair at djimenez@cse.tamu. edu . Details formatting and submission guidelines will be made available at HPCA-23 will host an Industrial Paper Session presenting novel insights from industry. See the HPCA 2017 website for submission details.

Sponsored by the IEEE Computer Society TC on Computer Architecture

General Chair:
Derek Chiou, Microsoft and UT Austin

Program Chair:
Daniel A. Jimenez, Texas A&M University

Program Committee:
Valeria Bertacco, Michigan
Abhishek Bhattacharjee, Rutgers
Reetuparna Das, Michigan
Hadi Esmaeilzadeh, Georgia Tech
Yoav Etsion, Technion
Babak Falsafi, EPFL
Michael Ferdman, Stony Brook University
Antonio Gonzalez, UPC
Paul Gratz, Texas A&M
Nikos Hardavellas, Northwestern University
Kei Hiraki, University of Tokyo
Jaehyuk Huh, KAIST
Engin Ipek, Rochester
David Kaeli, Northeastern
Samira Khan, UVA
Hyesoon Kim, Georgia Tech
Tao Li, Florida and NSF
Calvin Lin, UT Austin
Gabriel H. Loh, AMD
Shih-Lien Lu, TSMC
Pierre Michaud, Inria
Timothy N. Miller, Binghamton University (SUNY)
Miquel Moreto, BSC and UPC
Andreas Moshovos, Toronto
Trevor Mudge, Michigan
Onur Mutlu, ETH Zurich and CMU
Abdullah Muzahid, UT San Antonio
Vijay Nagarajan, University of Edinburgh
Soner Onder, Michigan Tech
Yale N. Patt, UT Austin
Miquel Pericas, Chalmers University of Technology
Alex Ramirez, NVIDIA
Karu Sankaralingam, Wisconsin
Yan Solihin, NCSU and NSF
Yingying Tian, AMD
Mohit Tiwari, UT Austin
Josep Torrellas, UIUC
Thomas F. Wenisch, Michigan
David Wentzlaff, Princeton
Carole-Jean Wu, ASU
Yuan Xie, UCSB
Mohamed Zahran, NYU
Antonia Zhai, Minnesota
Lixin Zhang, Institute of Computing Technology, CAS
Huiyang Zhou, NCSU

Industrial Session Chair:
Chris Wilkerson, Intel Labs

Local Arrangements Chair:
Mohit Tiwari, UT Austin

Workshops and Tutorials Chair:
Mike Ferdman, Stony Brook University

Finance Chair:
Dam Sunwoo, ARM

Publications Chair:
Xuehai Qian, USC

Travel Awards Chair:
Zhenman Fang, UCLA

Publicity Chair:
Michael Papamichael, Microsoft Research

Web and Submissions Chairs:
Hung-Wei Tseng, UCSD and Elvira Teran, Texas A&M and Intel Labs

Industrial Session Chair:
Chris Wilkerson, Intel Labs

Local Arrangements Chair:
Mohit Tiwari, UT Austin

Workshops and Tutorials Chair:
Mike Ferdman, Stony Brook University

Finance Chair:
Dam Sunwoo, ARM

Publications Chair:
Xuehai Qian, USC

Travel Awards Chair:
Zhenman Fang, UCLA

Publicity Chair:
Michael Papamichael, Microsoft Research

Web and Submissions Chairs:
Hung-Wei Tseng, UCSD and Elvira Teran, Texas A&M and Intel Labs

Call for Papers: CGO 2017

2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
co-located with CC, HPCA and PPoPP
Austin, TX USA
February 4-8, 2017

Abstract Submission: Sept 2, 2016
Paper Submission: Sept 9, 2016
Notification: Oct 25, 2016

The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and  practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

Original contributions are solicited on, but not limited to, the following topics:
– Code Generation, Translation, Transformation, and Optimization for performance, energy, virtualization, portability, security, or reliability concerns, and architectural support
– Efficient execution of dynamically typed and higher-level languages
– Optimization and code generation for emerging programming models, platforms, domain-specific languages
– Dynamic/static, profile-guided, feedback-directed, and machine learning based optimization
– Static, Dynamic, and Hybrid Analysis
– Program characterization methods
– Efficient profiling and instrumentation techniques; architectural support
– Novel and efficient tools
– Compiler design, practice and experience
– Compiler abstraction and intermediate representations
– Vertical integration of language features, representations, optimizations, and runtime support for parallelism
– Solutions that involve cross-layer (HW/OS/VM/SW) design and integration
– Deployed dynamic/static compiler and runtime systems for general purpose, embedded system and Cloud/HPC platforms
– Parallelism, heterogeneity, and reconfigurable architectures
– Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA
– Compiler-support for vectorization, thread extraction, task scheduling, speculation, transaction, memory management, data distribution and synchronization

General Chair
Vijay Janapa Reddi, UT Austin

Program Co-chairs
Aaron Smith, Microsoft Research/University of Edinburgh
Lingjia Tang, University of Michigan

Program Committee
Adrian Sampson, Cornell
Albert Cohen, Inria
Alexandra Jimborean, UPPSALA
Antoniu Pop, University of Manchester
Ayal Zaks, Intel
Carol Eidt, Microsoft
Changhee Jung, Virginia Tech
Chenggang Wu, ICT
Christophe Dubach, University of Edinburgh
Derek Bruening, Google
Erik Altman, IBM
Evelyn Duesterwald, IBM
Jack Davidson, University of Virginia
Jason Mars, University of Michigan
Jennifer Sartor, UGhent
Jingling Xue, UNSW
Joe Devietti, University of Pennsylvania
Lisa Wu, UC Berkeley
Louis-Noel Pouchet, Ohio State University
Michael Carbin, MIT
Michael Laurenzano, University of Michigan
Michael O’Boyle, University of Edinburgh
Milind Chabbi, HP
Naveen Kumar, Google
Nuno Lopes, MSR Cambridge
Peng Wu, Huawei
Robert Hundt, Google
Saman Amarasinghe, MIT
Santosh Nagarakatte, Rutgers
Scott Mahlke, University of Michigan
Simone Campanoni, Northwestern University
Vinod Grover, Nvidia
Youfeng Wu, Intel
Yun Liang, Peking University

Finance Chair
Carol Eidt, Microsoft

Local Arrangements Chair
Mauricio Breternitz, AMD

Regional Publicity Chairs
Jason Mars, University of Michigan (North America)
Wei-Chung Hsu, NTU (Asia)
Simone Campanoni, Northwestern (Europe)
Edson Borin, Unicamp (South America)

Proceedings Chair
Antonia Zhai, University of Minnesota

Registration Chair
Carole Wu, Arizona State University

Sponsorship Chair
Robert Hundt, Google

Students/Travel Chair
Brandon Lucia, CMU

Web Chair
Matthew Halpern, UT Austin

Workshops/Tutorials Chair
Adrian Sampson, Microsoft Research/Cornell

Artifacts Chairs
Joseph Devietti, University of Pennsylvania
Grigori Fursin, Dividiti/cTuning Foundation