Call for Workshops and Tutorials: HPCA 2017

International Symposium on High-Performance Computer Architecture (HPCA)
Austin, Texas, USA
February 4-8, 2017

– Deadline for submission: September 16, 2016, 11:59 PM EDT
– Notification of acceptance: October 10, 2016

The 2017 IEEE International Symposium on High-Performance Computer Architecture (HPCA-23) is seeking proposals for workshops and tutorials to accompany the conference. Workshops and tutorials will be held on Saturday-Sunday, February 4-5, and may be a half day or a full day in length.

We encourage members of the community to consider submitting proposals for workshops and tutorials that bring together researchers and practitioners working on research topics of significant current interest to the HPCA community.
Prospective workshop and tutorial organizers are invited to submit proposals by completing the online submission form:

For questions, please contact the Workshops and Tutorials chair, Michael Ferdman (

Call for Workshops and Tutorials: ASPLOS 2017

22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
Xi’an, China
April 8–12, 2017

Workshop and tutorial proposals are solicited for ASPLOS-2017, Xi’an,China. Workshops and tutorials will be held on April 8, 2017 (Saturday) and April 9, 2017 (Sunday).


Submission deadline: Monday, November 21, 2016
Notification:Monday, December 12 2016

Proposals for both half- and full-day tutorials are solicited on any topic that is relevant to the ASPLOS audience. In previous years, tutorials seeking to achieve either of the following goals have been particularly successful:
– Describe an important piece of research infrastructure.
– Educate the community on an emerging topic.

Proposals should provide the following information:
– Title
– Presenter(s) and contact information
– Proposed duration (full day, half day)
– 1-2 paragraph abstract suitable for tutorial publicity
– 1 paragraph biography per presenter suitable for tutorial publicity
– 1-3 page description (for evaluation). This should include:
      o Tutorial scope and objectives
      o Topics to be covered
      o Target audience
      o If the tutorial has been held previously, the location (i.e., conference), date, and number of attendees

Proposals should be submitted in PDF format via e-mail to Boris Grot ( and Guangyu Sun ( with the subject “ASPLOS2017 Tutorial Proposal”. Submissions will be acknowledged via e-mail.


Submission Deadline : Monday, November 21, 2016
Notification : Monday, December 12 2016

Proposals in the interplay between programming languages, computer architecture, operating systems, and user interfaces to deal with power, performance, resilience, and programmer productivity issues in emerging areas such as datacenters and cloud computing, systems based on non-volatile memory technologies, large scale data analysis, smart infrastructure, and extreme scale computing are encouraged.

Please include in your proposal
– Title of the workshop
– Organizers and their affiliations
– Sample call for papers
– Duration – Half-Day or Full Day
– Preferred Day – Saturday or Sunday
– If the workshop was previously held, the location (conference), date, and number of attendees

Proposals should be submitted via e-mail to Albert Cohen ( and Shan Lu ( with the subject “ASPLOS2017 Workshop Proposal”. Submissions will be acknowledged via e-mail.

Contact Albert and Shan if you have any questions about the suitability of a workshop or tutorial for ASPLOS or for any other related matters.

Call for Papers: Workshop on Communication Optimizations in HPC

First International Workshop on Communication Optimizations in High Performance Computing (COMHPC)
co-located with SC16
in cooperation with ACM SIGHPC
Salt Lake City, Utah, USA
November 18, 2016

Submission deadline: September 8, 2016 AOE
Notification of Acceptance: September 28, 2016
Camera Ready copy: October 11, 2016
Workshop Date: November 18, 2016

As HPC applications scale to large supercomputing systems, their communication and synchronization need to be optimized in order to deliver high performance. In order to achieve this, capabilities of modern network interconnect and parallel runtime systems need to be advanced and the existing ones to be leveraged optimally. The workshop will bring together researchers and developers to present and discuss work on optimizing communication and synchronization in HPC applications. This includes state-of-the-art methodological and algorithmic advances in topology-aware or topology-oblivious blocking and non-blocking collective algorithms, offloading of communication to network interface cards, topology aware process mappings for minimizing communication overhead on different network topologies such as dragonfly, high-dimensional torus networks, fat trees, optimizations for persistent communication patterns, studies and solutions for inter-job network interference, overlapping of communication with computation, optimizing communication overhead in the presence of process imbalance, GPU-GPU and GPU-CPU communication. The workshop also aims at bringing researchers together to foster discussion, collaboration, and ideas for optimizing communication and synchronization that drive the design of future peta/exascale systems and of HPC applications. In addition, we expect that researchers and others looking for research directions in this area will get up-to-date with the state of the art so that they can drive their research in a manner that will impact the future of communication methods in high-performance computing.

Topics of interest for workshop submissions include (but are not limited to):
– Communication optimizations on Peta/Exascale systems, heterogeneous systems, and GPUs
– Scalable communication endpoints for many-core architectures
– Topology-aware collective algorithms and process mappings
– Communication offloading design and optimizations (such as offloaded triggered operations)
– Modeling and simulation of traffic patterns (including collectives) for generic/specific network topologies
– Blocking and non-blocking collective operations
– Neighborhood collective optimizations
– Optimizations for persistent communication patterns
– Inter-job network interference
– Computation-communication overlap in HPC applications
– Communication optimization in presence of process imbalance
– Static/runtime tuning of collective operations
– Network congestion studies and mitigation methods
– Machine learning to optimize communication
– Communication aspects of GPGPU
– Communication aspects of Graph Applications
– Communication aspects of Fault Tolerance

Prof. William Gropp, UIUC

Papers must follow the ACM format (see We invite two kinds of submissions to this workshop:
1. Full-length research papers (10-page limit)
2. Short papers (5-page limit), which can take the form of position papers, experience reports, work in progress, late breaking ideas, or surveys/comparisons

The page limit does not include references, for which there is no page limit. Papers should be submitted electronically via EasyChair: Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. Papers will be peer-reviewed by the Program Committee for novelty, scientific merit, technical strength, originality, quality of presentation and scope of the workshop. It is also expected that at least one author of an accepted paper must register for and attend the workshop. Accepted papers will be published in the workshop proceedings by SIGHPC and made available in the ACM Digital Library and IEEE Xplore. One outstanding paper will be selected for the Best Paper Award by the Program Committee.

Michael Chuvelev (Intel, Russia)
Daniel Faraj (SGI, USA)
Maria Garzaran (UIUC and Intel, USA )
Akhil Langer (Intel, USA)
Malek Musleh (Intel, USA)
Gengbin Zheng (Intel, USA)

Program Committee:
Ahmad Afsahi (Queen’s University, Canada)
George Almasi (IBM, USA)
Abhinav Bhatele (LLNL, USA)
Bill Gropp (University of Illinois Urbana-Champaign, USA)
Manish Gupta (Xerox Research Center, India)
Ram Huggahalli (Intel, USA)
Nikhil Jain (LLNL, USA)
David Lowenthal (University of Arizona, USA)
Vijay Pai (Google, USA)
D. K. Panda (Ohio State University, USA)
Sameh Sharkawi (IBM, USA)
Yogish Sabharwal (IBM, India)
Martin Schulz (LLNL, USA)
Bronis Supinski (LLNL, USA)
Sayantan Sur (Intel, USA)
Michela Taufer (University of Delaware, USA)
Keith Underwood (Intel, USA)
Abhinav Vishnu (PNNL, USA)
Alan Wagner (University of British Columbia, Canada)
Xin Yuan (Florida State University, USA)

Call for Participation: Workshop on In-Memory and In-Storage Computing with Emerging Technologies

Workshop on In-Memory and In-Storage Computing with Emerging Technologies
in conjunction with PACT 2016
Haifa, Israel
September 11, 2016.

Workshop on In-Memory and In-Storage Computing with Emerging Technologies invites you to share your research and creative endeavors with your colleagues. Early registration (with PACT) lasts until August 15th.

We are delighted to have Prof. Uri Weiser of Technion and Prof. Engin Ipek of Rochester University as our keynote speakers.

Our program features 6 selected papers on a variety of subjects including computer architecture and algorithms based on resistive memory technologies such as memristors, RRAM, PCM, 3D Xpoint, STT-MRAM and others. Authors will present a wide range of potential applications including digital computing, non-volatile storage with processing capabilities, neuromorphic computing, etc. We will further discuss the use of emerging technologies as an enabler of the next generation of new architectures that address the major shortcomings of today’s conventional high-performance computing such as latency, energy, power efficiency and scalability.

The workshop will take place in the Dan Carmel Hotel in Haifa, Israel, overlooking the Mediterranean Sea.

General Chairs:
Shahar Kvatinsky, Technion – Israel Institute of Technology, Israel
Leonid Yavits, Technion – Israel Institute of Technology, Israel

Program Committee:
Albert Cohen, INRIA.
Mattan Erez, UT Austin.
Dietmar Fey, FAU.
Said Hamdioui, TU Delft.
Engin Ipek, University of Rochester.
Onur Mutlu, CMU.
Moin Qureshi, Georgia Tech.
Ronny Ronnen, Intel.
Uri Weiser, Technion.
Yuan Xie, UC Santa Barbara.

Call For Papers: ISPASS 2017

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
San Francisco Bay Area, California, USA
April 23-25, 2017

Paper abstract submission: October 7, 2016
Full submission: October 14, 2016
Rebuttal: January 13-16, 2017
Notification: January 30, 2017
Conference: April 23-25, 2017

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software. Authors are invited to submit previously unpublished work for possible presentation at the conference. Papers are solicited in fields that include the following:

Performance and power evaluation methodologies
– Analytical modeling
– Statistical approaches
– Tracing and profiling tools
– Simulation techniques
– Hardware (e.g., FPGA) accelerated simulation
– Hardware performance counter architectures
– Power/Temperature/Variability/Reliability models for computer systems
– Microbenchmark-based hardware analysis techniques
Performance and power analysis
– Metrics
– Bottleneck identification and analysis
– Visualization
Power/Performance analysis of commercial and experimental hardware
– General-purpose microprocessors
– Multithreaded, multicore and many-core architectures
– Accelerators and graphics processing units
– Memory systems including storage class memory
– Embedded and mobile systems
– Enterprise systems and data centers
– Supercomputers
– Computer networks
Power/Performance analysis of emerging workloads and software
– Software written in managed languages
– Virtualization and consolidation workloads
– Internet-sector workloads
– Embedded, multimedia, games, telepresence
– Bioinformatics, life sciences, security, biometrics
– Deep learning and convolutional neural networks
Application and system code tuning and optimization
Confirmations or refutations of important prior results

In addition to research papers, ISPASS welcomes tools and benchmarks papers. The conference is an ideal forum to publicize new tools and benchmarks to the community. These papers, which can detail tools and benchmarks in any of the above fields of interest, will be judged primarily on their potential impact and use than on their research contribution.

See the conference web site for submission details.

General Chair:
Suzanne Rivoire, Sonoma State University

Program Committee Chair:
Bronis R. de Supinski, LLNL

Program Committee:
Dorian Arnold, University of New Mexico
Laura Carrington, San Diego Supercomputing Center
Almadena Chtchelkanova, NSF
Marcelo Cintra, Intel
Jeanine Cook, Sandia National Laboratories
Luiz DeRose, Cray
Christina Delimitrou, Cornell University
Andi Drebes, The University of Manchester
Lieven Eeckhout, Ghent University
Wendy Elsasser, ARM
Nikos Hardavellas, Northwestern University
David Hass, Broadcom
Hillery Hunter, IBM Research
Katherine Isaacs, University of Arizona
Lizy John, University of Texas
Samira Khan, University of Virginia
Masaaki Kondo, The University of Tokyo
David Lowenthal, University of Arizona
Xiaosong Ma, Qatar Computing Research Institute
Naoya Maruyama, RIKEN AICS
Dimitrios Nikolopoulos, Queen’s University, Belfast
Tapasya Patki, LLNL
Indrani Paul, AMD
Michael Pellauer, NVIDIA
Fabrizio Petrini, Intel
Suzanne Rivoire, Sonoma State University
Valentina Salapura, IBM Research
Yanos Sazeides, University of Cyprus
Thomas Scogland, LLNL
Kelly Shaw, University of Richmond
Estela Suarez, Jülich Supercomputing Centre
Linglia Tang, University of Michigan
Michela Taufer, University of Delaware
Valerie Taylor, Texas A&M University
Eric Van Hensbergen, ARM
Jeffrey S. Vetter, Oak Ridge National Laboratory
Vince Weaver, University of Maine
Thomas F. Wenisch, University of Michigan

Call for Papers: Workshop on Irregular Applications: Architectures and Algorithms

IA^3 2016 – Sixth Workshop on Irregular Applications: Architectures and Algorithms
in conjunction with SC16 and SIGHPC
Salt Lake City, UT
November 13, 2016

Abstract submission: August 23, 2016
Position or full paper submission: August 29, 2016
Notification of acceptance: October 3, 2016
Camera-ready position and full papers: October 10, 2016
Workshop: November 13, 2016

Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, tables, sparse matrices, deep nets, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:

– Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors
– Network architectures and interconnect (including high-radix networks, optical interconnects)
– Novel memory architectures and designs (including processors-in memory)
– Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing)
– Modeling, simulation and evaluation of novel architectures with irregular workloads
– Innovative algorithmic techniques
– Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
– Impact of irregularity on machine learning approaches
– Parallelization techniques and data structures for irregular workloads
– Data structures combining regular and irregular computations (e.g., attributed graphs)
– Approaches for managing massive unstructured datasets (including streaming data)
– Languages and programming models for irregular workloads
– Library and runtime support for irregular workloads
– Compiler and analysis techniques for irregular workloads
– High performance data analytics applications, including graph databases

Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.

All submissions should be in double-column, single-spaced letter format, using 10-point size fonts, with at least one-inch margins on each side, and respect the IEEE conference templates available at
Submission site:

The proceedings of the workshop will be published in cooperation with ACM SIGHPC and available from the ACM Digital Library.

Submitted manuscripts may not exceed 8 pages in length for regular papers and 4 pages for position papers including figures, tables and references.

Antonino Tumeo, PNNL
John Feo, PNNL, Northwest Institute for Advanced Computing (NIAC)
Oreste Villa, NVIDIA Research

Program Committee:
Scott Beamer, Lawrence Berkeley National Laboratory, US
Michela Becchi, University of Missouri, US
David Brooks, Harvard University, US
Hubertus Franke, IBM TJ Watson, US
John Gilbert, University of California at Santa Barbara, US
Maya Gokhale, Lawrence Livermore National Laboratory, US
Vivek Kumar, Rice University, US
John Leidel, Texas Tech University, US
Kamesh Madduri, Penn State University, US
Naoya Maruyama, RIKEN AICS, JP
Satoshi Matsuoka, Tokio Institute of Technology, JP
Tim Mattson, Intel, US
Richard Murphy, Micron, US
Miquel Moretó, UPC-BSC, ES
Walid Najjar, University of California Riverside, US
Jacob Nelson, University of Washington, US
Ozcan Ozturk, Bilkent University, TR
Gianluca Palermo, Politecnico di Milano, IT
D.K. Panda, The Ohio State University, US
Fabrizio Petrini, Intel, US
Jason Riedy, Georgia Institute of Technology, US
Daniel Sanchez, Massachusetts Institute of Technology, US
Erik Saule, University of North Carolina at Charlotte, US
John Shalf, Lawrence Berkeley National Laboratory, US
Ruud Van Der Pas, Oracle, US
Flavio Vella, Sapienza, University of Rome, IT

Call for Papers: International Symposium on Hardware Oriented Security and Trust

IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2017)
McLean, Virginia, USA
May 3-5, 2016

Abstract Deadline: November 1, 2016
Paper Submission Deadline: November 8, 2016
Notification of Acceptance: January 31, 2017
Camera-ready Version: February 28, 2017
Hardware Demo Proposal: March 15, 2017

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) aims to facilitate the rapid growth of hardware-based security research and development. HOST highlights new results in the area of hardware and system security. Relevant research topics include techniques, tools, design/test methods, architectures, circuits, and applications of secure hardware.

HOST 2017 invites original contributions related to, but not limited by, the following topics:
– Hardware Trojan attacks and detection techniques
– Hardware techniques to facilitate software and/or system security
– Hardware-based security primitives (PUFs, RNGs)
– System-on-chip (SoC) security
– Side-channel attacks and protection
– Security, privacy, and trust protocols
– Metrics, policies, and standards related to hardware security
– Hardware IP trust (watermarking, metering, trust verification)
– Trusted manufacturing including split manufacturing and 3D ICs
– Security analysis and protection of Internet of Things (IoT)
– Secure and efficient implementation of crypto algorithms
– Reverse engineering and hardware obfuscation
– Supply chain risks mitigation (e.g., counterfeit detection & avoidance)
– Hardware tampering attacks and protection
– Applications of hardware security to secure system development

You can register and submit your paper at: The page limit is 6 pages, double column, IEEE format, with a minimum font size of 10 points. Submissions are anonymous and must not identify the authors, directly or indirectly, anywhere in the manuscript.

Students can participate in a hardware demo session by submitting a 1-page proposal describing the research and features to be demonstrated on an FPGA or other hardware platform. Please upload your proposal to EasyChair by March 15, 2017.
A best paper award will be given to paper whose first author is a full-time student.
A best presentation award will be given to a speaker who is a full-time student.
Travel grants are available for graduate and undergraduate students.

General Chair:
William H. Robinson, Vanderbilt University

Program Chair:
Swarup Bhunia, University of Florida

Call for Participation: NOCS 2016

10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)
August 31 – September 2, 2016
Nara, Japan

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation.

NOCS 2016 will be held in Nara. It is well connected to Kyoto and Osaka. The nearest airport is Kansai International Airport, which is also well connected to many international cities. Nara was the capital of Japan about 1300 years ago. There are historical temples, shrine, palace, and forest encompassed as Historic Monuments of Ancient Nara.

Advanced program, registration, and hotel reservation are available online.

Keynote Talks:
– Near-Field Coupling Integration Technology. Tadahiro Kuroda (Keio University, Japan)
– Identifying On-Chip Communication Requirements for IOT. Rob Aitken (ARM Inc., USA)

Embedded Tutorial:
Inter/Intra-Chip Optical Interconnection Network: Opportunities, Challenges, and Implementations. Jiang Xu (Hong Kong University of Science and Technology, Hong Kong), Yuichi Nakamura (NEC Corp., Japan)

General Co-Chairs:
– Hideharu Amano (Keio University, Japan)
– Partha Pratim Pande (Washington State University, USA)

Technical Program Co-Chairs:
– Hiroki Matsutani (Keio University, Japan)
– Sriram Vangal (Intel, USA)

Call for Papers: CCGrid 2017

The 17th IEEE/ACM International Symposium On Cluster, Cloud And Grid Computing (CCGrid 2017)
Madrid, Spain
May 14-17

Papers due: November 16, 2016
Author notifications: January 15, 2017

Advances in architectures, networks, systems and middleware technologies are leading to new concepts and platforms for computing, ranging from Clusters and Grids to Clouds and Datacenters. CCGrid 2017 is a forum bringing together international researchers, developers, and practitioners to present leading research activities and results on a broad range of topics related to these concepts, platforms, and their applications. The conference features keynotes, technical presentations, workshops, and posters, as well as the Doctoral Symposium and the SCALE challenge featuring live demonstrations. In 2017, CCGrid will come to Spain and will be held in Madrid.

Topics of interest include, but are not limited to:
– Applications and Big Data
– Architecture and Networking
– Data Centers and CyberInfrastructure
– Programming Models and Runtime Systems
– Performance Modeling and Evaluation
– Scheduling and Resource Management
– Mobile and Hybrid Clouds
– Storage and I/O
– Security, Privacy and Reliability

Authors are invited to submit papers electronically in PDF format. Submitted manuscripts should be structured as technical papers and may not exceed 10 letter-size (8.5 x 11) pages including all figures, tables and references using the IEEE format for conference proceedings. For the final camera-ready version, authors with accepted papers may purchase up to two additional pages at the following rates: 100 USD for each page.

Submissions not conforming to these guidelines may be returned without review. The official language of the conference is English. All manuscripts will be reviewed and judged on technical strength, originality, significance, quality of presentation, and interest and relevance to the conference attendees.

The proceedings will be published through the IEEE Computer Society Conference Publishing Services. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding the page limit, or not appropriately structured may not be considered. Authors may contact the conference chairs for more information.

The paper submission online system is

General Chairs:
Jesús Carretero (University Carlos III of Madrid, Spain)
Manish Parashar (Rutgers University, USA)

Program Chairs:
Franck Cappello, (Argonne National Laboratory and University of Illinois at Urbana, USA) Geoffrey Charles Fox (Indiana University, USA)
Javier Garcia-Blas (University Carlos III of Madrid, Spain)

Honorary Chair:
Mateo Valero, Barcelona Supercomputing Center, Spain