Call for Papers: Non-Volatile Memory Workshop 2017

Non-Volatile Memory Workshop 2017
University of California, San Diego, USA
March 12-14, 2017

The submission deadline: December 2, 2016
Notification of acceptance: January 23, 2017

The 8th Annual Non-Volatile Memories Workshop (NVMW 2017) provides a unique showcase for outstanding research on solid state, non-volatile memories. It features a “vertically integrated” program that includes presentations on devices, data encoding, systems architecture, and applications related to these exciting new data storage technologies. Last year’s workshop (NVMW 2016) included 40 speakers from top universities, industrial research labs, and device manufacturers and attracted nearly 230 attendees. (The website for NVMW 2016 can be found at NVMW 2017 will build on this success.

The organizing committee is soliciting presentations on any topic related to non-volatile, solid state memories, including:
– Advances in memory devices or memory cell design.
– Characterization of commercial or experimental memory devices.
– Error correction and data encoding schemes for non-volatile memories.
– Advances in non-volatile memory-based storage systems.
– Operating system and file system designs for non-volatile memories.
– Security and reliability of solid-state storage systems.
– Applications of non-volatile memories to scientific, “big data”, and high-performance workloads.
– Implications of non-volatile memories for applications such as databases and NoSQL systems.

The goal is to facilitate the exchange of the latest ideas, insights, and knowledge that can propel future progress. To that end, presentations may include new results or work that has already been published during the 18 months prior to the submission deadline. In lieu of printed proceedings, we will post the slides and extended abstracts of the presentations online. Presentation of new work at the workshop does not preclude future publication.

Workshop submissions should be in the form of a 2-page presentation abstract. Submissions will be evaluated on the basis of impact, novelty, and general interest.

Further details on abstract submission, technical program, tutorials, travel, social program, and travel grant will be provided on this website.

Paul Siegel, UCSD ECE/CMRR
Eitan Yaakobi, Technion
Steven Swanson, UCSD CSE
Hung-wei Tseng, NC State University

Call for Papers: IEEE Transactions on Multi-Scale Computing Systems, Special Issue on Emerging Technologies and Architectures for Manycore Computing

IEEE Transactions on Multi-Scale Computing Systems
Special Issue on Emerging Technologies and Architectures for Manycore Computing

Open for submissions in ScholarOne Manuscripts: October 1, 2016
Closed for submissions: December 1, 2016
Results of first round of reviews: March 1, 2017
Submission of revised manuscripts: April 1, 2017
Results of second round of reviews: May 1, 2017
Publication materials due: June 1, 2017

The pursuit of Moore’s Law is slowing and the exploration of alternative devices is underway to replace the CMOS transistor and traditional architectures at the heart of data processing. Moreover, the emergence of stringent application constraints, particularly those linked to energy consumption, require new system architectural strategies (e.g. manycore) and real-time operational adaptability approaches. Such complex systems require new and powerful design and programming methods to ensure optimal and reliable operation. This special issue aims at collating new research along all the dimensions of emerging technologies and architectures for computing in manycores.

The topics of interest include, but are not limited to:
– Emerging on-chip computing technologies and architectures
– Many-core architecture customization, heterogeneous architectures
– Runtime resource management (energy, memory, reliability …)
– Programming models, languages, compilers and virtualization techniques for new computing paradigms

Prospective authors are invited to submit their manuscripts electronically after the “open for submissions” date, adhering to the /IEEE Transactions on Multi-Scale Computing Systems/ guidelines ( Please submit your papers through the online system ( and be sure to select the special issue name. /Manuscripts should not be published or currently submitted for publication elsewhere/. Please submit only full papers intended for review, not abstracts, to the ScholarOne portal.

Sébastien Le Beux, Ecole Centrale de Lyon (France)
Paul V. Gratz, Texas A&M University (USA)
Ian O’Connor, Ecole Centrale de Lyon (France)

Call for Workshops and Tutorials: ISPASS 2017

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2017)
San Francisco Bay Area, California, USA
April 23-25, 2017

– Deadline for submission: December 1, 2016, 11:59 PM EDT
– Notification of acceptance: December 8, 2016

The 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2017) is seeking proposals for workshops and tutorials to accompany the conference. Workshops and tutorials will be held on Sunday, April 23, and may be a half day or a full day in length.

We encourage members of the community to consider submitting proposals for workshops and tutorials that bring together researchers and practitioners working on research topics of significant current interest to the ISPASS community.

Prospective workshop and tutorial organizers are invited to submit proposals by completing the online submission form:

Selection committee:
The workshop proposals will be evaluated by members of the ISPASS 2017 organizing committee.

For questions, please contact the Workshops and Tutorials chair, Michael Ferdman (

Call for Papers: SPAA 2017

29th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2017)
co-located with PODC 2017
Washington D.C., USA
July 24 – 26, 2017

– Submission deadline for Regular papers: February 9, 11:59pm EDT
– Submission deadline for Brief announcements: February 9, 11:59pm EDT
– Rebuttal period: March 27-30, 11:59pm EDT
– Notification: April 23
– Camera-ready copy due: May 23

Submissions are sought in all areas of parallel algorithms and architectures, broadly construed, including both theoretical and experimental perspectives. Topics of interest include, but are not limited to:
– Parallel and Distributed Algorithms
– Parallel and Distributed Data Structures
– Algorithmic Game Theory
– Scheduling in Parallel Systems
– Parallel/Distributed Issues in Big Data
– Parallel and Distributed Architectures and I/O
– Streaming Algorithms
– Collaborative Learning Algorithms
– Network Algorithms
– Algorithms for Social Networks
– Multiprocessor and Multicore Architectures
– Transactional Memory Hardware and Software
– Algorithms for GPUs and Other Alternative Parallel Architectures
– High-Performance Parallel Computing and Architectures
– Green & Power-Efficient Algorithms and Architectures
– Instruction Level Parallelism and VLSI
– Biological Distributed Algorithms
– Mobile, Ad-Hoc, Wireless and Sensor Networks
– Algorithms for Routing and Information Dissemination
– Peer-to-Peer Systems
– Compilers and Tools for Concurrent Programming
– Fault-tolerance and Reliability
– Self-stabilization and Self-organization
– Security and Privacy in Distributed and Parallel Systems
– Parallel/Distributed Computational Learning
– Parallel Complexity Theory
– Specification and Verification of Concurrent Systems
– Resource Management and Awareness

Regular papers should report on original research, submitted exclusively to this conference. Submissions may not exceed ten (10) single-spaced double-column pages. (Papers will be judged based on their quality and not their length — short papers are welcome.) The title page, bibliography and designated figure pages (containing only figures) are not counted toward the ten pages. (Illustrative figures are encouraged.) All necessary details to substantiate the main claims of the paper should be included in a clearly marked appendix. Regular papers will be allotted up to 10 pages in the proceedings.

SPAA also solicits brief announcements that raise issues of interest to the SPAA community. Brief announcements may not exceed three pages and their titles should start with “Brief Announcement:’’. Examples of good brief announcements include: (i) papers previously published elsewhere of interest to SPAA, (ii) work in progress, (iii) announcement of tools/libraries, (iv) challenge problems posed to the community, (v) corrections to earlier results. Brief announcements may also include smaller results of interest.

All regular rejected papers automatically will be considered for brief announcements. Titles of regular papers which do not want to be considered for this option should start with “Full Paper ONLY:’’. Brief announcements will be allotted up to 3 pages in the proceedings.

Submitted manuscripts may not exceed ten (10) single-spaced double-column pages for regular papers and three (3) single-spaced double-column pages for brief announcements, using 10-point size font on 8.5×11 inch pages, not counting the title page, bibliography and designated figure pages ). The title page should contain the title, author names and affiliations, followed by a brief abstract. See (version 2.8, May 2015)
for details, including the sig-alternate-05-2015.cls style file and a sample file. Additional details may be added in a clearly marked appendix that will be read at the discretion of the program committee. Please indicate in the title of your manuscript whether this is a regular paper or a brief announcement.

Regular papers submitted to SPAA may not be under simultaneous consideration for a journal or any conference or workshop with published proceedings (other than as a brief announcement for a previous conference).
Authors are encouraged to post full versions of their submissions in a freely accessible on-line repository such as the arxiv, the ECCC, or the Cryptology ePrint archive. We expect that authors of accepted regular papers will make full versions of their papers, with proofs, available by the camera-ready deadline. (This should be done in a manner consistent with the ACM Copyright Policy.)
The deadline for ALL submissions is February 9.


General Chair:
Christian Scheideler, University of Paderborn

PC Chair:
Mohammad T. Hajiaghayi, University of Maryland, College Park

Program Committee:
Umut Acar Carnegie Mellon University
Susanne Albers Technical University of Munich
Hossein Asadi Sharif University of Technology
Nikhil Bansal Eindhoven University of Technology
Hossein Bateni Google Research
Petra Berenbrink Simons Fraser University
Keren Censor-Hillel Technion
Hubert Chan The University of Hong Kong
Rajesh Chitnis Weizmann Institute of Science
Frank Dehne Carleton University
Martin Farach-Colton Rutgers University
Pierre Fraigniaud CNRS and University Paris Diderot
Mohsen Ghaffari ETH Zurich
Michael Goodrich University of California, Irvine
Fabrizio Grandoni IDSIA
Mohammad Hajiaghayi (chair) University of Maryland, College Park
Martin Hoefer MPI Informatik, Saarbrücken
Samir Khuller University of Maryland
Ravi Kumar Google Research
Silvio Lattanzi Google Research
Aleksander Madry MIT
Friedhelm Meyer auf der Heide Paderborn University
Vahab Mirrokni Google Research
Morteza Monemizadeh Rutgers University
Seffi Naor Technion
Boaz Patt-Shamir Tel Aviv University
Giuseppe Persiano Università di Salerno
Cynthia A Phillips Sandia National Laboratories
Yuval Rabani The Hebrew University of Jerusalem
Rachid Guerraoui EPFL
Harald Raecke TU München
Rajmohan Rajaraman Northeastern University
Mauricio Resende Amazon
Laura Sanità University of Waterloo
Alex Slivkins Microsoft Research, NYC
Peter Varman Rice University
Roger Wattenhofer ETH Zurich
Ryan Williams Stanford University and MIT
David Woodruff IBM Almaden Research Center

Call for Contributions: Workshop on Pioneering Processor Paradigms

Call for Contributions: First Workshop on Pioneering Processor Paradigms (WP3)
in conjunction with HPCA’16
Austin, Texas, USA
February 4, 2017

– Submission deadline: November 27, 2016
– Notification of acceptance: December 11, 2016
– Final paper submission: January 8, 2017
– Workshop date: February 4, 2017

In trying to forge a path of innovation, it is sometimes worth examining the past to look for major paradigm shifts in (micro)-architecture, circuits, modeling and software that helped us keep going in the face of past technology-driven disruption points. With this in mind, we present a new workshop pioneering processor paradigms (P3). With the help of true pioneers as well as budding new researchers, P3 will take a retrospective look at how past technological hurdles were circumvented through major innovations. The goal is to learn from the past in devising new solution strategies for the future.

The P3 workshop will offer a number of invited talks from true pioneers as well as reviewed selections from the new generation of researchers and teachers who are eager to take a retrospective look into surveying past pioneering work that can teach us a lesson about solution strategies of the future.

The workshop on pioneering processor paradigms invites survey (or tutorial)-like submissions for review. The ideal paper would highlight a single pioneering paper (or set of papers) constituting a major processing, design, modeling or software paradigm shift in the past. In addition to explaining the context and basic concepts articulated in such work, the author(s) should draw relevant conclusions about how this pioneering work could or should influence computing paradigms of the future.

Note: Ph.D dissertation research topic proposals from (junior graduate students) that contain a survey of a key paper or two to build up the motivational justification of the proposal are quite welcome, for example.

Example topic areas include (but are not limited to):
– Processing and cache taxonomy papers.
– RISC architectures and CISC-to-RISC dynamic translation support.
– Processor pipelining, super scalar processing and branch prediction innovations.
– Register renaming, out-of-order execution and precise interruption.
– Cycle-accurate processor performance modeling.
– Innovations in floating point arithmetic units and vector/SIMD acceleration.
– VLIW architectures.
– Multi-threading, multiscalar and speculative multi-threading.
– Homogeneous and heterogeneous multi-core processors; accelerator-enabled efficiency boost.
– Power, temperature, and reliability-aware computing – with associated modeling innovations.
– Compiler innovations in support of novel microarchitectural paradigms.
– Circuit design innovations in support of (micro)-architectural paradigm shifts.

John-David Wellman, IBM
Robert Montoye, IBM
Ramon Bertran, IBM
Pradip Bose, IBM

Call for Papers: ISCA 2017

The 44th ACM/IEEE International Symposium on Computer Architecture (ISCA)
Toronto, ON, Canada
June 24-28, 2017

– Abstract Deadline: November 11, 2016, 11:59:59PM EST (Mandatory)
– Final Submission Deadline: November 18, 2016, 11:59:59PM EST no extensions
– Rebuttal Period: Early/mid February, 2017
– Author Notification: March 8, 2017
– Final Manuscript Submission: May 1, 2017
– Early Registration Deadline: May 1, 2017

Submissions Site:

The International Symposium on Computer Architecture is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. Papers are solicited on a broad range of topics, including (but not limited to):
– Processor, memory, and storage systems architecture
– Parallel and multicore systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Accelerator-based architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems

– General Chair: Andreas Moshovos, University of Toronto
– Program Chair: David Brooks, Harvard University
– Finance Chair: Mike Ferdman, University of New York, Stony Brook
– Tutorials Chair: Paul Gratz, Texas A&M
– Workshops Chair: TBD
– Publicity Chair: Christina Delimitrou, Cornell University
– Web and Social Media Chair: Gennady Pekhimenko, MSR and University of Toronto
– Publications Chair: Mahdi Bojnordi, University of Utah
– Student Travel Awards Chair: Natalie Enright Jerger, University of Toronto
– Registrations Chair: Adrian Sampson, Cornell University
– Industry Laison Chair: José F. Martínez, Cornell University

Program Committee:
Aamer Jaleel – Nvidia
Abdullah Muzahid – UT San Antonio
Abhishek Bhattacharjee – Rutgers
Adrian Sampson – Cornell
Alper Buyuktosunoglu – IBM
Antonia Zhai – U.Minnesota
Antonio Gonzalez – UPC
Babak Falsafi – EPFL
Benjamin Lee – Duke
Carole-Jean Wu – Arizona State
Chia-Lin Yang – National Taiwan University
Chris Batten – Cornell
Chris Wilkerson – Intel
Christina Delimitrou – Cornell
Daniel Sorin – Duke University
Daniel Sanchez – MIT
Debbie Marr – Intel
Doug Burger – Microsoft
Drew Hilton – Duke
G. Edward Suh – Cornell
Emre Ozer – ARM Research
Hadi Esmaeilzadeh – Georgia Tech
James Hoe – CMU
Jangwoo Kim – POSTECH
Josep Torrellas – UIUC
Jun Yang – Pittsburgh
Jung Ho Ahn – Seoul National University
Karu Sankaralingam – Wisconsin
Kei Hiraki – U.Tokyo
Kim Hazelwood – Facebook
Koji Inoue – Kyushu University
Kunle Olukotun – Stanford
Lieven Eeckhout – Ghent Univ.
Lingjia Tang – Michigan
Lisa Wu – Berkeley
Lizy John – UT Austin
Luis Ceze – Washington
Martha Kim – Columbia
Mattan Erez – UT Austin
Michael Ferdman – Stony Brook University
Michael Taylor – UCSD
Mike O’Connor – Nvidia
Moinuddin Qureshi – Georgia Tech
Nam Sung Kim – UIUC
Natalie Enright-Jerger – U.Toronto
Omer Khan – Connecticut
Onur Mutlu – ETH
Paul Whatmough – Harvard
Paul Gratz – Texas A&M
Pierre Michaud – INRIA
Qiang Wu – Facebook
Rajeev Balasubramonian – Utah
Ramon Canal – UPC-Barcelona Tech
Ravi Iyer – Intel
Reetuparna Das – Michigan
Russ Joseph – Northwestern
Sally McKee – Chalmers University of Technology
Sandhya Dwarkadas – Rochester
Shih-Lien Lu – TSMC
Simha Sethumadhavan – Columbia/Chip Scan
Yakun Sophia Shao – Nvidia
Sreenivas Subramoney – Intel
Steve Swanson – UCSD
Tao Li – University of Florida/NSF
Vijay Janapa Reddi – UT Austin
Viji Srinivasan – IBM
Xiaoyao Liang – Shanghai Jiao Tong University
Xuehai Qian – USC
Yan Solihin – NSF/NC State
Yiannakis Sazeides – U. of Cyprus