Call for Papers: LCTES 2017

ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded systems (LCTES)
in conjunction with PLDI 2017
Barcelona, Spain
June 21-22, 2017

Paper submission: February 14, 2017
Author notification: March 31, 2017
Final version: April 15, 2017

LCTES provides a link between the programming languages and embedded systems engineering communities. Researchers and developers in these areas are addressing many similar problems, but with different backgrounds and approaches. LCTES is intended to expose researchers and developers from either area to relevant work and interesting problems in the other area and provide a forum where they can interact. To that end, LCTES ’17 solicits papers presenting original work on programming languages, compilers, tools, theory, and architectures that help in overcoming these challenges. Research papers on innovative techniques are welcome, as well as experience papers on insights obtained by experimenting with real-world systems and applications.

Papers are solicited on, but not limited to, the following topics in embedded systems:
– Programming language challenges, including:
      Domain-specific languages
      Features to exploit multicore, reconfigurable, and other emerging architectures
      Virtual machines, concurrency, inter-processor synchronization, and memory management
– Compiler challenges, including:
      Interaction between embedded architectures, operating systems, and compilers
      Support for enhanced programmer productivity, debugging and profiling
      Optimization for low power/energy, code and data size, and best-effort and real-time performance
– Tools for analysis, specification, design, and implementation, including:
      Hardware, system software, application software, and their interfaces
      Performance estimation, monitoring, and tuning
      Design space exploration tools
– Theory and foundations of embedded systems, including:
      Predictability of resource behaviour: energy, space, time
      Validation and verification, in particular of concurrent and distributed systems
– Novel embedded architectures, including:
      Design and implementation of novel architectures
      Workload analysis and performance evaluation
      Architecture support for new language features, virtualization, compiler techniques, debugging tools
      Architectural features to improve power/energy, code/data size, and predictability
– Mobile systems and IoT, including:
      Operating systems, compilers, and software tools for mobile and IoT devices
      Compiler and software tools for mobile and IoT systems
      Memory and IO techniques for mobile and IoT devices
– Empirical studies and their reproduction, and confirmation

Submissions must be in ACM proceedings format, 9-point type, and may not exceed 10 pages (all inclusive). Word and LaTeX templates for this format are available on the ACM website ( Submissions must be in PDF, printable on US Letter and A4 sized paper. To enable double-blind reviewing, submissions must adhere to two rules:
– author names and their affiliations should be omitted; and,
– references to related work by the authors should be in the third person (e.g., not “We build on our previous work …” but rather “We build on the work of …”).

However, nothing should be done in the name of anonymity that weakens the submission or makes the job of reviewing the paper more difficult (e.g., important background references should not be omitted or anonymized). Papers must describe unpublished work that is not currently submitted for publication elsewhere as discussed here. Authors of accepted papers will be required to sign an ACM copyright release.

Submission site:

All accepted papers will appear in the published proceedings. We expect to make a best paper award.

General Chair: Vijay Nagarajan, University of Edinburgh
Program Chair: Zili Shao, The Hong Kong Polytechnic University

Call for Papers: FCCM 2017

25th International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
Napa, CA USA
April 30-May 2, 2017

– Full Paper Submission Deadline: January 11, 2017 (extended)
– Short Paper Submission Deadline: January 18, 2017 (extended)
– Notification of Acceptance: March 1, 2017

The IEEE Symposium on Field Programmable Custom Computing Machines (FCCM) is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. For 25 years, FCCM has been the place to present papers on architectures, tools, and programming models for field programmable custom computing machines and applications that use such systems. Papers are solicited on the following topics related to Field Programmable Custom Computing Machines (FCCMs):

Abstractions, Architectures, and Programming Models:
– Novel reconfigurable architectures, including overlay architectures
– Architectures for high performance and/or low power computing
– Security enhancements for reconfigurable computing
– Volatile and non-volatile memory subsystems; stacked/hybrid memory cubes
– Clusters or large systems of reconfigurable devices

– Abstractions, programming models, and runtimes, including virtualization
– New languages and design frameworks for spatial or heterogeneous applications
– High-level synthesis and designer productivity in general
– Software-Defined-systems (SDN, SDR, frameworks for new domains)

– Run-time management of reconfigurable hardware
– System resilience/fault tolerance for reconfigurable hardware
– Evolvable, adaptable, or autonomous reconfigurable computing systems
– Security implications of run-time reconfiguration

– Applications built using new high level synthesis technologies
– Data center/cluster with reconfigurable applications
– New uses of run-time reconfiguration in applications-specific systems
– Applications that utilize reconfigurable technology for performance and efficiency
– Novel use of state-of-the-art commercial FPGAs

FCCM will accept 8-page papers for oral presentation and 4-page short papers for short oral and poster presentation. FCCM uses a double blind reviewing system. Manuscripts must not identify authors or their affiliations. An online submission link will be available on the FCCM website in late December. Papers should use the formatting template linked at the FCCM website.

Authors are encouraged to submit preliminary work using the 4-page format. This category is intended for new projects and early results. These submissions will be accepted one week later than the 8-page papers.

FCCM reviews submissions in two, separate streams: 8-page papers for oral presentation and 4-page papers for brief oral and poster presentation. Both appear in the published proceedings. All submissions are reviewed in English. Papers must meet the IEEE guidelines to be reviewed and published; links to templates are at the FCCM website.

FCCM 2017 will continue the tradition of having a best paper award. We will also invite the authors of the best papers to extend their work to be considered for publication in a special section of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS) for FCCM 2017. Send in your best work for consideration!

General Chair: Jason D. Bakos, University of South Carolina
Program Chair: Ron Sass, UNC-Charlotte
Finance Chair: Ken Eguro, Microsoft Research
Publications Chair: Greg Stitt, University of Florida
Sponsorships Chair: Jan Gray, Gray Research LLC
Publicity Chair: Kyle Rupnow, UIUC
Exhibitions and Demo Night: Nachiket Kapre, University of Waterloo

Call for Papers: FPL 2017

27th International Conference on Field Programmable Logic and Applications
Ghent, Belgium
September 4-8, 2017

Abstract and Title Submission Deadline (mandatory): March 19, 2017
Full Paper Submission Deadline: March 26, 2017

The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. During the past 26 years, many of the advances in reconfigurable system architectures, applications, embedded processors, design automation methods and tools were first published in the proceedings of the FPL conference series. The conference objective is to bring together researchers and practitioners from both academia and industry and from around the world.

Contributions within (but not limited to) the following five conference tracks are welcome:
– Architectures and Technology
– Applications and Benchmarks
– Design Methods and Tools
– Self-aware and Adaptive Systems
– Surveys, Trends and Education

Authors are invited to submit original and unpublished contributions as 6 page papers in IEEE double column format to be considered as regular papers. Submissions accepted as posters will have 4 pages and extended abstracts for PhD forum contributions appear with 2 pages in the proceedings. The conference proceedings will be published at IEEE Xplore. Authors of selected papers will be invited to submit extended versions to a special issue in ACM TRETS. All contributions must be submitted electronically in PDF format.

FPL’s PhD forum is intended as a venue for PhD students to present their work in progress and preliminary results in a special poster session to receive feedback from other researchers.

Use the SoftConf submission site ( to submit your paper. Please note that the submission of the full- and short-paper abstracts by the relevant deadline is mandatory and that deadlines are not going to be extended.

General Co-chairs
Dirk Stroobandt, Ghent University
Nele Mentens, KU Leuven

Program Co-chairs
Marco Santambrogio, Politecnico di Milano
Diana Göhringer, Ruhr University Bochum

Call For Papers: SYSTOR 2017

The 10th ACM International Systems and Storage Conference (SYSTOR)
Haifa, Israel
May 22-24, 2017

– Full and short paper submission: February 22, 2017
– Paper acceptance notification: March 29, 2017
– Poster submission: March 22, 2017
– Poster acceptance notification: April 5, 2017
– Highlights paper submission: March 29, 2017
– Camera-ready submission: April 26, 2017

SYSTOR has a broad scope, promoting experimental and practical computer systems research encompassing the following topics:
– Operating systems, computer architecture, and their interactions
– Distributed, parallel, and cloud systems
– Networked, mobile, wireless, peer-to-peer, and sensor systems
– Runtime systems and compiler/programming-language support
– File and storage systems
– Security, privacy, and trust
– Virtualization
– Embedded and real-time systems
– Fault tolerance, reliability, and availability
– Deployment, usage, and experience
– Performance evaluation and workload characterization

SYSTOR is a home for high-quality international systems research of a practical nature and welcomes both academic and industrial contributions. We solicit paper submissions in the following categories:
– Full Papers track – original research, at most 10 pages without the references
– Short Papers Track – original research, at most 5 pages without the references
– Highlight Papers Track – papers accepted at top-tier conferences
– Posters Track – original work presented as poster accompanied by the extended abstract

SYSTOR 2017 will host distinguished keynote speakers, a poster session, and several social events at the conference. Our goal is to provide an excellent forum for interaction across the systems community: international, academic, and industrial, for both students and more established members.

Formatting and submission instructions:

General Chair:
Doron Chen (IBM Research)

PC Co-Chairs:
Peter Desnoyers (Northeastern University)
Eyal de Lara (University of Toronto)

Publications Chair:
Aviad Zuck (Technion)

Poster Chair:
Adam Morrison (Tel-Aviv University)

Publicity Chair:
Moshik Hershcovitch (IBM Research)

Steering Committee Head:
Michael Factor (IBM Research)

Steering Committee:
Ethan Miller (University of California Santa Cruz)
Liuba Shrira (Brandeis University)
Dan Tsafrir (Technion)
Dalit Naor (IBM Research)

Call for Participation: Learning gem5 Tutorial

Learning gem5 Tutorial
in conjunction with HPCA 2017
Austin, USA
February 5, 2017

We will be holding a Learning gem5 Tutorial and a gem5 coding sprint at HPCA 2017 on February 5th in Austin, TX. The morning will consist of a “Learning gem5” half-day course. In the afternoon, we invite all gem5 developers senior, junior, and new developers to a “coding sprint.”

Morning: Learning gem5 tutorial is a half-day course on getting started with gem5. The goal is to leave the course with a solid foundation so you can be more productive using gem5 to explore your research aims. The main audience is first or second year computer architecture students who are interested in using gem5 for their graduate studies. Anyone who wants to learn basic gem5 best-practices are encouraged to attend.

Afternoon: During the gem5 coding sprint we will have a number of small projects that can be completed in an afternoon for developers to tackle. These are perfect opportunities to get started giving back to the gem5 community. We will pair senior developers with new contributors so you can get a feel for how the development community functions. Everyone is invited to participate.

Additional details can be found at the event web site.

Call for Paper: ICS 2017

International Conference on Supercomputing (ICS 2017)
Chicago, USA
June 14-16, 2017

IMPORTANT DATES (all deadlines are Anywhere on Earth)
Abstract submission: January 11, 2017
Paper submission: January 18, 2017
Author rebuttal period: March 5-7, 2017
Author notification: March 21, 2017
Camera-ready papers due: April 15, 2017

ICS is the premier international forum for the presentation of research results in high-performance computing. Papers are solicited on all aspects of research, development, and application of high-performance computing systems, including but not limited to the following:

– Computer architecture and hardware, including multicore, manycore and multiprocessor systems from small to very large scales, components in such systems such as accelerators, memory systems, storage architectures, interconnection networks at various levels, and heterogeneous systems

– Programming and execution models for high-performance computing, including new paradigms, languages, task creation and specification models, domain-specific language/programming support

– Static and dynamic compilation: optimization techniques to exploit all aspects of high performance architectures and auto-tuning techniques

– Runtime and system software support for high-performance computing, including task and resource management at chip-level, cluster-level, up to the level of large-scale academic/commercial computing service infrastructure, debugging, fault-tolerance, power/energy management, file systems, and performance evaluation/monitoring

– New computational algorithms and their applications for high performance computing systems

– Workload characterization empirical studies especially those on new scientific and commercial applications that pose significant challenges, and studies of highly experimental real systems

– Data intensive high performance computing: system support, algorithm design and application development for high performance computing that deal with large-scale collected data sets.

The review process will include a rebuttal period, and the papers will be judged based on novelty, technical soundness, and potential impact on the field.

Submissions should be a maximum of ten (10) pages, including references. Submissions (both abstract and paper) should be prepared for double blind review, i.e., without author names, or other identifying material in the submission. Authors should refer to themselves in the 3rd person when citing their own work. Further details available on the conference web site.

General Co-Chairs:
William Gropp, University of Illinois, Urbana-Champaign
Pete Beckman, Argonne National Laboratory / Northwestern University

Program Co-Chairs
Zhiyuan Li, Purdue University
Francisco J. Cazorla, Barcelona Supercomputing Center

Call for Papers: HPDC 2017

The 26th International ACM Symposium on High-Performance Parallel and Distributed Computing (HPDC)
Washington D.C., USA
June 26-30, 2017

Abstracts (required) due: January 10, 2017
Full Papers due: January 17, 2017 (no extensions)
Author notifications: March 29, 2017
Camera Ready: April 12, 2017

The ACM International Symposium on High-Performance Parallel and Distributed Computing (HPDC) is the premier annual conference for presenting the latest research on the design, implementation, evaluation, and the use of parallel and distributed systems for high-end computing.

Submissions are welcomed on high-performance parallel and distributed computing (HPDC) topics including but not limited to: clouds, clusters, grids, big data, massively multicore, and extreme-scale computing systems. Submissions that focus on the operating systems, runtime environments, architectures, and networks of high end computing systems are particularly encouraged. Experience reports of operational deployments that provide significantly novel insights for future research on HPDC applications and systems will also receive special consideration. All papers will be evaluated for their originality, technical depth and correctness, potential impact, relevance to the conference, and quality of presentation. Research papers must clearly demonstrate research contributions and novelty, while experience reports must clearly describe lessons learned and demonstrate impact.

In the context of high-performance parallel and distributed computing, the topics of interest include, but are not limited to:
– Operating systems, networks, and architectures
– High performance runtime environments
– Massively multicore systems, including heterogeneous systems
– Datacenter technology, resource virtualization
– Programming languages, APIs, and system interoperation approaches
– File and storage systems, I/O, and data management
– Big data stacks and big data ecosystems
– Resource management and scheduling, including energy-aware techniques
– Performance modeling, analysis, and engineering
– Fault tolerance, reliability, and availability
– Operational guarantees, and risk assessment and management
– Traditional and emerging applications and services that depend upon high-end computing

Authors are invited to submit technical papers of at most 12 pages in PDF format, including figures and references. Papers should be formatted in the ACM Proceedings Style and submitted via the conference web site. Accepted papers will appear in the conference proceedings, and will be incorporated into the ACM Digital Library. A limited number of papers will be accepted as posters.

Papers must be self-contained and provide the technical substance required for the program committee to evaluate their contributions. Submitted papers must be original work that has not appeared in and is not under consideration for another conference or a journal. See the ACM Prior Publication Policy for more details. Papers can be submitted at

General Co-Chairs:
Howie Huang, George Washington University, USA
Jon Weissman, University of Minnesota, USA

Program Co-Chairs:
Adriana Iamnitchi, University of South Florida, USA
Alexandru Iosup, TU Delft and Vrije Universiteit Amsterdam, the Netherlands

Program Committee:
Sameer Al-Kiswany, University of Waterloo, Canada
Gabriel Antoniu, INRIA, Rennes, France
Henri Bal, Vrije Universiteit Amsterdam, the Netherlands
Michela Becchi, University of Missouri, USA
Patrick Bridges, University of New Mexico, USA
Ali Butt, Virginia Tech, USA
Franck Cappello, Argonne National Laboratory, USA
Abhishek Chandra, University of Minnesota, USA
Andrew A. Chien, University of Chicago and Argonne National
Laboratory, USA
Frederic Desprez, INRIA, France
Peter Dinda, Northwestern University, USA
Dick Epema, Delft University of Technology, the Netherlands
Gilles Fedak, INRIA/ENS Lyon, France
Renato Figueiredo, University of Florida, USA
Liana Fong, IBM, USA
Haryadi Gunawi, University of Chicago, USA
Salim Hariri, University of Arizona, USA
David Irwin, University of Massachusetts at Amherst, USA
John (Jack) Lange, University of Pittsburgh, USA
Adrien Lebre, French Institute for Research in Computer Science, France
Jay Lofstead, Sandia National Laboratories, USA
Arthur Maccabe, Oak Ridge National Laboratory, USA
Satoshi Matsuoka, Tokyo Inst. Technology, Japan
Alberto Montresor, University of Trento, Italy
Christine Morin, INRIA, France
Radu Prodan, University of Innsbruck, Austria
Matei Ripeanu, University of British Columbia, Canada
Martin Schulz, Lawrence Livermore National Lab, USA
Yogesh Simmhan, Indian Institute of Science, India
Evgenia Smirni, College of William and Mary, USA
Shuaiwen Leon Song, Pacific Northwest National Lab, USA
Michela Taufer, University of Delaware, USA
Kenjiro Taura, The University of Tokyo, Japan
Douglas Thain, University of Notre Dame, USA
Ana Lucia Varbanescu, University of Amsterdam, the Netherlands
Rich Wolski, University of California at Santa Barbara, USA
Ming Zhao, Arizona State University, USA

Steering Committee:
Franck Cappello, Argonne National Lab, USA and INRIA, France
Peter Dinda, Northwestern University
Salim Hariri, University of Arizona
Dean Hildebrand, IBM Research Almaden
Jack Lange, University of Pittsburgh
Arthur Maccabe, Oak Ridge National Lab
Manish Parashar, Rutgers University
Kenjiro Taura, The University of Tokyo, Japan
Michela Taufer, University of Delaware
Douglas Thain, University of Notre Dame
Jon Weissman, University of Minnesota (Chair)
Dongyan Xu, Purdue University

Call for Papers: IEEE Symposium on Computer Arithmetic

24th IEEE Symposium on Computer Arithmetic (ARITH)
July 24-26, 2017
London, UK

Paper submission deadline: Dec 31, 2016
Acceptance notification: Mar 31, 2017
Deadline for upload of final versions: Apr 30, 2017
Early registration deadline: Jun 1, 2017

Since 1969, the ARITH symposia have served as the flagship conference for presenting scientific work on the latest research in computer arithmetic. Authors are invited to submit papers describing recent advances on all aspects of computer arithmetic and its applications or implementations. This includes, but is not restricted to, the following topics:
– Arithmetic processor design and implementation
– Arithmetic algorithms and their analysis
– Floating-point units, algorithms, and numerical analysis
– Elementary and special function implementations
– Power-efficient or low-energy arithmetic units and processors
– Industrial implementation of arithmetic units and processors
– Test, validation, and formal verification techniques for arithmetic implementations
– Fault/error-tolerance in arithmetic implementations
– Arithmetic for FPGAs and reconfigurable logic
– Design automation for computer arithmetic implementations
– Computer arithmetic for security and cryptography
– Arithmetic to enhance accuracy or reliability (multiple-precision, interval arithmetic, …)
– Arithmetic challenges in HPC and exascale computing (accuracy, reproducibility, …)
– Arithmetic for specific application domains (big-data analytics, signal processing, computer graphics, multimedia, computer vision, finance, …)
– Computer arithmetic in emerging technologies
– Non-conventional computer arithmetic and applications

A PDF version of the full paper should be submitted no later than December 31st, 2016. Papers under review elsewhere are not acceptable for submission to ARITH. By submitting a paper you implicitly confirm you are solely submitting it to ARITH. Authors will be notified of acceptance in March 2017, and final camera-ready papers will be due in May 2017.

The final submissions of accepted papers cannot exceed 8 pages (NO extra pages) using the IEEE Computer Society Conference format (two columns). However, for review, authors may submit a paper with a maximum of 20 pages, 12pt font size, single column and double spacing.

Submission site:

General Chairs:
Neil Burgess, ARM, UK

Program Chairs:
Javier Bruguera, ARM, USA
Florent de Dinechin, INSA Lyon, France

Call for Papers: JLPEA special issue on Emerging Network-on-Chip Architectures for Low Power Embedded Systems

Journal of Low Power Electronics and Applications (JLPEA)
Special issue on Emerging Network-on-Chip Architectures for Low Power Embedded Systems

Deadline for manuscript submissions: January 31, 2017

Network-on-Chip emerged in recent years as a viable solution for the design of manycore embedded systems of the next generation. However, communication infrastructure scalability, memory bottleneck and parallelization of tasks, just to cite few examples, are becoming the limiting factors that hardware designers and software developers will be facing in the upcoming years.

This Special Issue on “Emerging Network-on-Chip Architectures for Low Power Embedded Systems” will focus on emerging approaches and recent advances on architectures, design techniques, modeling and prototyping solutions for the design of power/performance efficient Network-on-Chip systems in the manycore era.

Guest Editor: Prof. Dr. Davide Patti

Call for Papers: Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era

The 3rd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB 2017)
in conjunction with the HPCA 2017
Austin, Texas, USA
February 5, 2017

IMPORTANT DATES (All deadlines are 11:59 p.m. anywhere on Earth)
Paper submission due: 7 December, 2016
Notification of acceptance: 3 January, 2017
Early Registration due: 6 January, 2017
Camera-ready papers due: 10 January, 2017
Workshop date: 5 February, 2017

By the year 2023, High-Performance Computing (HPC) Systems are expected to break the performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at current levels (or increases marginally), what is known as the Exascale challenge. In addition, more storage capacity and data-access speed is demanded to HPC clusters and datacenters to manage and store huge amounts of data produced by software applications, what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data challenges are driving the technological revolution of this decade, motivating big research and development efforts from industry and academia. In this context, the interconnection network plays an essential role in the architecture of HPC systems and datacenters, as the number of processing or storage nodes to be interconnected in these systems is very likely to grow significantly to meet the higher computing and storage demands. Besides, the capacity of the network links is expected to grow, as the roadmaps of several interconnect standards forecast. Therefore, the interconnection network should provide a high communication bandwidth and low latency, otherwise the network becoming the bottleneck of the entire system. In that regard, many design aspects are considered when it comes to improving the interconnection network performance, such as topology, routing algorithm, power consumption, reliability and fault tolerance, congestion control, programming models, control software, etc.

The main goal of the third edition of HiPINEB is to gather and discuss in a full-day event the latest and most prominent efforts and advances, both from industry and academia, in the design and development of scalable high-performance interconnection networks, especially those oriented to meet the Exascale challenge and Big-data demands.

The list of topics covered by this workshop includes, but is not limited to, the following:
– Interconnect architectures and network technologies for high-speed, low-latency interconnects.
– Scalable network topologies, suitable for interconnecting a huge number of nodes.
– Power saving policies in the interconnect devices and network infrastructure, both at software and hardware level.
– Good practices in the configuration of the network control software.
– Network communication protocols: MPI, RDMA, MapReduce, etc.
– APIs and support for programming models.
– Routing algorithms.
– Quality of Service (QoS).
– Reliability and Fault tolerance.
– Load balancing and traffic scheduling.
– Network Virtualization.
– Congestion Management.
– Applications and Traffic characterization.
– Modeling and simulation tools.
– Performance Evaluation.
– Interfacing accelerators through the interconnect (GPUs, Xeon Phi, etc).
– Network infrastructure in distributed storage, distributed databases and Big-Data.

Furthermore, short papers in the above topics will be also taken into consideration, as long as they are based on emerging ideas, work-in-progress and early, high-impact achievements.

Note, however, that papers focused on topics that are too far from the design, development and configuration of high-performance interconnects for HPC systems and Datacenters (e.g., mobile networks, intrusion detection, peer-to-peer networks or grid/cloud computing) will be automatically considered as out of scope and rejected without review.

Regular and short papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Submitted regular manuscripts may not exceed 8 single-spaced double-column pages using 10-point size font on 8.5×11 inch pages, including figures, tables, and references. Short papers may not exceed 4 single-spaced double-column pages using 10-point size font on 8.5×11 inch pages. At least one author of the paper must be registered for the conference workshop.

HiPINEB manuscript submissions are managed by easyChair. To submit a paper, go to and follow the instructions.

Authors are entitled to submit original papers of high technical quality, according to the list of topics described above. Papers will be reviewed based on originality, novelty, technical strength, presentation quality, correctness and relevance to the conference scope.

Papers will be published in the HiPINEB proceedings, edited by the IEEE CPS which will be submitted for indexing and inclusion in IEEE Xplore and CSDL.

Best papers among those selected for HiPINEB 2017 will be published in the Special Issue on “Trends in High-Performance Interconnection Networks in the Exascale and Big-Data Era 2017”, to be published in the Journal of Concurrency and Computation: Practice and Experience, Wiley, (2015 Impact Factor: 0.942). Further details in

– Keynote: Bill Dally, NVIDIA
– Technical sessions: Presentation of regular and short papers
– Panel: TBA

– Pedro Javier Garcia, University of Castilla-La Mancha, Spain
– Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain

Program Committee:
– Francisco J. Alfaro, University of Castilla-La Mancha, Spain
– Jose Cano-Reyes, University of Edinburgh, United Kingdom
– Lizhong Chen, Oregon State University, USA
– Nikolaos Chrysos, FORTH, Greece
– Holger Fröning, University of Heidelberg, Germany
– Maria Engracia Gomez, Technical University of Valencia, Spain
– Ernst Gunnar Gran, Simula Research Laboratory, Norway
– Ryan E. Grant, Sandia National Laboratories, USA
– Mitch Gusat, IBM Research, Switzerland
– Scott Hemmert, Sandia National Laboratories, USA
– John Kim, KAIST, South Korea
– Michihiro Koibuchi, National Institute of Informatics, Japan
– Yuho Jin, New Mexico State University, USA
– Pedro Lopez, Technical University of Valencia, Spain
– Jose Miguel Montañana, University of York, United Kingdom
– Gaspar Mora, Intel Corporation, USA
– Mondrian Nuessle, Extoll, Germany
– Julio Ortega, University of Granada, Spain
– Thibaut Palfer-Sollier, Numascale AS, Norway
– Dhabaleswar K. Panda, The Ohio State University, USA
– Matthieu Perotin, ATOS BULL, France
– Mikel Eukeni Pozo Astigarraga, CERN, Switzerland
– Samuel Rodrigo, Oracle Corporation, Norway
– Sebastien Rumley, Columbia University, USA
– Jose Luis Sanchez, University of Castilla-La Mancha, Spain
– Heiko Joerg Schick, Huawei Technologies, Germany
– Jörn Schumacher, CERN, Switzerland
– Alex Shpiner, Mellanox Technologies, Israel
– Evangelos Tasoulas, Simula Research Laboratory, Norway
– Francisco Triviño, Oracle Corporation, Norway
– Luis Tomas, Red Hat, Spain
– Enrique Vallejo, University of Cantabria, Spain
– Wainer Vandelli, CERN, Switzerland
– Pierre Vigneras, ATOS BULL, France