Call For Papers: MICRO 2017

The 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-50)
Boston, USA
Oct 14-18, 2017

Abstracts due: March 28, 2017
Papers due: April 4, 2017
Response period: June 1-14, 2017
Author notification: July 5, 2017

The International Symposium on Microarchitecture (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers — we aim to continue and strengthen this longstanding tradition at the 50th MICRO.

We invite original paper submissions related (but not limited) to the following topics:
– Processor, memory, interconnect, and storage architectures.
– Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, cost, complexity, predictability, quality of service, reliability, dependability, security, scalability, programmer productivity, etc.
– Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, manycore, etc.
– Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP).
– Low-power, high-performance, and cost/complexity-efficient architectures.
– Architectures for emerging platforms, including smartphones, cloud/datacenter, etc.
– Architectures and compilers for embedded processors, DSPs, GPUs, ASIPs (network processors, multimedia, wireless, deep learning, neuromorphic, etc.).
– Advanced software/hardware speculation and prediction schemes.
– Microarchitecture techniques to better support system software, programming languages, programmability, and compilation.
– Microarchitecture modeling and simulation methodology.
– Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads.

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