Call for contributions: FPL PhD Forum and Demo Night

Submitted by Mirjana Stojilovic

26th International Conference on Field-Programmable Logic and Applications (FPL)
Aug 29 – Sep 2, 2016
Lausanne, Switzerland

PhD Forum and Demo Night proposals deadline: May 8, 2016
Notifications: June 15, 2016


FPL 2016 PhD Forum is tailored for PhD students in two ways: Firstly,
it is an excellent occasion for PhDs to present their work in progress
or preliminary results, and receive early feedback from other
researchers in the domain. Secondly, it is a unique opportunity for
PhD students who are finishing their studies to give a broad overview
of their work and draw attention to it from both the academic and
industrial worlds.

PhD Forum authors are invited to submit 2-page papers using the format
of FPL 2016 regular papers. PhD Forum papers should include clear
descriptions of thesis motivation, objectives, problem definition,
addressed solutions, current status, and planned work. Contributions
based on preliminary results or on work in progress are particularly
encouraged. Accepted PhD Forum papers will be included in the
conference proceedings and presented at a special poster session.
Prior to this session, presenters will be offered the opportunity to
draw attention to their posters through a short “elevator pitch”
(2-minute presentation).


FPL 2016 Demo Night event is an excellent opportunity for conference
participants to demonstrate and disseminate their work, to increase
their visibility, and interact with attendees. Demonstrations may
include commercial and academic research-oriented tools, platforms,
systems, and more. The event will take place on one of the conference
evenings. Hors d’oeuvres and drinks will be offered to all attendees.

Demo Night presenters are invited to submit 1-page abstracts using the
same format as FPL 2016 regular papers. A cover page should be added
to the submission and should contain the following information:
– Demo title.
– Names and affiliations of all authors.
– Description of the main objectives and relevance of the demo to the
FPL community.
– Short biographies of demo presenters.
– Any logistical requirements the demonstration may have.

The 1-page abstract should include demo title, names and affiliations
of all authors, and an abstract of the demo. The authors of the
accepted demos will be asked to prepare a poster for the Demo Night.
All demo posters will be published on the FPL 2016 web page and the
abstracts will be included in the conference proceedings.

FPL PhD Forum and Demo Night chairs:
Mirjana Stojilović, University of Applied Sciences Western Switzerland
Yann Thoma, University of Applied Sciences Western Switzerland

Call for papers: WDDD 2016

Submitted by Karu Sankaralingam
June 19, 2016

Submitted by Karu Sankaralingam
12th Annual Workshop on Duplicating, Deconstructing and Debunking

12th Annual Workshop on Duplicating, Deconstructing and Debunking (WDDD)
Seoul, S. Korea
June 19, 2016

Abstract Submission: April 20, 2016
Paper Submission: April 22, 2016
Acceptance: May 14, 2016
Final Version: June 10, 2016

WDDD provides the computer systems research community a forum for work that
validates or duplicates earlier results; deconstructs prior findings by
providing greater, in-depth insight into causal relationships or correlations;
or debunks earlier findings by describing precisely how and why proposed
techniques fail where earlier successes were claimed, or succeed where failure
was reported.

Traditionally, computer systems research conferences have focused almost
exclusively on novelty and performance, neglecting an abundance of interesting
work that lacks one or both of these attributes. A significant part of
research–in fact, the backbone of the scientific method–involves independent
validation of existing work and the exploration of strange ideas that never
pan out. This workshop provides a venue for disseminating such work in our
community. Published validation experiments strengthen existing work, while
thorough comparisons provide new dimensions and perspectives. Studies that
refute or correct existing work also strengthen the research community, by
ensuring that published material is technically correct and has sound
assumptions. Publishing negative or strange or unexpected results will allow
future researchers to learn the hard lessons of others, without repeating
their effort.

This workshop will set a high scientific standard for such experiments, and
will require insightful analysis to justify all conclusions. The workshop will
favor submissions that provide meaningful insights, and identify underlying
root causes for the failure or success of the investigated technique.
Acceptable work must thoroughly investigate and communicate why the proposed
technique performs as the results indicate. WDDD has a unique tradition of
asking the original paper authors to provide a follow-up comment after the
WDDD paper has been presented, where appropriate. The follow-up comment may
take the form of a rebuttal or additional insight from the original authors.

In general, any topic that is of interest to computer architecture conferences
and related systems areas are of potential interest for WDDD, so long as the
paper is in the spirit of the themes of Duplication, Deconstruction, and/or

Topics of interest:
– Independent validation of earlier results with meaningful analysis
– In-depth analysis and sensitivity studies that provide further insight into
earlier findings, or identify key parameters or assumptions that affect the
– Studies that refute earlier findings, with clear justification and explanation
– Negative results for ideas that intuitively make sense and should work, along
with explanations for why they do not
– Validation/refutation of controversial advertising claims by industrial

Submit a manuscript of up to 10 pages in two-column format by April 22, 2016
using the submission website.

Murali Annavaram, USC
Karu Sankaralingam, University of Wisconsin – Madison
David Brooks, Harvard University
Gabriel Loh, AMD Research

Call for Participation: SELSE 2016

Submitted by William H. Robinson
March 29 to March 30, 2016

Submitted by William H. Robinson

The 12th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2016)
Austin, TX, USA
March 29 – 30, 2016

Early registration deadline: March 14th, 2016.

Keynote speakers:
SELSE 2016 will feature three keynote speeches by experts from
academia and industry.
– Dr. Krishna V. Palem, Rice University
Can the end of Moore’s Law result in new opportunities for computing?
– Dr. Nirmal Saxena, NVIDIA
Autonomous car is the new driver for resilient computing and
– Dr. Martin Roetteler from Microsoft Research
Quantum error correction and quantum algorithmic discovery

Panel Discussion:
We will have a very interesting panel on the topic of approximate computing
with experts from academia and industry. The panel discussion will explore
opportunities and challenges of approximate computing in the field of

Please do not forget to book your hotels early, as the hotel prices can
increase closer to the SELSE dates. You can find a list of nearby hotels
on the SELSE web page.

Travel grants:
We are very excited to offer, for the first time, travel grants to young
faculties, postdocs, and students. Please refer to SELSE web page for
application instructions. Submit your application by March 12th.

General Chairs:
Helia Naeimi, Intel
Dan Alexandrescu, iRoC

Program Chairs:
Sudhanva Gurumurthi, IBM/University of Virginia
Mattan Erez, The University of Texas at Austin

Finance Chairs:
Siva Hari, NVIDIA
Daniel Lowell, AMD

Publicity Chairs:
William H. Robinson, Vanderbilt University
Paolo Rech, UFRGS
Yiannakis Sazeides, University of Cyprus

Documents Chairs:
Mehdi Tahoori, Karlsruhe Institute of Technology
Mojtaba Ebrahimi, Karlsruhe Institute of Technology

Austin Industry Liaison:
Indrani Paul, AMD

Marios Kleanthous, Mesoyios College

Local Arrangements Chair:
Vijay Janapa Reddi, The University of Texas at Austin

Advisors to the Committee:
Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD
Adrian Evans, iRoC

Call for Papers: ASBD 2016

Submitted by xiufeng Sui
June 19, 2016

Submitted by xiufeng Sui

Sixth Workshop on Architectures and Systems for Big Data(ASBD 2016)
in conjunction with ISCA 2016
Seoul, S. Korea
June 18, 2016

Submissions deadline: April 10, 2016
Author notification: April 30, 2016

The term “Big Data” refers to the continuing massive expansion in the data
volume and diversity as well as the speed and complexity of data processing.
The use of big data underpins critical activities in all sectors of our
society. Achieving the full transformative potential of big data in this
increasingly digital world requires both new data analysis algorithms and
a new class of systems to handle the dramatic data growth, the demand to
integrate structured and unstructured data analytics, and the increasing
computing needs of massive-scale analytics.

We are pleased to request papers for presentation at the upcoming Sixth
Workshop on Architectures and Systems for Big Data (ASBD 2016) held in
conjunction with ISCA-43. The workshop will provide a forum to exchange
research ideas related to all critical aspects of emerging analytics systems
for big data, including architectural support, benchmarks and metrics, data
management software, operating systems, and emerging challenges and
opportunities. We hope to attract a group of interdisciplinary researchers
from academia, industry and government research labs. To encourage
discussion between participants, the workshop will include significant time
for interactions between the presenters and the audience. We also plan to
have a keynote speaker and/or panel session.

Topics of interest include but are not limited to:
– Processor, memory and system architectures for data analytics
– Benchmarks, metrics and workload characterization for big data
– Accelerators for analytics and data-intensive computing
– Implications of data analytics to mobile and embedded systems
– Energy efficiency and energy-efficient designs for analytics
– Availability, fault tolerance and data recovery in big data environments
– Scalable system & network designs for high concurrency/bandwidth streaming
– Data management and analytics for vast amounts of unstructured data
– Evaluation tools, methodologies and workload synthesis
– OS, distributed systems and system management support for large-scale
– Debugging and performance analysis tools for analytics and big data
– Programming systems and language support for deep analytics
– MapReduce and other processing paradigms for analytics

We encourage researchers from all institutions to submit their work for review.
Preliminary results of interesting ideas and work-in-progress are welcome.
Submissions that are likely to generate vigorous discussion will be favored!

All papers should be submitted in PDF format, using 10 point
or larger font for text (8 points or larger for figures and tables),
total length not to exceed 6 pages.
Submission site:

Workshop Co-Organizers:
Lixin Zhang, ICT/CAS China
Yungang Bao, ICT/CAS China

Program Co-Chairs:
John Kim, KAIST South Korea
Xiufeng Sui, ICT/CAS China

Program Committee:

Steering Committee:
Jian Li, Huawei
Jichuan Chang, Google
Evan Speight, IBM Research

Call for Participation: ASPLOS 2016

Submitted by Changhee Jung
April 2 to April 6, 2016

Submitted by Changhee Jung

The Twenty First International Conference on Architectural Support
for Programming Languages and Operating Systems (ASPLOS 2016)

Atlanta, Georgia, USA
April 2-6, 2016

– Travel Grant Application Deadline: March 1:

– Hotel Registration Deadline: March 11:

– Conference Early Registration Deadline: March 11:

Call for Papers: Emerging Technologies for Reconfigurable Systems in the Manycore Era

Submitted by Patti Davide
June 27 to June 29, 2016

Submitted by Patti Davide
Emerging Technologies for Reconfigurable Systems in the Manycore Era
Special session in Int’l Symposium on Reconfigurable Communication-centric SoC’s (ReCoSoC 2016)
Tallinn, Estonia
June 27-29, 2016

Abstract submission deadline: April 1, 2016
Full paper submission deadline: April 6, 2016
Author notification: May 15, 2016
Camera-ready due: June 5, 2016

Current multicore architectures formed by tens of processing cores will be
soon replaced by the next generation of manycore architectures with hundreds
of cores. Although manycore architectures are envisaged as the most effective
for meeting the energy and performance constraints which characterize future
applications, some technical and technology aspects start to exacerbate. Dark
silicon, memory wall, on-chip communication scalability, represent just a
short list. Emerging technologies, novel architectures and design techniques,
which stress the reconfiguration concept, are currently investigated by the
research community as viable opportunities for tackling the
performance-in-the-energy-envelop problem in the manycore era.

The aim of this Special Session is to bring together a group of leading
academic researchers and technology experts to provide a platform for
discussion on novel ideas and studies related to design, modelling and
analysis of reconfigurable manycore architectures based on emerging

Authors are invited to submit contributions as maximum 8 page papers in IEEE
conference format. ReCoSoC 2016 follows a double-blind review process:
author’s should not reveal their identity in the manuscript. Contribution(s)
have to be submitted electronically through the EasyChair portal of the
conference at

Davide Patti, Univ. of Catania, Italy,
Maurizio Palesi, Univ. of Enna – KORE, Italy,

Call for Participation: MobiTools Tutorial Co-located with ISCA 2016

Submitted by Yuhao Zhu
June 19, 2016

Submitted by Yuhao Zhu

MobiTools: Tutorial on Infrastructure and Tools for Mobile Computer
Architecture Research with an Emphasis on Real System Measurement

co-located with ISCA 2016
Seoul, Korea
June 19, 2016

The tutorial is a step to overcome the increasing barrier of entry for
conducting mobile computer architecture research. We present a series of tools
and infrastructures that enable computer system and architecture research in
the mobile computing space. The tutorial will span three key components of
mobile computing: software, hardware, and end-users. The tools that we will
cover strongly emphasize real system measurement, including performance,
power/energy, and user QoS experience.

Being co-located with ISCA provides an opportunity to have some great invited
speakers and an exciting panel: a great opportunity to see the masterminds
behind mobile computer architecture research.

MobiTools also invites mobile research tool developers to give a thirty minute
presentation about their tool and how to conduct productive research with it.
An ideal presentation will briefly introduce the tool and its underlying
mechanisms and then walk the audience through a (possibly hands on)
“quickstart” tutorial.

Call for Papers: Workshop on Cognitive Architectures

Submitted by Karthik Swaminathan
April 2, 2016 at 13:00

Submitted by Karthik Swaminathan

The 2nd Workshop on Cognitive Architectures (CogArch 2016)
co-located with ASPLOS 2016
Atlanta, Georgia, USA
April 2, 2016

Submission deadline: Feb 15, 2016
Notification: Feb 29, 2016
Camera ready deadline: Mar 30, 2016

Recent advances in Cognitive Computing Systems (as evidenced by innovations
like Watson from IBM and self-driving cars from Google), coupled with
neurally-inspired hardware designs (such as the IBM True North chip), have
spawned new research and development activity in machine learning,
neuromorphic and other brain-inspired computing models, and architectures for
efficient support of complex tasks in computer vision, speech recognition and
artificial intelligence. The proliferation of mobile computing platforms, IoT
and cloud support features thereof have opened up exciting new opportunities
for real-time, mobile (distributed or swarm-driven) cognition. This half-day
workshop solicits formative ideas and new product offerings in this general

Topics of interest include (but are not limited to):
– Algorithms in support of cognitive reasoning: recognition, intelligent
search, diagnosis, inference and informed decision-making.
– Swarm intelligence and distributed architectural support; brain-inspired and
neural computing architectures.
– Accelerators and micro-architectural support for cognitive computing.
– Cloud-backed autonomics and mobile cognition: architectural and OS support
– Resilient design of distributed (swarm) mobile cognitive architectures.
– Energy efficiency, battery life extension and endurance in mobile, cognitive
– Case studies and real-life demonstrations/prototypes in specific application
domains: e.g. Smart homes, connected cars and UAV-driven commercial services,
as well as applications of interest to defense and homeland security.

The workshop shall consist of short presentations by authors of selected
submissions. In addition, it will include invited keynotes by eminent
researchers from industry and academia as well as interactive panel
discussions to kindle further interest in these research topics. Submitted
papers will be reviewed by a workshop program committee, in addition to
the organizers. Submissions are limited to 6 pages, including references,
with same formatting guidelines as main conference.

Karthik Swaminathan, Augusto Vega, Alper Buyuktosunoglu, Pradip Bose –
IBM T.J Watson Research Center
Vijaykrishnan Narayanan – Pennsylvania State University

Call for Papers: Workshop on Heterogeneous and Unconventional Cluster Architectures and Applications

Submitted by Federico Silla
August 16, 2016

Submitted by Federico Silla

5th International Workshop on Heterogeneous and Unconventional
Cluster Architectures and Applications (HUCAA 2016)

in conjunction with ICPP 2016
Philadelphia, PA, USA
August 16, 2016

Paper submission: March 21, 2016
Notification of acceptance: May 13, 2016
Camera-ready paper: June 3, 2016
Workshop: August 16, 2016

The workshop on Heterogeneous and Unconventional Cluster Architectures and
Applications gears to gather recent work on heterogeneous and unconventional
cluster architectures and applications, which might have an impact on future
mainstream cluster architectures. This includes any cluster architecture that
is not based on the usual commodity components and therefore makes use of
some special hard- or software elements, or that is used for special and
unconventional applications. In particular we call for GPUs and other
accelerators (Intel MIC/Xeon Phi, FPGA) used at cluster level. Even though
accelerators are already used pervasively, we still see many unconventional
and even disruptive uses of them.

Other examples of unconventional cluster architectures and applications
include virtualization, in-memory storage, hard- and software interactions,
run-times, databases, and device-to-device communication. We are in
particular encouraging work on disruptive approaches, which may show inferior
performance today but can already point out their performance potential. The
broad scope of the workshop facilitates submissions on unconventional uses of
hardware or software, gearing to gather ideas that are coming to life now and
not limiting them except for their context: clusters. Also, these proposals
may rather be reflective of a broader industry trend.

Topics of interest include any heterogeneous or unconventional cluster
architecture or application. Examples include, but are not limited to:
– Clustered GPUs, Xeon Phis or other accelerators
– Runtimes, resource management and scheduling for heterogeneous cluster
– Communication methods for distributed or clustered accelerators
– Energy-aware data movement techniques
– Energy efficiency at the cluster or node level
– New industry and technology trends and their potential impact
– High-performance, data-intensive, and power-aware computing
– Application-specific cluster and datacenter architectures
– Emerging programming paradigms for parallel heterogeneous computing
– Software cluster-level virtualization for consolidation purposes
– Hardware techniques for resource aggregation
– New uses of GPUs, FPGAs, and other specialized hardware

Submissions may not exceed 8 pages in PDF format including figures and
references, and must be formatted in the 2-column IEEE format. Submitted
papers must be original work that has not appeared in and is not under
consideration for another conference or journal. Work in progress is welcome,
but first results should be made available as a proof of concept. Submissions
only consisting of a proposal will be rejected. Please visit the workshop
website for additional details.

Workshop Co-Chairs:
– Federico Silla, Technical University of Valencia, Spain
– Holger Fröning, U. Heidelberg, Germany

Program Committee:
– Tarek Abdelrahman, U. Toronto, Canada
– José Luis Abellán, Catholic University of Murcia, Spain
– Olivier Aumage, INRIA, France
– José María Cecilia, Catholic University of Murcia, Spain
– Pierfrancesco Foglia, University of Pisa, Italy
– Basilio Fraguela, U. Coruna, Spain
– Efstratios Gallopoulos, University of Patras, Greece
– Marc Gonzalez, Universitat Politecnica de Catalunya, Spain
– Sascha Hunold, Technical University of Vienna, Austria
– Christos Kartsaklis, Oak Ridge National Lab, US
– Christoph Kessler, Linköping University, Sweden
– Tomàs Margalef, U. Autonoma Barcelona, Spain
– Gaspar Mora, Intel, US
– Thu D. Nguyen, U. Rutgers, US
– Dimitrios S. Nikolopoulos, Queen’s University, Belfast, UK
– Lena Oden, Argonne National Labs, US
– Alberto Ros, University of Murcia, Spain
– Dirk Pleiter, Research Center Jülich, Germany
– Alistar Rendell, Australian National University, Australia
– Etienne Riviere, University of Neuchatel, Switzerland
– Won Ro, Yonsei University, South Korea
– Antonio Robles, Technical University of Valencia, Spain
– Douglas Thain, U. Notre Dame, US
– Matthew Jacob Thazhuthaveetil, Indian Institute of Science, India
– Blesson Varghese, U. St Andrews, UK
– Shuangyang Yang, Louisiana State University, US

Steering Committee:
– José Duato, Technical University of Valencia, Spain
– Sudhakar Yalamanchili, Georgia Tech, US
– Ulrich Brüning, U. Heidelberg, Germany

Call for Contributions: FPL 2016

Submitted by Kubilay Atasu
August 29 to September 2, 2016

Submitted by Kubilay Atasu

26th International Conference on Field-Programmable Logic and
Applications (FPL)

Lausanne, Switzerland
29th Aug – 2nd Sep, 2016

Abstract submission deadline: March 20, 2016
Paper submission deadline: March 27, 2016
Demo night, PhD forum, Workshops, and Tutorial submission deadline: May 8, 2016
Notifications: June 15, 2016 (approximate)
Final manuscript deadline: July 4, 2016

The International Conference on Field-Programmable Logic and Applications
(FPL) was the first and remains the largest conference covering the rapidly
growing area of field-programmable logic and reconfigurable computing.
During the past 25 years, many of the advances in reconfigurable system
architectures, applications, embedded processors, design automation methods
and tools were first published in the proceedings of the FPL conference
series. The conference objective is to bring together researchers and
practitioners from both academia and industry and from around the world.
FPL 2016 looks for contributions in the following areas:

Architectures and Technology
– FPGAs, GPUs and DSPs
– Heterogeneous datacentre/embedded computing
– Low power architectures
– Fault tolerant architectures
– Security and cryptography for FPGA Design
– 2.5D and 3D architectures
– Advanced on-chip interconnect technologies
– Analog and mixed-signal arrays
– Emerging technologies

Applications and Benchmarks
– Aerospace, automotive and industry automation
– Bioinformatics & medical systems
– Communications, software defined networking and Internet-of-Things
– Finance, HPC and database acceleration
– Big data analytics
– Embedded & cyber physical systems
– Signal processing and SDR
– Benchmarks for FPGA designs

Design Methods and Tools
– System-level design tools
– High-level synthesis
– Hardware / software co-design
– Logic optimization and technology mapping
– Optimizations for power efficiency
– Packing, placement and routing
– Rapid prototyping and emulation
– Testing, debugging and verification
– Open-source tools

Self-aware and Adaptive Systems
– Self-awareness in FPGA-based systems
– Self-adaptive architectures and design techniques
– Virtualization of reconfigurable hardware
– Runtime resource management
– Partial reconfiguration

Surveys, Trends, and Education
– Surveys on reconfigurable logic architectures and design techniques
– Deployment of FPGAs in new application domains
– Roadmap of reconfigurable computing platforms
– Teaching courses and tutorials

General Chairs:
Paolo Ienne, EPFL, CH
Walid Najjar, University of California Riverside, US

Programme Chairs:
Jason Anderson, University of Toronto, CA
Philip Brisk, University of California Riverside, US

Workshop and Tutorial Chairs:
Pierre-Emmanuel Gaillardon, University of Utah, US
Michael Huebner, University of Bochum, DE

PhD Forum and Demo Night Chairs:
Mirjana Stojilovic, HEIG-VD, CH
Yann Thoma, HEIG-VD, CH

Proceedings Chair:
Walter Stechele, TU München, DE

Publicity Chair:
Kubilay Atasu, IBM ZRL, CH

Local Arrangements Chair:
Chantal Schneeberger, EPFL, CH

Registration Chair:
Andrew J. Becker, EPFL, CH

Steering Committee:
Jürgen Becker, KIT Karlsruhe, DE
Koen Bertels, TU Delft, NL
Eduardo Boemo, Univ. Autónoma de Madrid, ES
João M. P. Cardoso, Universidade do Porto, PT
Peter Y. K. Cheung, Imperial College London, UK
Martin Danek, Daiteq, CZ
Apostolos Dollas, TU of Crete, GR
Fabrizio Ferrandi, Politecnico di Milano, IT
Manfred Glesner, TU Darmstadt, DE
John Gray, Consultant, UK
Reiner Hartenstein, TU Kaiserslautern, DE
Andreas Herkersdorf, TU München, DE
Udo Kebschull, Goethe University Frankfurt, DE
Wayne Luk, Imperial College London, UK
Patrick Lysaght, Xilinx, Inc., US
Jari Nurmi, Tampere University of Technology, FI
Lionel Torres, University of Montpellier II, FR
Jim Tørresen, University of Oslo, NO