Call for contributions: FPL PhD Forum and Demo Night

Submitted by Mirjana Stojilovic

26th International Conference on Field-Programmable Logic and Applications (FPL)
Aug 29 – Sep 2, 2016
Lausanne, Switzerland

PhD Forum and Demo Night proposals deadline: May 8, 2016
Notifications: June 15, 2016


FPL 2016 PhD Forum is tailored for PhD students in two ways: Firstly,
it is an excellent occasion for PhDs to present their work in progress
or preliminary results, and receive early feedback from other
researchers in the domain. Secondly, it is a unique opportunity for
PhD students who are finishing their studies to give a broad overview
of their work and draw attention to it from both the academic and
industrial worlds.

PhD Forum authors are invited to submit 2-page papers using the format
of FPL 2016 regular papers. PhD Forum papers should include clear
descriptions of thesis motivation, objectives, problem definition,
addressed solutions, current status, and planned work. Contributions
based on preliminary results or on work in progress are particularly
encouraged. Accepted PhD Forum papers will be included in the
conference proceedings and presented at a special poster session.
Prior to this session, presenters will be offered the opportunity to
draw attention to their posters through a short “elevator pitch”
(2-minute presentation).


FPL 2016 Demo Night event is an excellent opportunity for conference
participants to demonstrate and disseminate their work, to increase
their visibility, and interact with attendees. Demonstrations may
include commercial and academic research-oriented tools, platforms,
systems, and more. The event will take place on one of the conference
evenings. Hors d’oeuvres and drinks will be offered to all attendees.

Demo Night presenters are invited to submit 1-page abstracts using the
same format as FPL 2016 regular papers. A cover page should be added
to the submission and should contain the following information:
– Demo title.
– Names and affiliations of all authors.
– Description of the main objectives and relevance of the demo to the
FPL community.
– Short biographies of demo presenters.
– Any logistical requirements the demonstration may have.

The 1-page abstract should include demo title, names and affiliations
of all authors, and an abstract of the demo. The authors of the
accepted demos will be asked to prepare a poster for the Demo Night.
All demo posters will be published on the FPL 2016 web page and the
abstracts will be included in the conference proceedings.

FPL PhD Forum and Demo Night chairs:
Mirjana Stojilović, University of Applied Sciences Western Switzerland
Yann Thoma, University of Applied Sciences Western Switzerland

Call for Participation: ISPASS 2016

Submitted by Erik Hagersten
April 17 to April 19, 2016

Submitted by Erik Hagersten

The 17th International Symposium on Performance Analysis of
Systems and Software (ISPASS)

Uppsala, Sweden

April 17: Workshops/Tutorials (3 workshops and 4 tutorial)
April 18-19: Conference (including 3 keynotes)

Early registration: March 18
Hotel reservation: March 18

The name says it all: IEEE International Symposium on Performance Analysis of
Systems and Software. The focus is on performance-related problems, solutions,
methods and tools for software and system performance and power analysis
and optimisation.

After 16 years in the US, the ISPASS conference is now moving “abroad” for
the first time.

General Chair: Erik Hagersten, Uppsala University
Program Chair: Andreas Moshovos, University of Toronto

Call for Papers: NVMSA 2016

Submitted by Onur Mutlu
April 1, 2016

Submitted by Onur Mutlu

The 4th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)
Daegu, Korea
August 17-19, 2016

April 1: Abstract Submission Deadline
April 14: Paper Submission Deadline
June 1: Acceptance notification
June 12: Camera ready

Non-Volatile memory (NVM) technologies have demonstrated great potential to
improve many aspects of present and future memory hierarchies, offering high
integration density, larger capacity, zero standby power and good resilience
to soft errors. The recent research progress of various NVMs, e.g., NAND
flash, PCM, STT-RAM, RRAM, FeRAM, etc., have drawn tremendous attentions from
both academia and industry. Besides developing robust and scalable devices,
the unique characteristics of these NVM technologies, such as read-write
asymmetry, stochastic programming behavior, performance-power-nonvolatility
tradeoff, etc., introduce plenty of opportunities and challenges for novel
circuit designs, architectures, system organizations, and management
strategies. There is an urgent need for technology invention, modeling,
analysis, design and application of these NVMs ranging from circuit design to
system design levels.

IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) provides a
fantastic opportunity for global nonvolatile memory researchers from different
communities to discuss and exchange knowledge, ideas, and insights, and to
facilitate the establishment of potential collaborations that can speed up the
progress in the design and application of NVMs. An expanded technical program
will be offered in NVMSA 2016 for the audience from academy and industry. The
organizing committee is soliciting papers on various topics related to NVMs
including (but not limited to):

Device/Circuit design of NVMs
– Emerging Non-volatile Memory Circuit Design
– NVM Device Design
– Error correction for NVMs
– Nonvolatile Logic Circuit Design

NVM Architectures and Systems
– Non-volatile Registers
– Non-volatile Memory Architectures
– Non-volatile Cache Design
– NVM-based Neuromorphic Architectures
– NVM-based Storage

NVM Software
– Operating System Support for NVM
– Compiler Optimization for NVM
– NVM-based File Systems
– NVM-based Storage Software
– NVM-based Databases
– NVM Controller Design

NVM Applications
– In-memory Computing
– NVM for Big Data Analytics
– NVM in Mobile Healthcare Applications
– NVM in Wearable Applications
– NVM and the Internet of Things

The topics of NVMSA cover the research and development advances in both
mainstream and emerging NVMs. The event is designed to foster interaction and
presentation of early results, new ideas and speculative directions. Thus,
NVMSA will combine the presentations of the papers accepted from the regular
submissions as well as a number of invited talks from researchers in academia,
technologists from industry, and case studies on the use of NVMs.
Participating authors are invited to submit six-page manuscripts to the
conference. All accepted papers will be published in the conference
proceedings. Conference content will be submitted for inclusion into IEEE
Xplore as well as other Abstracting and Indexing (A&I) databases.
Extensions of some selected papers will be published in a special issue of The
Journal of Systems Architecture: Embedded Software Design.

Associated Conference: The 22nd IEEE International Conference on
Embedded and Real-Time Computing Systems and Applications (RTCSA 2016)

Call for papers: WDDD 2016

Submitted by Karu Sankaralingam
June 19, 2016

Submitted by Karu Sankaralingam
12th Annual Workshop on Duplicating, Deconstructing and Debunking

12th Annual Workshop on Duplicating, Deconstructing and Debunking (WDDD)
Seoul, S. Korea
June 19, 2016

Abstract Submission: April 20, 2016
Paper Submission: April 22, 2016
Acceptance: May 14, 2016
Final Version: June 10, 2016

WDDD provides the computer systems research community a forum for work that
validates or duplicates earlier results; deconstructs prior findings by
providing greater, in-depth insight into causal relationships or correlations;
or debunks earlier findings by describing precisely how and why proposed
techniques fail where earlier successes were claimed, or succeed where failure
was reported.

Traditionally, computer systems research conferences have focused almost
exclusively on novelty and performance, neglecting an abundance of interesting
work that lacks one or both of these attributes. A significant part of
research–in fact, the backbone of the scientific method–involves independent
validation of existing work and the exploration of strange ideas that never
pan out. This workshop provides a venue for disseminating such work in our
community. Published validation experiments strengthen existing work, while
thorough comparisons provide new dimensions and perspectives. Studies that
refute or correct existing work also strengthen the research community, by
ensuring that published material is technically correct and has sound
assumptions. Publishing negative or strange or unexpected results will allow
future researchers to learn the hard lessons of others, without repeating
their effort.

This workshop will set a high scientific standard for such experiments, and
will require insightful analysis to justify all conclusions. The workshop will
favor submissions that provide meaningful insights, and identify underlying
root causes for the failure or success of the investigated technique.
Acceptable work must thoroughly investigate and communicate why the proposed
technique performs as the results indicate. WDDD has a unique tradition of
asking the original paper authors to provide a follow-up comment after the
WDDD paper has been presented, where appropriate. The follow-up comment may
take the form of a rebuttal or additional insight from the original authors.

In general, any topic that is of interest to computer architecture conferences
and related systems areas are of potential interest for WDDD, so long as the
paper is in the spirit of the themes of Duplication, Deconstruction, and/or

Topics of interest:
– Independent validation of earlier results with meaningful analysis
– In-depth analysis and sensitivity studies that provide further insight into
earlier findings, or identify key parameters or assumptions that affect the
– Studies that refute earlier findings, with clear justification and explanation
– Negative results for ideas that intuitively make sense and should work, along
with explanations for why they do not
– Validation/refutation of controversial advertising claims by industrial

Submit a manuscript of up to 10 pages in two-column format by April 22, 2016
using the submission website.

Murali Annavaram, USC
Karu Sankaralingam, University of Wisconsin – Madison
David Brooks, Harvard University
Gabriel Loh, AMD Research

Call for Participation: SELSE 2016

Submitted by William H. Robinson
March 29 to March 30, 2016

Submitted by William H. Robinson

The 12th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2016)
Austin, TX, USA
March 29 – 30, 2016

Early registration deadline: March 14th, 2016.

Keynote speakers:
SELSE 2016 will feature three keynote speeches by experts from
academia and industry.
– Dr. Krishna V. Palem, Rice University
Can the end of Moore’s Law result in new opportunities for computing?
– Dr. Nirmal Saxena, NVIDIA
Autonomous car is the new driver for resilient computing and
– Dr. Martin Roetteler from Microsoft Research
Quantum error correction and quantum algorithmic discovery

Panel Discussion:
We will have a very interesting panel on the topic of approximate computing
with experts from academia and industry. The panel discussion will explore
opportunities and challenges of approximate computing in the field of

Please do not forget to book your hotels early, as the hotel prices can
increase closer to the SELSE dates. You can find a list of nearby hotels
on the SELSE web page.

Travel grants:
We are very excited to offer, for the first time, travel grants to young
faculties, postdocs, and students. Please refer to SELSE web page for
application instructions. Submit your application by March 12th.

General Chairs:
Helia Naeimi, Intel
Dan Alexandrescu, iRoC

Program Chairs:
Sudhanva Gurumurthi, IBM/University of Virginia
Mattan Erez, The University of Texas at Austin

Finance Chairs:
Siva Hari, NVIDIA
Daniel Lowell, AMD

Publicity Chairs:
William H. Robinson, Vanderbilt University
Paolo Rech, UFRGS
Yiannakis Sazeides, University of Cyprus

Documents Chairs:
Mehdi Tahoori, Karlsruhe Institute of Technology
Mojtaba Ebrahimi, Karlsruhe Institute of Technology

Austin Industry Liaison:
Indrani Paul, AMD

Marios Kleanthous, Mesoyios College

Local Arrangements Chair:
Vijay Janapa Reddi, The University of Texas at Austin

Advisors to the Committee:
Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD
Adrian Evans, iRoC

Call for Papers: ASBD 2016

Submitted by xiufeng Sui
June 19, 2016

Submitted by xiufeng Sui

Sixth Workshop on Architectures and Systems for Big Data(ASBD 2016)
in conjunction with ISCA 2016
Seoul, S. Korea
June 18, 2016

Submissions deadline: April 10, 2016
Author notification: April 30, 2016

The term “Big Data” refers to the continuing massive expansion in the data
volume and diversity as well as the speed and complexity of data processing.
The use of big data underpins critical activities in all sectors of our
society. Achieving the full transformative potential of big data in this
increasingly digital world requires both new data analysis algorithms and
a new class of systems to handle the dramatic data growth, the demand to
integrate structured and unstructured data analytics, and the increasing
computing needs of massive-scale analytics.

We are pleased to request papers for presentation at the upcoming Sixth
Workshop on Architectures and Systems for Big Data (ASBD 2016) held in
conjunction with ISCA-43. The workshop will provide a forum to exchange
research ideas related to all critical aspects of emerging analytics systems
for big data, including architectural support, benchmarks and metrics, data
management software, operating systems, and emerging challenges and
opportunities. We hope to attract a group of interdisciplinary researchers
from academia, industry and government research labs. To encourage
discussion between participants, the workshop will include significant time
for interactions between the presenters and the audience. We also plan to
have a keynote speaker and/or panel session.

Topics of interest include but are not limited to:
– Processor, memory and system architectures for data analytics
– Benchmarks, metrics and workload characterization for big data
– Accelerators for analytics and data-intensive computing
– Implications of data analytics to mobile and embedded systems
– Energy efficiency and energy-efficient designs for analytics
– Availability, fault tolerance and data recovery in big data environments
– Scalable system & network designs for high concurrency/bandwidth streaming
– Data management and analytics for vast amounts of unstructured data
– Evaluation tools, methodologies and workload synthesis
– OS, distributed systems and system management support for large-scale
– Debugging and performance analysis tools for analytics and big data
– Programming systems and language support for deep analytics
– MapReduce and other processing paradigms for analytics

We encourage researchers from all institutions to submit their work for review.
Preliminary results of interesting ideas and work-in-progress are welcome.
Submissions that are likely to generate vigorous discussion will be favored!

All papers should be submitted in PDF format, using 10 point
or larger font for text (8 points or larger for figures and tables),
total length not to exceed 6 pages.
Submission site:

Workshop Co-Organizers:
Lixin Zhang, ICT/CAS China
Yungang Bao, ICT/CAS China

Program Co-Chairs:
John Kim, KAIST South Korea
Xiufeng Sui, ICT/CAS China

Program Committee:

Steering Committee:
Jian Li, Huawei
Jichuan Chang, Google
Evan Speight, IBM Research

Call for Nominations: The Rau Award 2016

Submitted by Milagros Lovos
February 26, 2016 at 08:00

Submitted by Milagros Lovos

The Rau Award

Established in memory of Dr. B. (Bob) Ramakrishna Rau, the award recognizes his
distinguished career in promoting and expanding the use of innovative computer
microarchitecture techniques, including his innovation in compiler technology,
his leadership in academic and industrial computer architecture, and his
extremely high personal and ethical standards.

The candidate will have made an outstanding, innovative contribution or
contributions to microarchitecture, use of novel microarchitectural techniques
or compiler/architecture interfacing. It is hoped, but not required, that the
winner will have also contributed to the computer microarchitecture
community through teaching, mentoring, or community service.

Certificate and a $2,000 honorarium.

This year’s award will be presented at the ACM/IEEE International Symposium
on Microarchitecture (MICRO-49), held in October 15-19, 2016 in Taipei Taiwan.

This award requires 3 endorsements.
Nominations are being accepted electronically through

Robert P. Colwell – “For contributions to critical analysis of microarchitecture and
the development of the Pentium Pro processor.”

IEEE Computer Society Awards site:
IEEE Computer Society Award Nominations site:

Call for Participation: ASPLOS 2016

Submitted by Changhee Jung
April 2 to April 6, 2016

Submitted by Changhee Jung

The Twenty First International Conference on Architectural Support
for Programming Languages and Operating Systems (ASPLOS 2016)

Atlanta, Georgia, USA
April 2-6, 2016

– Travel Grant Application Deadline: March 1:

– Hotel Registration Deadline: March 11:

– Conference Early Registration Deadline: March 11:

Call for Papers: MEMSYS 2016

Submitted by Aamer Jaleel
March 18, 2016

Submitted by Aamer Jaleel

Memory Systems Conference (MEMSYS)
Washington, DC, USA

Submission Deadline: March 18*, 2016
Notification: May 15, 2016
Camera-Ready: July 1, 2016
* There will be an automatic submission extension of one week

The memory system has become extremely important recently: memory is slow,
and this is the primary reason that computers don’t run significantly faster than
they do. In large-scale computer installations such as the building-sized
systems powering,, and the financial sector, memory is
often the largest dollar cost as well as the largest consumer of energy.
Consequently, improvements in the memory system can have significant impact on
the real world, improving power and energy, performance, and/or dollar cost.

Moreover, many of the problems we see in the memory system are
cross-disciplinary in nature—their solution would likely require work at all
levels, from applications to circuits. Thus, while the scope of the problem is
memory, the scope of the solutions will be much wider.

Areas of Interest

Previously unpublished papers containing significant novel ideas and technical
results are solicited. Papers that focus on system, software, and architecture
level concepts, outside of traditional conference scopes, will be preferred
over others (e.g., the desired focus is away from pipeline design, processor
cache design, prefetching, data prediction, etc.). Symposium topics include,
but are not limited to, the following:

– Memory system design from both hardware & software perspectives
– Operating system design for hybrid/nonvolatile memories
– Technologies including PCM, flash, DRAM, STT-RAM, 3DXP, etc.
– Data-movement issues and mitigation techniques
– Interconnects to support large-scale data movement
– Software & application techniques for distributed memories
– Software management techniques
– Near-memory computing
– Memory-centric programming models & compiler techniques
– Memory failure modes and mitigation strategies
– Memory and system security issues

To reiterate, papers that focus on topics outside of traditional conference
scopes will be preferred over others.

Our primary goal is to showcase interesting ideas that will spark conversation
between disparate groups—to get applications people and operating systems
people and system architecture people and interconnect people and circuits
people to talk to each other. We accept extended abstracts, position papers,
and/or full research papers, and each accepted submission is given a 20-minute
presentation time slot. All accepted papers will be published in the ACM
Digital Library.

Submission formats:
2 page Extended Abstracts
5–6 page Position Papers
10–12 page Research Papers

Conference paper layout, no less than 9pt font in body, two-column, blind
submission, up to 15 pages in length.

All accepted submissions will be presented, published in the ACM Digital
Library, and included in the printed conference proceedings.

Note: Submitting either Extended Abstracts or Position Papers will not
preclude an author from submitting their work, in a longer research format,
to another publication forum at a later date.

Bruce Jacob, U. Maryland
Kathy Smiley, Memory Systems
Ameen Akel, Micron
James Ang, Sandia National Labs
Yitzhak Birk, Technion
Bruce Childers, U. Pittsburgh
Zeshan Chishti, Intel
Chen Ding, U. Rochester
David Donofrio, Berkeley Lab
Wendy Elsasser, ARM
Maya Gokhale, LLNL
Thuc Hoang, NNSA/DOE
Hillery Hunter, IBM
Mike Ignatowski, AMD
Aamer Jaleel, NVIDIA
David Kaeli, Northeastern
Scott Lloyd, LLNL
Gabriel Loh, AMD
Kenneth Ma, Hynix
Richard Murphy, Micron
Mike O’Connor, NVIDIA
Petar Radojkovic, BSC
David Resnick, Sandia National Labs
Arun Rodrigues, Sandia National Labs
John Shalf, Berkeley Lab
Anouk Van Laer, U. College London
Jeffrey Vetter, Georgia Tech & ORNL
Robert Voigt, Northrop Grumman
David Wang, Inphi
Christian Weis, U. Kaiserslautern
Kenneth Wright, Rambus
Sudhakar Yalamanchili, Georgia Tech

Call for Papers: Emerging Technologies for Reconfigurable Systems in the Manycore Era

Submitted by Patti Davide
June 27 to June 29, 2016

Submitted by Patti Davide
Emerging Technologies for Reconfigurable Systems in the Manycore Era
Special session in Int’l Symposium on Reconfigurable Communication-centric SoC’s (ReCoSoC 2016)
Tallinn, Estonia
June 27-29, 2016

Abstract submission deadline: April 1, 2016
Full paper submission deadline: April 6, 2016
Author notification: May 15, 2016
Camera-ready due: June 5, 2016

Current multicore architectures formed by tens of processing cores will be
soon replaced by the next generation of manycore architectures with hundreds
of cores. Although manycore architectures are envisaged as the most effective
for meeting the energy and performance constraints which characterize future
applications, some technical and technology aspects start to exacerbate. Dark
silicon, memory wall, on-chip communication scalability, represent just a
short list. Emerging technologies, novel architectures and design techniques,
which stress the reconfiguration concept, are currently investigated by the
research community as viable opportunities for tackling the
performance-in-the-energy-envelop problem in the manycore era.

The aim of this Special Session is to bring together a group of leading
academic researchers and technology experts to provide a platform for
discussion on novel ideas and studies related to design, modelling and
analysis of reconfigurable manycore architectures based on emerging

Authors are invited to submit contributions as maximum 8 page papers in IEEE
conference format. ReCoSoC 2016 follows a double-blind review process:
author’s should not reveal their identity in the manuscript. Contribution(s)
have to be submitted electronically through the EasyChair portal of the
conference at

Davide Patti, Univ. of Catania, Italy,
Maurizio Palesi, Univ. of Enna – KORE, Italy,