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June 15, 2015

Call for Papers: ACM SIGMETRICS 2015

Submitted by Niklas Carlsson
http://www.sigmetrics.org/sigmetrics2015/
CALL FOR PAPERS – ACM SIGMETRICS 2015
HELD AS PART OF FCRC 2015
June 15-19, 2015
Portland, Oregon, USA

IMPORTANT DATES:

Abstract Registration: November 17, 2014 (11:59pm EST)
Paper Submission: November 24, 2014 (11:59pm EST)
Notification: February 17, 2015
Conference: June 15-19, 2015

CONFERENCE OVERVIEW:

ACM SIGMETRICS 2015 solicits papers on the development and application
of state-of-the-art, broadly applicable analytic, simulation and
measurement-based performance evaluation techniques. Of particular
interest is work that presents new performance evaluation methods or
that creatively applies previously developed methods to make
predictions about, or gain insights into key design trade-offs in,
computer and networked systems. The main conference will be held from
June 16-18, 2015. There will be workshops and tutorials on June 15,
2015. There will also be workshops on June 19, 2015. Submission details
will be published shortly on this Web site. All accepted regular papers
will include oral (short or long time slot, single track)
presentations. We foresee a continuation in the recent organic growth
of the size of ACM SIGMETRICS, while still keeping it a single track
venue. All regular papers will be allocated 12 pages in the conference
proceedings. In addition, poster papers will be accepted (2 pages in
proceedings, no oral presentation).

The notion of performance is broadly construed including considerations
of speed and scalability as well as reliability, availability,
sustainability and manageability of systems. We encourage both
theoretical contributions and also submissions relating to real world
empirical studies or focusing on implementation and experimental
issues.

Quantitative design and evaluation studies of:

* Computer and communication networks, protocols and algorithms
* Wireless, mobile, ad-hoc and sensor networks
* Computer architectures, multi-core processors, memory systems and
storage systems/networks
* Operating systems, file systems and databases
* Virtualization, data centers, distributed and cloud computing
* Social networks, multimedia systems, service-oriented architectures
and Web services
* Energy-efficient computing systems
* Real-time and fault-tolerant systems
* Mobile and personal computing systems
* Large-scale operational systems
* Software systems and enterprise applications
* Smart power grids
* Emerging technologies
* Data processing

Methodologies, formalisms, solution techniques and algorithms for:

* Performance, scalability, power and reliability analysis
* Sustainability analysis and power management
* Capacity planning, resource allocation, run time management and
scheduling
* Anomaly detection, system measurement, monitoring and forecasting
* Analytical modeling techniques and model validation
* System measurement, monitoring and forecasting
* Workload characterization and benchmarking
* Quality of service, total cost of ownership and pricing
* Experimental design, statistical analysis, simulation
* Performance-oriented applications of game theory, economics and
control theory
* Big data, machine learning and signal processing

SUBMISSION GUIDELINES:

Papers should not exceed 12 pages double column including figures,
tables, and references in standard ACM format. In addition, a 2-page
appendix is permitted, where the appendix does not count towards the
original 12 pages. Papers must be submitted electronically in printable
pdf form. Templates for the standard ACM format can be found at this
link.

http://www.acm.org/sigs/publications/proceedings-templates

Both strict and alternate styles are acceptable for submission. No
changes to margins, spacing, or font sizes are allowed from those
specified by the style files. Papers violating the formatting
guidelines will be returned without review.

All submissions will be reviewed using a double-blind review process.
The identity of authors and referees will not be revealed to each
other. To ensure blind reviewing, author names and affiliations should
not appear in the paper; bibliographic references should be made in
such a way as to preserve author anonymity. Accepted papers will appear
in the conference proceedings published in the ACM Performance
Evaluation Review.

Warning: It is ACM policy not to allow double submissions, where the
same paper is submitted to more than one conference/journal
concurrently. Any double submissions detected will be immediately
rejected from all conferences/journals involved.

GENERAL CHAIRS:
Bill Lin, UCSD
Jun (Jim) Xu, Georgia Tech

PROGRAM CHAIRS:
Sudipta Sengupta, Microsoft Research
Devavrat Shah, Massachusetts Institute of Technology

PROGRAM COMMITTEE:
Mohammad Alizadeh Insieme Networks
Lakshmi Bairavasundaram Datrium
Randall Berry Northwestern University
Sem Borst Eindhoven U. of Technology and
Alcatel-Lucent Bell Labs
Ana Busic INRIA
John C S Lui CUHK
Y Charlie Hu Purdue University
Mark Crovella Boston University
Peter Desnoyers Northeastern University
Ayalvadi Ganesh University of Bristol
Javad Ghaderi Columbia University
Philip Gibbons Intel Research Pittsburgh
Leana Golubcik University of Southern California
Varun Gupta University of Chicago
Bruce Hajek UIUC
Mor Harchol-Balter CMU
John Hasenbein UT Austin
Kyomin Jung Seoul National University
Ramana Kompella Purdue University
Peter Marbach University of Toronto
Athina Markopoulou UC Irvine
Vishal Misra Columbia University
Eytan Modiano MIT
Jason Nieh Columbia University
Sewoong Oh UIUC
Alexandre Proutiere France Telecom
Konstantinos Psounis University of Southern California
Kavita Ramanan Brown University
Rhonda Righter UC Berkeley
Dan Rubenstein Columbia University
Saswati Sarkar University of Pennsylvania
Srinivas Shakkottai Texas A&M University
Mayank Sharma IBM T. J. Watson Research Center
Jinwoo Shin KAIST
Evgenia Smirni College of William and Mary
Alex Snoeren UCSD
Mark Squillante IBM T. J. Watson Research Center
Alexander (Sasha) Stolyar Alcatel-Lucent Bell Labs
Ryan Stutsman Microsoft Research
Lakshmi Subramanian NYU
Vijay Subramanian Northwestern University
Y C Tay National University of Singapore
Don Towsley University of Massachusetts Amherst
Milan Vojnovic Microsoft Research
Neil Walton University of Amsterdam
Jia Wang AT&T Research
Adam Wierman California Institute of Technology
Lau Wing-Cheong CUHK
Cathy Xia Ohio State University
Kuang Xu Stanford
Tauhid Zaman MIT
Li Zhang IBM T. J. Watson Research Center
Zhi-Li Zhang University of Minnesota
Yuan Zhong Columbia University
Gil Zussman Columbia University
Bert Zwart CWI

Start: June 15, 2015
End: June 19, 2015
Venue: Portland, Oregon, USA

Call for Papers: SIGMETRICS 2015

Submitted by Niklas Carlsson
http://www.sigmetrics.org/sigmetrics2015/

ACM SIGMETRICS 2015
Held as part of FCRC 2015
June 15-19, 2015
Portland, Oregon, USA
 

IMPORTANT DATES
Abstract Registration: November 17, 2014 (11:59pm EST)
Paper Submission: November 24, 2014 (11:59pm EST)
Notification: February 17, 2015
Conference: June 15-19, 2015

CONFERENCE OVERVIEW
ACM SIGMETRICS 2015 solicits papers on the development and application
of state-of-the-art, broadly applicable analytic, simulation and
measurement-based performance evaluation techniques. Of particular
interest is work that presents new performance evaluation methods or
that creatively applies previously developed methods to make
predictions about, or gain insights into key design trade-offs in,
computer and networked systems. The main conference will be held from
June 16-18, 2015. There will be workshops and tutorials on June 15,
2015. There will also be workshops on June 19, 2015. Submission details
will be published shortly on this Web site. All accepted regular papers
will include oral (short or long time slot, single track)
presentations. We foresee a continuation in the recent organic growth
of the size of ACM SIGMETRICS, while still keeping it a single track
venue. All regular papers will be allocated 12 pages in the conference
proceedings. In addition, poster papers will be accepted (2 pages in
proceedings, no oral presentation).

The notion of performance is broadly construed including considerations
of speed and scalability as well as reliability, availability,
sustainability and manageability of systems. We encourage both
theoretical contributions and also submissions relating to real world
empirical studies or focusing on implementation and experimental
issues.

Quantitative design and evaluation studies of:

- Computer and communication networks, protocols and algorithms
- Wireless, mobile, ad-hoc and sensor networks
- Computer architectures, multi-core processors, memory systems and
storage systems/networks
- Operating systems, file systems and databases
- Virtualization, data centers, distributed and cloud computing
- Social networks, multimedia systems, service-oriented architectures
and Web services
- Energy-efficient computing systems
- Real-time and fault-tolerant systems
- Mobile and personal computing systems
- Large-scale operational systems
- Software systems and enterprise applications
- Smart power grids
- Emerging technologies
- Data processing

Methodologies, formalisms, solution techniques and algorithms for:

- Performance, scalability, power and reliability analysis
- Sustainability analysis and power management
- Capacity planning, resource allocation, run time management and
scheduling
- Anomaly detection, system measurement, monitoring and forecasting
- Analytical modeling techniques and model validation
- System measurement, monitoring and forecasting
- Workload characterization and benchmarking
- Quality of service, total cost of ownership and pricing
- Experimental design, statistical analysis, simulation
- Performance-oriented applications of game theory, economics and
control theory
- Big data, machine learning and signal processing

SUBMISSION GUIDELINES
The submission website will be online in early November. Papers
should not exceed 12 pages double column including figures, tables,
and references in standard ACM format. In addition, a 2-page appendix
is permitted, where the appendix does not count towards the original
12 pages. Papers must be submitted electronically in printable pdf
form. Templates for the standard ACM format can be found at this link.

http://www.acm.org/sigs/publications/proceedings-templates

Both strict and alternate styles are acceptable for submission. No
changes to margins, spacing, or font sizes are allowed from those
specified by the style files. Papers violating the formatting
guidelines will be returned without review.

All submissions will be reviewed using a double-blind review process.
The identity of authors and referees will not be revealed to each
other. To ensure blind reviewing, author names and affiliations should
not appear in the paper; bibliographic references should be made in
such a way as to preserve author anonymity. Accepted papers will appear
in the conference proceedings published in the ACM Performance
Evaluation Review.

Warning: It is ACM policy not to allow double submissions, where the
same paper is submitted to more than one conference/journal
concurrently. Any double submissions detected will be immediately
rejected from all conferences/journals involved.

The paper submission website is available at:

http://cass.lids.mit.edu/sigmetrics2015/

GENERAL CHAIRS
Bill Lin, UCSD
Jun (Jim) Xu, Georgia Tech

PROGRAM CHAIRS
Sudipta Sengupta, Microsoft Research
Devavrat Shah, Massachusetts Institute of Technology

PROGRAM COMMITTEE
Mohammad Alizadeh Insieme Networks
Lakshmi Bairavasundaram Datrium
Randall Berry Northwestern University
Sem Borst Eindhoven U. of Technology and
Alcatel-Lucent Bell Labs
Ana Busic INRIA
John C S Lui CUHK
Y Charlie Hu Purdue University
Mark Crovella Boston University
Peter Desnoyers Northeastern University
Ayalvadi Ganesh University of Bristol
Javad Ghaderi Columbia University
Philip Gibbons Intel Research Pittsburgh
Leana Golubchik University of Southern California
Varun Gupta University of Chicago
Bruce Hajek UIUC
Mor Harchol-Balter CMU
John Hasenbein UT Austin
Kyomin Jung Seoul National University
Ramana Kompella Purdue University
Alex Liu Michigan State University
Peter Marbach University of Toronto
Athina Markopoulou UC Irvine
Vishal Misra Columbia University
Eytan Modiano MIT
Jason Nieh Columbia University
Sewoong Oh UIUC
Alexandre Proutiere France Telecom
Konstantinos Psounis University of Southern California
Kavita Ramanan Brown University
Rhonda Righter UC Berkeley
Dan Rubenstein Columbia University
Saswati Sarkar University of Pennsylvania
Srinivas Shakkottai Texas A&M University
Mayank Sharma IBM T. J. Watson Research Center
Jinwoo Shin KAIST
Evgenia Smirni College of William and Mary
Alex Snoeren UCSD
Mark Squillante IBM T. J. Watson Research Center
Alexander (Sasha) Stolyar Alcatel-Lucent Bell Labs
Ryan Stutsman Microsoft Research
Lakshmi Subramanian NYU
Vijay Subramanian Northwestern University
Wee Peng Tay Nanyang Technological University
Don Towsley University of Massachusetts Amherst
Milan Vojnovic Microsoft Research
Neil Walton University of Amsterdam
Jia Wang AT&T Research
Adam Wierman California Institute of Technology
Lau Wing-Cheong CUHK
Cathy Xia Ohio State University
Kuang Xu Stanford
Tauhid Zaman MIT
Li Zhang IBM T. J. Watson Research Center
Zhi-Li Zhang University of Minnesota
Yuan Zhong Columbia University
Gil Zussman Columbia University
Bert Zwart CWI

Start: June 15, 2015
End: June 19, 2015
Venue: Portland, Oregon, USA

Call for Papers: Transact 2015

Submitted by Victor Luchangco
http://transact2015.cse.lehigh.edu/

10th ACM SIGPLAN Workshop on Transactional Computing (Transact 2015)
Portland, Oregon, USA
15-16 June 2015
 

This year, Transact will be part of the Federated Computing Research
Conference (FCRC).
General FCRC information is available at http://fcrc.acm.org.
Also note Transact will two days this year rather than just one.

IMPORTANT DATES
Submission Deadline: 19 February 2015 (Thursday)
Author Notification: 24 April 2015 (Friday)
Workshop: 15-16 June 2015 (Monday-Tuesday)

OVERVIEW
The past decade has seen an explosion of interest in programming languages,
systems, and hardware to support transactions, speculation, and related
alternatives to classical lock-based concurrency. Recently, transactional
memory has crossed two new thresholds. First, IBM and Intel are now shipping
processors with hardware support for transactional memory. Second, the C++
Standard Committee has begun investigation into transactional memory as a
new language feature. These developments highlight the demand for continued
high quality TM research.

Transact 2015 will provide a forum to present and discuss the latest research
on all aspects of transactional computing. The tenth in the series, it will
extend over two days (rather than the usual one) during the Federated
Computing Research Conference (FCRC). The scope of the workshop is
intentionally broad, with the goal of encouraging interaction across the
languages, architecture, systems, database, and theory communities. Papers
may address implementation techniques, foundational results, applications and
workloads, or experience with working systems. Environments of interest
include the full range from multithreaded or multicore processors to high-end
parallel computing.

TOPICS
Transact seeks papers on topics related to all areas of software and hardware
for transactional computing. Specific topics of interest include but are not
limited to:

- Run-time systems
- Hardware support
- Applications, workloads, and test suites
- Experience reports
- Language mechanisms and semantics
- Memory models
- Formal verification
- Speculative concurrency
- Conflict detection and contention management
- Debugging and tools
- Static analysis and compiler optimizations
- Checkpointing and failure atomicity
- Persistence and I/O
- Nesting and exceptions

Papers should present original research. As transactional memory spans many
disciplines, papers should provide sufficient background material to make them
accessible to the broader community. Papers focused on foundations should
indicate how the work can be used to advance practice; papers on experiences
and applications should indicate how the experiments reinforce or reflect principles.

SUBMISSIONS
Papers must be submitted in PDF, and be no more than 8 pages in standard
two-column SIGPLAN conference format including figures and tables but not
including references. Shorter submissions are welcome. Submissions will be
judged based on the merit of the ideas rather than the length. Submissions
must be made through the on-line submission site. Final papers will be
available to participants electronically at the meeting, but to facilitate
resubmission to more formal venues, no archival proceedings will be published,
and papers will not be sent to the ACM Digital Library.

Authors will have the option of having their final paper accessible from the
workshop website. Authors must be familiar with and abide by SIGPLAN’s
republication policy, which forbids simultaneous submission to multiple venues
and requires disclosing prior publication of closely related work. At the
discretion of the program committee and with the consent of the authors,
particularly worthy papers may be recommended for a special journal issue.

PROGRAM COMMITTEE
Cristiana Amza, University of Toronto
Annette Bieniusa, Universitat Kaiserslautern
Luke Dalessandro, Indiana University
Dave Dice, Oracle Labs
Stephan Diestelhorst, ARM
Pascal Felber, Universite de Neuchatel
Justin Gottschlich, Intel Labs
Victor Luchangco, Oracle Labs (chair)
Alessia Milani, Bordeaux Institute of Technology
Binoy Ravindran, Virginia Tech
Torvald Riegel, Red Hat
Paolo Romano, University of Lisbon
Michael Scott, University of Rochester
Michael Spear, Lehigh University
Osman Unsal, BSC-Microsoft Research Centre

ORGANIZING COMMITTEE
General Chair:
Justin Gottschlich, Intel Labs

Program Chair:
Victor Luchangco, Oracle Labs

Web Chair:
Michael Spear, Lehigh University

Steering Committee:
Pascal Felber, University de Neuchatel
Justin Gottschlich, Intel Labs
Dan Grossman, University of Washington
Rachid Guerraoui, EPFL
Tim Harris, Oracle Labs
Maurice Herlihy, Brown University
Eliot Moss, UMass
Jan Vitek, Purdue University
Michael Scott, University of Rochester
Tatiana Shpeisman, Intel Labs
Michael Spear, Lehigh University

 

Start: June 15, 2015
End: June 16, 2015
Venue: Portland, OR, USA

Call for Participation: ACM SIGMETRICS 2015

Submitted by Niklas Carlsson
http://www.sigmetrics.org/sigmetrics2015/

ACM SIGMETRICS 2015
The organizing committee is excited to invite you to take part in
ACM SIGMETRICS 2015 to be held at the Oregon Convention Center in
Portland Oregon during June 15-19, 2015, as part of the Federated
Computer Research Conference (FCRC). ACM SIGMETRICS is the flagship
conference of the ACM special interest group for the computer systems
performance evaluation community.

CONFERENCE AND WORKSHOP DATES:
Conference dates: June 16-18, 2015
Workshops: June 15, 2015
Tutorials: June 19, 2015

CONFERENCE LOCATION:
Oregon Convention Center in Portland, Oregon, USA

REGISTRATION DEADLINES:
- Early conference registration deadline: May 18, 2015
- Special FCRC hotel rate available at each hotel until May 16, 2015

FCRC REGISTRATION:

https://www.regonline.com/Register/Checkin.aspx?EventID=1692718

HOTEL RESERVATION:
ACM has blocked sleeping rooms at five hotels all within a short walk
of the Oregon Convention Center with rates ranging from a very
affordable $110/night to $169/night for the higher end properties.

CO-LOCATED WORKSHOPS:
- NetEcon 2015
The 10th Workshop on the Economics of Networks, Systems and Computation
- DCC 2015
The 3rd Workshop on Distributed Cloud Computing
- MAMA 2015
The 17th Workshop on MAthematical performance Modeling and Analysis

SPONSORS:
We are grateful to the following organizations for sponsoring and
supporting ACM SIGMETRICS 2015.
- Akamai
- Facebook
- Hewlett-Packard (HP)
- IBM
- Intel
- National Science Foundation (NSF)

ORGANIZING COMMITTEE:
General Chairs: Bill Lin (UCSD) and Jun (Jim) Xu (Georgia Tech)
TPC Chairs: Sudipta Sengupta (Microsoft) and Devavrat Shah (MIT)

Start: June 15, 2015
End: June 19, 2015
Venue: Portland, Oregon

June 14, 2015

Call for Participation: Workshop on Computer Architecture Research Directions

Submitted by Joshua J. Yi
http://www.ele.uri.edu/CARD

Fourth Workshop on Computer Architecture Research Directions (CARD 2015)
in conjunction with ISCA 2015
Portland, OR, USA
Sunday, June 14, 2015
 

CARD 2015 presents three mini-panels consisting of three experts in the field,
two as panelists and the third as a moderator/panelist. The purpose of this
workshop is to serve as a forum in which experts in each field can debate the
state of the field and future directions. The format is designed to quickly
focus on areas of disagreement, rather than expounding on areas of agreement
which, presumably, have ceased to be controversial, at least between the two
panelists. The mini-panels are intended to help clarify the open issues of
each topic and to discuss those open issues. The hope is that the workshop will
be useful to a diverse audience from a graduate student looking for good thesis
topic areas to a senior researcher who wants to hear the opinions of other area
experts.

Each 60 minute panel will consist of an opening statement from each panelist
(10 minutes each, 20 minutes total), discussion between the moderator and
panelists (5 to 10 minutes), and questions from the audience (30 to 35 minutes).

CARD 2015 consists of following three mini-panels:

Mini-panel #1: Open-source versus Proprietary ISAs
Moderator: Mark Hill (University of Wisconsin)
Panelist: Dave Patterson (University of California – Berkeley)
Panelist: Dave Christie (AMD)

Mini-panel #2: FPGAs versus GPUs for Datacenters
Moderator: Babak Falsafi (EPFL)
Panelist: Desh Singh (Altera)
Panelist: Bill Dally (Stanford / NVIDIA)

Mini-panel #3: Impact of Future Technologies
Moderator: Trevor Mudge (University of Michigan)
Panelist: Fred Chong (University of Chicago)
Panelist: Igor Markov (University of Michigan)

Descriptions of each panel and the panelists position statement should be
posted on the CARD website shortly.

Organizers:
Derek Chiou, Microsoft/University of Texas at Austin
Resit Sendag, University of Rhode Island
Joshua J. Yi, Dechert LLP

Start: June 14, 2015 1:30 pm
End: June 14, 2015 5:30 pm
Venue: Portland, OR

Call for Participation: Workshop on Architectural Research Prototyping

Submitted by David Wentzlaff
http://www.csl.cornell.edu/warp2015/

WARP: 6th Workshop on Architectural Research Prototyping
Co-Located with ISCA 2015
Portland, Oregon, USA
Sunday, June 14th, 2015 (Afternoon)
 

Building prototype systems can be one of the best ways to validate
assumptions, gain intuition about practical design issues, and
provide platforms for future software research. While the research
ideas behind these prototypes can be published in top-tier
conferences, there are not many venues suitable for focusing on the
actual prototype itself. At the same time, building an FPGA, ASIC, or
full-custom computer architecture prototype is a non-trivial endeavor
and requires a significant financial and time commitment. This
workshop is intended as a forum for the builders in our community to
share their practical on-the-ground experiences, to provide a status
update on their progress, and to convey insights for those
considering prototyping their ideas.

This half-day workshop will be held on Sunday, June 14th, 2015,
co-located with ISCA-42 in Portland, OR. The technical program
committee and workshop organizers have selected a particularly strong
program from a record number of submissions. The 11 talks cover a
broad range of exciting prototypes including: millimeter-scale
full-system sensor motes and large-scale ASIC designs with 100′s of
millions of transistors; chip tapeouts in older technologies, chip
tapeouts in a state-of-the-art 28nm process, and chip tapeouts using
3D integration; multicore chip tapeouts with heterogeneous
accelerators; and FPGA prototypes focusing on multicore processors,
network interfaces, and memory systems.

Participation is encouraged for anyone interested in learning about
some of the best prototyping work going on within the computer
architecture research community. Participation is also encouraged for
researchers that have recently constructed or are currently
constructing prototypes, for those considering embarking on a
prototyping effort, or even for those who strongly disagree with the
need to build prototypes.

ADVANCE PROGRAM:
– “Prototyping Heterogeneous System-on-Chip Architectures:
A System-Level Design Approach”
L. Carloni (Columbia University)

– “Post Mortem on Building 28nm/45nm RISC-V Vector Microprocessors
with Chisel and the Rocket Chip Generator”
Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun,
B. Zimmer, K. Asanovic (University of California, Berkeley)

– “State of the Tinuso Platform and Toolset”
A. Hindborg, N. Jensen, P. Schleuniger, S. Karlsson (Technical
University of Denmark)

– “Designing a Complex 25-Core Academic Processor”
D. Wentzlaff, M. McKeown, Y. Fu, T. Nguyen, Y. Zhou, J. Balkind,
A. Lavrov, M. Shahrad, S. Payne (Princeton University)

– “From PDF to GDS: Designing the RoboBee SoC”
B. Reagen, X. Zhang, D. Brooks, G.-Y. Wei (Harvard University)

– “Lessons from Five Years of Making Michigan Micro Motes”
P. Pannuto, Y. Lee, Z. Foo, G. Kim, D. Blaauw, P. Dutta (University
of Michigan)

– “NVM-Charade: Open-Sourced FPGA-Based NVM Characterization Scheme”
G. Park, M. Shihab, L. Nahar, S. Kang, D. Donofrio, J. Shalf,
M. Jung (UT Dallas and Lawrence Berkeley National Laboratory)

– “Experiences with Two FabScalar-Based Chips”
E. Forbes, R. Chowdhury, B. Dwiel, A. Kannepalli, V. Srinivasan,
Z. Zhang, R. Widialaksono, T. Belanger, S. Lipa, E. Rotenberg,
W.R. Davis, P.D. Franzon (North Carolina State University)

– “Experiences and Lessons from a 3D Integrated Prototype”
R. Dreslinski (University of Michigan)

– “A 10G NetFPGA Prototype for In-network Aggregation”
V.T. Lee, J. Nelson, M. Oskin, L. Ceze (University of Washington)

– “Cymric: A Framework for Prototyping Near-Memory Architectures”
C. Kersey, H. Kim, S. Yalamanchili (Georgia Tech)

WORKSHOP ORGANIZERS:
– Christopher Batten, Cornell University
– Dave Wentzlaff, Princeton University

PROGRAM COMMITTEE:
– David Brooks, Harvard University
– Steve Keckler, NVIDIA/University of Texas at Austin
– Mark Oskin, University of Washington
– Jose Renau, University of California, Santa Cruz

Start: June 14, 2015 12:30 pm
End: June 14, 2015 5:30 pm
Venue: Portland, OR

Call for Papers: Workshop on Architectural Research Prototyping

Submitted by Christopher Batten
http://www.csl.cornell.edu/warp2015

WARP: 6th Workshop on Architectural Research Prototyping
Co-located with ISCA’15
Portland, Oregon, USA
Sunday, June 14th, 2015
 

Building prototype systems can be one of the best ways to validate
assumptions, gain intuition about practical design issues, and
provide platforms for future software research. While the research
ideas behind these prototypes can be published in top-tier
conferences, there are not many venues suitable for focusing on the
actual prototype itself. At the same time, building an FPGA, ASIC, or
full-custom computer architecture prototype is a non-trivial endeavor
and requires a significant financial and time commitment. This
workshop is intended as a forum for the builders in our community to
share their practical on-the-ground experiences, to provide a status
update on their progress, and to convey insights for those
considering prototyping their ideas.

This half-day workshop will be held on Sunday, June 14th, 2015,
co-located with ISCA-42 in Portland, OR. The workshop will primarily
include presentations selected by the technical program committee
based on extended abstract submissions.

We invite submissions on all aspects of building prototype systems
for computer architecture research. Submissions can be based on new
or pending prototypes that have not been discussed in any other
venue, or submissions can focus on the practical prototyping
implications of a previously published research paper. Submissions
more in the spirit of a short position paper are also encouraged.

Topics of particular interest include, but are not limited to:

– Status updates on FPGA, ASIC, or full-custom prototypes
that have been recently constructed or are under construction

– Implementation technology trade-offs (FPGAs, ASICs, full-custom)

– Practical guidance on what works and what doesn’t,
including strategies for:
    o High-level specification
    o Register-transfer-level implementation
    o Pre- and post-construction verification
    o Packaging and board design
    o Managing complex electronic design automation toolflows

– Practical advice on managing the increasing design complexity
inherent in building computer architecture research prototypes
that integrate general-purpose processors and memory systems with
specialized accelerators

– How to balance the often conflicting goals of prototypes as
research vehicles containing novel architectural mechanisms vs.
prototypes as high-performance software development platforms

– How to balance student’s thesis goals vs. engineering work
– How to secure funding for building prototypes

Participation is encouraged for all members of the computer
architecture community, including those considering embarking on a
prototyping effort or those who strongly disagree with the need to
build prototypes.

SUBMISSION GUIDELINES:
Participants are invited to submit an extended abstract of up to two
pages (single or double column, 10pt, single spaced). Please include
the authors’ names, affiliations, and clearly reference any previous
publications that were based on the prototype. Submissions must be in
PDF format and submitted according to the instructions posted on the
WARP website.

Participants may also include an appendix of any length. However, we
will not promise to read the appendix, so the extended abstract
should stand alone as a coherent description of what you will discuss
in your talk. The appendix can provide additional details such as
device micrographs or more detailed results.

Extended abstracts and presentation slides will only be posted on the
workshop website with permission of the authors. Authors should feel
free to submit work in progress or work under review (where
permitted) without fear of double publication issues.

IMPORTANT DATES:
– Submission Deadline: April 10, 2015
– Notification of Selection: April 20, 2015
– Final Abstract Submission: May 22, 2015

ORGANIZING COMMITTEE:
Workshop chairs:
– Christopher Batten, Cornell University
– Dave Wentzlaff, Princeton University

Program Committee:
– David Brooks, Harvard University
– Steve Keckler, NVIDIA/University of Texas at Austin
– Mark Oskin, University of Washington
– Jose Renau, University of California, Santa Cruz
 

Start: June 14, 2015 12:00 pm
End: June 14, 2015 5:00 pm
Venue: Portland, OR

Call for Papers: Workshop on Parallelism in Mobile Platforms

Submitted by Hyesoon Kim
http://prism.sejong.ac.kr

Third International Workshop on Parallelism in Mobile Platforms (PRISM-3 )
In conjunction with ISCA-42
Portland, OR, USA
June 14, 2015
 

IMPORTANT DATES
- Abstract submission: March 31, 2015
- Author notification: April 22, 2015
- Final camera-ready paper: June 4, 2015
- Workshop: June 14, 2015

One of the most important principles in designing today’s computing
systems is to exploit parallelism. Mobile platforms are no exception
and we find increasingly more instances of the use of parallelism in
them. At the hardware level, there are: multiple processor cores,
GPGPU, accelerators, multiple banks of memory, multiple channels to
non-volatile memory chips, and multiple radios, to name a few. At the
software level, parallel and concurrent threading techniques are
commonly employed to improve responsiveness and throughput in the OS
and applications alike. We anticipate that future mobile platforms
will make more extensive and creative use of parallelism. This
workshop focuses on how parallelism is, and can be, utilized in
hardware, software and their interaction in order to improve the user
experiences with mobile platforms.

Topics of particular interest include, but are not limited to:
- Emerging parallel application processor architectures and hardware
features in mobile platforms;
- Compelling future applications on mobile platforms that call for
unprecedented parallelism;
- Mobile GPGPU architectures and programming models;
- Hardware accelerators for mobile applications;
- Storage architectures in mobile platforms;
- Radio and networking architectures in mobile platforms;
- Compiler support for parallel mobile platforms;
- OS support to accommodate and promote parallelism in mobile
platforms;
- Experiences in parallel mobile applications development;
- Novel techniques to improve responsiveness by exploiting parallelism;
- Novel techniques to improve performance/energy by exploiting parallelism;
- Mobile platform performance evaluation methodologies;
- Application benchmarks for mobile platforms;
- Characterization of emerging workloads on mobile platforms; and
- Impact and interaction of emerging technologies to mobile platforms

Detailed instructions for electronic submission will be posted on the
conference web site. For additional information regarding paper
submissions, please contact the Program Co-chairs. The workshop aims
at providing a forum for researchers, engineers and students from
academia and industry to discuss their latest research in designing
mobile platforms and systems, to bring their ideas and research
problems to the attention of others, and to obtain valuable and
instant feedback from fellow researchers.

SUBMISSION INSTRUCTIONS:
Submit a 2‐page presentation abstract to a web‐based submission system
(TBA) by March 31, 2015. Notification of acceptance will be sent out
by April 22, 2015. Final presentation material (to be posted on the
workshop web site) due June 4, 2015. For additional information
regarding paper submissions, please contact the organizers.

ORGANIZERS:
Sangyeun Cho, Samsung Electronics
Hyesoon Kim, Georgia Tech.
Hsien-Hsin Lee, TSMC
Giho Park, Sejong Univ.

Web Chair:
Minkwan Kee, Hyunsoo Sun, Sejong Univ.

Program Committee:
Murali Annavaram, USC
Jesse Beu, ARM
Simone Campanoni, Harvard Univ.
Calin Cascaval, Qualcomm
Koji Inoue, Kyushu Univ.
Yoonbong Kim, SK Hynix
Masaaki Kondo, Univ. of Tokyo
Trevor Mudge, Univ. of Michigan
Vijay Janapa Reddi, UT Austin
Chulho Shin, LG Electronics
Youngmin Shin, Samsung Electronics
Guangyu Sun, Peking Univ.
Michael Taylor, UCSD
 

Start: June 14, 2015
End: June 14, 2015
Venue: Portland, OR, USA

Call for Papers: Workshop on Resource-Efficient Cloud Computing

Submitted by Christina Delimitrou
http://web.stanford.edu/~cdel/rec2

Workshop on Resource-Efficient Cloud Computing
In conjunction with ISCA 2015
June 14, 2015
 

With large-scale datacenters increasing in size and number, the challenge to
improve their efficiency is becoming more pressing. The goal of the workshop is
to bring together cloud computing researchers from academia and industry,
underline the most pressing challenges in large-scale system design, and
encourage new ways of improving the efficiency of these systems. We plan to
structure the workshop as a combination of invited talks from key people in the
area, and early-idea position papers.

Topics include but are not limited to:

- Hardware support for resource partitioning and isolation
- Scheduling, resource management and cloud provisioning systems
- Software techniques for enforcing resource isolation
- Runtimes that improve utilization and application QoS
- Scalable cluster management frameworks
- Bare-metal OSes for cloud applications
- Resource-efficient application design
- Datacenter monitoring and troubleshooting
- Implications of resource-efficiency to datacenter fault-tolerance
- Real-world measurements and analysis of cloud inefficiencies

SUBMISSION INSTRUCTIONS:
Papers should be 4-6 pages long (8.5″ x 11″ pages), including figures and
tables, but not including references. You may include any number of pages for
references. Papers should be formatted in 2 columns, using 10-point type on
12-point leading, in a text block of 6.5″ x 9″. Color may be used,
but the paper should remain readable when printed in monochrome. Papers must be
submitted for single-blind review, i.e., you can include the authors’ names.
Please submit your papers over email to the workshop organizers by the
submission deadline.

IMPORTANT DATES
Paper Submission: March 30 2015 23:59 PST
Author Notification: April 24 2015
Final Paper Submission: May 24 2015
Workshop: June 14 2015

ORGANIZERS
Christina Delimitrou, Stanford University (cdel@stanford.edu)
Prof. Christos Kozyrakis, Stanford University (kozyraki@stanford.edu)
Prof. Lingjia Tang, University of Michigan (lingjia@eecs.umich.edu)
Prof. Jason Mars, University of Michigan (profmars@eecs.umich.edu)
 

Start: June 14, 2015
End: June 14, 2015
Venue: Portland, Oregon, USA

June 13, 2015

Call for Papers: Workshop on Resource-Efficient Cloud Computing

Submitted by Christina Delimitrou
http://web.stanford.edu/~cdel/rec2

Workshop on Resource-Efficient Cloud Computing
Co-located with ISCA 2015
Half Day Workshop: Saturday, June 13, 2015 (morning)
 

With large-scale datacenters increasing in size and number, the challenge to
improve their efficiency is becoming more pressing. Despite their prevalence,
these systems remain greatly underutilized, even when techniques such as
virtualization and containers are used. Given that building new datacenters or
expanding existing systems is not a scalable approach to increase the compute
capabilities of cloud systems moving forwards, system architects and system
designers must focus on operating and managing these systems more efficiently.
For this reason, over the past few years, resource-efficient cloud computing
has attracted increased attention both from academia and industry. Effectively
improving the resource-efficiency of large-scale systems requires cooperation
among all layers of the system stack, from hardware to OSes, as well as
scheduling and resource management systems and application design. The goal of
the workshop is to bring together cloud computing researchers from academia and
industry, underline the most pressing challenges in large-scale system design,
and encourage new ways of improving the efficiency of these systems.

CALL FOR PAPERS:
We are aiming for a mix of invited talks by experts in academia and industry,
panels and peer-reviewed papers. Peer-reviewed papers will not be published in
workshop proceedings, so submitting to the workshop will not preclude future
publication opportunities. We especially welcome early work and position papers
on future research directions.

Topics include but are not limited to:
- Hardware support for resource partitioning and isolation
- Scheduling, resource management and cloud provisioning systems
- Software techniques for enforcing resource isolation
- Runtimes that improve utilization and application QoS
- Scalable cluster management frameworks
- Bare-metal OSes for cloud applications
- Resource-efficient application design
- Datacenter monitoring and troubleshooting
- Implications of resource-efficiency to datacenter fault-tolerance
- Real-world measurements and analysis of cloud inefficiencies

SUBMISSION GUIDELINES:
Papers should be 4-6 pages long (8.5″ x 11″ pages), including figures and
tables, but not including references. You may include any number of pages for
references. Papers should be formatted in 2 columns, using 10-point type on
12-point leading, in a text block of 6.5″ x 9″. Figures and tables must be
large enough to be legible when printed on 8.5″ x 11″ paper. Papers must be
submitted for single-blind review, i.e., you can include the authors’ names.
Please submit your papers over email to the workshop organizers by the
submission deadline.

For any questions, please contact Christina Delimitrou at cdel@stanford.edu

IMPORTANT DATES:
Paper Submission: April 10 2015 23:59 PST
Author Notification: April 24, 2015
Final Paper Submission: May 24, 2015
Workshop: June 13, 2015

ORGANIZERS:
Christina Delimitrou, Stanford University (cdel@stanford.edu)
Prof. Christos Kozyrakis, Stanford University (kozyraki@stanford.edu)
Prof. Lingjia Tang, University of Michigan (lingjia@eecs.umich.edu)
Prof. Jason Mars, University of Michigan (profmars@eecs.umich.edu)
 

Start: June 13, 2015 9:00 am
End: June 13, 2015 1:00 pm
Venue: Portland, OR