NOTE TO AUTHORS: Paper submission deadlines are earlier than for
previous SELSE workshops.
- Register an abstract: December 8, 2014
- Paper submission: December 15, 2014
- Authors notification: January 30, 2015
- Camera-ready submission: February 18, 2015
The growing complexity and shrinking geometries of modern
manufacturing technologies are making high-density, low-voltage
devices increasingly susceptible to the influences of electrical
noise, process variation, transistor aging, and the effects of natural
radiation. The system-level impact of these errors can be
far-reaching. Growing concern about intermittent errors, unstable
storage cells, and the effects of aging are influencing system design
and failures in memories account for a significant fraction of costly
product returns. Emerging logic and memory device technologies
introduce several reliability challenges that need to be addressed to
make these technologies viable. Finally, reliability is a key issue
for large-scale systems, such as those in data centers. The SELSE
workshop provides a forum for discussion of current research and
practice in system-level error management. Participants from industry
and academia explore both current technologies and future research
directions (including nanotechnology). SELSE is soliciting papers that
address the system-level effects of errors from a variety of
perspectives: architectural, logical, circuit-level, and semiconductor
processes. Case studies are also solicited.
Key areas of interest are (but not limited to):
- Technology trends and the impact on error rates.
- New error mitigation techniques.
- Characterizing the overhead and design complexity of error
- Case studies describing the tradeoffs analysis for reliable systems.
- Experimental silicon failure data.
- System-level models: derating factors and validation of
- Error handling protocols (higher-level protocols for robust
- Characterization of reliability of systems deployed in the field and
mitigation of issues.
Authors are requested to register to submit a paper by December 8th,
2014 and to submit their paper for review by December 15th 2014.
Papers will be considered for both oral and poster presentation, and
all accepted submissions will be distributed to SELSE participants.
Authors will be notified by January 30th, 2015. Final papers are due
on February 18th, 2015.
Additional information and guidelines for submission are available at
http://www.selse.org. Submissions and final papers should be in PDF
following IEEE two-column conference proceedings format that does not
exceed six printed pages. Papers are not made available through IEEE,
and authors retain the copyright of their work. Authors may optionally
choose to make their presentations available online at the workshop
Sarah Michalak, Los Alamos National Laboratory
Helia Naeimi, Intel
Dimitris Gizopoulos, University of Athens
Sudhanva Gurumurthi, AMD/University of Virginia
Dan Alexandrescu, iROC Technologies
Siva Hari, NVIDIA
Local Arrangements Chair:
Vijay Janapa Reddi, UT-Austin
Yi-Pin Fang, TSMC
Paolo Rech, UFRGS
William H. Robinson, Vanderbilt University
Yanos Sazeides, University of Cyprus
Mehdi Tahoori, Karlsruhe Institute of Technology
Marios Kleanthous, Mesoyios College
Advisors to the Committee:
Adrian Evans, iROC Technologies
Vilas Sridharan, AMD
Alan Wood, Oracle