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April 3, 2015

Call for Papers: NAS 2015

Submitted by Ramon Bertran
http://www.nas-conference.org/

10th IEEE International Conference on Networking, Architecture and Storage (NAS)
Boston, Massachusetts, USA,
August 6-7, 2015
 

Sponsored by IEEE Computer Society’s Technical Committees on Computer
Architecture (TCCA), Parallel Processing (TCPP) and Distributed Processing
(TCDP).

IMPORTANT DATES:
– Paper Submission: April 3, 2015
– Notification: May 20, 2015
– Camera-Ready Copy: June 29, 2015

The International Conference on Networking, Architecture, and Storage (NAS)
provides a high-quality international forum to bring together researchers and
practitioners from academia and industry to discuss cutting-edge research on
networking, high-performance computer architecture, and parallel and distributed
data storage technologies. NAS 2015 will expose participants to the most recent
developments in the interdisciplinary areas.

Authors are invited to submit previously unpublished work for possible
presentation at the conference. Papers should be submitted for double-blind
review. The program committee will nominate best papers for recognition in
the three conference topic areas. All papers will be evaluated based on their
novelty, fundamental insight, experimental evaluation, and potential for
long-term impact; new-idea papers are encouraged. All accepted papers will
be published in IEEE digital library.

Papers are solicited in fields that include, but are not limited to, the
following:
- Processor, cache, memory system architectures
- Parallel and multi-core architectures
- GPU architecture and programming
- Data-center scale architectures
- Architecture for handheld or mobile devices
- Accelerator-based architectures
- Application-specific, reconfigurable or embedded architectures
- HW/SW co-design and tradeoffs
- Power and energy efficient architectures and techniques
- Effects of circuits and emerging technology on architecture
- Cloud and grid computing
- Architecture, networking or storage modeling and simulation methodologies
- Non-volatile memory technologies
- Software defined networking
- Storage performance and scalability
- File systems, object-based storage
- Energy-aware storage
- SSD architecture and applications
- Parallel I/O
- Cloud storage
- Storage virtualization and security
- Software defined storage
- Big Data infrastructure
- Big Data services and analytics

ORGANIZATION COMMITTEE
General Chair
– Resit Sendag (U of Rhode Island)
Program Co-Chairs:
– Jun Wang (U of Central Florida)
– Iris Bahar (Brown U)
Vice Program Chairs:
– Networking: Weikuan Yu (Auburn U) and Haiying Shen (Clemson U)
– Architecture: Martin Herbordt (Boston U) and Tali Moreshet (Boston U)
– Storage: Xiaosong Ma (Qatar Computing Res. Inst. & NC State U) and Ali Butt
(Virginia Tech)
Local Arrangements Chair:
– Ningfang Mi (Northeastern U)
Publications Chair:
– Gus Uht (U of Rhode Island)
Registration Chair:
– Yan Sun (U of Rhode Island)
Finance Chair:
– Yan Luo (U of Massachussetts-Lowell)
Industry Liaison Chair:
– Ming Zhang (EMC)
Publicity Co-chairs:
– Chengsheng Xie (Huazhong U Sci. Tech)
– Andre Brinkmann (Universitat Mainz)
– Ramon Bertran (IBM)
– Alper Buyuktosunoglu (IBM)
Submission Chair:
– Xunchao Chen (U of Central Florida)
Web Chair:
– Ibrahim Burak Karsli (U of Rhode Island)
Steering Committee
– Xubin He (Virginia Commonwealth U)
– Changsheng Xie(Huazhong U of Sci.Tech)
– Andre Brinkmann (U Mainz)
– Jian Li (IBM Austin Research Lab)
– Tao Li (University of Florida)
– Marco D Santambrogio (Politec. Milano)
– Hongbin Sun (Xi’An Jiaotong U)

PROGRAM COMMITTEE
Networking Track
– Weikuan Yu, Auburn University (co-chair)
– Haiying Shen, Clemson University (co-chair)
– Sarp Oral, Oak Ridge National Lab
– Shane Canon, Lawrence Berkeley National Lab
– Richard Graham, Mellanox
– Amith R Mamidala, IBM
– Jian Tan, IBM
– Ronald Brightwell, Sandia National Lab
– Gerald F II Lofstead, Sandia National Lab
– Wenjun Wu, Beihang University
– Jia Rao, University of Colorado Cold Springs
– Seung-Jong Park, Louisiana State University
– Xin Yuan, Florida State University
– Saad Biaz, Auburn University
– Kang Chen, Clemson University
– Yaohang Li, Old Dominion University
– Shan Lin, Temple University
– Chuan Yue, University of Colorado Colorado Springs
– Mengjun Xie, University of Arkansas at Little Rock
– Lei Yu, Georgia State University
– Yang Guo, Bell Labs
– Yongning Tang, Illinois State University
– Fangzhe Chang, Bell Labs, Alcatel-Lucent
– Feng Deng, Clemson University
– Weichen Liu, Chongqing University
– Zhi Wang, Tsinghua University
– Xiaojun Hei, Huazhong University of Science and Technology
– Yuan He, Hong Kong University of Science and Technology
– Di Wu, Sun Yat-Sen University
– Liudong Xing, University of Massachusetts Dartmouth
– Gang Zhou, College of William and Mary
– Jiangyi Hu, Devry University
– Junwei Cao, Tsinghua University
– Wenzhong Li, Nanjing University
– Surendar Chandra, EMC Data Protection and Availability Division
– Wei Zhang, Hong Kong University of Science and Technology
– Yao Liu, SUNY Binghamton
– Chiu Tan, Temple University
– Kyoungwon Suh, Illinois State University
Architecture Track
– Martin Herbordt, Boston University (co-chair)
– Tali Moreshet, Boston University (co-chair)
– Lide Duan , University of Texas at San Antonio
– Cesare Ferri , Marvel
– Mark Hempstead , Drexel University
– Ajay Joshi , Boston University
– Dong Li , Qualcomm
– Xiaoyao Liang , Shanghai Jiao Tong University
– Yan Luo , University of Massachusetts Lowell
– Vijay Nagarajan , University of Edinburgh
– Gi-Ho Park , Sejong University
– Dmitry Ponomarev , SUNY
– Kelly Shaw , University of Richmond
– Magnus Sjalander, Uppsala University
– Bharat Sukhwani, IBM
– Radu Teodorescu , Ohio-State University
– Jing Wang , Capital Normal University
– Jason Xue , City University of Hong Kong
– Zhibin Yu , Shenzhen Institute of Advanced Technology
– Jidong Zhai , Tsinghua University
– Dongyuan Zhan , AMD
– Chuanjun Zhang , Intel
– Wei Zhang , Virginia Commonwealth University
– Ping Zhou , Intel
– Zhichun Zhu , University of Illinois at Chicago
Storage Track
– Ali Butt, Virginia Tech (co-chair)
– Xiaosong Ma, Qatar Computing Research Institute and North Carolina State
University (co-chair)
– Youngjae Kim, Oak Ridge National Laboratory
– Gary Liu, Oak Ridge National Laboratory
– Fei Meng, North Carolina State University and PureStorage
– Xing Wu, Amazon
– Xuanhua Shi, Huazhong University of Science and Technology
– Zhe Zhang, Cloudera
– Sudharshan Vazhkuda, ORNL
– Shuibing He, IIT
– Yong Chen, TTU
– Suren Byna, LBL
– Medha Bhadkamkar, Symantec Research Labs
– Avani Wildani, Salk Institute
– Min Li, IBM TJ Watson Research Center
– Aayush Gupta, IBM Almaden Research Center
– Lei Tian, Tintri
– Tao Xie, San Diego State University
– Song Jiang, Wayne State University
– Abhishek Chandra, University of Minnesota
– Jay Lofstead, Sandia National Laboratories
– Jinho Hwang, IBM Research
– Yifeng Zhu, University of Maine
– Xiao Qin, Auburn University
– Douglas Thain, University of Notre Dame
– Alan Sussman, University of Maryland
– Peter Varman, Rice University
– Nitin Agrawal, NEC Labs
– Fang Zheng, IBM T.J. Watson Research Center
– Qingdong Wang, University of Central Florida/Huizhou University
 

Start: April 3, 2015
End: April 3, 2015

March 31, 2015

Call for Papers: Workshop on Silicon Errors in Logic – System Effects

Submitted by William H. Robinson
http://www.selse.org
Workshop on Silicon Errors in Logic – System Effects (SELSE 2015)
March 31 – April 1, 2015 – Austin, TX

NOTE TO AUTHORS: Paper submission deadlines are earlier than for
previous SELSE workshops.

Important dates:
- Register an abstract: December 8, 2014
- Paper submission: December 15, 2014
- Authors notification: January 30, 2015
- Camera-ready submission: February 18, 2015

The growing complexity and shrinking geometries of modern
manufacturing technologies are making high-density, low-voltage
devices increasingly susceptible to the influences of electrical
noise, process variation, transistor aging, and the effects of natural
radiation. The system-level impact of these errors can be
far-reaching. Growing concern about intermittent errors, unstable
storage cells, and the effects of aging are influencing system design
and failures in memories account for a significant fraction of costly
product returns. Emerging logic and memory device technologies
introduce several reliability challenges that need to be addressed to
make these technologies viable. Finally, reliability is a key issue
for large-scale systems, such as those in data centers. The SELSE
workshop provides a forum for discussion of current research and
practice in system-level error management. Participants from industry
and academia explore both current technologies and future research
directions (including nanotechnology). SELSE is soliciting papers that
address the system-level effects of errors from a variety of
perspectives: architectural, logical, circuit-level, and semiconductor
processes. Case studies are also solicited.

Key areas of interest are (but not limited to):
- Technology trends and the impact on error rates.
- New error mitigation techniques.
- Characterizing the overhead and design complexity of error
mitigation techniques.
- Case studies describing the tradeoffs analysis for reliable systems.
- Experimental silicon failure data.
- System-level models: derating factors and validation of
error models.
- Error handling protocols (higher-level protocols for robust
system design).
- Characterization of reliability of systems deployed in the field and
mitigation of issues.

Authors are requested to register to submit a paper by December 8th,
2014 and to submit their paper for review by December 15th 2014.
Papers will be considered for both oral and poster presentation, and
all accepted submissions will be distributed to SELSE participants.
Authors will be notified by January 30th, 2015. Final papers are due
on February 18th, 2015.

Additional information and guidelines for submission are available at
http://www.selse.org. Submissions and final papers should be in PDF
following IEEE two-column conference proceedings format that does not
exceed six printed pages. Papers are not made available through IEEE,
and authors retain the copyright of their work. Authors may optionally
choose to make their presentations available online at the workshop
web site.

Organizing Committee

General Chairs:
Sarah Michalak, Los Alamos National Laboratory
Helia Naeimi, Intel

Program Chairs:
Dimitris Gizopoulos, University of Athens
Sudhanva Gurumurthi, AMD/University of Virginia

Finance Chairs:
Dan Alexandrescu, iROC Technologies
Siva Hari, NVIDIA

Local Arrangements Chair:
Vijay Janapa Reddi, UT-Austin

Publicity Chairs:
Yi-Pin Fang, TSMC
Paolo Rech, UFRGS
William H. Robinson, Vanderbilt University
Yanos Sazeides, University of Cyprus

Documents Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology

Webmaster:
Marios Kleanthous, Mesoyios College

Advisors to the Committee:
Adrian Evans, iROC Technologies
Vilas Sridharan, AMD
Alan Wood, Oracle

Start: March 31, 2015
End: April 1, 2015
Venue: Austin, TX

March 29, 2015

Call for Papers: FastPath 2015

Submitted by Parijat Dube
http://www.ispass.org/ispass2015/fastpath2015

FastPath 2015: Fourth International Workshop on Performance Analysis of
Workload Optimized Systems

Co-located with ISPASS 2015
Philadelphia, PA USA
March 29, 2015

The goal of FastPath is to bring together researchers and practitioners
involved in cross-stack hardware/software performance analysis, modeling,
and evaluation of workload optimized systems. With microprocessor clock
speeds being held constant, optimizing systems around specific workloads
is an increasingly attractive means to improve performance.
More precisely, workload optimized systems have hardware
and/or software specifically designed to run well for a
particular application or application class. The types and
components of workload optimized systems vary, but a partial list
includes traditional CPUs assisted with accelerators
(ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators,
hybrid systems, converged infrastructure, and IT appliances.

The importance of workload optimized systems is seen
in their ubiquitous deployment in diverse systems from
cellphones to tablets to routers to game machines to
Top500 supercomputers. Prominent commercial examples of
workload optimized systems include IBM DataPower, IBM Purescale
Application System, IBM Watson, Oracle Exadata, and HP Moonshot Servers.
Exploiting CPU savings and speed-ups offered by workload optimized
systems for application level performance improvement poses several
cross stack hardware and software challenges. These include
developing alternate programming models to exploit massive
parallelism offered by accelerators, designing low-latency,
high-throughput H/W-S/W interfaces,developing techniques to
efficiently map processing logic on hardware, and
cross system stack performance optimization and tuning.
Emerging infrastructure supporting big data analytics,
cognitive computing, large-scale machine learning, mobile computing,
and internet-of-things, further exemplify workload optimized design
at large.

TOPICS:
FastPath seeks to facilitate the exchange of ideas on performance analysis
and evaluation of workload optimized systems and seeks papers on a wide
range of topics including, but not limited to:
- Workload characterization and profiling
- Industrial experiences
- GPUs, FPGAs, ASIC accelerators
- Memory, I/O, Storage, Network accelerators
- Hardware/Software co-design
- Workload optimized servers
- Hybrid/Heterogeneous systems
- Measurements and Experimentation
- Analytical techniques
- Performance modeling and prediction
- Performance tooling and optimization
- Programming models for workload optimized systems
- Runtime management systems
- Workload scheduling and orchestration
- Workload optimized clusters in Cloud
- Big Data analytics systems
- Large-scale machine learning systems
- Intelligent/Cognitive systems
- Mobile computing systems
- Converged/integrated infrastructure
- Workload optimized systems from specific domains,
e.g., financial, biological, education, commerce, healthcare.

SUBMISSIONS:
The authors should submit PDF of a 2-4 page extended abstract by the
submission deadline at

https://www.easychair.org/conferences/?conf=fastpath2015

The submission should follow standard format (2-column,
10 to 12-point type, single spaced, 1-inch margins).
Abstracts should provide sufficient detail about the work
and its technical contributions.

Authors of selected abstracts will be invited to present their work
at the workshop. Accepted abstracts will be made available through
the workshop website and hard copies will be provided at the
workshop to the attendees. There are no copyright issues with FastPath,
and thus authors retain the copyright of their work with complete
freedom to submit their work elsewhere.

IMPORTANT DATES:
Submission: March 1, 2015
Author Notification: March 10, 2015
Workshop: March 29, 2015

ORGANIZING COMMITTEE:
General Chair:
Erik Altman (IBM)

Program Chairs:
Vijay Janapa Reddi (U-Texas, Austin)
Parijat Dube (IBM)

Web Chair: Augusto Vega (IBM)

PROGRAM COMMITTEE:
David Brooks, Harvard University
Trey Cain, Qualcomm Research
Mike Ferdman, Stony Brook University
Sudhanva Gurumurthi, AMD, University of Virginia
Eric Van Hensbergen, ARM Research
Arrvindh Shriraman, Simon Fraser University
Devesh Tiwari, Oak Ridge National Lab
Sudhakar Yalamanchili, Georgia Tech
Chuanjun Zhang, Intel
 

Start: March 29, 2015
End: March 29, 2015
Venue: Philadelphia, PA, USA.

Call for Participation: ISPASS 2015

Submitted by Kelly Shaw
http://ispass.org

2015 IEEE International Symposium on Performance Analysis of Systems
and Software (ISPASS)

Philadelphia, PA USA
March 29-31, 2015
 

EARLY REGISTRATION DEADLINE: March 1st, 2015 at 5PM Pacific

Online registration: http://www.regonline.com/ispass15

ISPASS 2015 will be held at the Hyatt Regency Philadelphia at Penn’s Landing.
Please use the following link to register for the hotel:

https://resweb.passkey.com/go/ieeehq2015

Note: The hotel registration cutoff is March 7, 2015.

VISA FOR TRAVEL TO U.S.
If you require an invitation letter for purposes of a visa application, please
send an email with your name, email address, mailing address, IEEE
member number (if any), the ID of the paper you are presenting (if any) and
a copy of your registration confirmation to Jose Renau, the Program Chair,
at renau@ucsc.edu.

The 2015 IEEE International Symposium on Performance Analysis of Systems and
Software is sponsored by the IEEE Computer Society’s Technical Committee on
Internet, Technical Committee on Computer Architecture, and Technical Committee
on Microprogramming and Microarchitecture.

For the conference program and other details, please visit http://ispass.org
 

Start: March 29, 2015
End: March 31, 2015
Venue: Philadelpha, PA

March 24, 2015

Call for Papers: Workshop on Multi-Objective Many-Core Design

Submitted by Stefan Wildermann
https://www12.cs.fau.de/momac/

Call for Papers: Second International Workshop on Multi-Objective Many-Core Design (MOMAC)
in conjunction with International Conference on Architecture of Computing Systems (ARCS 2015)
Porto, Portugal, March 24, 2015

IMPORTANT DATES
Paper submission deadline: December 1, 2014
Notification of acceptance: January 16, 2015
Final version: February 16, 2015

ABOUT MOMAC
Semiconductor industry is hitting the utilization wall, resulting in
parallel and heterogeneous many-core architectures. Applications have
to exploit the available parallelism and heterogeneity to meet their
functional and non-functional requirements and to gain performance
improvements. A main challenge originates from many-cores promoting
highly dynamic usage scenarios as already observable in today’s “smart
devices”, where multiple and varying numbers of applications are
running at different points in time. As a consequence, providing
mapping of applications to processor cores which is optimal and
predictable with respect to performance, timing, energy consumption,
safety, security, etc. may not be guaranteed by static design-time
optimization alone. At the same time, pure run-time optimization may
result in unpredictable and non-optimal system states. This workshop
investigates this field of tension of run-time, design-time, and
hybrid design methodologies for the mapping of applications on
many-core systems, particularly addressing the aspect of multiple
conflicting objectives that drive the design.

This field of research includes numerous intermeshed aspects:
- Languages, Models, and Compilers: How to specify, analyze,
parallelize, and compile programs which support dynamic usage
scenarios in many-cores?
- Formal methods, Test, and Verification: How to analyze and verify
predictable execution of applications despite unforeseeable
run-time events?
- Optimization Techniques: Which design-time and run-time techniques
as well as combinations of them provide optimized and predictable
application mapping for many-cores?
- Architecture: Which architectural concepts are required to support
predictability, run-time management and (self-)optimization?

TOPICS OF INTEREST
Topics of interest include, but are not limited to:

Multiple Objectives and Predictability
- Performance
- Hard & Soft Real-time
- Energy Efficiency
- Fault Tolerance & Reliability
- Safety
- Security
- Scalability
- Flexibility

Specification
- Programming
- Modelling
- Parallelization
- Resource awareness

Design-time Optimization
- Multi-Objective Optimization
- Design Space Exploration
- Verification
- Profiling
- Performance Analysis

Run-time Optimization
- Resource Management
- Temperature and Power Management
- Decentralized vs Centralized Management
- Reconfigurable Computing
- Operating System
- Online Verification
- Auto-tuning
- Machine Learning

Architecture
- Architectural Predictability
- Reconfiguration
- Power Management
- Benchmarking
- Monitoring

SUBMISSION
Paper can be submitted as regular papers or as position papers.
Formats requirements:

- up to 8 pages (regular paper) IEEE style
- 4 pages (position paper) IEEE style: Preliminary and exploratory
work are welcome in this category, including wild & crazy ideas.
Authors submitting papers in this category must prepend
“Position Paper:” to the title of the submitted paper.

Papers are required to be in English using the IEEE style in A4 paper
size.

Full Paper submission until December 01, 2014 via EasyChair:

https://easychair.org/conferences/?conf=momac2015

All papers undergo a blind review process. Authors will be notified
until January 16, 2015. Final version is due to February 16, 2015.
All accepted papers will be published in the ARCS Workshop Proceedings
and are expected to be published online under IEEE Xplore.

LOCATION
MOMAC will be held conjunction with the 28th International Conference
on Architecture of Computing Systems (ARCS 2015), March 24-27,
2015 in Porto, Portugal.

ORGANIZERS
Stefan Wildermann (FAU, Germany, stefan.wildermann@fau.de)
Michael Glaß (FAU, Germany, michael.glass@fau.de)

PROGRAM COMMITTEE
Lars Bauer (Karlsruhe Institute of Technology (KIT), Germany)
Jens Gladigau (Robert Bosch GmbH, Germany)
Omar Hammami (ENSTA, France)
Markus Happe (ETH Zurich, Switzerland)
Christian Haubelt (University of Rostock, Germany)
Akash Kumar (National University of Singapore, Singapore)
Martin Lukasiewycz (TUM CREATE, Singapore)
Sanaz Mostaghim (Otto von Guericke University of Magdeburg, Germany)
Mathias Pacher (University of Hannover, Germany)
Gianluca Palermo (Politecnico Di Milano, Italy)
Marco Domenico Santambrogio (Politecnico di Milano, Italy)
Muhammad Shafique (Karlsruhe Institute of Technology (KIT), Germany)
Lucian Vintan (Lucian Blaga University of Sibiu, Romania)
Sebastian Voss (fortiss GmbH, Germany)

Start: March 24, 2015
End: March 24, 2015
Venue: Porto, Portugal

Call for Papers: Workshop on Multi-Objective Many-Core Design (Deadline Extension)

Submitted by Stefan Wildermann
https://www12.cs.fau.de/momac/

2nd International Workshop on Multi-Objective Many-Core Design (MOMAC)
in conjunction with ARCS 2015
Porto, Portugal
March 24, 2015

Regular Paper submission deadline (EXTENDED): December 8, 2014

Special Call for 4-page Position Papers and Tutorials

IMPORTANT DATES:
Paper submission deadline: December 8, 2014 (extended)
Notification of acceptance: January 16, 2015
Final version: February 16, 2015

ABOUT MOMAC:
Semiconductor industry is hitting the utilization wall, resulting in
parallel and heterogeneous many-core architectures. Applications have
to exploit the available parallelism and heterogeneity to meet their
functional and non-functional requirements and to gain performance
improvements. A main challenge originates from many-cores promoting
highly dynamic usage scenarios as already observable in today’s “smart
devices”, where multiple and varying numbers of applications are
running at different points in time. As a consequence, providing
mapping of applications to processor cores which is optimal and
predictable with respect to performance, timing, energy consumption,
safety, security, etc. may not be guaranteed by static design-time
optimization alone. At the same time, pure run-time optimization may
result in unpredictable and non-optimal system states. This workshop
investigates this field of tension of run-time, design-time, and
hybrid design methodologies for the mapping of applications on
many-core systems, particularly addressing the aspect of multiple
conflicting objectives that drive the design.

This field of research includes numerous intermeshed aspects:
- Languages, Models, and Compilers: How to specify, analyze,
parallelize, and compile programs which support dynamic usage
scenarios in many-cores?
- Formal methods, Test, and Verification: How to analyze and verify
predictable execution of applications despite unforeseeable
run-time events?
- Optimization Techniques: Which design-time and run-time techniques
as well as combinations of them provide optimized and predictable
application mapping for many-cores?
- Architecture: Which architectural concepts are required to support
predictability, run-time management and (self-)optimization?

TOPICS OF INTEREST:
Topics of interest include, but are not limited to:

Multiple Objectives & Predictability
- Performance
- Hard & Soft Real-time
- Energy Efficiency
- Fault Tolerance & Reliability
- Safety
- Security
- Scalability
- Flexibility

Specification
- Programming
- Modelling
- Parallelization
- Resource awareness

Design-time Optimization
- Multi-Objective Optimization
- Design Space Exploration
- Verification
- Profiling
- Performance Analysis

Run-time Optimization
- Resource Management
- Temperature and Power Management
- Decentralized vs Centralized Management
- Reconfigurable Computing
- Operating System
- Online Verification
- Auto-tuning
- Machine Learning

Architecture
- Architectural Predictability
- Reconfiguration
- Power Management
- Benchmarking
- Monitoring

SUBMISSION:
Paper can be submitted as regular papers or as position papers.
Formats requirements:
- up to 8 pages (regular paper) IEEE style
- 4 pages (position paper) IEEE style: Preliminary and exploratory
work are welcome in this category, including wild & crazy ideas.
Authors submitting papers in this category must prepend
“Position Paper:” to the title of the submitted paper.
- This year: Special call for Tutorials, introducing tools and
techniques for modeling, programming, analysis, and optimization
of many-core systems. Each tutorial should be accompanied by a
4-page tutorial paper. The title of a tutorial paper should be
prepended with “Tutorial:”.

The proceedings will be published through VDE Verlag on CD and online
by the IEEE Computer Society through the IEEE Xplore Digital Library.
Papers should not exceed 8 pages (regular papers) or 4 pages (position
& tutorial papers) in IEEE format A4, templates can be found at

http://www.ieee.org/conferences_events/conferences/publishing/

templates.html

PDF submission via EasyChair:

https://easychair.org/conferences/?conf=momac2015

By submitting a paper, the authors accept the copyright form:

http://www.cister.isep.ipp.pt/arcs2015/VDE_copy_engl.pdf

Paper submission deadline: December 8, 2014 (extended).

All papers undergo a blind review process. Authors will be notified
until January 16, 2015. Final version is due to February 16, 2015.
All accepted papers will be published in the ARCS Workshop Proceedings
and by the IEEE Computer Society, through the IEEE Xplore Digital Library.

LOCATION:
MOMAC will be held conjunction with the 28th International Conference
on Architecture of Computing Systems (ARCS 2015), March 24-27,
2015 in Porto, Portugal.

ORGANIZERS:
Stefan Wildermann (FAU, Germany, stefan.wildermann@fau.de)
Michael Glaß (FAU, Germany, michael.glass@fau.de)

PROGRAM COMMITTEE:
Lars Bauer (Karlsruhe Institute of Technology (KIT), Germany)
Jens Gladigau (Robert Bosch GmbH, Germany)
Omar Hammami (ENSTA, France)
Markus Happe (ETH Zurich, Switzerland)
Christian Haubelt (University of Rostock, Germany)
Jörg Hähner (Augsburg University, Germany)
Akash Kumar (National University of Singapore, Singapore)
Martin Lukasiewycz (TUM CREATE, Singapore)
Sanaz Mostaghim (Otto von Guericke University of Magdeburg, Germany)
Mathias Pacher (University of Hannover, Germany)
Gianluca Palermo (Politecnico Di Milano, Italy)
Sophie Quinton (INRIA, France)
Marco Domenico Santambrogio (Politecnico di Milano, Italy)
Muhammad Shafique (Karlsruhe Institute of Technology (KIT), Germany)
Lucian Vintan (Lucian Blaga University of Sibiu, Romania)
Sebastian Voss (fortiss GmbH, Germany)

Start: March 24, 2015
End: March 24, 2015
Venue: Porto, Portugal

March 23, 2015

Call for Papers: Workshop on Architectures and Systems for Big Data

Submitted by Boris Grot
http://acs.ict.ac.cn/asbd2015/

Fifth Workshop on Architectures and Systems for Big Data (ASBD 2015)
Held in conjunction with ISCA 2015
Portland, Oregon, USA
June 13, 2015
 

IMPORTANT DATES:
Submissions deadline: April 10, 2015
Author notification: April 31, 2015

The workshop will provide a forum to exchange research ideas related to all
aspects of emerging analytics systems for big data, including architectural
support, benchmarks and metrics, data management software, operating
systems, and emerging challenges and opportunities. We hope to attract a
group of interdisciplinary researchers from academia, industry and government
research labs. To encourage discussion between participants, the workshop
will include significant time for interactions between the presenters and the
audience. We also plan to have a keynote speaker and a panel session.

Topics of interest include but are not limited to:
- Processor, memory and system architectures for data analytics
- Benchmarks, metrics and workload characterization for big data
- Accelerators for analytics and data-intensive computing
- Implications of data analytics to mobile and embedded systems
- Energy efficiency and energy-efficient designs for analytics
- Availability, fault tolerance and data recovery in big data environments
- Scalable system and network designs for high concurrency/bandwidth streaming
- Data management and analytics for vast amounts of unstructured data
- Evaluation tools, methodologies and workload synthesis
- OS, distributed systems and system management support for large-scale analytics
- Debugging and performance analysis tools for analytics and big data
- Programming systems and language support for deep analytics
- MapReduce and other processing paradigms for analytics

Preliminary results of interesting ideas and works-in-progress are welcome.
Submissions that are likely to generate vigorous discussion will be favored!

SUBMISSIONS:
All papers should be submitted in PDF format, using 10 point or larger font
for text (8 points or larger for figures and tables), total length not to
exceed 6 pages.
Submission site: https://www.easychair.org/conferences/?conf=asbd2015

WORKSHOP ORGANIZERS:
Yungang Bao, ICT/CAS China
Boris Grot, University of Edinburgh
Lixin Zhang, ICT/CAS China

PROGRAM COMMITTEE:
Rajeev Balasubramonian, University of Utah
Arka Basu, AMD
Yunji Chen, ICT
Eric Chung, Microsoft
Babak Falsafi, EPFL
Mike Ferdman, Stony Brook University
John Kim, KAIST
Chao Li, Shanghai Jiao Tong University
Tao Li, University of Florida
David Meisner, Facebook
Lingjia Tang, University of Michigan

STEERING COMMITTEE:
Jian Li, Huawei
Jichuan Chang, HP Labs
Evan Speight, IBM Research  

Start: March 23, 2015
End: March 23, 2015
Venue: Portland, Oregon, USA

March 15, 2015

Call For Papers: Workshop on Approximate Computing Across the System Stack

Submitted by Natalie Enright Jerger
https://sites.google.com/site/2wacas/

Second Workshop on Approximate Computing Across the System
Stack (WACAS)

Co-located with ASPLOS 2015
Istanbul, Turkey
March 15, 2015
 

Traditional computing imposes an “exactness” that is becoming both
energy expensive and unnecessary, especially so in the era of big data.
The relaxation of accuracy, and more importantly the relaxation of the
requirement of deterministic execution provide an opportunity to explore
new energy-efficient execution models to process this vast data. Recently,
the approximate computing paradigm has continued to gain importance
as a vehicle to reason about changes across the stack from algorithms to
devices to produce results that are acceptable albeit different from exact
computation.

Making approximate computing successful requires cooperation among
all layers of the stack, from algorithms to programming languages to OSes
to architecture to circuits, as well as system components like storage and
networks. This workshop aims to bring together an interdisciplinary group
of researchers to present and discuss thoughts and ideas on how to
effectively exploit approximate computing.

Topics include but are not limited to the following:
- Position papers on approximate computing: trends, potential, pitfalls
- Cross-layer approximate computing solutions
- Hardware/Software support for approximate computing
- Tools for writing, debugging, and reasoning about approximate programs
- Characterization of workloads suitable to approximation
- Methodology/Models to estimate cost/benefits of approximate computing
solutions

SUBMISSIONS:
Peer-reviewed papers will not be published in a proceedings, so submitting
to WACAS will not preclude future publication opportunities.

Prospective authors of research papers should aim for 6 pages including
references.

Submissions may optionally be blind: authors can choose whether to include
their names.

Submission website: https://easychair.org/conferences/?conf=wacas2015

IMPORTANT DATES:
Paper submission: February 2, 2015
Author notification: February 16, 2015
Camera-ready submission: Mach 2, 2015
Workshop: Sunday, March 15, 2015

ORGANIZING COMMITTEE:
Vijayalakshmi Srinivasan, IBM T.J. Watson Research Center
Rajeev Balasubramonian, University of Utah
Hadi Esmaeilzadeh, Georgia Tech
Kailash Gopalakrishnan, IBM T.J. Watson Research Center
Natalie Enright Jerger, University of Toronto
Rakesh Kumar, University of Illinois Urbana-Champaign
Avinash Lingamneni, Cadence
Asit Mishra, Intel
Daniel Prener, IBM T.J. Watson Research Center
Anand Raghunathan, Purdue University
Lakshminarayanan Renganarayana, Symantec
Yavuz Yetim, Google
 

Start: March 15, 2015
End: March 15, 2015
Venue: Istanbul, Turkey

March 14, 2015

Call for Talk Proposals: Workshop on Cognitive Architectures

Submitted by Karthik Swaminathan
http://researcher.watson.ibm.com/researcher/view_group.php?id=5848

Workshop on Cognitive Architectures (CogArch)
Co-located with ASPLOS 2015
Istanbul, Turkey
March 14th, 2015
 

Deadline for submission: February 9th, 2015
Notification of Acceptance: February 16th, 2015

The emerging new interest in cognitive computing points to the need for
defining hardware-software co-optimized architectures in support of this
new paradigm. This workshop proposes to bring together researchers and
practitioners within systems architecture, computer vision, artificial
intelligence and robotics to discuss the latest ideas, applications and
commercialization strategies around the cognitive computing theme. The
primary focus is expected to be on driving towards a better
understanding of key cognitive algorithms of interest and the
architectural support issues thereof. Of particular interest is the
special application area of mobile cognition: the distributed swarm
intelligence represented by the promise of connected cars or a
cooperating group of unmanned aerial and ground vehicles (UAVs and
UGVs), distributed agents, robots, etc. The need for real-time response,
coupled by the requirements of high energy efficiency and system
resilience make this a particularly interesting and challenging arena
for multi-disciplinary research innovations.

Topics of interest include (but not limited to):
- Algorithms in support of cognitive reasoning: recognition, intelligent
search, diagnosis, inference and informed decision-making.
- Swarm intelligence and distributed architectural support; brain-inspired
and neural computing architectures.
- Accelerators and microarchitectural support for cognitive computing.
- Cloud-backed autonomics and mobile cognition: architectural and OS
support thereof.
- Resilient design of distributed (swarm) mobile cognitive architectures.
- Energy efficiency, battery life extension and endurance in mobile, cognitive
architectures.
- Case studies and real-life demonstration prototypes in specific application
domains: e.g. connected cars and UAV-driven commercial services, defense
and homeland security applications.

SUBMISSIONS:
We invite interested participants to send in a lecture proposal (30 mins
minimum to 60 mins maximum). The submission should include a title and
abstract, along with a bio-sketch of the speaker and the proposed talk
duration. Submitted lecture proposals will be reviewed by a Workshop
Program Committee (TBA) chaired by the co-organizers. Please e-mail your
submissions to one of the organizers, with the subject: “CogArch 2015: “.

ORGANIZERS:
Karthik Swaminathan (kvswamin@us.ibm.com), IBM T.J Watson
Chung-Ching Lin (cclin@us.ibm.com), IBM T.J Watson
Sharath Pankanti (sharat@us.ibm.com), IBM T.J Watson
Pradip Bose (pbose@us.ibm.com), IBM T.J Watson

 

Start: March 14, 2015 8:00 am
End: March 14, 2015 12:00 pm
Venue: Istanbul, Turkey

Call for Papers: ASPLOS 2015

Submitted by Engin Ipek
http://asplos15.bilkent.edu.tr/
20th International Conference on
Architectural Support for Programming Languages and Operating Systems

Istanbul, Turkey, March 14-18, 2015

ASPLOS is the premier forum for multidisciplinary systems research spanning
computer architecture and hardware, programming languages and compilers,
operating systems and networking, as well as applications and user interfaces.
The 2015 conference will be held in Istanbul, Turkey, a city where two
continents meet on the blue waters of the Bosphorus to offer an abundance of
unique natural, historical, cultural, and culinary experiences.

Like its predecessors, ASPLOS 2015 invites papers on ground-breaking research
at the intersection of at least two ASPLOS disciplines:
architecture, programming languages, operating systems, and related areas.
Non-traditional topics are especially encouraged.
The importance of cross-cutting
research continues to grow as we grapple with the end of Dennard scaling,
the explosion of big data, scales ranging from ultra-low power wearable devices
to exascale parallel and cloud computers, the need for sustainability, and
increasingly human-centered applications.

ASPLOS embraces systems research that directly targets these new problems
in innovative ways.
The research may target diverse goals such as performance, energy and thermal
efficiency, resiliency, security, and sustainability.
The review process will be sensitive to the challenges of
multidisciplinary work in emerging areas.

Areas of interest include, but are not limited to:
-Emerging platforms at all scales, from embedded to cloud
-Heterogeneous multicore architectures and accelerators
-Systems for enabling parallelism at an extreme scale
-Non-traditional computing systems
-Systems that address social, educational, and environmental challenges
-Programming models and compilation for existing and emerging platforms
-Managing, storing, and computing on big data
-Virtualization
-Memory and storage technologies and architectures
-Power, energy, and thermal management
-Security, reliability, and availability
-Verification and testing, and their impact on design

Papers should be submitted for double-blind review
following the submission guidelines available at the conference website –

http://asplos15.bilkent.edu.tr

Important dates:

Abstracts July 31, 2014
Full Paper Submissions Aug 7, 2014
Author Response Period Oct 20-22, 2014
Notification Nov 10, 2014
Final Copy Deadline Jan 14, 2015*

*Proceedings will be available in the
ACM DL up to two weeks prior to the conference

General Co-Chairs: Kemal Ebcioglu, Global Supercomputing Corporation
Ozcan Ozturk, Bilkent University

Program Chair: Sandhya Dwarkadas, University of Rochester

Program Committee:
Rajeev Balasubramonian, U. Utah / HP Labs
Andrew Baumann, Microsoft
Ricardo Bianchini, Rutgers U. / Microsoft
Hans Boehm, Google
John Carter, IBM Research
Calin Cascaval, Qualcomm
Yunji Chen, ICT, Chinese Academy of Sciences
Andrew Chien, U. Chicago / Argonne
Alan Cox, Rice U.
John Criswell, U. Rochester
Angela Demke, Brown U. Toronto
Peter Druschel, Max Planck Inst. for Software Systems (MPI-SWS)
Sandhya Dwarkadas, U. Rochester (chair)
Jason Flinn, U. Michigan
Antonio Gonzalez, UPC Barcelona
R. Govindarajan, IISc, India
Dan Grossman, U. Washington
Boris Grot, U. Edinburgh
Erik Hagersten, Uppsala U.
Mary Hall, U. Utah
Kim Hazelwood, Google
Gernot Heiser, NICTA / UNSW, Australia
Hillery Hunter, IBM Research
Alvin Lebeck, Duke U.
David Meisner, Facebook
Jason Nieh, Columbia U.
Mark Oskin, U. Washington
Steve Reinhardt, AMD
Jennifer Sartor, Ghent U.
Xipeng Shen, College of William and Mary
Tatiana Shpeisman, Intel
Asia Slowinska, Vrije U. Amsterdam
Serdar Tasiran, Koc U., Turkey
Dan Tsafrir, Technion
Jeffrey Vetter, Oak Ridge National Lab / Georgia Tech.
Yuanyuan Zhou, UC San Diego

Publicity Chairs:
Onur Mutlu, Carnegie Mellon University
Engin Ipek, University of Rochester
Atakan Dogan, Anadolu University

Registration Chair:
Ulya Karpuzcu, University of Minnesota, Twin Cities

Finance Chair:
Smail Niar, University of Valenciennes

Industry Chairs:
Emre Ozer, ARM
Bugra Gedik, Bilkent University

Workshop Chairs:
Alper Buyuktosunoglu, IBM
Augusto Vega, IBM
Haluk Topcuoglu, Marmara University

Publication Chair:
Seda Ogrenci Memik, Northwestern University

Poster/Lightning Session Chair:
Arrvindh Shriraman, Simon Fraser University

Local Arrangements Chair:
Alper Sen, Bogazici University

Travel Grant Chair:
Suleyman Tosun, Ankara University

Web Chair:
Oguz Ergin, TOBB University

Tutorial Chairs:
Osman Unsal, Barcelona Supercomputing Center
Serdar Tasiran, Koc University

Student Advocates:
Gurhan Kucuk, Yeditepe University

Steering Committee:
Sarita Adve, UIUC
Rajeev Balasubramonian, U. Utah
Ras Bodik, UC Berkeley
Doug Burger, Microsoft
George Candea, EPFL
Al Davis, U. Utah
Jeremy Gibbons, Oxford University
Vivek Sarkar, Rice University
David Wood, U. Wisconsin

Start: March 14, 2015
End: March 18, 2015
Venue: Istanbul, Turkey