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October 21, 2014

Call for Papers: Dynamic Languages Symposium

Submitted by Edd Barrett
Dynamic Languages Symposium 2014
October 21, 2014

Co-located with SPLASH 2014, Portland, OR, USA

The 10th Dynamic Languages Symposium (DLS) at SPLASH 2014 is the premier
forum for researchers and practitioners to share knowledge and research on
dynamic languages, their implementation, and applications. The influence of
dynamic languages — from Lisp to Smalltalk to Python to Javascript — on
real-world practice, and research, continues to grow.

DLS 2014 invites high quality papers reporting original research, innovative
contributions, or experience related to dynamic languages, their
implementation, and applications. Accepted papers will be published in the
ACM Digital Library, and freely available for 2 weeks before and after the
event itself. Areas of interest include but are not limited to:

* Innovative language features and implementation techniques
* Development and platform support, tools
* Interesting applications
* Domain-oriented programming
* Very late binding, dynamic composition, and run-time adaptation
* Reflection and meta-programming
* Software evolution
* Language symbiosis and multi-paradigm languages
* Dynamic optimization
* Hardware support
* Experience reports and case studies
* Educational approaches and perspectives
* Semantics of dynamic languages


Submissions should not have been published previously nor be under review at
other events. Research papers should describe work that advances the current
state of the art. Experience papers should be of broad interest and should
describe insights gained from substantive practical applications. The program
committee will evaluate each contributed paper based on its relevance,
significance, clarity, length, and originality.

Papers are to be submitted electronically at in PDF format. Submissions
must be in the ACM format (see
and not exceed 12 pages. Authors are reminded that brevity is a virtue.

DLS 2014 will run a two-phase reviewing process to help authors make their
final papers the best that they can be. After the first round of reviews,
papers will be rejected, conditionally accepted, or unconditionally accepted.
Conditionally accepted papers will be given a list of issues raised by
reviewers. Authors will then submit a revised version of the paper with a
cover letter explaining how they have / why they have not addressed these
issues. The reviewers will then consider the cover letter and revised paper
and recommend final acceptance / rejection.

Important dates

Submissions: June 8 2014 (FIRM DEADLINE)
First phase notification: July 14 2014
Revisions due: August 4 2014
Final notification: August 11 2014
Camera ready: August 15 2014
DLS: October 21 2014

Programme chair

Laurence Tratt, King’s College London, UK

Publicity chair

Edd Barrett, King’s College London, UK

Programme committee

Gilad Bracha, Google, US
Jonathan Edwards, MIT, US
Robert Hirschfeld, Hasso-Plattner-Institut Potsdam, DE
Roberto Ierusalimschy, PUC-Rio, BR
Sergio Maffeis, Imperial College London, UK
Stefan Marr, INRIA, FR
Oscar Nierstrasz, University of Bern, CH
James Noble, Victoria University of Wellington, NZ
Shriram Krishnamurthi, Brown University, US
Chris Seaton, University of Manchester, UK
Nikolai Tillmann, Microsoft Research, US
Sam Tobin-Hochstadt, Indiana University, US
Jan Vitek, Purdue University, US
Christian Wimmer, Oracle Labs, US
Peng Wu, IBM Research, US

Start: October 21, 2014
End: October 21, 2014
Venue: Portland, OR, USA

September 19, 2014

Call for Papers: ISPASS 2015

Submitted by Kelly Shaw
2015 IEEE International Symposium on Performance Analysis of Systems and

Philadelphia, PA
March 29-31, 2015

Abstracts Due: September 19, 2014
Full Submissions Due: September 26, 2014

The IEEE International Symposium on Performance Analysis of Systems and
Software provides a forum for sharing advanced academic and industrial
research work focused on performance analysis in the design of
computer systems and software. Authors are invited to submit
previously unpublished work for possible presentation at the
conference. Papers are solicited in fields that include the

* Performance and power evaluation methodologies
– Analytical modeling
– Statistical approaches
– Tracing and profiling tools
– Simulation techniques
– Hardware (e.g. FPGA) accelerated simulation
– Hardware performance counter architectures
– Power/Temperature/Variability/Reliability models for computer systems
– Micro-benchmark based hardware analysis techniques

* Performance and power analysis
– Metrics
– Bottleneck identification and analysis
– Visualization

* Power/Performance analysis of commercial and experimental hardware
– General-purpose microprocessors
– Multi-threaded, multi-core and many-core architectures
– Accelerators and graphics processing units
– Embedded and mobile systems
– Enterprise systems and data centers
– Supercomputers
– Computer networks

* Power/Performance analysis of emerging workloads and software
– Software written in managed languages
– Virtualization and consolidation workloads
– Internet-sector workloads
– Embedded, multimedia, games, telepresence
– Bioinformatics, life sciences, security, biometrics

* Application and system code tuning and optimization

* Confirmations or refutations of important prior results

In addition to research papers, we also welcome tool papers. The
conference is an ideal forum to publicize new tools to the
community. Tool papers will be judged primarily on their potentially
wide impact and use than on their research contribution. Tools in any
of the above fields of interest are eligible.

See for submission details.

Paper abstract submission: September 19, 2014
Full submission: September 26, 2014
Rebuttal: December 3-4, 2014
Notification: December 11, 2014
Final paper due: January 31, 2015

Benjamin C. Lee, Duke University

Jose Renau, UC Santa Cruz

Alaa Alameldeen, Intel
Fred Chong, University of California – Santa Barbara
Stijn Eyerman, Ghent University
Ilya Ganusov, Xilinx
Kanad Ghose, Binghamton University
Joseph Greathouse, AMD
Andrew Hilton, Duke University
Michael Huang, Rochester University
Chris Hughes, Intel
Russ Joseph, Northwestern University
Ulya R. Karpuzcu, University of Minnesota
Omer Khan, University of Connecticut
Nam Sung Kim, University of Wisconsin – Madison
Krishna Malladi, Samsung
Jason Mars, University of Michigan
Albert Meixner, Google
Gokhan Memik, Northwestern University
Andreas Moshovos, University of Toronto
David Penry, Brigham Young University
Vijay Janapa Reddi, University of Texas – Austin
Bronis de Supinski, Lawrence Livermore National Laboratory
Lingjia Tang, University of Michigan
Radu Teodorescu, Ohio State University
Devesh Tiwari, Oak Ridge National Laboratory
David Wentzlaff, Princeton University
Walid Najjar, University of California – Riverside

Kelly Shaw, University of Richmond

Nadeem Malik, IBM

Houman Homayoun, George Mason University

Mike Ferdman, Stonybrook University

Drew Hilton, Duke University

Mark Hempstead, Drexel University

Suzanne Rivoire, Sonoma State University

Rajeev Balasubramonian, University of Utah
Lieven Eeckhout, Ghent University
Craig Chase, University of Texas
David Brooks, Harvard University
Lizy John, University of Texas
Nadeem Malik, IBM
Pradip Bose, IBM Research
Nasr Ullah, Samsung
David Albonesi, Cornell University
Sandhya Dwarkadas, University of Rochester
Vijayalakshmi Srinivasan, IBM Research

Start: September 19, 2014
End: September 19, 2014

September 15, 2014

Call for Nominations: MICRO Test of Time Award 2014

Submitted by Onur Mutlu
MICRO Test of Time Award — Call for Nominations (deadline: September 15, 2014)

PDF link:
Eligible papers:

The Micro Test-of-Time (ToT) Award Committee is soliciting nominations
for the first Micro ToT Award to be given at the International
Symposium on Microarchitecture in December 2014, to be held in
Cambridge, United Kingdom. This is a new award that is established to
recognize the most influential papers published in past Micro
conferences that have had significant impact in the field.

For this special first year when the award is to be given the first
time (2014), the award will recognize at most ten papers that were
published at Micro conferences held between 1968-1992 (1968 and 1992
inclusive). After this “bootstrapping” year, at steady state, the
award will recognize an influential Micro paper whose influence is
still felt 18-22 years after its initial publication. In other words,
in each future year N (where N >= 2015), the award will be given to
one paper that was published at Micro conferences in any of the years
N-22, N-21, N-20, N-19, or N-18. Paper nominations will not carry over.
That is, a paper nominated in 2015 (e.g.) will not be carried-over
for nomination in 2016 or later — it must be renominated while

We invite anyone to submit a nomination by the deadline of September 15,
2014. Only papers published at the Micro conferences held between
1968-1992 (1968 and 1992 inclusive) will be considered for this year’s
award. Please submit your nomination to The following describes
the nomination criteria, how to submit a nomination and the selection

Which papers are eligible for the 2014 Micro ToT (Test of Time) Award?
Only papers published at Micro conferences that happened between
1968-1992 (1968 and 1992 inclusive).

An almost-complete list of eligible papers is at:

Who can nominate a paper?
Anyone can nominate a paper except for the author or co-author of the
nominated paper.

Is there a limit on the number of papers one person can nominate?
Yes. One can nominate up to 5 papers from all eligible papers. These
five papers can be published at any eligible year.

When is the last day to submit a nomination?
Nominations must be received by September 15, 2014.

How should a nomination be submitted?
Nominations must be submitted via email to

What should be included in the nomination email?
All of the following must be included in the nomination email. Only
one paper can be nominated in a single email.

1. The title of the nominated paper
2. The author list of the nominated paper
3. Which Micro the nominated paper appeared in? (It must be a Micro in
between 1968-1992, inclusive)
4. A 100-word (maximum) nomination statement, describing why the paper
deserves the Test-of-Time Award
5. The name of the nominator
6. The title of the nominator
7. The affiliation(s) of the nominator
8. The relationship of the nominator to the authors (please describe
any relationship in any way)

Selection process
Micro ToT Award committee will evaluate all submitted nominations to
select at most ten papers for the 2014 Micro ToT (Test of Time) Award.
The committee will produce an award citation for each selected paper.
A strict conflict of interest policy will be followed. If a ToT Award
Committee Member has a conflict of interest with a paper that is
nominated, the member will recuse himself/herself from the discussion
process and a substitute is placed in.

Who are the current Micro ToT Award committee members?
Rich Belgard, Chair
Pradip Bose
Bill Mangione-Smith
Onur Mutlu
Uri Weiser

When will the award be announced and given?
The award will be presented to the authors of the selected paper(s) at
the Awards Ceremony during the International Symposium on
Microarchitecture in December 2014, to be held in Cambridge, United
Kingdom. The Awards Ceremony will be a dedicated half-hour.
Awardees are not expected to make a presentation.

What does the award consist of?
An award certificate and peer recognition.

Start: September 15, 2014
End: September 15, 2014

August 25, 2014

Call for Papers: TASUS 2014

Submitted by Jesus Carretero

The ever-increasing data and processing requirements of applications
from various domains are constantly pushing for dramatic increases in
computational and storage capabilities. Today, we have
reached a point where computer systems’ growth cannot be addressed
anymore in an incremental way, due to the huge challenges lying ahead, in
particular scalability, energy barrier, data management, programmability,
and reliability.

Ultrascale computing systems (UCS) are envisioned as a
large-scale complex system joining parallel and distributed
computing systems, maybe located
at multiple sites, that cooperate to provide solutions to the
users. As a growth of two or three orders of magnitude of today’s
computing systems is expected, including systems with unprecedented
amounts of heterogeneous hardware, lines of source code, numbers
of users, and volumes of data, sustainability is critical to ensure the
feasibility of those systems. Due to those needs, currently there is an
emerging cross-domain interaction between high-performance in clouds or
the adoption of distributed programming paradigms, such as Map-Reduce,
in scientific applications, the cooperation between HPC and
distributed system communities still poses many challenges towards
building the ultrascale
systems of the future. Especially in unifying the services to deploy
sustainable applications portable to HPC systems, multi-clouds,
data centers, and big data.

TASUS workshop focuses on the software side, aiming at bringing
together researchers from academia and industry interested in the design,
implementation, and evaluation of services and system software
mechanisms to improve sustainability in ultrascale computing systems
with a holistic approach.


We are looking for original high quality research and position papers
on applications, services, and system software for sustainable ultrascale
systems. Topics of interest include:

- Existing and emerging designs to achieve sustainable ultrascale systems.
- High-level parallel programming tools and programmability
techniques to improve applications sustainability on ultrascale
platforms. (model driven, refactoring, dynamic code generation, unified
services, middlewares, …).
- Synergies among emerging programming models and run-times
from HPC, distributed systems, and big data communities to provide
sustainable execution models (increased productivity, transparency,
elasticity, …).
- New energy efficiency techniques for monitoring, analyzing, and
modeling ultrascale systems, including energy efficiency metrics for
multiple resources (computing, storage, networking) and sites.
- Eco-design of ultrascale components and applications, with
special emphasis on energy-aware software components that help
users to shape energy issues for their applications.
- Sustainable resilience and fault-tolerant mechanisms that can
cooperate throughout the whole software stack to handle errors.
- Fault tolerance techniques in partitioned global address space
(e.g. PGAS, MPI, hybrid) and federated cooperative environments.
- Data management optimization techniques through cross layer
adaptation of the I/O stack to provide global system information to
improve data locality.
- Enhanced data management lifecycle on scalable architectures
combining HPC and distributed computing (clouds and data centers).
- Experiences with applications, high-level algorithms, and services
amenable to ultrascale systems.

Important dates:

· Workshop papers due: May 30, 2014

· Workshop author notification: July 4, 2014

· Workshop early registration: July 25, 2014
· Workshop camera-ready papers due: October 3, 2014


Workshop Organizers:
Prof. Jesus Carretero. University Carlos III of Madrid. Spain.
Dr. Laurent Lefevre. INRIA, ENS of Lyon. France
Prof. Gudula Rünger. Technical University of Chemnitz. Germany.
Prof. Domenico Talia. Universitá della Callabria. Italy.

Start: August 25, 2014
End: August 25, 2014
Venue: Porto, Portugal

August 11, 2014

Call For Papers: ISLPED 2014

Submitted by Jose L. Ayala

La Jolla, CA, USA
Aug. 11 – Aug. 13, 2014

The International Symposium on Low Power Electronics and Design (ISLPED) is the
premier forum for presentation of recent advances in all aspects of low power
design and technologies, ranging from process and circuit technologies,
simulation and synthesis tools, to system level design and optimization.
Specific topics include, but are not limited to, the following two main areas,
each with three sub-areas:

1. Technology, Circuits, and Architecture

1.1. Technologies
Emerging Low-power technologies for Device, Interconnect, Logic, Memory,
Cooling, Harvesting, Sensors, Optical, Printable, Biomedical, Battery, and
Alternative energy storage devices.

1.2. Circuits
Low-power digital circuits for Logic, Memory arrays, Reliability, Clocking,
Power gating, Resiliency, NearThreshold Voltage (NTV), Sub-threshold,
Variability, and Digital assist schemes; Low-power analog/mixed-signal circuits
for Wireless, RF, MEMS, AD/DA Converters, I/O circuits, PLLs/DLLS, Imaging, DC
DC converters, and Analog assist schemes.

1.3. Logic and Architecture
Low-power logic and microarchitectures for SoC designs, Processor cores
(compute, graphics and other special purpose cores), Register file, Cache,
Memory, Arithmetic/Signal processing, Encryption, Variability, Asynchronous
design, and Non-conventional computing.

2. CAD, Systems, and Software

2.1. CAD Tools and Methodologies
CAD tools and methodologies for low-power and thermalaware design addressing
power estimation, optimization, reliability and variation impact on power, and
power-down approaches at all design levels: physical, circuit, gate, RTL,
behavioral, and algorithmic.

2.2. Systems & Platform
Low-power, power-aware, and thermal-aware system design and platforms for
microprocessors, DSP, embedded systems, FPGA, ASIC, SoC, heterogeneous
computing, novel systems, data-center power delivery and cooling, and system
level power implications due to reliability and variability.

2.3. Software & Applications
Energy-efficient, energy-aware, and thermal-aware software and application
design including scheduling and management, reliability and variability
optimizations, and emerging low power applications like approximate and
braininspired computing, low power distributed body-area/inbody networks, and
sensor networks.

Submissions on new topics: emerging technologies, architectures/platforms, and
applications are particularly encouraged.

TECHNICAL PAPER SUBMISSIONS DEADLINE: Abstract registration: Feb 28, 2014; Full
paper: March 7, 2014
Submissions should be full-length papers of up to 6 pages (double-column, ACM
SIG Proceedings format, available at, including all
illustrations, tables, references and an abstract of no more than 100 words.
Papers exceeding the six-page limit will not be reviewed. Submission must be
anonymous: papers identifying the authors and/or with explicit references to
their prior work will be automatically rejected. Electronic submission in pdf
format only via the web is required. More information on electronic submission
to ISLPED’14 can be found at

Submitted papers must describe original work that will not be announced or
published prior to the Symposium and that is not being considered or under
review by another conference at the same time. Accepted papers will be
in one of two parallel tracks: one focusing on architectures, circuits and
technologies, the other on design tools and systems and software design for low
power. Notification of paper acceptance will be mailed by April 28, 2014 and
camera-ready version of the paper will be due by June 2, 2014. Accepted papers
will be published in the Symposium Proceedings and included in the ACM Digital
Library. Authors of a few selected papers from the Symposium will also be given
an opportunity to submit enhanced versions of their papers for publication in a
special issue of a reputed journal. ISLPED’14 will present two Best Paper
Awards based on the ratings of reviewers and an invited panel of judges.


There will be several invited talks by industry and academic thought leaders on
key issues in low power electronics and design. All invited talks will be in
plenary sessions. The Symposium may also include embedded tutorials to provide
attendees with the necessary background to follow recent research results, as
well as panel discussions on future directions and design/technology
alternatives in low power electronics and design. Proposals for invited talks,
embedded tutorials, and the panel should be sent to the Technical Program Co


Renu Mehra

Muhammad M. Khellah

EXHIBITION REQUESTS DEADLINE: Received by: April 28, 2014

People from Industry or Academia interested in exhibiting at ISLPED’14 should
contact the symposium General Co-Chairs.

Start: August 11, 2014
End: August 13, 2014
Venue: La Jolla, CA, USA

August 6, 2014

Call for Papers: The 9th IEEE International Conference on Networking, Architecture, and Storage (NAS 2014)

Submitted by Jianhui Yue
The 9th IEEE International Conference on Networking, Architecture,
and Storage (NAS 2014) will be held from August 6 − 8, 2014 in
Tianjin, China. It will serve as an international forum to bring
together researchers and practitioners from academia and industry
to discuss cutting-edge research on networking, high-performance
computer architecture, and parallel and distributed data storage

Topics (Topics of interest include but are not limited to the list as follow)
- Virtual and overlay networks
- Network applications and services
- Ad hoc and sensor networks
- Networks and protocols
- Network architectures
- Processor architectures
- Cache and memory systems
- Parallel computer architectures
- Impact of technology on architecture
- Network information theory & network coding
- Network modeling and measurement
- Power and energy efficient architectures and techniques
- Storage management
- Storage performance and scalability
- File systems, object-based storage and block storage
- Energy-aware storage
- Architecture and applications of solid state disks
- Cloud storage
- Storage visualization
- HW/SW co-designs&trade-offs

Important Dates
- Deadline for Paper Submission: March 21st, 2014
- Notification of Paper Acceptance: May 19th, 2014
- Camera-ready Paper and Author Registration: June 9th, 2014

NAS 2014 invites authors to submit original and unpublished work.
All accepted papers will be included in the IEEE digital library
and indexed by EI. (IEEE sponsorship is pending approval.)

Start: August 6, 2014
End: August 8, 2014
Venue: Tianjian, China

June 30, 2014

Call for Papers: ICDCS-2014

Submitted by Ernesto Jiménez
ICDCS 2014
34th Int. Conf. on Distributed Computing Systems
30th June-3rd July 2014
Madrid, Spain


The conference provides a forum for engineers and scientists in academia,
industry and government to present their latest research findings
in any aspects of distributed computing.
Topics of particular interest include, but are not limited to:

- Big Data, Data Management and Analytics
- Cloud Computing and Data Center Systems
- Distributed OS and Middleware
- Algorithms and Theory
- Fault Tolerance and Dependability
- Security and Privacy
- Social Networks, Crowdsourcing, and P2P systems
- Energy Management and Green Computing
- Sensor Networks and Systems
- Mobile and Wireless Computing
- File and Storage Systems

NOTE: To build a broad program and to encourage a diverse set of
submissions, a limited number of papers will be accepted within each
topic area, and every topic area will accept a minimum quota of papers.

Workshops will be held in conjunction with the conference.
Workshop proposals should be submitted to Workshops Co-Chairs
Prof. Roberto Baldoni (
and Prof. Jason Gu( by September 30th, 2013.
Notification of acceptance will be made by October 10th, 2013. Please
see the conference web page for details.

Form of Manuscript: All paper submissions should follow the IEEE 8.5” x 11”
Two-Column Format.
Each submission can have 10 pages. If the paper is accepted for publication,
up to 2 overlength pages may be purchased for the final camera-ready
version. Submitted papers should NOT be blinded for review.

Electronic Submission: Submissions will be handled via the conference
web page.


Abstract registration 22nd November 2013
Paper Submission 29th November 2013
Author Notification 17th March 2014
Final Manuscript Due 7th April 2014

For further information, please contact General Chair,
Prof. Marta Patiño-Martínez ( or
Program Co-Chair, Prof. Ricardo Jimenez-Peris (


General Chair
Marta Patiño-Martínez (Univ. Politécnica de Madrid, Spain)

Program Co-Chairs
Ricardo Jimenez-Peris (Univ. Politécnica de Madrid, Spain)
Hui Lei (IBM Watson, US)

Program Vice Chairs
Big Data, Data Management and Analytics
Phillip Gibbons (Intel Labs, US)

Cloud Computing and Data Center Systems
Flavio Junqueira (MSR-Cambridge, UK)

Distributed OS and Middleware
Gustavo Alonso (ETH Zurich, Switzerland)

Algorithms and Theory
Antonio Fernandez-Anta (IMDEA, Spain)

Fault Tolerance and Dependability
Bettina Kemme (McGill Univ., Canada)

Security and Privacy
Elisa Bertino (Purdue, US)

Social Networks, Crowdsourcing, and P2P systems
Alberto Montresor (Trento Univ., Italy)

Energy Management and Green Computing
Tarek F. Abdelzaher (UIUC, US)

Sensor Networks and Systems
Tian He (University of Minnesota, US)

Mobile and Wireless Computing
Guohong Cao ( Pennsylvania State Univ, US)

File and Storage Systems
André Brinkmann (Meinz Univ., Germany)

Program Committee Members

Workshops Co-Chairs
Roberto Baldoni (Univ. Sapienza, Italy)
Jason Gu (Singapore Univ., Singapore)

Publicity Chair
Ernesto Jimenez (Univ. Politecnica Madrid, Spain)

Publication Chair
Mikel Larra (Univ. Pais Vasco, Spain)

TCDP Chair
Jiannong Cao,(Hong Kong Polyt. Univ., HK)

Steering Committee Chair
Xiaodong Zhang (Ohio State Univ., USA)

Microsoft Research Cambridge

Start: June 30, 2014
End: July 3, 2014
Venue: Madrid, Spain

June 23, 2014

Call for Participation: SPAA 2014

Submitted by Jeremy Fineman
26th ACM Symposium on
Parallelism in Algorithms and Architectures (SPAA 2014)
June 23-25, 2014 Charles University, Prague, Czech Republic

Highlight: The two keynote speakers will be Bruce Maggs and Fabian Kuhn.

Registration is open. The early registration deadline is May 23.

Please visit the conference webpage for:
- list of accepted papers
- registration
- information on local arrangements

Start: June 23, 2014
End: June 25, 2014
Venue: Charles University, Prague, Czech Republic

Call for Participation: D43D: International Workshop on Design for 3D Silicon Integration

Submitted by Djordje Jevdjic
D43D: International Workshop on Design for 3D Silicon Integration
June 23-24, 2014
EPFL, Lausanne

Scope & Venue

3D IC is emerging as a promising approach to extend Moore’s law, overcome pin bandwidth limitations, and improve digital platform density and cost beyond a single chip. 3D IC as a technology, however, also introduces a number of key design, methodological, implementation and technological challenges that must be overcome to become practical and cost-effective.
This workshop is a two-day forum that brings together experts from industry and academia to shed light on these near-term to long-term challenges and solutions, and covers topics including, but not limited to, applications requiring 3D, 3D processor, memory and interconnect architectures, thermal management, design methodologies and tools, and testing.

The workshop will take place at EPFL, one of the premier institutions of computer science and engineering, consistently ranked among the most internationally diverse campuses, located on the shores of Lake Geneva in Switzerland.

Registration & Info
For hotel accommodation and workshop information please check our website:
Registration is open until May 25th, 2014.

General Chair:
Babak Falsafi, EPFL

Program Chair:
Pascal Vivet, CEA-LETI

Finance Chair:
Stéphanie Baillargues, EPFL

Website Chair:
Javier Picorel, EPFL

Steering Committee:
David Atienza, EPFL
Ahmed Jerraya, CEA-LETI

The workshop is partially sponsored by EcoCloud ( and IEEE CEDA.

Start: June 23, 2014
End: June 24, 2014
Venue: Lausanne

June 18, 2014

Call for Papers: ASAP 2014, extended deadline

Submitted by Kubilay Atasu
25th IEEE International Conference on
Application-specific Systems, Architectures and Processors
18-20 June 2014, IBM Research – Zurich, Switzerland

Important Dates

– Abstract Due 21 February 2014
– Paper Submission 28 February 2014
– Notification of Acceptance 11 April 2014
– Conference 18-20 June 2014

Quick Links

– Conference
– Call for Papers
– Submission site:

The ASAP 2014 conference is organized by IBM Research – Zurich and
the Swiss Federal Institute of Technology Zurich (ETH). The conference
will cover the theory and practice of application-specific systems,
architectures and processors. The 2014 conference will build upon
traditional strengths in areas such as computer arithmetic, cryptography,
compression, signal and image processing, network processing,
reconfigurable computing, and all types of hardware accelerators.
We especially encourage submissions in the following areas:

– Big data analytics: extracting and correlating information
from large-scale semi-structured and unstructured data
using application-specific systems.

– Scientific computing: architectures and algorithms that
address scientific applications requiring significant
computing power and design customization (bioinformatics,
climate modeling, astrophysics, seismology, etc.).

– Industrial computing: systems and architectures for
providing high-throughput or low latency in various
industrial computing applications.

– System security: cryptographic hardware architectures,
security processors, countermeasures against side-channel
attacks, and secure cloud computing.

– Heterogeneous systems: applications and platforms that
exploit heterogeneous computing resources, including
FPGAs, GPUs, or CGRAs.

– Design space exploration: methods for customizing and
tuning application-specific architectures to improve
efficiency and productivity.

– Platform-specific architectures: novel architectures for
exploiting specific compute domains such as smartphones,
tablets, and data centers, particularly in the context of
energy efficiency.

Conference Venue

The conference is hosted at
IBM Research – Zurich
Säumerstrasse 4
CH-8803 Rüschlikon (Switzerland)

Conference Organization

General Chair:
Kubilay Atasu, IBM Research – Zurich, Switzerland

General Co-Chair:
Melissa Smith, Clemson University, USA

Program Co-Chairs:
Haohuan Fu, Tsinghua University, China
David Thomas, Imperial College London, UK

Start: June 18, 2014
End: June 20, 2014
Venue: IBM Research - Zurich, Switzerland