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June 30, 2014

Call for Papers: ICDCS-2014

Submitted by Ernesto Jiménez
ICDCS 2014
34th Int. Conf. on Distributed Computing Systems
30th June-3rd July 2014
Madrid, Spain


The conference provides a forum for engineers and scientists in academia,
industry and government to present their latest research findings
in any aspects of distributed computing.
Topics of particular interest include, but are not limited to:

- Big Data, Data Management and Analytics
- Cloud Computing and Data Center Systems
- Distributed OS and Middleware
- Algorithms and Theory
- Fault Tolerance and Dependability
- Security and Privacy
- Social Networks, Crowdsourcing, and P2P systems
- Energy Management and Green Computing
- Sensor Networks and Systems
- Mobile and Wireless Computing
- File and Storage Systems

NOTE: To build a broad program and to encourage a diverse set of
submissions, a limited number of papers will be accepted within each
topic area, and every topic area will accept a minimum quota of papers.

Workshops will be held in conjunction with the conference.
Workshop proposals should be submitted to Workshops Co-Chairs
Prof. Roberto Baldoni (
and Prof. Jason Gu( by September 30th, 2013.
Notification of acceptance will be made by October 10th, 2013. Please
see the conference web page for details.

Form of Manuscript: All paper submissions should follow the IEEE 8.5” x 11”
Two-Column Format.
Each submission can have 10 pages. If the paper is accepted for publication,
up to 2 overlength pages may be purchased for the final camera-ready
version. Submitted papers should NOT be blinded for review.

Electronic Submission: Submissions will be handled via the conference
web page.


Abstract registration 22nd November 2013
Paper Submission 29th November 2013
Author Notification 17th March 2014
Final Manuscript Due 7th April 2014

For further information, please contact General Chair,
Prof. Marta Patiño-Martínez ( or
Program Co-Chair, Prof. Ricardo Jimenez-Peris (


General Chair
Marta Patiño-Martínez (Univ. Politécnica de Madrid, Spain)

Program Co-Chairs
Ricardo Jimenez-Peris (Univ. Politécnica de Madrid, Spain)
Hui Lei (IBM Watson, US)

Program Vice Chairs
Big Data, Data Management and Analytics
Phillip Gibbons (Intel Labs, US)

Cloud Computing and Data Center Systems
Flavio Junqueira (MSR-Cambridge, UK)

Distributed OS and Middleware
Gustavo Alonso (ETH Zurich, Switzerland)

Algorithms and Theory
Antonio Fernandez-Anta (IMDEA, Spain)

Fault Tolerance and Dependability
Bettina Kemme (McGill Univ., Canada)

Security and Privacy
Elisa Bertino (Purdue, US)

Social Networks, Crowdsourcing, and P2P systems
Alberto Montresor (Trento Univ., Italy)

Energy Management and Green Computing
Tarek F. Abdelzaher (UIUC, US)

Sensor Networks and Systems
Tian He (University of Minnesota, US)

Mobile and Wireless Computing
Guohong Cao ( Pennsylvania State Univ, US)

File and Storage Systems
André Brinkmann (Meinz Univ., Germany)

Program Committee Members

Workshops Co-Chairs
Roberto Baldoni (Univ. Sapienza, Italy)
Jason Gu (Singapore Univ., Singapore)

Publicity Chair
Ernesto Jimenez (Univ. Politecnica Madrid, Spain)

Publication Chair
Mikel Larra (Univ. Pais Vasco, Spain)

TCDP Chair
Jiannong Cao,(Hong Kong Polyt. Univ., HK)

Steering Committee Chair
Xiaodong Zhang (Ohio State Univ., USA)

Microsoft Research Cambridge

Start: June 30, 2014
End: July 3, 2014
Venue: Madrid, Spain

June 23, 2014

Call for Participation: SPAA 2014

Submitted by Jeremy Fineman
26th ACM Symposium on
Parallelism in Algorithms and Architectures (SPAA 2014)
June 23-25, 2014 Charles University, Prague, Czech Republic

Highlight: The two keynote speakers will be Bruce Maggs and Fabian Kuhn.

Registration is open. The early registration deadline is May 23.

Please visit the conference webpage for:
- list of accepted papers
- registration
- information on local arrangements

Start: June 23, 2014
End: June 25, 2014
Venue: Charles University, Prague, Czech Republic

Call for Participation: D43D: International Workshop on Design for 3D Silicon Integration

Submitted by Djordje Jevdjic
D43D: International Workshop on Design for 3D Silicon Integration
June 23-24, 2014
EPFL, Lausanne

Scope & Venue

3D IC is emerging as a promising approach to extend Moore’s law, overcome pin bandwidth limitations, and improve digital platform density and cost beyond a single chip. 3D IC as a technology, however, also introduces a number of key design, methodological, implementation and technological challenges that must be overcome to become practical and cost-effective.
This workshop is a two-day forum that brings together experts from industry and academia to shed light on these near-term to long-term challenges and solutions, and covers topics including, but not limited to, applications requiring 3D, 3D processor, memory and interconnect architectures, thermal management, design methodologies and tools, and testing.

The workshop will take place at EPFL, one of the premier institutions of computer science and engineering, consistently ranked among the most internationally diverse campuses, located on the shores of Lake Geneva in Switzerland.

Registration & Info
For hotel accommodation and workshop information please check our website:
Registration is open until May 25th, 2014.

General Chair:
Babak Falsafi, EPFL

Program Chair:
Pascal Vivet, CEA-LETI

Finance Chair:
Stéphanie Baillargues, EPFL

Website Chair:
Javier Picorel, EPFL

Steering Committee:
David Atienza, EPFL
Ahmed Jerraya, CEA-LETI

The workshop is partially sponsored by EcoCloud ( and IEEE CEDA.

Start: June 23, 2014
End: June 24, 2014
Venue: Lausanne

June 18, 2014

Call for Papers: ASAP 2014, extended deadline

Submitted by Kubilay Atasu
25th IEEE International Conference on
Application-specific Systems, Architectures and Processors
18-20 June 2014, IBM Research – Zurich, Switzerland

Important Dates

– Abstract Due 21 February 2014
– Paper Submission 28 February 2014
– Notification of Acceptance 11 April 2014
– Conference 18-20 June 2014

Quick Links

– Conference
– Call for Papers
– Submission site:

The ASAP 2014 conference is organized by IBM Research – Zurich and
the Swiss Federal Institute of Technology Zurich (ETH). The conference
will cover the theory and practice of application-specific systems,
architectures and processors. The 2014 conference will build upon
traditional strengths in areas such as computer arithmetic, cryptography,
compression, signal and image processing, network processing,
reconfigurable computing, and all types of hardware accelerators.
We especially encourage submissions in the following areas:

– Big data analytics: extracting and correlating information
from large-scale semi-structured and unstructured data
using application-specific systems.

– Scientific computing: architectures and algorithms that
address scientific applications requiring significant
computing power and design customization (bioinformatics,
climate modeling, astrophysics, seismology, etc.).

– Industrial computing: systems and architectures for
providing high-throughput or low latency in various
industrial computing applications.

– System security: cryptographic hardware architectures,
security processors, countermeasures against side-channel
attacks, and secure cloud computing.

– Heterogeneous systems: applications and platforms that
exploit heterogeneous computing resources, including
FPGAs, GPUs, or CGRAs.

– Design space exploration: methods for customizing and
tuning application-specific architectures to improve
efficiency and productivity.

– Platform-specific architectures: novel architectures for
exploiting specific compute domains such as smartphones,
tablets, and data centers, particularly in the context of
energy efficiency.

Conference Venue

The conference is hosted at
IBM Research – Zurich
Säumerstrasse 4
CH-8803 Rüschlikon (Switzerland)

Conference Organization

General Chair:
Kubilay Atasu, IBM Research – Zurich, Switzerland

General Co-Chair:
Melissa Smith, Clemson University, USA

Program Co-Chairs:
Haohuan Fu, Tsinghua University, China
David Thomas, Imperial College London, UK

Start: June 18, 2014
End: June 20, 2014
Venue: IBM Research - Zurich, Switzerland

Call for Participation: ASAP 2014

Submitted by Jason D. Bakos
The 25th IEEE International Conference on Application-specific Systems,
Architectures and Processors (ASAP 2014)
June 18-20, 2014,
IBM Research – Zurich, Switzerland

Advanced registration deadline: May 9, 2014

Keynote speakers:
- Oskar Mencer, Imperial College London “Computing in Space”
- Jeff Stuecheli, IBM Systems and Technology Group “Open Innovation with
- Onur Mutlu, Carnegie Mellon University “Rethinking Memory System Design for
Data-Intensive Computing”
More information available at:

The 25th IEEE International Conference on Application-specific Systems,
Architectures and Processors 2014 takes place June 18-20, 2014 in
Zurich, Switzerland.
The 2014 edition of the conference is organized by IBM Research – Zurich and
the Swiss Federal Institute of Technology Zurich (ETH).

The history of the event traces back to the International Workshop on Systolic
Arrays, organized in 1986 in Oxford, UK. It later developed into the
International Conference on Application Specific Array Processors. With its
current title, it was organized for the first time in Chicago, USA in 1996.
Since then it has alternated between Europe and North-America.

The conference will cover the theory and practice of application-specific
systems, architectures and processors. The 2014 conference will build upon
traditional strengths in areas such as computer arithmetic, cryptography,
compression, signal and image processing, network processing, reconfigurable
computing, application-specific instruction-set processors, and hardware

Start: June 18, 2014
End: June 20, 2014
Venue: Zurich, Switzerland

June 15, 2014

Call for Lectures: ESSA 2014

Submitted by Augusto Vega
ESSA 2014
Fourth Annual Offering
Workshop on Energy-Secure System Architectures

June 15th, 2014 – Minneapolis, Minnesota (United States)
In conjunction with ISCA 2014

Organizers: Augusto Vega (IBM Research)
Alper Buyuktosunoglu (IBM Research)
Pradip Bose (IBM Research)

The “power wall” has forced chip and system architects to design with
smaller margins between nominal and worst-case operating points.
Dynamic power and thermal management control loops have already become
an integral part of chip and system design. New research papers in
wearout and general reliability management have recently been
published. These new generation management protocols have, however,
opened up other sources of concern: e.g. control loop stability and
robustness of the management protocols. The potential security holes
exposed by the integrated control loops and system safety issues
triggered by potential violations of power or thermal limits are other
areas of concern. We seek to motivate the research community into
adopting a holistic approach to mitigating the power wall and the
concomitant reliability-security wall.

We have coined the term “Energy-Secure System Architectures” to cover
the range of research being pursued within industry and academia in
order to ensure robust and secure functionality, while meeting the
energy-related constraints of the emerging “green computing” era.
This workshop offering, composed of lectures provided by experts in
the areas of power/thermal management, reliability and security, is
targeted to provide a comprehensive view of the hardware and software
aspects of Energy-Secure System Architectures. This is the fourth year
of the offering of this workshop.


This full-day workshop is organized across the following sub-topics:

– Power and thermal management solutions for modern multi-core
– Robustness of system power/thermal managers: verification and
design for verification.
– Reliability and security holes exposed by power/thermal management
– Guarded, two-level management protocols for safety and low
verification complexity.
– Architectural implications of and system software support for
energy-secure systems.
– Security and reliability issues in emerging low power memory

CALL FOR LECTURES (deadline: April 11, 2014)
We invite interested participants to send in a lecture proposal (30
mins minimum to 75 mins maximum). The submission should include a
title and abstract, along with a bio-sketch of the speaker and the
proposed talk duration. Submitted lecture proposals will be reviewed
by a Workshop Program Committee (TBA) chaired by the co-organizers.
The deadline for submission is: April 11, 2014. Please send it to the
co-organizers: Alper Buyuktosunoglu, Pradip Bose and Augusto Vega at:, and
Notification of acceptance: April 25, 2014. There will be a post-
workshop digest consisting of the lecture abstracts and corresponding
slide sets; and depending on interest, a post-workshop special journal
or magazine issue will be organized, in which written versions of
selected articles would be published.

Start: June 15, 2014
End: June 15, 2014
Venue: Minneapolis (United States)

June 14, 2014

Call for Papers: ISCA 2014

Submitted by Natalie Enright Jerger
The International Symposium on Computer Architecture is the premier forum
for new ideas and experimental results in computer architecture. The conference
specifically seeks particularly forward-looking and novel submissions. Papers
are solicited on a broad range of topics, including (but not limited to):

Processor, memory, and storage systems architecture
Parallel and multicore systems
Data-center scale computing
Architectures for handheld and mobile devices
Application-specific, reconfigurable, or embedded architectures
Accelerator-based architectures
Architectures for security and virtualization
Power and energy efficient architectures
Interconnection networks
Instruction, thread, and data-level parallelism
Dependable architectures
Architectural support for programming productivity
Network processor and router architectures
Architectures for emerging technologies and applications
Effect of circuits and technology on architecture
Architecture modeling and simulation methodology
Performance evaluation and measurement of real systems

Abstract Deadline: November 14, 2013, 11:59PM EST
Final Paper Deadline: November 21, 2013, 11:59PM EST
Rebuttal Period: February 11-14, 2014
Author Notification: March 7, 2014

** Program Chair:

Steve Keckler, NVIDIA/University of Texas at Austin

** Program Committee:

David Albonesi Cornell
David I. August Princeton University
Todd Austin University of Michigan
David Brooks Harvard
Doug Burger Microsoft
Doug Carmean Intel
John Carter IBM Research
Derek Chiou Microsoft/UT-Austin
Fred Chong UC-Santa Barbara
Al Davis University of Utah
Pradeep Dubey Intel
Sandhya Dwarkadas University of Rochester
Yoav Etsion Technion
Boris Grot University of Edinburgh
Rajiv Gupta UC-Riverside
David Hansquine Qualcomm
Mark D. Hill University of Wisconsin-Madison
Wen-mei Hwu University of Illinois
Stefanos Kaxiras Uppsala University
Hyesoon Kim Georgia Tech
John Kim KAIST
Martha Kim Columbia
Ronny Krashinsky NVIDIA
James Laudon Google
Alvin Lebeck Duke
Hsien-Hsin Lee Georgia Tech
Srilatha Manne AMD
Nacho Navarro U. Politecnica de Catalunya
Scott Rixner Rice
Simha Sethumadhavan Columbia
Ed Suh Cornell
Olivier Temam INRIA
Mohit Tiwari UT-Austin
Brian Towles DE Shaw Research
Dean Tullsen UC San Diego
Uri Weiser Technion
David Wentzlaff Princeton University
Carole-Jean Wu Arizona State University
Yuan Xie Pennsylvania State University
Sudhakar Yalamanchili Georgia Tech
Lixin Zhang Chinese Academy of Sciences
Craig Zilles University of Illinois

Organizing Committee:

** General Co-Chairs
Pen-Chung Yew, University of Minnesota
Antonia Zhai, University of Minnesota

** Workshop Co-Chairs
David Wentzlaff, Princeton University
Nuwan Jayasena, AMD Research

** Tutorial Co-Chairs
Martha Kim, Columbia University
Debbie Marr, Intel

** Finance Chair
Yuan Xie, Pennsylvania State University

** Industry Liaison Co-Chairs
Hyesoon Kim, Georgia Institute of Technology
Samantika Subramaniam, Intel

** Local Arrangements Chair
John Sartori, University of Minnesota

** Web Chair
Omer Khan, University of Connecticut

** Publicity Co-Chairs
Chia-Lin Yang, National Taiwan University
Natalie Enright Jerger, University of Toronto
Lieven Eeckhout, Ghent University

** Registration Chair
Ulya Karpuzcu, University of Minnesota

** Proceedings Chair
Eric Chung, Microsoft Research

** Travel Award Chair
James Tuck, NC State University

** Submission Chair
Paul Gratz, Texas A&M University

** Steering Committee
Mark Horowitz, Stanford University
David Kaeli, Northeastern University
Shih-Lien Lu, Intel
Avi Mendelson, Technion
Margaret Martonosi, Princeton University
Yale Patt, University of Texas at Austin
Joseph Torrellas, University of Illinois
David Wood, University of Wisconsin

Start: June 14, 2014
End: June 18, 2014

Call for Papers: Workshop on Neuromorphic Architectures (NeuroArch) @ ISCA 2014

Submitted by Hadi Esmaeilzadeh
Workshop on Neuromorphic Architectures (NeuroArch)

Saturday, June 14th, 2014
(held in conjunction with ISCA 2014)
Minneapolis, MN, USA


The first workshop on Neuromorphic Architectures (NeuroArch) aims at exploring
novel ideas and research opportunities in design, programming, and application
of neuromorphic and brain-inspired accelerators. In the current realm of
processor design, where energy and power constraint has shifted the designs
toward heterogeneity, hardware neural networks are emerging as candidate
accelerators with attractive characteristics and broad application scope.

In addition to the power-efficiency and fault tolerance of neural accelerators,
we are at the junction of time where: As technology scales down to the atomic
levels, the increasing process variability causes the designers to pay a high
tax in performance and efficiency to provide fault-free designs; the intrinsic
robustness of neural networks may lead to fault-tolerant accelerators. Novel
neural network algorithms such as Deep Belief Networks outperform many
alternative machine learning algorithms across a broad set of applications.
Significant progress in neuroscience sheds light on the operating principles of
biological neural networks, which can thus be partially replicated in hardware.
The landscape of computing has changed toward providing a more personalized and
more targeted experience for the users, thus increasing the importance of
applications that require learning.

Therefore, we believe it is imperative and timely for the computer architecture
community and the design of next generation computing systems to explore and
research neural models of computing.


To this end, NeuroArch invites research papers and talks on topics including
but not limited to: Hardware design for biologically or mathematically inspired
neural networks Applications of hardware neural networks Advanced technologies
and devices for neural hardware design (3D, memristors, …) Programming models
and environments for neural accelerators

NeuroArch 2014 will include both invited talks and peer-reviewed papers.
Peer-reviewed papers will not be published in a proceedings; therefore,
submitting to NeuroArch will not preclude future publication opportunities.
However, papers and presentation slides will be made available online with the
authors’ approval.


Paper Submission: April 1st, 2014
Author Notification: April 15th, 2014


Paper submissions are limited to two-page extended abstracts. Please use the
formatting guidelines from the main conference (see

Please send a PDF version of your paper to and

Submissions may optionally be blind (authors can choose whether to include
names on the submitted PDF; this option will be relevant if the organizing
committee decides to query the opinion of an external reviewer).


Daniel Ben Dayan-Rubin, Intel Labs, ICRI, Israel
Hadi Esmaeilzadeh, Georgia Tech
Abdullah Muzahid, University of Texas at San Antonio
Emre Neftci, UCSD
Olivier Temam, Inria

For any question related to the workshop organization, please contact and

Start: June 14, 2014
End: June 14, 2014
Venue: Minneapolis, MN, USA

Call for Papers: HASH @ ISCA 2014

Submitted by Mohamed Zahran
The First Annual Workshop on Heterogeneous Architectures:
Software and Hardware (HASH)

June 14, 2014, Minneapolis, MN, USA
(co-located with ISCA 2014)

The architecture and microarchitecture of multicore/manycore
processors is moving rapidly toward heterogeneity. Heterogeneous
multicore/manycore processors provide a promising opportunity to
achieve better performance together with power efficiency. However,
the complexity of the architecture, microarchitecture, software
applications, and system software presents a challenging problem. The
varying requirements of the different applications running on a single
machine, the changing behavior of a single application during its
lifetime, as well as the ever-changing characteristics of
multiprogramming environment make the design and programming of
heterogeneous architectures a big challenge.

The Heterogeneous Architecture: Software and Hardware workshop
provides a high-quality forum for computer scientists and engineers to
present their latest research findings in the rapidly evolving field of
heterogeneous architecture where the
heterogeneouity can be in the form of cores of different strength,
general purpose cores and GPUs, cores with different memory
hierarchies, accelerators, etc; as well as their interconnect. The
interaction among the different layers of the stack is part of the
objectives, which involves compilers, OS, and programming models.

Submissions deadline: March 10, 2014
Notification: April 10, 2014
Camera-Copy Papers Due: April 30, 2014

Topics of interest include, but are not limited to:

*Memory hierarchy for heterogeneous multicores

*Power efficiency of heterogeneous architectures

Programming models for heterogeneous architectures

* The effect of heterogeneity on NoC

* Compilation techniques for heterogeneous architectures


* Reliability issues in heterogeneous computing

* OS management of heterogeneous architecture

The Program Committee invites authors to submit papers up to 8 pages
(11pt font) double-column describing original, unpublished recent
work, or work in progress related to the workshop theme.

Submission must be in pdf format and emailed to:

Trey Cain
(Qualcomm )
John Cavazos
(U. Delaware)
Aamer Jaleel
Pierre Michaud
Vijay Janapa Reddi
(UT Austin)
Aaron Smith
(Microsoft Research)
Jessica Tseng
( IBM Research )
Dong Ping Zhang

Mohamed Zahran, (NYU)
Hubertus Franke (IBM T. J. Watson)

Start: June 14, 2014
End: June 14, 2014
Venue: Minneapolis, MN, USA (Co-located with ISCA 2014)

Call for Papers: The Memory Forum

Submitted by Rajeev Balasubramonian
The Memory Forum

A Workshop in conjunction with ISCA 2014
Saturday June 14th 2014, Minneapolis, MN

Call for Papers:

We invite short 4-page papers along the lines of IEEE Computer
Architecture Letters. Papers should focus on the key new ideas and
preliminary evaluations are fine. Accepted papers will be posted on
the workshop webpage and should not preclude later publication at
other conferences and journals.

Important Dates:

Paper submissions due: Friday April 11th, 2014
Notification: Friday April 25th, 2014
Final Paper Due: Monday June 9th, 2014

Workshop Scope:

In recent years, the memory bottleneck has grown and new memory
technologies are emerging to challenge the traditional dominance
of DRAM. DRAM itself has also been evolving, through the development
of 3DS, HBM, HMC, and Wide IO. All of these factors demand novel
memory architectures and organizations, methods of scheduling and
managing memory, and algorithms for maintaining reliable data
storage with unreliable bits. The Memory Forum will bring together
researchers from both academia and industry to discuss advances in
memory architecture, organization, and management. The workshop will
include a few invited talks to educate the audience about upcoming
technologies. The rest of the program will include short
presentations based on submitted papers — the goal is to provide
feedback to authors on early-stage and exciting ideas. Approaches
to memory management that rely on programming language techniques
may be better suited to the SIGPLAN-sponsored MSPC workshop that is
co-located with PLDI.


Rajeev Balasubramonian, University of Utah
Michael Healy, IBM TJ Watson Research Center
Onur Mutlu, Carnegie Mellon University

Program Committee:

Jung Ho Ahn, Seoul National University
Rajeev Balasubramonian, University of Utah
Ricardo Bianchini, Rutgers University
John Carter, IBM
Mattan Erez, UT Austin
Babak Falsafi, EPFL
Michael Healy, IBM TJ Watson Research Center
Engin Ipek, University of Rochester
Hyesoon Kim, Georgia Tech
Benjamin Lee, Duke University
Gabriel Loh, AMD
Krishna Teja Malladi, Samsung
Jose Martinez, Cornell University
Naveen Muralimanohar, HP Labs
Onur Mutlu, Carnegie Mellon University
Mike O’Connor, NVIDIA, UT Austin
Jong Hoon Oh, SK Hynix
Churoo Park, Samsung
Yanos Sazeides, University of Cyprus
Andre Seznec, IRISA/INRIA
Jeff Stuecheli, IBM
Aniruddha N. Udipi, ARM
Chris Wilkerson, Intel
Jun Yang, University of Pittsburgh
Lixin Zhang, ICT, CAS

Start: June 14, 2014
End: June 14, 2014
Venue: Minneapolis, MN