Submitted by Josef Weidendorfer
http://computingfrontiers.org

Call for papers
ACM International Conference on Computing Frontiers
Ischia, Italy, May 14-16 2013

http://computingfrontiers.org

CONFERENCE DESCRIPTION
———————-

The increasing complexity, performance, cost and energy efficiency
needs of current and future applications require novel and innovative
approaches for the design of computing systems. Boundaries between
state of the art and revolutionary innovation constitute the computing
frontiers that must be pushed forward to provide the support required
for the advancement of science, engineering and information
technology. The Computing Frontiers conference focuses on a wide
spectrum of advanced technologies and radically new solutions relevant
to the development of the whole spectrum of computer systems, from
embedded to high-performance computing.

KEY DATES
———
Submission Deadline: January 18, 2013
Ph.D. Forum Deadline: February 8, 2013
Notification of Acceptance: February 28, 2013
Final Papers Due: March 15, 2013

TOPICS OF INTEREST
——————
We seek contributions on novel algorithms, computing paradigms,
computational models, application paradigms, computer architecture,
development environments, compilers, or operating environments. In
recognition of the maturation of several exciting areas at the
frontiers, this year, we are soliciting papers in thematic tracks in
addition to the general track. The topics of these tracks listed below
are suggestive and authors are invited to submit their papers in the
track that they believe matches their interests the best. In case the
authors prefer not to submit to any of the thematic tracks, they are
invited to submit their papers for review through the general
track. The program committee has identified the following tracks for
CF2013. In each track, a few key words identifying suggested topics
for research are listed below. These topics are not meant to be
exhaustive but instead, are broadly indicative of the range topics
being considered.

Thematic Tracks:

* Algorithms and Models of Computing: Approximate and Inexact, Quantum
and Probabilistic Computing, Neuromorphic Architectures
* Big Data: Analytics, Machine Learning, Search and Representation,
System Design
* System Complexity Management: Cloud Systems, Datacenters,
Computational Neuroscience, Neuromorphic and Biologically-inspired
Architectures
* Computers and Society: Education, Health and Frugal Design
delivering significantly lower energy and cost, Smart Cities and
Urban Design
* Security: Architecture and Systems support for Side-channel attacks,
Trojans
* Technology Scaling and Moore’s Law: Defect- and variability-tolerant
designs, Graphene and other novel materials, Inexact computing,
Nanoscale Design, Optoelectronics, coping with the Power Wall
* User Experience and Interfaces: Technology Convergence Enabling
Psychology and Neuroscience guided design

General track:

Topics in the general track can intersect with the above themes and/or
provide cutting-edge solutions in established disciplines such as:
Applications, programming and performance analysis of advanced
architectures next-generation high performance computing and systems,
Accelerators: many-core, GPU, custom, reconfigurable, embedded, and
hybrid, Virtualization and virtual machines, Compilers and operating
systems: adaptive, run-time, and auto-tuning, System management and
security, Computational aspects of intelligent systems and robotics,
Reconfigurable, autonomic, organic, and self-organizing computation
and systems, Sensors and sensor networks.

Demo Night:

We are pleased to announce that this year Computing Frontiers will
feature a special DEMO NIGHT session, to present EU and National
collaborative projects, to promote inter-project clustering and
networking, and to show demonstrations (hardware platforms, prototypes,
design frameworks, tools.). Short papers up to 3 pages, presenting the
projects, their technical challenges and the objectives of the
demonstration, are going to be included in the Computing Frontiers
proceedings. The proposals should be submitted through the conference
submission site and should include a description of the resources
required for the demo.

PAPER SUBMISSION
—————-

Authors are invited to submit full papers to the main conference and
short papers with the proposal for the demo night. Ph.D. students are
invited to submit an extended abstract for a special Ph.D. forum and
poster session.

Full papers should not exceed 10 double-column pages in standard ACM
conference format, including figures, tables, and references. Papers
will be reviewed in a double blind fashion. This means that submissions
must be anonymous. When submitting for a double blind process, authors
need to take special care in removing their names and any hints that
might reveal their identities to the reviewers.

Short papers for the demo night and extended abstracts for the Ph.D.
forum cannot exceed 3 double-column pages. If accepted, both are going
to be included in the Computing Frontiers proceedings.

As per ACM guidelines, at least one of the authors of accepted papers
is required to register for the conference.

ORGANIZING COMMITTEE
——————–

General Chairs: Hubertus Franke, IBM, US
Alexander Heinecke, TU Muenchen, DE

Program Chairs: Krishna Palem, Rice University, US
and Nanyang Technological University, SG
Eli Upfal, Brown University, US

Workshop/Demo Chairs: Francesca Palumbo, University of Cagliari, IT
Paolo Meloni, University of Cagliari, IT

Finance Chair: Carsten Trinitis, TU Muenchen, DE
and University of Bedfordshire, UK

Scholarships Chair: Yanyong Zhang, Rutgers University, US

Poster Chair: Rui Hou, Chinese Academy of Science, CN

Local Arrangements Chairs: Claudia Di Napoli, CNR, IT
Maurizio Giordano, CNR, IT

Publicity Chairs: Gokul Kandiraju, IBM, US
Josef Weidendorfer, TU Muenchen, DE

Publication Chair: Mohamed Zahran, New York University, US

Web Chair: Karl Fuerlinger, LMU Muenchen, DE

STEERING COMMITEE
—————–

Monica Alderighi, INAF, IT
Steven Beaty, National Center for Atmospheric Research, US
Calin Cascaval, Qualcomm Research, US
Sergio D’Angelo, INAF, IT
Kemal Ebcioglu, Global Supercomputing, US
Paolo Faraboschi, HP, ES
John Feo, Pacific Northwest National Lab, US
Gearold Johnson, Colorado State Univ., US
Sally A. McKee, Chalmers Univ. of Tech., SE
Cecilia Metra, University of Bologna, IT
Viktor Prasanna, USC, US
Valentina Salapura, IBM TJ Watson, US
Pedro Trancoso, University of Cyprus, CY
Carsten Trinitis, TU Muenchen, DE
Oreste Villa, Pacific Northwest National Lab, US

Submitted by Carole-Jean Wu
http://nocsymposium.org
Seventh ACM/IEEE International Symposium on Networks-on-Chip
April 2013
Tempe, Arizona

The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip and chip-scale communication
technology, architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and applications
from inter-related research communities, including computer architecture,
networking, circuits and systems, embedded systems, and design automation.
Topics of interest include, but are not limited to:

NoC architecture and implementation
- Network architecture (topology, routing, arbitration)
- NoC Quality of Service
- Timing, synchronous/asynchronous communication
- NoC reliability issues
- Network interface issues
- NoC design methodologies and tools
- Signaling & circuit design for NoC links
- Physical design of interconnect & NoC

NoC analysis and verification
- Power, energy & thermal issues (at the NoC, un-core and/or system-level)
- Benchmarking & experience with real NoC-based hardware
- Modeling, simulation, and synthesis of NoCs
- Verification, debug & test of NoCs
- Metrics and benchmarks for NoCs

NoC application
- Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
- Network design for 2.5D & 3D stacked logic and memory

NoC at the un-core and system-level
- Design of memory subsystem (un-core) including memory controllers, caches,
cache coherence protocols & NoCs
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and novel
programming models
- Multi/many-core workload characterization & evaluation
- Optical, RF, & emerging technologies for on-chip/inpackage interconnects
- Issues related to large-scale systems (datacenters, supercomputers) with
NoC-based systems as building blocks

Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation. Submitted papers must describe original
work that has not been published before or is under review by another conference
at the same time. Each submission will be checked for any significant similarity
to previously published works or for simultaneous submission to other archival
venues, and such papers will be rejected. Furthermore, NOCS will notify the
technical chair of the venue where the duplicate was submitted. Please see the
paper submission instructions for details.

Proposals for tutorials, special sessions, and panels are also invited. Please
see the detailed submission instructions for paper, tutorial, special sessions,
and panel proposals at the submission page. A special section related to the
theme of the conference will be organized in one of the IEEE journals.

Important Dates
Abstract registration deadline Nov 19, 2012
Full paper submission deadline Nov 26, 2012
Proposals for tutorials, special sessions and panels Jan 11, 2013
Notification of acceptance Feb 1, 2013
Final version due Mar 1, 2013

Organizing Committee
General Co-Chairs:
Karam S. Chatha, Arizona State University, USA
Chita R. Das, Penn State University, USA
Finance Chair:
Sudeep Pasricha, Colorado State, USA
Registration Chair:
Mohammed Al Faruque, Siemens, USA
Publicity Chair:
Carole Jean Wu, Arizona State University, USA
Program Co-Chairs:
John Bainbridge, Sonics Inc., USA
Natalie Enright Jerger, University of Toronto, CA
Publications Chair:
Paul Gratz, Texas A&M, USA
Tutorials/Demo Chair
Zhonghai Lu, KTH, Sweden
Industrial Chair
Umit Ogras, Intel, USA

Contact Information
Karam Chatha, kchatha@asu.edu
John Bainbridge, jbainbridge@ieee.org
Chita Das, das@cse.psu.edu
Natalie Enright Jerger, enright@eecg.toronto.edu

Submitted by Carole Wu
http://www.nocsymposium.org
Call for Tutorials, Demos and Special Sessions
Seventh ACM/IEEE International Symposium on Networks-on-Chip, April 21-24, 2013
Tempe, Arizona, USA

http://www.nocsymposium.org

A. General Information

Researchers from both academia and industry are invited to submit proposals for
Tutorials, Demo and Special Sessions for the NOCS 2013 conference, to be held
April 21-24 in Tempe, Arizona, USA. See below for each specific call. Proposals
must be sent via e-mail (in either pdf or plain ascii text form) to Prof.
Zhonghai Lu, Tutorial/Demo/Special Session Chair (zhonghai@kth.se). While
submitting a proposal, please indicate whether the proposal is for a tutorial,
demo or special session.

Important dates:
- Tutorial/ Demonstration/Special Session proposals due: Jan 20th 2013
- Acceptance notification: Feb 10th 2013

In general, tutorial, demo and special session proposals will be evaluated in
terms of their quality and technical/scientific contribution. Sessions
strengthening and/or extending the conference program will be prioritized. The
Demo/Tutorial/Special Session Chair reserves the right to refuse proposals in
case of logistic constraints.

B. Tutorials

The purpose of tutorials is to educate attendees about specific topics or to
provide the background necessary to understand technical advances in relevant
areas. The tutorial should be attractive to a wide audience with interests in
NoC research. Possible topics of interest include, but are not limited to, a
wide variety of NoC related areas from multicore architecture and programming,
to circuit-level design and emerging architectures based on 3D integration,
optical interconnects and on-chip RF/wireless communications, from industrial
case studies, design methodology to performance analysis. There will be two
tutorial sessions, each of half day duration.

The tutorial proposal (length limit: 2 pages in 10-point font) should include:
- Title of the tutorial
- Contact information for the presenter(s) (name, email address, affiliation)
- Keywords
- Short description of the target audience
- A detailed outline of the tutorial
- A short biography of the presenter(s)
- If the tutorial has been offered previously at a conference, the proposers
need to provide the conference information (location, date) and number of
attendees.

The evaluation of the proposal will include its general interest for NOCS
attendees, the quality of the proposal, and the expertise of the presenters.

Further, the selected tutorials are expected to adhere to the following
guidelines:
- Speakers are required to provide tutorial material to the Chair one month
prior to the conference.
- The NOCS conference will reproduce the tutorial material for the attendees.
- The NOCS conference committee reserves the right to cancel any tutorial if too
few attendees are registered for a given tutorial.

C. Demos

The purpose of the demo session is to exhibit the latest results related to NoC
research and developments. A complete conference session will be devoted to the
demonstrations. The conference chairs encourage CAD tool, circuit and integrated
system demonstrations, and FPGA prototyping of their latest developments in the
domains of NoC architectures and design methodology. The evaluation of the demo
proposal will consider its general interest for NOCS attendees, the quality and
significance of the demonstration. A demonstration table, a poster board, and
electrical plug will be available for each selected demo. A Best Demonstration
Award will be conferred at the end of the session.

The demo proposal should include:
- Title, abstract (50 words) and description of the demonstration (limit:
1 page in 10 point format)
- Contact information for the presenter(s) (name, email address, affiliation)
- Any special demo requirements (Electrical appliance, scope, …)

D. Special Sessions

Special session is devoted to either a traditional core NoC topic, or a topic of
future interest to the audience. The topic should be presented from a viewpoint
that does not overlap with content from traditional research manuscripts.
-A complete submission should list at least three inspiring speakers who can
address the various issues within the topic.
-Special session proposals require an overall title, abstract for the special
session plus a title, short abstract, and name of the speaker (with full
contact information and short biography) for each of the proposed talks.
Note that the organizer/submitter of the special session may also be a
speaker for the session.

Submitted by Carole Wu
http://nocsymposium.org

Call for Papers [Deadline Extension]
The 7th ACM/IEEE International Symposium on Networks-on-Chip
April 21-24, 2013
Tempe, Arizona, USA

The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip and chip-scale communication
technology, architecture, design methods, applications and systems. NOCS brings
together scientists and engineers working on NoC innovations and applications
from inter-related research communities, including computer architecture,
networking, circuits and systems, embedded systems, and design automation.
Topics of interest include, but are not limited to:

NoC architecture and implementation
- Network architecture (topology, routing, arbitration)
- NoC Quality of Service
- Timing, synchronous/asynchronous communication
- NoC reliability issues
- Network interface issues
- NoC design methodologies and tools
- Signaling & circuit design for NoC links
- Physical design of interconnect & NoC

NoC analysis and verification
- Power, energy & thermal issues (at the NoC, un-core and/or system-level)
- Benchmarking & experience with real NoC-based hardware
- Modeling, simulation, and synthesis of NoCs
- Verification, debug & test of NoCs
- Metrics and benchmarks for NoCs

NoC application
- Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
- Network design for 2.5D & 3D stacked logic and memory

NoC at the un-core and system-level
- Design of memory subsystem (un-core) including memory controllers, caches,
cache coherence protocols & NoCs
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and novel
programming models
- Multi/many-core workload characterization & evaluation
- Optical, RF, & emerging technologies for on-chip/inpackage interconnects
- Issues related to large-scale systems (datacenters, supercomputers) with
NoC-based systems as building blocks

Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation. Submitted papers must describe original
work that has not been published before or is under review by another conference
at the same time. Each submission will be checked for any significant similarity
to previously published works or for simultaneous submission to other archival
venues, and such papers will be rejected. Furthermore, NOCS will notify the
technical chair of the venue where the duplicate was submitted. Please see the
paper submission instructions for details.

Proposals for tutorials, special sessions, and panels are also invited. Please
see the detailed submission instructions for paper, tutorial, special sessions,
and panel proposals at the submission page. A special section related to the
theme of the conference will be organized in one of the IEEE journals.

Abstract registration deadline Dec. 4, 2012
Full paper submission deadline Dec. 7, 2012
Proposals for tutorials, special sessions and panels Jan 11, 2013
Notification of acceptance Feb 1, 2013
Final version due Mar 1, 2013

Organizing Committee
General Co-Chairs:
Karam S. Chatha, Arizona State University, USA
Chita R. Das, Penn State University, USA
Finance Chair:
Sudeep Pasricha, Colorado State, USA
Registration Chair:
Mohammed Al Faruque, UC-Riverside, USA
Publicity Chair:
Carole Jean Wu, Arizona State University, USA
Program Co-Chairs:
John Bainbridge, Sonics Inc., USA
Natalie Enright Jerger, University of Toronto, CA
Publications Chair:
Paul Gratz, Texas A&M, USA
Tutorials/Demo Chair
Zhonghai Lu, KTH, Sweden
Industrial Chair
Umit Ogras, Intel, USA

Contact Information
Karam Chatha, kchatha@asu.edu
John Bainbridge, jbainbridge@ieee.org
Chita Das, das@cse.psu.edu
Natalie Enright Jerger, enright@eecg.toronto.edu

Submitted by Ioana Baldini
Call for Participation: ISPASS 2013 — Workshops and Tutorials:

The following two tutorials and one workshop are being held on
Sunday April 21, 2013 in conjunction with ISPASS:

Modeling Exascale Applications with SST/macro and Eiger
(half day)
(http://casl.gatech.edu/research/eiger-tutorial)

GPUWattch + GPGPU-Sim: An Integrated Framework for
Energy Optimizations in Manycore (half day)
(http://ready.ece.utexas.edu/workshops/gpuwattch/)

FastPath 2013 Workshop on Performance Analysis
of Workload Optimized Systems (full day)
(http://researcher.watson.ibm.com/researcher/view_project.php?id=4338)
Submission deadline: March 10, 2013

Detailed information:

Modeling Exascale Applications with SST/macro and Eiger
(half day)

In high performance computing (HPC), the importance of fast, large
scale models of high fidelity are only increasing as we move towards
the next frontier of exascale. Hardware/software codesign is viewed as
a key methodology to reaching this end. The SST/macro toolkit[1]
provides HPC engineers the ability to explore current and future
hardware/software design constraints. Instead of costly (in time and
user effort) cycle-accurate simulation, macro-scale simulation can
provide valuable insight into the performance of large
applications. The value of these tools lies in high quality
application models for increasingly complex hardware designs.

The Eiger Performance Modeling Framework[2] generates models by
applying statistical techniques from the field of machine learning on
empirical performance data. While macro-scale simulation can provide a
reasonable overview of system wide phenomena, Eiger can leverage data
acquired from micro-scale sources to inform large scale simulations in
SST/macro. Eiger provides an API and data store for aggregating data
from micro-scale sources such as simulators, emulators, and runtime
instrumentation.

This tutorial will present attendees with the techniques and
methodologies to leverage SST/macro and Eiger for modelling large
scale applications on upcoming supercomputer hardware. This
presentation is geared towards domain experts and HPC hardware
designers, as well as students and researchers whose work requires
exploration of programming models, interaction between computation and
communication, and data-driven modelling techniques for large scale
systems. These tools are geared toward ease of use and rapid
iteration, allowing area experts to generate verbose performance
models without requiring intricate knowledge of every facet of the
computing environment. This tutorial will require only a basic level
of programming skill.

GPUWattch + GPGPU-Sim: An Integrated Framework for
Energy Optimizations in Manycore (half day)

The objective of this tutorial is to present an overview of the design
and implementation of the GPGPU- Sim simulation infrastructure along
with a newly developed power model. The integrated GPUWattch power
model is highly configurable and extensible.

GPGPU-Sim version 3.x represents a significant update to GPGPU-Sim,
featuring a more accurate and detailed microarchitectural model. It
includes support for NVIDIA’s native ISA and the Fermi
Architecture. With the tightly-coupled GPUWattch, the simulation
infrastructure is now a complete platform for performance and energy
optimization research. The infrastructure follows a rigorous design
methodology that has been tested and validated against hardware
performance and power measurements for both the Fermi and Quadro
architectures.

FastPath 2013 Workshop on Performance Analysis
of Workload Optimized Systems (full day)

The goal of FastPath is to bring together researchers and
practitioners involved in cross-stack hardware/software performance
analysis, modeling, and evaluation of workload optimized systems.

With microprocessor clock speeds being held constant, optimizing
systems around specific workloads is an increasingly attractive means
to improve performance. The importance of workload optimized systems
is seen in their ubiquitous deployment in diverse systems from
cellphones to tablets to routers to game machines to Top500
supercomputers, and IT appliances such as IBM’s DataPower and Netezza,
and Oracle’s Exadata.

More precisely, workload optimized systems have hardware and/or
software specifically designed to run well for a particular
application or application class. The types and components of workload
optimized systems vary, but a partial list includes traditional CPUs
assisted with accelerators (ASICs, FPGAs, GPUs), memory accelerators,
I/O accelerators, hybrid systems, and IT appliances.

Exploiting CPU savings and speed-ups offered by workload optimized
systems for application level performance improvement poses several
cross stack hardware and software challenges. These include developing
alternate programming models to exploit massive parallelism offered by
accelerators, designing low-latency, high-throughput H/W-S/W
interfaces, and developing techniques to efficiently map processing
logic on hardware.