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April 13, 2014

Call for Participation: 4th Workshop on Systems for Future Multicore Architectures (SFMA’14)

Submitted by Simon Peter
Future multi-core architectures will present a variety of challenges
for system developers, such as non-cache-coherent memory,
heterogeneous processing cores and the exploitation of novel
architectural features. SFMA ’14 is a forum for researchers in the
architecture, operating systems, language runtime and virtual machine
communities to present and discuss their experiences with the new
generation of highly-parallel hardware.

SFMA ’14 is co-located with EuroSys ’14 and takes place April 13,
2014 in Amsterdam, The Netherlands.

Start: April 13, 2014
End: April 13, 2014
Venue: Amsterdam, The Netherlands

Call for Papers: The First International Workshop on Rack Scale Computing (WRSC 2014)

Submitted by Paolo Costa
The First International Workshop on Rack Scale Computing (WRSC 2014)

WRSC will be a venue to discuss the impact of game-changing
technologies such as SoCs, integrated fabrics, low-latency RDMA,
silicon photonics, on the design of data center hardware and
software. These technologies and implications span different
areas, so as a unifying theme we are using the term “rack-scale
computing” because many of these changes are happening at the
scale of a rack. We are already seeing early platforms from
companies like AMD SeaMicro, HP and Intel.

However, fully unleashing their potential requires a deep and
cross-layer rethinking of the way the hardware, OS and network
stacks, and applications are built and interact. While some of
these ideas have already started being discussed in various
research communities, we believe it’s important to have a common
forum for researchers and practitioners from different
areas (hardware architectures, networking, operating systems,
storage, distributed systems, and HPC) to discuss new ideas on
how to design next-generation rack-scale systems. We hope that
this workshop will help shaping the research agenda in the field.
- Submission deadline: Sunday Feb 16, 2014

- Notification to the authors: Saturday, Mar 8, 2014

- Workshop: Sunday April 13, 2014 in Amsterdam (co-located with Eurosys 2014).

= Organization =

Paolo Costa, Microsoft Research (Program Chair)

Dushyanth Narayanan, Microsoft Research (General Chair)

= Program Committee=

Gustavo Alonso, ETH Zurich
Edouard Bugnion, EPFL
Luis Ceze, U. Washington
Paolo Costa, Microsoft Research
Leendert van Doorn, AMD
Babak Falsafi, EPFL
Blake Fitch, IBM Research
Nathan Farrington, Facebook
Tim Harris, Oracle Labs
Michael Kaminsky, Intel Labs
Dushyanth Narayanan, Microsoft Research
Parthasarathy (Partha) Ranganathan, Google
Luigi Rizzo, U. Pisa
Thomas Wenisch, U. Michigan
Bernard Wong, U. Waterloo

Start: April 13, 2014
End: April 13, 2014
Venue: Amsterdam

April 10, 2014

Call for Papers: ASBD @ ISCA 2014

Submitted by Yungang Bao
Paper Due April 11th

We are pleased to request papers for presentation at the upcoming Fourth
Workshop on Architectures and Systems for Big Data (ASBD 2014) held in
conjunction with ISCA-41. The workshop will provide a forum to exchange
research ideas related to all critical aspects of emerging analytics
systems for big data, including architectural support, benchmarks and
metrics, data management software, operating systems, and emerging
challenges and opportunities. We hope to attract a group of interdisciplinary
researchers from academia, industry and government research labs.
To encourage discussion between participants, the workshop will include
significant time for interactions between the presenters and the audience.
We also plan to have a keynote speaker and/or panel session.

Start: April 10, 2014
End: April 11, 2014
Venue: Minneapolis, MN, USA

April 1, 2014

Call for Papers: SELSE 2014

Submitted by William H. Robinson
Workshop on Silicon Errors in Logic – System Effects (SELSE 2014)
April 1 – 2, 2014 – Stanford University

Important dates:
– Register an abstract: December 13, 2013
– Paper submission: December 20, 2013
– Authors notification: February 4, 2014
– Camera-ready submission: February 28, 2014

The growing complexity and shrinking geometries of modern manufacturing
technologies are making high-density, low-voltage devices increasingly
susceptible to the influences of electrical noise, process variation,
transistor aging, and the effects of natural radiation. The system-level
impact of these errors can be far-reaching. Growing concern about
intermittent errors, unstable storage cells, and the effects of aging are
influencing system design, and failures in memories account for a significant
fraction of costly product returns. The SELSE workshop provides a forum for
discussing current research and practice in system-level error management.
Participants from industry and academia explore both current technologies and
future research directions (including nanotechnology). SELSE is soliciting
papers that address the system-level effects of errors from a variety of
perspectives: architectural, logical, circuit-level, and semiconductor
processes. Case studies are also solicited.

Key areas of interest are (but not limited to):
– Technology trends and the impact on error rates.
– New error mitigation techniques.
– Characterizing the overhead and design complexity of error mitigation
– Case studies describing the tradeoffs analysis for reliable systems.
– Experimental silicon failure data.
– System-level models: derating factors and validation of error models.
– Error handling protocols (higher-level protocols for robust system design).

Authors are requested to register an abstract by December 13th, 2013 and to
submit their paper by December 20th, 2013. Papers will be considered for both
oral and poster presentation. All accepted submissions are included in the
workshop proceedings. Authors will be notified by February 4th, 2014.
Camera-ready papers are due on February 28th, 2014.

Additional information and guidelines for submission are available at Submissions should be in PDF following IEEE two-column
conference proceedings format that does not exceed four printed pages. Final
papers may be up to six pages in length. Papers are not made available
through IEEE and authors retain the copyright of their work. Authors may
optionally choose to make their final papers and/or presentations available
online at the workshop web site.

Organizing Committee
General chairs: Vilas Sridharan (AMD) and
Sarah Michalak (LANL)
Program chairs: Adrian Evans (iROC Technologies) and
Dimitris Gizopoulos (University of Athens)
Finance chairs: Dan Alexandrescu (iROC Technologies) and
Naveen Muralimanohar (HP)
Local arrangements chair: Helia Naeimi (Intel)
Publicity chairs: William H. Robinson (Vanderbilt University) and
Yanos Sazeides (University of Cyprus)
Proceedings chair: Mehdi Tahoori (Karlsruhe Institute of Technology)
Webmaster: Marios Kleanthous (Mesoyios College)

Start: April 1, 2014
End: April 2, 2014
Venue: Stanford University

March 31, 2014

Call for Papers: ASBD 2014

Submitted by Yungang Bao
We are pleased to request papers for presentation at the upcoming Fourth
Workshop on Architectures and Systems for Big Data (ASBD 2014) held in
conjunction with ISCA-41. The workshop will provide a forum to exchange
research ideas related to all critical aspects of emerging analytics
systems for big data, including architectural support, benchmarks and
metrics, data management software, operating systems, and emerging
challenges and opportunities. We hope to attract a group of interdisciplinary
researchers from academia, industry and government research labs.
To encourage discussion between participants, the workshop will include
significant time for interactions between the presenters and the audience.
We also plan to have a keynote speaker and/or panel session.

Start: March 31, 2014
End: March 31, 2014
Venue: Minneapolis, MN, USA

March 24, 2014

Call for Papers: EMBS at ACM SAC 2014

Submitted by Alessio Bechini

29th ACM Symposium on Applied Computing
Gyeongju, Korea, March 24-28, 2014

New Perspectives
for Hardware, System Software, and Applications

High performance embedded computing has recently become more and more present in
devices used in everyday life. A wide variety of applications, from consumer
electronics to biomedical systems, require building up powerful yet cheap
embedded devices. In this context, embedded software has turned out to be more
and more complex, posing new challenging issues. The adoption of further
flexible programming paradigms/architectures is becoming almost mandatory.
Nonetheless, even nowadays the development of embedded systems must rely on a
tight coupling of hardware and software components. Moreover, the market
pressure calls for the employment of new methodologies for shortening the
development time, and for driving the evolution of existing products.
New efficient solutions to problems emerging in this setting can be put into
action by means of a joint effort of academia and industry.

Design of embedded systems must take into account a wide variety of constraints:
performance, code size, power consumption, presence of real-time tasks,
robustness, maintainability, security, and possibly scalability. The more
convenient trade-off has to be found, often operating on a large number of
different parameters. In this scenario, solutions can be proposed at different
levels of abstraction, making use of an assortment of tools and methodologies:
researchers and practitioners have a chance to propose new ideas and to compare

The focus of this conference track is on the application of both novel and
well-known techniques to the embedded systems development. Particular attention
is paid to solutions that require expertise in different fields
(e.g. computer architecture, OS, compilers, security, software engineering,
simulation). The track will benefit also from direct experiences in the
employment of embedded devices in “unconventional” application areas, so
to show up new challenges in the system design/development process.
In this setting, researchers and practitioners from academia and industry will
get a chance to keep in touch with problems, open issues and future directions
in the field of development of dedicated applications for embedded systems.

Topics of Interest

* Methodologies and tools for design-space exploration
* System-level design and simulation techniques for Embedded Systems
* OS & Real-Time support for Embedded Systems
* Verification, validation, testing, debugging, and performance analysis of
Embedded Systems
* Cyber physical systems and networked sensor devices
* Multicore, SoC-based, and heterogeneous Embedded Systems and applications
* Time-predictable computer architecture
* GPU computing in Embedded Systems applications
* Memory/storage management for Embedded Systems
* Power-aware design and computing
* Runtime adaptability in Embedded Systems
* Middleware and virtual machines in Embedded Systems
* Multithreading in Embedded Systems design and development
* Compilation strategies, code transformation and parallelization for Embedded
* Java embedded computing
* Software architectures and SOA for Embedded Systems
* Data management in Embedded Systems
* Embedded Systems as components in Information Systems
* Multimedia in Embedded Systems
* Reliability in Embedded Computing and Systems
* Security within Embedded Systems and Embedded Systems for security
* Safety-critical Embedded Systems
* Special-purpose appliances and applications
* Case studies

Important dates (PAPERS & SRC ABSTRACTS)

* September 13th, 2013: Paper Submission
* November 15th, 2013: Author Notification
* December 6th, 2013: Camera-Ready Copies

Paper Submissions

Only papers based on original, unpublished work and addressing the listed
topics of interest will be considered.

Each submitted paper will be fully refereed and undergo a blind review process.
In order to facilitate blind review, the author(s) name(s) and address(es) must
NOT appear in the body of the paper, and self-reference should be in the third
person. Only the title should be shown at the first page without the author’s
Please note that submission of the same paper to multiple tracks is not allowed.

Upon acceptance, paper registration is required, allowing the inclusion of the
paper/poster in the conference proceedings. An author or a proxy attending SAC
MUST present the paper. This is a requirement for the paper/poster to be
included in the ACM/IEEE digital library. No-show of scheduled papers and
posters will result in excluding them from the ACM/IEEE digital library.

Submissions are accepted only in electronic form, through the SAC web submission
system at
Submissions must follow the template reported here:

Camera-ready papers can be up to 6 pages long according to the conference
template; up to 2 extra pages are allowed, at an additional fee of 80 USD per
extra page (this last figure will be confirmed later).

SAC also hosts a poster session; authors of relevant papers that are positively
evaluated, but cannot be included in the conference because of space limits,
can be invited to provide their contribution in the form of a poster. A poster
contribution is given a two-page space in the official SAC proceedings, and
possibly an extra page is allowed (with the same rules used for regular papers).

Student Research Competition at ACM SAC

Graduate students seeking feedback from the scientific community on their
research ideas are invited to submit abstracts of their original unpublished and
in-progress research work in areas of experimental computing and application
development related to SAC 2013 Tracks. The Student Research Competition (SRC)
program is designed to provide graduate students the opportunity to meet and
exchange ideas with researcher and practitioners in their areas of interest.

All research abstract submissions will be reviewed by researchers and
practitioners with expertise in the track focus area to which they are
submitted. Authors of selected abstracts will have the opportunity to give
poster presentations of their work and compete for three top winning places.
The SRC committee will evaluate and select First, Second, and Third place
winners. The winners will receive cash awards and SIGAPP recognition
certificates during the conference banquet dinner. Authors of selected abstracts
are eligible to apply to the SIGAPP Student Travel Award program for support.

Submission – Graduate students are invited to submit abstracts (minimum of two
pages; maximum of four pages) of their original unpublished and in-progress
research work following the instructions published at SAC 2013 web-site.
The submissions must address research work related to a SAC track, with emphasis
on the innovation behind the research idea, including the problem being
investigated, the proposed approach and research methodology, and sample
preliminary results of the work. In addition, the abstract should reflect on the
originality of the work, innovation of the approach, and applicability of
anticipated results to real-world problems. All abstracts must be submitted
thought the START Submission system, at

Please note SRCs and regular papers must be submitted at different pages of the
START web system.
Submitting the same abstract to multiple tracks is not allowed.

It is recommended to refer to the official SRC Information Sheet
for further details.

Track Chairs & Program Committee


Alessio Bechini – Univ. of Pisa – Italy
Li-Pin Chang – National Chiao-Tung University – Taiwan

Program Committee:

Peter Altenbernd – University of Applied Sciences, Darmstadt – Germany
Erik Altman – IBM T.J. Watson Research Center – USA
Sandro Bartolini – University of Siena – Italy
Valerie Bertin – ST Microelectronics – France
João M. P. Cardoso – University of Porto – Portugal
Naehyuck Chang – Seoul National University – Korea
Mingsong Chen – East China Normal University – China
Alexander G. Dean – North Carolina State University – USA
Lavinia Egidi – University of Eastern Piedmont – Italy
Marc Engels – Flanders’ Mechatronics Technology Centre, Leuven – Belgium
Pierfrancesco Foglia – University of Pisa – Italy
Gerhard Fohler – TU Kaiserslautern – Germany
Björn Franke – University of Edinburgh – UK
Malay Ganai – NEC labs America – USA
Catherine H. Gebotys – University of Waterloo – Canada
Roberto Giorgi – University of Siena – Italy
Matthias Gries – Intel Labs – Germany
Zonghua Gu – Zhejiang University, Hangzhou – China
Raphael Guerra – Universidade Federal Fluminense – Brasil
Rajiv Gupta – University of California Riverside – USA
Frank Hannig – University of Erlangen-Nuremberg – Germany
Niraj K. Jha – Princeton University – USA
Per Gunnar Kjeldsberg – Norwegian Univ. of Science and Technology,
Trondheim – Norway
Andreas Krall – TU Wien – Austria
Arindam Mallik – IMEC – Belgium
Claire Pagetti – ONERA – France
Sri Parameswaran – Univ. of New South Wales – Australia
Andy D. Pimentel – University of Amsterdam – The Netherlands
Christine Rochange – IRIT – France
Bastian Schlich – ABB Corporate Research – Germany
Martin Schoeberl – DTU – Denmark
Henk Sips – TU Delft – The Netherlands
Jean-Pierre Talpin – INRIA/IRISA – France
Hiroyuki Tomiyama – Ritsumeikan University – Japan
Yi Wang – Hong Kong Polytechnic University – Hong Kong
Ning Weng – Southern Illinois University Carbondale – USA
Tilman Wolf – University of Massachusetts Amherst – USA
I-Ling Yen – University of Texas at Dallas – USA
Wang Yi – Uppsala University – Sweden

Start: March 24, 2014
End: March 28, 2014
Venue: Gyeongju, Korea

March 23, 2014

Call for Papers: ISPASS 2014

Submitted by Byeong Kil Lee
2014 IEEE International Symposium on Performance Analysis of Systems
and Software (ISPASS 2014)
March 23-25, 2014
Monterey, CA

Call for Papers:
The IEEE International Symposium on Performance Analysis of Systems
and Software provides a forum for sharing advanced academic and
industrial research work focused on performance analysis in the design
of computer systems and software. Authors are invited to submit
previously unpublished work for possible presentation at the
conference. Papers are solicited in fields that include the following:

* Performance and power evaluation methodologies
– Analytical modeling
– Statistical approaches
– Tracing and profiling tools
– Simulation techniques
– Hardware (e.g., FPGA) accelerated simulation
– Hardware performance counter architectures
– Power/Temperature/Variability/Reliability models for computer systems
– Micro-benchmark based hardware analysis techniques

* Performance and power analysis
– Metrics
– Bottleneck identification and analysis
– Visualization

* Power/Performance analysis of commercial and experimental hardware
– General-purpose microprocessors
– Multi-threaded, multi-core and many-core architectures
– Accelerators and graphics processing units
– Embedded and mobile systems
– Enterprise systems and data centers
– Supercomputers
– Computer networks

* Power/Performance analysis of emerging workloads and software
– Software written in managed languages
– Virtualization and consolidation workloads
– Internet-sector workloads
– Embedded, multimedia, games, telepresence
– Bioinformatics, life sciences, security, biometrics

* Application and system code tuning and optimization
* Confirmations or refutations of important prior results

In addition to research papers, we also welcome tool papers. The
conference is an ideal forum to publicize new tools to the
community. Tool papers will be judged primarily on their potentially
wide impact and use than on their research contribution. Tools in any
of the above fields of interest are eligible.

See for submission details.

Paper abstract submission: September 20, 2013
Full submission: September 27, 2013 (No extensions)
Rebuttal: November 27-29, 2013
Notification: December 11, 2013
Final paper due: January 31, 2014

Tor M. Aamodt, University of British Columbia

Benjamin C. Lee, Duke

Alaa Alameldeen, Intel
Abhishek Bhattacharjee, Rutgers
Ramon Canal, UPC Barcelona
Fred Chong, UC Santa Barbara
Bronis de Supinski, LLNL
Stijn Eyerman, Ghent
Andrew Hilton, Duke
Nuwan Jayasena, AMD
Xiaoyao Liang, Shanghai Jiaotong
Kevin Lim, HP
Albert Meixner, NVIDIA
Karthick Rajamani, IBM
Jose Renau, UC Santa Cruz
Ali Saidi, ARM
Karu Sankaralingam, Wisconsin
Arrvindh Shriraman, Simon Fraser
Ravi Soundararajan, VMWare
Lingjia Tang, Michigan
Devesh Tiwari, ORNL
Mohit Tiwari, Texas
David Wentzlaff, Princeton
Qiang Wu, Facebook
Hongzhong Zheng, Samsung

Byeong Kil Lee, Samsung

Nadeem Malik, IBM

Mike Ferdman, Stonybrook

Mark Hempstead, Drexel

Jason Mars, University of Michigan

Suzanne Rivoire, Sonoma State University

Carole-Jean Wu, Arizona State University

Start: March 23, 2014
End: March 25, 2014
Venue: Monterey, CA

Call for Participation: ISPASS 2014 — Early Registration Deadline: 3/1

Submitted by Byeong Kil Lee
2014 IEEE International Symposium on Performance Analysis of Systems and
Software (ISPASS 2014)
March 23-25, 2014
Monterey, CA

Call for Participation:
The 2014 IEEE International Symposium on Performance Analysis of Systems and
Software is sponsored by the IEEE Computer Society’s Technical Committee on
Internet, Technical Committee on Computer Architecture,
and Technical Committee on Microprogramming and Microarchitecture.

***** Early Registration deadline is March 1st, 2014 at 5PM Pacific *****

[ Keynotes ]
Keynote I. Bridging the Energy-Efficiency Gap in a Future of Massive Data
Prof. Fred Chong (University of California, Santa Barbara)

Keynote II. Life Lessons and Datacenter Performance Analysis
Dr. Amer Diwan (Google)

[ Program ]
Session 1: Best Paper Nominees
BarrierPoint: Sampled Simulation of Multi-threaded Applications
Sources of Error in Full-System Simulation
Exploiting Spatial Architectures for Edit Distance Algorithms
A Top Down Method for Performance Analysis and Counters Architecture

Session 2: Applications and Benchmarks
Moby: A Mobile Benchmark Suite for Architectural Simulators
The Design Space of Ultra-low Energy Asymmetric Cryptography
Optimized Hardware for Suboptimal Software: The Case for SIMD-aware Benchmarks

Session 3: Analytical and Statistical Models
Applying the Roofline Model
Extending Statistical Cache Models to Support Detailed Pipeline Simulators
Modeling Cache Coherence Misses on Multicore

Session 4: Simulators
Manifold: A Parallel Simulation Framework for Multicore Systems
PriME: A Parallel and Distributed Simulator for Thousand-Core Chips

Poster Session
A Study on Mobile Device Utilizations
Steps Towards Wider Use of Concurrency Code Patterns
ParTejas: A Parallel Simulator for Multicore Processors
Diamond: An Integrated Performance and Power Simulator for Large Scale Multicores
Weighted-Tuple Synchronization for Parallel Architecture Simulators
Accelerating Network-on-Chip Simulation via Sampling
A Case for Resource Efficient Prefetching in Multicores
Evaluating Trace Aggregation through Entropy Measures for Performance
Visualization of Large Distributed Systems
Reverse Engineering of Cache Replacement Policies in Intel Microprocessors and
Their Evaluation
Energy Introspector: A Parallel, Composable Framework for Integrated
Power-Reliability-Thermal Modeling for Multicore Architectures
Characterizing the Latency Hiding Ability of GPUs

Session 5: Online Profiling
A Software Based Profiling Method for Obtaining Speedup Stacks on Commodity
MIAMI: A Framework for Application Performance Diagnosis
Quality Time: A Simple Online Technique for Quantifying Multicore Execution
Variability of Data Dependences and Control Flow

Session 6: Cache and Memory Systems
NDC: Analyzing the Impact of 3D-Stacked Memory+Logic Devices on MapReduce
Simulating DRAM controllers for future system architecture exploration
Energy-Efficient Reconfigurable Cache Architectures for Accelerator-Enabled
Embedded Systems

Session 7: GPUs
GPU-Qin: A Methodology for Evaluating the Error Resilience of GPGPU Applications
Understanding the Tradeoffs between Software-Managed vs. Hardware-Managed Caches
in GPUs

[ Tutorial ]
GPUWattch (morning)
CloudSuite (afternoon)

[ Workshop ]
Fastpath ( full day workshop)

[ Registration ]
Online Registration:
Early Registration deadline is March 1st, 2014 at 5PM Pacific.

[ Hotel Information ]
ISPASS 2014 will be held at the Hyatt Regency Hotel in Monterey, California
Please use the following link to register for the hotel:

Note: The hotel registration cutoff is March 1st at 5PM (Pacific).

[ NSF Travel Support for Eligible Students ]
The deadline for submitting travel funding applications is March 1st. Please
send them by email to the Student Travel Grant Chair, Carole-Jean Wu
( Use the subject line “ISPASS 2014 Student Travel Grant

[ Visas for Travel to U.S. ]
If you require an invitation letter for purposes of a visa application, please
send an email with your name, email address, mailing address, IEEE member number
(if any), the ID of the paper you are presenting (if any) and a copy of your
registration confirmation to Suzanne Rivoire, the Registration Chair at

For more details, please see

Start: March 23, 2014
End: March 25, 2014
Venue: Hyatt Regency Hotel in Monterey, CA, USA

March 9, 2014

Call for Abstracts: Non-Volatile Memories Workshop 2014

Submitted by Steven Swanson
The 5th Annual Non-Volatile Memories Workshop (NVMW 2014) provides a unique
showcase for outstanding research on solid state, non-volatile memories. It
features a “vertically integrated” program that includes presentations on
devices, data encoding, systems architecture, and applications related to these
exciting new data storage technologies. Last year’s workshop (NVMW 2013)
included 32 speakers from top universities, industrial research labs, and
device manufacturers and attracted nearly 200 attendees. (The website for NVMW
2013 can be found at NVMW 2013 will build on this

The organizing committee is soliciting presentations on any topic related to
non-volatile, solid state memories, including:

• Advances in memory devices or memory cell design.

• Characterization of commercial or experimental memory devices.

• Error correction and data encoding schemes for non-volatile memories.

• Advances in non-volatile memory-based storage systems.

• Operating system and file system designs for non-volatile memories.

• Security and reliability of solid-state storage systems.

• Applications of non-volatile memories to scientific, “big data”, and
high-performance workloads.

• Implications of non-volatile memories for applications such as
databases and NoSQL systems.

The goal is to facilitate the exchange of the latest ideas, insights, and
knowledge that can propel future progress. To that end, presentations may
include new results or work that has already been published during the 18
months prior to the submission deadline. In lieu of printed proceedings, we
will post the slides and extended abstracts of the presentations
online. Presentation of new work at the workshop does not preclude future

Workshop submissions should be in the form of a 2-page presentation
abstract. Submissions will be evaluated on the basis of impact, novelty, and
general interest.

The submission deadline is November 25, 2013, with notification of acceptance
by January 31, 2014.

Further details on abstract submission, technical program, tutorials, travel,
social program, and travel grant will be provided at

Start: March 9, 2014
End: March 11, 2014
Venue: UC San Diego

Call for Participation: 5th Non-Volatile Memories Workshop

Submitted by Steven Swanson
Call for Participation
5th Non-Volatile Memories Workshop
La Jolla, California USA
March 9-11, 2014

The 5th Annual Non-Volatile Memories Workshop (NVMW 2014)
provides a unique showcase for outstanding research on solid
state, non-volatile memories. It features a “vertically
integrated” program that includes includes presentations on
a wide range of topics spanning devices, data encoding,
systems architecture, and applications:

* Big data applications for NVMs
* Flash-based SSD optimization
* Power management in NVMs
* Operating system optimizations
* SSD wear management
* Persistent objects
* Novel NVM array architectures
* Error coding for NVMs

The workshop program will include around 30 speakers from
top universities, industrial research labs, and around the

Workshop information is available here

Early registration ends February 28th.
Travel grant applications are due February 12th.

Platinum Sponsors
National Science Foundation

Gold Sponsors
Microsoft Research
PMC Sierra
Western Digital
SK Hynix memory solutions

Steven Swanson, UCSD CSE
Paul Siegel, UCSD ECE/CMRR

Program Committee

Al Borchers, Google
Alexander Driskill-Smith, Samsung
Alexandros Dimakis, UT Austin
Andrew Jiang, Texas A & M
Bipin Rajendran, IIT, Bombay
Bongki Moon, Seoul National University
Brian Kurkoski, JAIST
Chaitan Baru, SDSC
Chao Tian, AT&T Labs – Research
Christophe Chevallier, Rambus
Dalia Malkhi, Microsoft Research
Douglas Santry, NetApp
Edwin Kan, Cornell University
Eitan Yaakobi, Caltech
Ethan Miller, UC Santa Cruz
Hemant Thapar, UCSD
Hironori Uchikawa, Toshiba
Ken Lee, Qualcomm
Maya Gokhale, LLNL
Nitin Agrawal, NEC
Rick Coulson, Intel
Robert Calderbank, Duke
Shruti Patil, Univ. of Minnesota
Sudhanva Gurumurthi, AMD Research and Univ. of Virginia
Xinmiao Zhang, SanDisk
Yingquan Wu, Tidal Systems
Yitzhak (Tsahi) Birk, Technion
Yuval Cassuto, Technion
Zvonimir Bandic, HGST

Start: March 9, 2014
End: March 11, 2014
Venue: UC San Diego