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February 5, 2016

Call For Papers: Workshop on Multicore and Rack-scale Systems

Submitted by Boris Grot

Workshop on Multicore and Rack-scale Systems (MARS)
co-located with EuroSys 2016
London, UK
April 18, 2016

Submission deadline: February 5, 2016
Acceptance Notification: March 9, 2016
Workshop date: April 18, 2016

Present and future multi-core architectures pose a variety of challenges for
system developers: non-cache-coherent memory, heterogeneous processing cores
and the exploitation of novel architectural features, such as systems-on-chip
(SoCs), distributed switching fabrics, silicon photonics, and programmable
hardware. In the near future, we expect to see “rack-scale computers” with
1,000s of cores and terabytes of memory, connected with bandwidth and latency
comparable to today’s smaller-scale NUMA servers.

MaRS 2016 is a forum for researchers in the hardware, networking, storage,
operating systems, language runtime and virtual machine communities to present
their experiences with and discuss innovative designs and implementations for
these new architectures.

Topics of interest include, but are not limited to:
- novel multi-core and rack-scale operating system designs,
- System-on-chip (SoC) and Network-on-chip (NoC) designs,
- runtime systems and programming environments for future hardware,
- low-latency and optical networking,
- OS or runtime support for heterogeneous processing cores,
- non-cache-coherent shared memory,
- scheduling on many-core and rack-scale architectures,
- programmable hardware,
- energy efficiency, fault tolerance and resource management on
future multi-core and rack-scale architectures,
- rack-scale storage,
- performance evaluation of emerging hardware,
- architectural support for systems-level software,
- case studies of system-level software design for current or future
multi-core and rack-scale hardware, and
- applications for and experiences with multi-core and rack-scale

Authors are invited to submit original and unpublished work that exposes a
new problem, advocates a specific solution, or reports on actual experience.
Papers should be submitted using the standard two-column ACM SIG proceedings
or SIG alternate template, and are limited to 5 pages (including everything
except references). Additional pages can be used for references if required.
Papers that violate the submission guidelines may be rejected without
consideration of their merit.

Final papers will be made available to participants electronically at the
meeting, but to facilitate resubmission to more formal venues, no archival
proceedings will be published, and papers will not be sent to the ACM Digital
Library. Authors will be given the option of having their final paper
accessible from the workshop website. Authors of accepted papers will be
invited to give a talk at the workshop.

If you are interested in giving a talk at MaRS 2016, please submit a one-page
abstract instead of a full paper. Authors of accepted papers/talks will also
be invited to present a poster and/or demo in the EuroSys ’16 joint poster
session. Student speakers will be eligible to apply for EuroSys travel grants
to attend.

Boris Grot (University of Edinburgh)
Simon Peter (UT Austin)
Chris Rossbach (VMware and UT Austin)

Program Committee:
Mahesh Balakrishnan (Yale)
Antonio Barbalace (Virginia Tech)
Taesoo Kim (Georgia Tech)
Mark Oskin (University of Washington)
Mark Silberstein (Technion)
Cheng-Chun Tu (VMware)
John Wilkes (Google)
Bernard Wong (University of Waterloo)

Start: February 5, 2016
End: February 5, 2016

February 1, 2016

Call for Proposals: 2016 Fellowships in ACM History

Submitted by Sarita Adve

2016 Fellowships in ACM History

Proposals due: February 1, 2016

ACM will support up to four research projects with awards of up to $4,000
each. Successful candidates may be of any rank, from graduate students
through senior researchers. See the list of past supported projects at

Applicants should send a 2-page CV as well as a 750-word project description
- describes the proposed research;
- identifies specific ACM historical materials, whether traditional archival
collections or online historical materials (oral histories, digitized
conference papers, ACM organizational records, etc.);
- discusses project outcomes (e.g. journal article, book or dissertation
chapter, teaching resource, museum exhibit, website); and
- outlines a timeline for completing the project—generally within 12 months.

In preparing a proposal, applicants should examine the document “ACM Research
Materials” posted at as well as
“Sources for ACM History,” CACM 50 #5 (May 2007): 36-41 Other research materials relating
to ACM may also be used. Applicants should include a letter of endorsement
from their home institution or an external scholarly reference.

Proposals are due by 1 February 2016. Proposals should be submitted as a
single pdf-format document to Notification of
awards will be made within 8 weeks.

The current and past winners of the fellowship can be found at

Start: February 1, 2016
End: February 1, 2016

January 19, 2016

Call for Papers: Workshop on Reconfigurable Computing

Submitted by Kubilay Atasu

10th HiPEAC Workshop on Reconfigurable Computing (WRC’2016)
Prague, Czech Republic
January 19, 2016

The HiPEAC Workshop on Reconfigurable Computing (WRC) provides a forum for
researchers active in domains within the reconfigurable computing area. Its
main focus is on reconfigurable architectures, tools and algorithms that
facilitate reconfigurable systems and applications tailored for reconfigurable
platforms. The WRC’2016 forum intends to provide a substantially different
event from the well-known conferences and workshops related to reconfigurable
computing, by focusing on an informal way to discuss challenges, new ideas,
future trends, and work in progress. For the second time, the Hot Topic of WRC
is High Performance Reconfigurable Computing. We encourage submissions in the
following areas:

- High Performance Reconfigurable Computing: languages and compilation, tools
and design flows, adaptability, virtualization, reliability, and

- Reconfigurable Architectures: novel reconfigurable fabrics, memory design,
low power design, adaptive architectures, networks on chip, fault tolerance.

- Reconfigurable Tools and Technologies: system-level design, HW/SW co-design,
partitioning, mapping, modeling, cost and power optimization, dynamic
reconfiguration, verification, testing, benchmarking.

- Reconfigurable Applications and Algorithms: scientific computing, adaptive
computing, bio-inspired computing, domain-specific computing, multimedia,
bioinformatics, signal processing, rapid prototyping, low-latency.

- Big Data Architectures: Scalable reconfigurable architectures for graph,
text, and multimedia data mining, machine learning, and deep neural networks.

- System Security: cryptographic hardware architectures, security processors,
countermeasures against side-channel attacks, and secure cloud computing.

Selected papers will be invited for publication in a special issue of the
Springer’s Journal of Signal Processing Systems (JSPS), dedicated to WRC’2016.

- Workshop:
- Submissions:
- HiPEAC 2016:

WRC’2016 will accept 8-page full papers and 4-page short papers. Submissions to
WRC’2016 must use the double-column IEEE conference proceedings format. An
online submission page will be available on the WRC’2016 website, which will
include detailed submission guidelines and formatting templates.

- Submission Deadline: November 13, 2015
- Notification E-mails: December 18, 2015
- Camera-Ready Version: January, 8, 2016

General Co-Chairs
Juergen Becker, KIT, Germany
João M. P. Cardoso, University of Porto, Portugal

Program Co-Chairs
Kubilay Atasu, IBM Research – Zurich, Switzerland
Steven Derrien, IRISA/INRIA, University of Rennes 1, France

Web Chair
João Bispo, University of Porto, Portugal

Start: January 19, 2016
End: January 19, 2016
Venue: Prague, Czech Republic (co-located with HiPEAC 2016)

January 18, 2016

Call for Papers: ADAPT’16

Submitted by Grigori Fursin

6th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)
co-located with HiPEAC 2016
Prague, Czech Republic
January 18, 2016

ADAPT is an interdisciplinary workshop to discuss and demonstrate practical and
reproducible techniques, methodology and tools that can help convert existing
or future software and hardware into adaptive, scalable and self-tuning
systems. Such systems should be able to automatically improve their
characteristics (execution time, energy usage, size, accuracy, reliability,
bandwidth, adaptation time and memory usage) depending on an application
and its input, available resources, run-time state of the system, and user

ADAPT topics include but are not limited to machine learning based autotuning,
representative benchmarking, real application self-tuning, automatic
performance modelling, self-tuning compilers, automatic bug detection, run-time
adaptation, automatic fault tolerance, dynamic hardware reconfiguration,
predictive scheduling, new programming models, green data centres, adaptive
embedded devices, reproducible experimentation, and optimization knowledge
sharing. You can check out accepted papers from the past ADAPT workshops at:

Based on positive feedback from last year’s edition, we have decided to use
exclusively our new submission and publication model where authors submit
their articles (and artifacts) directly to open ArXiv, we then open a discussion
thread for each paper on Reddit, and eventually let our PC select the most
appropriate ones for presentation.

We hope you will be able to submit a paper and be part of this new experiment.
See our ADAPT website for motivation and further details.

We encourage earlier submissions before the deadline to allow more time
for open discussions!

- Paper submission deadline: 9 October 2015
- End of public discussions: 30 October 2015
- Author notification: 20 November 2015
- Early fees registration: ~15 December 2015

Christophe Dubach, University of Edinburgh (UK)
Grigori Fursin, dividti (UK) / cTuning Foundation (France)

Start: January 18, 2016
End: January 18, 2016
Venue: Prague, Czech Republic ( co-located with HiPEAC 2016 )

Call for Papers: MULTIPROG 2016

Submitted by Oscar Palomar

9th International Workshop on Programmability and
Architectures for Heterogeneous Multicores (MULTIPROG-2016)

in conjunction with HiPEAC 2016
Prague, Czech Republic
January 18, 2016

Computer manufacturers have embarked on the many-core roadmap, promising to add
more and more cores/hardware threads on their chips. The ever-increasing number
of cores and heterogeneity in architectures has placed new burdens on the
programming community. Software needs to be parallelized and optimized for
accelerators such as GPUs in order to take advantage of the new breed of
multi-/many-core computers. As a result, progress in how to easily harness the
computing power of multi-core architectures is in great demand.

The ninth edition of the MULTIPROG workshop aims to bring together researchers
interested in programming models, runtimes, and computer architecture. The
workshop’s emphasis is on heterogeneous architectures and covers issues such
- How can future parallel programming models improve software productivity?
- How should compilers, runtimes and architectures support programming
models and emerging applications?
- How to design efficient data structures and innovative algorithms?

MULTIPROG is intended for quick publication of early results, work-in-progress,
etc., and is not intended to prevent later publication of extended papers.
Informal proceedings with accepted papers will be made available at the
workshop and online at the workshop’s web page.

Papers are sought on topics including, but not limited to:
1) Multi-core architectures
- Architectural support for compilers/programming models
- Processor (core) architecture and accelerators, in particular GPUs
- Memory system architecture
- Performance, power, temperature, and reliability issues
2) Heterogeneous computing
- Algorithms and data structures for heterogeneous systems
- Applications for heterogeneous computing and real-time graphics
3) Programming models for multi-core architectures
- Language extensions
- Run-time systems
- Compiler optimizations and techniques
4) Benchmarking of multi-/many-core architectures
- Tools for discovering and understanding parallelism
- Tools for understanding performance and debugging
- Case studies and performance evaluation

Full paper submission: Extended until November 6, 2015
Author notification: December 4, 2015

Submissions should not exceed 12 pages and should be formatted according
to the LNCS format for CS Proceedings. This limit includes text, figures,
tables and references. Further submission instructions and templates are
available at the workshop website.

Workshop chairs:
- Miquel Pericàs, Chalmers University of Technology, Sweden
- Vassilis Papaefstathiou, Chalmers University of Technology, Sweden
- Oscar Palomar, Barcelona Supercomputing Center, Spain
- Ferad Zyulkyarov, Barcelona Supercomputing Center, Spain

Steering committee:
- Eduard Ayguade, UPC/Barcelona Supercomputing Center, Spain
- Benedict R. Gaster, Qualcomm, USA
- Lee Howes, Qualcomm, USA,
- Per Stenstrom, Chalmers University of Technology, Sweden
- Osman Unsal, Barcelona Supercomputing Center, Spain

Program committee:
- Abdelhalim Amer, Argonne National Lab, USA
- Ali Jannesari, TU Darmstadt, Germany
- Avi Mendelson, Technion, Israel
- Christos Kotselidis, University of Manchester, UK
- Daniel Goodman, Oracle, UK
- Dong Ping Zhang, AMD, USA
- Håkan Grahn, Blekinge TH, Sweden
- Hans Vandierendonck, Queen’s University Belfast, UK
- Kenjiro Taura, University of Tokyo, Japan
- Luigi Nardi, Imperial College London, UK
- Naoya Maruyama, RIKEN AICS, Japan
- Oscar Plata, University of Malaga, Spain
- Pedro Trancoso, University of Cyprus, Cyprus
- Polyvios Pratikakis, FORTH-ICS, Greece
- Roberto Gioiosa, PNNL, USA
- Ruben Titos, BSC, Spain
- Sasa Tomic, IBM Research, Switzerland
- Simon McIntosh-Smith, University of Bristol, UK
- Timothy G. Mattson, Intel, USA
- Trevor E. Carlson, Uppsala University, Sweden

Start: January 18, 2016
End: January 18, 2016
Venue: Prague, Czech Republic

Call for Participation: HiPEAC 2016 Conference

Submitted by Daniel A. Jiménez

11th International Conference on High Performance
and Embedded Architecture and Compilation (HiPEAC)

Prague, Czech Republic
January 18-20, 2016

The HiPEAC conference is the premier European forum for experts in computer
architecture, programming models, compilers and operating systems for embedded
and general-purpose systems. This year’s highlights include:
- 3 Keynotes
- Paper Track
- 31 Workshops
- 8 Tutorials

More information:

Start: January 18, 2016
End: January 20, 2016
Venue: Prague, Czech Republic

January 15, 2016

Call for Participation: ACM Workshop on Oral History

Submitted by Sarita Adve

ACM Workshop on Oral History
University of North Carolina at Chapel Hill, USA
Friday, May 12-13, 2016

Project proposal deadline: Friday, January 15, 2016

Applications are invited to a 1.5 day oral history workshop, to be held
Thursday and Friday, May 12-13, 2016 at the University of North Carolina at
Chapel Hill, North Carolina. For each successful application, one person’s
expenses for workshop travel, lodging, and meals will be paid by the ACM
History Committee. The workshop will be led by Mary Marshall Clark, director
of the Columbia Center for Oral History (CCOH); see

Who should attend?
ACM members and others who are planning or actually doing oral history
projects. The audience is people who are performing interviews for oral
histories, or thinking about doing so. The workshop should be of special
interest to ACM officers and staff, SIG leaders, historically minded ACM
members, and others working on oral history projects. Priority will be given
to ACM members and members of other national computer societies affiliated
with the ACM, but some places have been reserved for non-affiliated
individuals who are actively engaged in oral history projects.

Workshop topics and activities include:
- developing an oral history program;
- presentation and training on oral history processes and principles;
- hands-on exercises interviewing each other;
- analysis and discussion of the exercises;
- how to analyze results, findings and evaluate an oral history project;
- practical considerations: lessons learned and best practices; and
- ample networking time, including lunches and the workshop dinner.
Participants will leave with a “tool kit” of practical, useful procedures as
well as insight into professional oral history practices.

Small workshop format will permit maximum hands-on experience and personal
interaction. We are planning for 16 participants.

The ACM History Committee will fund travel, hotel and meals for accepted
invitees. Applicants should send a 2-page CV as well as a 250-word proposed
project and/or oral history interest description that
(1) explains the significance of a proposed oral history project (if
applicable), potential uses of the techniques learned, and its importance;
(2) affirms your willingness to participate fully in the 1.5 day agenda.

Project proposals are due by Friday, January 15, 2016. Proposals should be
submitted as a single PDF document to Notification
of project acceptance will be made within eight weeks.

Questions about the workshop or requests for clarification may be directed, at
any time, to

Start: January 15, 2016
End: January 15, 2016

December 30, 2015

Call for Proposals: ISPASS 2016 Workshops and Tutorials

Submitted by Stefanos Kaxiras

Workshops and Tutorials at ISPASS
Uppsala, Sweden
April 17, 2016


Submission deadline: Wednesday, December 30, 2015
Notification: Friday, January 8, 2016

Tutorial proposals are solicited for ISPASS-2016, Uppsala, Sweden.
Tutorials will be held on Apr 17, 2016.

Proposals for both half- and full-day tutorials are solicited on any
topic that is relevant to the ISPASS audience. Tutorials that focus on
workload characterization and analysis tools and techniques that enable
research across layers of the computational stack are strongly encouraged.

In previous years, tutorials seeking to achieve any of the following
goals have been particularly successful:
- Describe an important piece of research/experimental infrastructure.
- Educate the community on an emerging topic.

Proposals should provide the following information:
- Title of the tutorial
- Presenter(s) and contact information.
- Proposed duration (full day, half day).
- 1-2 paragraph abstract suitable for tutorial publicity.
- 1 paragraph biography per presenter suitable for tutorial publicity.
- Short description (for evaluation). This should include:
1) Tutorial scope and objectives,
2) Topics to be covered,
3) Target audience,
4) If the tutorial has been held previously, the location (i.e.,
conference), date, and number of attendees.

Proposals should take the form of a PDF document, and be submitted via
e-mail to Stefanos Kaxiras (, with the subject
“ISPASS 2016 Tutorial Proposal”. Submissions will be acknowledged via


Submission deadline: Wednesday, December 30, 2015
Notification: Friday, January 8, 2016

Workshop proposals are solicited for ISPASS-2016, Uppsala, Sweden.
Workshops will be held on Apr 17, 2016.

Proposals related to power/performance analysis and workload
characterization as it relates to computer architecture, operating
systems, programming languages/compilers in current and emerging areas
such as datacenters and cloud computing, systems based on non-volatile
memory technologies, mobile technologies, large scale data analysis,
smart infrastructure, and extreme scale computing are encouraged.

Proposals should provide the following information:
- Title of the workshop
- Organizers and their affiliations
- Sample call for papers
- Duration – Half-Day or Full Day
- Preferred Day – Saturday or Sunday
- If the workshop was previously held, the location (conference), date,
and number of attendees

Proposals should take the form of a PDF document, and be submitted via
e-mail to Stefanos Kaxiras (, with the subject
“ISPASS 2016 Workshop Proposal”. Submissions will be acknowledged via

Start: December 30, 2015
End: December 30, 2015

December 21, 2015

Call for Papers: iNIS 2015

Submitted by Saraju Mohanty

1st IEEE International Symposium on Nanoelectronic and Information Systems
Indore, India
December 21-23, 2015

iNIS 2015 is to provide a platform for both hardware and software
researchers to interact under one umbrella for further development of
efficient and secure information processing technologies. Efficient and
secure data sensing, storage and processing play pivotal roles in the
current information age. State-of-the-art nanoelectronic technology
based hardware systems cater to the needs of efficient sensing, storage,
and computing. At the same time, efficient algorithms and software used
for faster analysis and retrieval of desired information are becoming
increasingly important. Big data which are large, complex data sets, are
now an integral part of the Internet world. Storing and processing needs
of the enormous amount of structured and unstructured data are getting
increasingly challenging. At the same time, Internet of Things (IoT) and
Cyber-Physical Systems (CPS) have been evolving with the simultaneous
development of hardware and software. The performance and efficiency of
the present as well as the future generation of computing and
information processing systems are largely dependent upon advances in
both hardware and software.

iNIS 2015 is sponsored by IEEE-CS and has technical co-sponsorship of
IEEE-CAS. The iNIS brings together leading scientists and researchers
from academia and industry. Contributions are sought in (but are not
limited to) the following areas: 1) Nanoelectronic VLSI and Sensor
Systems (NVS) 2) Energy-Efficient, Reliable VLSI Systems (ERS) 3)
Hardware/Software Solutions for Big Data (SBD) 4) Hardware/Software for
Internet of Things (IOT) 5) Hardware for Secure Information Processing
(SIP) 6) Cyber Physical Systems and Social Networks (CSN) Detailed
description of the tracks is provided in the iNIS website.

iNIS 2015 proceedings will be published by IEEE-CS. Authors are invited to
submit full-length (6 pages maximum), original, unpublished research
papers with an abstract (200 words maximum). For blind review, author
informations should be omitted from the main document. Papers violating
length and blind-review criteria will be excluded from the review process.
Previously published papers or papers currently under review elsewhere
should not be submitted and will not be considered for publication.
Authors should submit their original work of maximum 6 pages using
double-column IEEE-CS conference format-template
A selected papers from iNIS 2015 will be invited for submission
to a peer-reviewed journal special issue based on reviewer feedback and
quality of conference presentation.

Paper Submission Site:

Submission Deadline: July 20, 2015
Acceptance Notification: September 14, 2015
Submission of Final Version: October 12, 2015

Special Sessions and Panels: iNIS 2015 will consider proposals for
special sessions as well as panels. Special session and panel proposals
can be submitted to the special session chairs by email:
and The submission deadline is the
same as specified for the regular paper submissions.

Student Research Symposium: iNIS 2015 will host a student research
symposium. A single 2-page pdf file for student research symposium paper
can be submitted to the student symposium chairs by email: and The submission deadline
is the same as specified for the regular paper submissions. All the
accepted student research symposium papers will be published in the
conference souvenir. A selected top 10 of these will be published in the
iNIS 2015 proceedings.

General Chairs:
Saraju Mohanty, University of North Texas, USA
Dhruva Ghai, Oriental University, India

Program Chairs:
Ashok Srivastava, Louisiana State University, USA
Shiyan Hu, Michigan Technological University, USA
Prasun Ghosal, IIEST, Shibpur, India

Publication Chair:
Himanshu Thapliyal, University of Kentucky, USA

Web Chair:
Mike Borowczak, Erebus Labs & Consulting LLC, USA

Publicity Chairs:
Sudeep Pasricha, Colorado State University, USA
Aida Todri-Sanial, CNRS-LIRMM, France
Shanq-Jang Ruan, National Taiwan University of Science & Technology
Vaskar Raychoudhury, Indian Institute of Technology Roorkee, India

Local Arrangement Chair:
Rishab Pareek, Oriental University, India

Special Session Chairs:
Xin Li, Carnegie Mellon University, USA
Siva Yellampalli, UTL Technologies, India

Student Symposium Chairs:
Anirban Sengupta, Indian Institute of Technology Indore, India
Bishnu P. Das, Indian Institute of Technology Roorkee, India

Finance Chair:
Garima Ghai, Oriental University, India

Registration Chair:
Hare Ram Singh, Oriental University, India

Technical Program Committee:
The complete list is being made available in the website.
Following are the track chairs.

Nanoelectronic VLSI and Sensor Systems (NVS):
Jawar Singh, IIITDM, Jabalpur, India
Yiyu Shi, Missouri University of Science and Technology, USA

Energy-Efficient, Reliable VLSI Systems (ERS):
Manisha Pattanaik, ABV-IIITM, Gwalior, India
Saket Srivastava, University of Lincoln, UK

Hardware/Software Solutions for Big Data (SBD):
Theocharis Theocharides, University of Cyprus
Rajiv Ranjan, Commonwealth Scientific and Industrial Research Organization

Hardware/Software for Internet of Things (IOT):
Vaskar Raychoudhury, Indian Institute of Technology Roorkee, India
Gustavo Marfia, University of Bologna, Italy, Visiting Scholar, UCLA

Hardware for Secure Information Processing (SIP):
Kailash Chandra Ray, Indian Institute of Technology Patna, India
Kamalakanta Mahapatra, National Institute of Technology, Rourkela, India

Cyber Physical Systems and Social Networks (CSN):
Qi Zhu, University of California, Riverside, USA
Madhavi Ganapathiraju, University of Pittsburgh, USA

Steering Committee:
(1) Saraju Mohanty, University of North Texas, USA (Chair)
(2) Prasun Ghosal, IIEST, Shibpur, India (Vice Chair)
(3) Dhruva Ghai, Oriental University, India (Vice Chair)
(4) Aida Todri-Sanial, CNRS-LIRMM, France
(5) Ashok Srivastava, Louisiana State University, USA
(6) Helen Li, University of Pittsburg, USA
(7) Himanshu Thapliyal, University of Kentucky, USA
(8) Jia Di, University of Arkansas, USA
(9) Nabanita Das, Indian Statistical Institute, India
(10) Sudeep Pasricha, Colorado State University, USA
(11) Xin Li, Carnegie Mellon University, USA

Start: December 21, 2015
End: December 23, 2015
Venue: Indore, India

December 14, 2015

Call for Papers: Workshop on Low-Power Dependable Computing

Submitted by Abdullah Muzahid

2nd Workshop on Low-Power Dependable Computing (LPDC)
in conjunction with International Green and Sustainable Computing Conference (IGSC)
Las Vegas, Nevada, USA
Dec 14-16, 2015

Submission Deadline: Sept. 15, 2015

Dependable computing is normally achieved through various redundancy (such
as modular, temporal and/or information) techniques at different levels (for
instance, circuit, architecture, runtime, operating systems and software) in
the systems. With the scaled technology size and miniaturization of computing
systems, faults will become more common and it is imperative for most modern
computing systems to deploy various fault-tolerance techniques. On the other
hand, redundancy based fault-tolerance generally has energy implications, which
warrants careful consideration since energy has been promoted to be the
first-class system resource recently.

This workshop aims at establishing a forum for practitioners and researchers
from both industry and academia who work on different aspects of fault
tolerance and system energy efficiency to exchange ideas on how to achieve
low-power dependable computing. To cover a broad range of research related to
energy efficiency and dependable computing, the workshop will consider various
levels (from circuits to software), components (from memory to computation) and
systems (from battery-powered embedded systems to large scale reliable

The topics of interest include (but are not limited to) the following:
- Novel energy-efficient redundant circuit design
- Novel energy-efficient fault-tolerance architecture
- Compilation techniques for redundancy and low-power
- Runtime management for energy-efficiency and fault tolerance
- Scheduling algorithms for energy-efficiency and fault tolerance
- Energy-efficiency tradeoffs for different fault-tolerance techniques
- Low-power reliable memory and storage systems
- Low-power and reliable on-chip communications
- Case study on low-power dependable systems

The workshop invites authors to submit papers in the above mentioned areas that
describe original and unpublished work that are not concurrently under review

The papers submitted to this workshop is limited to be six (6) single-spaced,
double-column pages (with IEEE Computer Society Proceedings Manuscripts style:
11-point fonts and 8.5 x 11 inch), which should include everything (e.g.,
abstract, research description, figures, tables, and references).

All submissions will be reviewed by the program committee. Once a submission
is accepted, at least one author needs to register the conference following the
instructions on IGSC webpage (, and attends the
conference to present the work. Each accepted workshop paper will require a
full IGSC registration at the IEEE member or at the non-member rate (NOT
student rate).

Accepted papers will be published in the workshop proceedings and included in
the IEEE Xplore Digital Library.

Please submit your papers through the following link with EasyChair:

Submission deadline: Aug. 28, 2015
Notification date: Sep. 30, 2015
Final paper due: Oct. 15, 2015

Workshop Chairs:
Tam Chantem (Utah State University, USA)
Dakai Zhu (University of Texas at San Antonio, USA)

Technical Program Committee:
Jian-Jia Chen (TU Dortmund, Germany)
Steven Drager (Air Force Research Lab, USA)
Petru Eles (Linköping University, Sweden)
Alireza Ejlali (Sharif University of Technology, Iran)
Nathan Fisher (Wayne State University, USA)
Yifeng Guo (NetApp. Inc., USA)
Song Han (University of Connecticut, USA)
Houman Homayoun (George Mason University, USA)
Cong Liu (University of Texas at Dallas, USA)
Muhammad Shafique (Karlsruhe Institute of Technology, Germany)
Kaijie Wu (Chongqing University, China)
Xuan Qi (Oracle, USA)
Jun Yi (Amazon, USA)
Zhao Zhang (Iowa State University, USA)
Baoxian Zhao (MicroStrategy Inc, USA)

Start: December 14, 2015
End: December 16, 2015
Venue: Las Vegas