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November 1, 2014

Call for Papers: IEEE Computer Special Issue on Irregular Applications

Submitted by Antonino Tumeo
http://www.computer.org/portal/web/computingnow/cocfp8

IEEE Computer Special issue on Irregular Applications

Full paper submission deadline: 1 February 2015
Publication date: August 2015
 

The broad class of irregular applications is characterized by unpredictable
memory access patterns, control structures, and/or network transfers. These
applications typically use pointers or linked list–based data structures
such as graphs, unbalanced trees, and unstructured grids. Their complex
behavior makes it difficult to fully exploit their significant latent
parallelism. In addition to performance concerns, dataset size presents a
challenge in emerging irregular applications because they often operate
on massive amounts of unstructured heterogeneous data that is
usually difficult to partition.

Current high-performance architectures rely on data locality as well as regular
computations, structured data, and easily partitionable datasets; consequently,
they do not cope well with the computational and data requirements of
irregular applications. Furthermore, scaling on current supercomputing machines
is problematic, because of limits associated with fine-grained communication and
synchronization. These applications exist in well established and emerging
fields such as: CAD; bioinformatics; semantic graph databases; machine
learning; analysis of social, transportation, communication, and other types of
networks; and computer security. Addressing the many system-related issues
posed by irregular applications on current and future system architectures
is critical to solving future scientific challenges.

This special issue seeks to explore solutions for supporting the efficient
design, development, and execution of irregular applications. Practical
and theoretical topics of interest include but are not limited to:

- Micro- and system-level architectures;
- Network and memory architectures;
- Many-core, hybrid, heterogeneous, and custom architectures
(tiled processors, GPUs, FPGAs);
- Modeling, evaluation, and characterization of architectures for
memory-intensive and irregular applications;
- Innovative algorithmic techniques;
- Combinatorial (graph) algorithms and their applications;
- Languages and programming models;
- Library and runtime support;
- Compiler and analysis techniques; and
- Case studies of irregular applications (for example,
semantic graph databases, data mining, security, bioinformatics).

Articles focused on approaches that span multiple levels of the stack
— ideally providing application-specific, end-to‐end solutions — are of
particular interest. Articles should provide context for their contributions
with respect to existing solutions as well as potential commercial impact.

GUEST EDITORS
Antonino Tumeo (antonino.tumeo@pnnl.gov), PNNL
John Feo (john.feo@pnnl.gov), PNNL

SUBMISSION GUIDELINES
Paper submissions are due 1 February 2015.

Only technical articles describing previously unpublished, original,
state-of-the-art research, and not currently under review by a conference
or a journal will be considered. Articles should be understandable to a
broad audience of computer science and engineering professionals,
avoiding a focus on theory, mathematics, jargon, and abstract concepts.
All manuscripts are subject to peer review on both technical merit and
relevance to Computer’s readership. Accepted papers will be professionally
edited for content and style.

For author guidelines and information on how to submit a manuscript,
visit http://www.computer.org/portal/web/peerreviewmagazines/computer.

Start: November 1, 2014
End: February 1, 2015

Call for Papers: IJPP Special Issue on Workload Optimized Systems

Submitted by Parijat Dube
http://www.springer.com/10766

Springer International Journal of Parallel Programming (IJPP)
Special Issue on Workload Optimized Systems

 

The slowdown in Moore’s Law makes it increasingly important to optimize
systems around specific workloads. Such workload optimized systems have
hardware and/or software specifically designed to run well for a particular
workload or workload class. Such systems include, but are not limited to
traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory
accelerators, I/O accelerators, hybrid systems, and IT appliances. This
workload optimized system approach contrasts to the broad general purpose
direction of computing over many decades. The workload optimized systems
approach is growing in importance, as we see in systems from cellphones to
tablets to routers to game machines to Top500 supercomputers, and IT
appliances such as IBM’s DataPower and Netezza, and Oracle’s Exadata. The
goal of this special issue is to foster awareness in industry and academic
community on workload optimized systems and to expose cross hw/sw stack
unique systems and software research challenges associated with such
systems. All submitted papers are subject to the same review process as those
papers accepted for publication in the regular issues. The special issue seeks
original papers on a range of topics related to workload optimized systems
including, but not limited to

- GPUs, FPGAs, ASIC Accelerators
- Memory and I/O accelerators
- Network accelerators
- Storage optimized systems
- System level accelerators
- IT Appliances
- Systems in specific domains like analytics, cloud, cognitive, mobile etc.
- Converged/Hybrid/Heterogeneous systems
- Cross hardware/software stack design and optimization
- Programming models for workload optimized systems
- Measurements and Experimentation
- Workload characterization and profiling
- Performance modeling and optimization
- Workload scheduling and orchestration
- Runtime management systems
- Industrial Experiences

IMPORTANT DATES
Manuscript due: March 27, 2015
First decision notification: June 5, 2015
Revision due: July 10, 2015
Final decision notification: August 14, 2015
Final version due: September 11, 2015

SUBMISSIONS
Authors are encouraged to submit high-quality, original work that
has neither appeared in, nor is under consideration by, other
journals. All papers will be reviewed following standard reviewing
procedures for the Journal.
Papers must be prepared in accordance with the Journal guidelines:

http://www.springer.com/10766.

Manuscripts must be submitted to: http://IJPP.edmgr.com.
Choose “S.I.: Workload Optimized Systems” as the article type.

GUEST EDITORS
Erik Altman, IBM Research, Yorktown Heights, NY. ealtman@us.ibm.com
Parijat Dube, IBM Research, Yorktown Heights, NY. pdube@us.ibm.com

 

Start: November 1, 2014
End: October 1, 2015

January 31, 2015

Call for Papers: CCPE Journal Special Issue on Heterogeneous and Unconventional Cluster Architectures and Applications

Submitted by Holger Froening
http://www.hucaa-workshop.org/ccpe2015

Journal of Concurrency and Computation: Practice and Experience
Special Issue on Heterogeneous and Unconventional Cluster Architectures
and Applications

Submission deadline: Jan 31, 2015
 

This special issue gears to gather recent work on heterogeneous and
unconventional cluster architectures and applications, which might have
a big impact on future cluster architectures. This includes any cluster
architecture that is not based on the usual commodity components and
therefore makes use of some special hard- or software elements, or that
is used for very special and unconventional applications. Examples
include GPUs and other accelerators (Intel MIC/Xeon Phi, FPGA) used at
cluster level. Other examples include run-time management,
virtualization, in-memory storage, hard- and software interactions,
databases, and device-to-device communication. We are in particular
encouraging work on disruptive approaches, which may show inferior
performance today but can already point out their performance
potential. The broad scope of the special issue facilitates submissions
on unconventional uses of hardware or software, gearing to gather ideas
that are coming to life now and not limiting them except for their
context: clusters. Also, these proposals may rather be reflective of a
broader industry trend.

We are seeking new proposals presented from a holistic perspective. In
this regard, one of the aims of the special issue is anticipating the
evolution of clusters, instead of just presenting new work carried out
in the traditional cluster areas usually addressed in other journals
and conferences.

TOPICS OF INTEREST
Topics of interest include any heterogeneous or unconventional cluster
architecture or application. Examples include, but are not limited to:

- Clustered GPUs, Xeon Phis or other accelerators
- Runtimes, resource management and scheduling for heterogeneous
clusters
- Communication methods for distributed or clustered accelerators
- Energy-aware data movement techniques
- New industry and technology trends and their potential impact
- High-performance, data-intensive, and power-aware computing
- Application-specific cluster, datacenter, and high performance
cloud architectures
- Emerging programming paradigms for parallel heterogeneous computing
- Software cluster-level virtualization for consolidation purposes
- Hardware techniques for resource aggregation
- Management layers for large-scale systems
- New uses of GPUs, FPGAs, and other specialized hardware
- Dedicated support for novel parallel programming paradigms like PGAS
or MapReduce

IMPORTANT DATES
- Submission deadline: Jan 31, 2015
- Notification to authors: April 15, 2015
- Revision Due: May 15, 2015
- Final decision due: June 15, 2015
- Final manuscript due: July 15, 2015
- Publication: 4th Quarter of 2015 (estimated)

INSTRUCTIONS FOR SUBMISSION
Manuscripts must not have been previously published nor currently under
review by other journals or conferences. If prior work was published in
a conference, the submitted manuscript should include a substantial
extension of at least 30% novel contributions. In this case, authors
are also required to submit their published conference articles and a
summary document explaining the enhancements made in the journal
version.

GUEST EDITORS
Federico Silla, Technical University of Valencia, Spain,
fsilla@disca.upv.es
Holger Fröning, University of Heidelberg, Germany,
holger.froening@ziti.uni-heidelberg.de

ADDITIONAL INFORMATION

http://www.hucaa-workshop.org/ccpe2015

http://www.cc-pe.net/journalinfo/issues/2015.html#HUCAA2015

Start: January 31, 2015
End: January 31, 2015

February 7, 2015

Call for Papers: CGO 2015

Submitted by Aaron Smith
http://www.cgo.org
2015 IEEE/ACM International Symposium on Code Generation and Optimization
February 2015 – San Francisco Bay Area

http://cgo.org/cgo2015/

The International Symposium on Code Generation and Optimization (CGO) provides
a premier venue to bring together researchers and practitioners working at the
interface of hardware and software on a wide range of optimization and code
generation techniques and related issues. The conference spans the spectrum
from purely static to fully dynamic approaches, including techniques ranging
from pure software-based methods to architectural features and support.

Original contributions are solicited on, but not limited to, the following
topics:

Code Generation and Optimization
- Efficient execution of dynamically typed and higher-level languages
- Optimization and code generation for emerging programming models, platforms
- Optimizations for energy efficiency
- Profile-guided, feedback-directed, and machine learning based optimization
- Compiler abstractions and intermediate representations

Static and Dynamic Analysis
- Profiling and instrumentation for power, memory, throughput or latency
- Efficient profiling and instrumentation techniques
- Program characterization methods
- Profile-guided optimization
- Novel and efficient tools for power, performance analysis, debugging and
testing

Optimization for Parallelism
- Runtime systems for parallelism & heterogeneity
- Optimizations for heterogeneous or specialized parallel targets, e.g. GPUs
- Compiler-driven data distribution and synchronization
- Thread extraction

OS, Architecture and Runtime Support
- Architectural support for improved profiling, optimization and code
generation
- Integrated system design (HW/OS/VM/SW)
- Memory management and garbage collection

Security and Reliability
- Code analysis and transformations to address security or reliability concerns

Practical Experience
- Deployed dynamic and static compiler and runtime systems for general purpose,
embedded system and Cloud/HPC platforms

Applications of above in emerging technology areas, such as
- Web programming environments, application runtimes, optimizations
- SOCs, heterogeneous platforms hardware/software co-design, analysis and
optimization

CGO 2015 is co-located with HPCA 2015 and PPoPP 2015 this year. Authors should
carefully consider the difference in focus of the conferences when deciding
where to submit a paper.

CGO will make the proceedings freely available via the ACM DL platform for up
to two weeks before and two weeks after the event. This option will facilitate
easy access to the proceedings by conference attendees, and it will also enable
the community at large to experience the excitement of learning about the
latest developments being presented in the period surrounding the event itself.

Important Dates
Abstract Submission: August 29, 2014
Paper Submission: September 5, 2014
Author Response Period: October 21-23, 2014
Notification to Authors: November 3, 2014

General Chairs
Kunle Olukotun, Stanford University
Aaron Smith, Microsoft Research

Program Chairs
Robert Hundt, Google
Jason Mars, University of Michigan

Program Committee
Saman Amarsinghe, MIT
Derek Bruening, Google
Simone Campanoni, Harvard
Mike Carbin, MIT
John Cavazos, U. of Delaware
Albert Cohen, INRIA
Jack Davidson, UVA
Gregory Diamos, NVidia
Evelyn Duesterwald, IBM
Xiaobing Feng, ICT Chinese Academy
Mike Ferdman, Stony Brook University
Ravi Iyer, Intel
Alexandra Jimborean, Uppsala University
Naveen Kumar, Google
Calvin Lin, UT Austin
Scott Mahlke, Michigan
Kathryn S McKinley, Microsoft
Abdullah Muzahid, UT San Antonio
Chris J Newburn, Intel
Michael O’Boyle, Edinburgh
David Padua, UIUC
Depei Qian, Xi’an Jiaotong University
Lawrence Rauchwerger, Texas A&M University
Vijay Janapa Reddi, The University of Texas at Austin
Behnam Robatmili, Qualcomm Research
Norm Rubin, NVidia
Jennifer Sartor, Ghent
Xipeng Shen, William and Mary
Lingjia Tang, Michigan
Mike Taylor, UCSD
Mohit Tiwari, UT Austin
James M. Tuck, NCSU
Cheng Wang, Intel Labs
Chenggang Wu, Chinese Academy of Sciences
Jingyue Wu, Google
Eddy Zhang, Rutgers
Ben Zorn, Microsoft Research

Workshop and Tutorials Chair
Christophe Dubach, University of Edinburgh

Finance Chair
Vijay Janapa Reddi, The University of Texas at Austin

Local Chairs
Jose Renau, University of California, Santa Cruz
Behnam Robatmili, Qualcomm Research

Publications Chair
Fabrice Rastello, INRIA

Students Chair
Jennifer Sartor, Ghent University

Sponsors Chair
Ben Zorn, Microsoft Research

Registration Chair
Lingjia Tang, University of Michigan

Submission Chairs
Michael Laurenzano, University of Michigan
Yunqi Zhang, University of Michigan

Web Chair
Mehrzad Samadi, University of Michigan

Steering Committee
Kim Hazelwood, Google
Robert Hundt, Google
Scott Mahlke, University of Michigan
Kathryn S McKinley, Microsoft
Kunle Olukotun, Stanford University
Vijay Janapa Reddi, The University of Texas at Austin
Olivier Temam, INRIA (Chair)

Start: February 7, 2015
End: February 11, 2015
Venue: San Francisco Bay Area

Call for Papers: HPCA 2015

Submitted by Lingjia Tang
http://darksilicon.org/hpca
The 21st IEEE International Symposium on High Performance Computer Architecture

Feb 2015 — Bay Area, CA
[HPCA 2015 will be co-located with CGO-2015 and PPoPP-2015]

The IEEE International Symposium on High Performance Computer Architecture
(HPCA) provides a high-quality forum for scientists and engineers to
present their latest research findings in this rapidly changing field.
Authors are invited to submit papers on all aspects of high-performance
computer architecture. Topics of interest include, but are not limited to:

• Processor, cache, and memory architectures
• Parallel computer architectures
• Multicore architectures
• Impact of technology on architecture
• Power-efficient architectures and techniques
• Dependable/secure architectures
• High-performance I/O systems
• Embedded and reconfigurable architectures
• Interconnect and network interface architectures
• Architectures for cloud-based HPC and data centers
• Innovative hardware/software trade-offs
• Impact of compilers and system software on architecture
• Performance modeling and evaluation
• Architectures for emerging technology and applications

Regular papers.
Authors should submit an abstract by Friday, September 5, 2014, 11:59 PM CET.
They should submit the full version of the paper by
Friday, September 12, 2014, 11:59 PM CET. No extensions will be granted.
The full version should be a PDF file that follows the submission guidelines
available at the conference website. Papers should be submitted for
double-blind review. We anticipate selecting a Best Paper award.
All papers will be evaluated based on their novelty, fundamental insight,
experimental evaluation, and potential for long-term impact; new-idea papers
are encouraged. Submission issues should be directed to the
program chair at Lieven.Eeckhout@UGent.be.

Industry track papers.
HPCA has the tradition of hosting an Industrial Paper Session presenting
novel results and insights from industry. Industry track papers go through
a separate review process. Questions about the industry track should be
directed to the industrial session chair at Sudhanva.Gurumurthi@amd.com.

Accepted regular and industry track papers will be published in the
conference proceedings distributed to conference attendees.
Papers will also be uploaded to IEEE Xplore.

Workshops and tutorials.
Workshop and tutorial submissions should be directed to the
workshop and tutorial chair at sampson@cse.psu.edu.

Important dates
Regular papers
• Abstract deadline: September 5, 2014, 11:59 PM CET
• Paper deadline: September 12, 2014, 11:59 PM CET
• Rebuttal: October 27-29, 2014
• Notification of paper outcome: November 10, 2014
• Final reviews and comments sent out: November 13, 2014
Industry track papers
• Paper deadline: October 1, 2014, 11:59 PM CET
• Author notification: November 10, 2014
Workshops and tutorials
• Workshop and tutorial proposals due: October 3, 2014

Sponsored by the IEEE Computer Society TC on Computer Architecture (TCCA).

General Chair
Michael Taylor, UCSD

Program Chair
Lieven Eeckhout, Ghent University

Program Committee
Erik Altman, IBM
Abhishek Bhattacharjee, Rutgers
David Black-Schaffer, Uppsala
Pradip Bose, IBM
David Brooks, Harvard
Fred Chong, UCSB
John Demme, Columbia
Natalie Enright Jerger, Toronto
Hadi Esmaeilzadeh, GATech
Stijn Eyerman, Ghent
Babak Falsafi, EPFL
Paolo Faraboschi, HP
Wilson Fung, UBC
Antonio Gonzalez, Intel/UPC
Boris Grot, Edinburgh
Engin Ipek, Rochester
Aamer Jaleel, Intel
John Kim, KAIST
James Laudon, Google
Benjamin Lee, Duke
Mikko Lipasti, Wisconsin
Gabriel Loh, AMD
José Martinez, Cornell
Jason Mars, Michigan
Margaret Martonosi, Princeton
Andreas Moshovos, Toronto
Onur Mutlu, CMU
Satish Narayanasamy, Michigan
Mike O’Connor, NVidia
Moin Qureshi, GATech
Ravi Rajwar, Intel
Vijay Janapa Reddi, UTAustin
Daniel Sanchez, MIT
Jack Sampson, Penn State
Arrvindh Shriraman, Simon Fraser
André Seznec, INRIA
Dan Sorin, Duke
Viji Srinivasan, IBM
Samantika Subramaniam, Intel
Mohit Tiwari, UTAustin
Josep Torrellas, UIUC
Dean Tullsen, UCSD
Tom Wenisch, Michigan
Lixin Zhang, ICT

Industrial Session Committee Chair
Sudhanva Gurumurthi, AMD Research/University of Virginia

Finance Chair
Reese Nguyen, Keker & Van Nest LLP

Local Arrangements Chairs
José Renau, UC Santa Cruz
Behnam Robatmili, Qualcomm

Publicity Chair
Lingjia Tang, Michigan

Publications Chair
Henry Hoffmann, University of Chicago

Registration Chair
Joe Devietti, U Penn

Workshop/Tutorial Chair
Jack Sampson, Penn State

Student Travel Grants Chair
Christopher Batten, Cornell

Web Chair
Jason Mars, Michigan

Steering Committee
Laxmi Bhuyan, University of California, Riverside
Natalie Enright Jerger, University of Toronto
David Kaeli, Northeastern University
Tao Li, University of Florida
Yale Patt, University of Texas at Austin
Josep Torrellas, University of Illinois, Urbana-Champaign
Dean Tullsen, University of California, San Diego
Lixin Zhang, ICT/Chinese Academy of Sciences

Start: February 7, 2015
End: February 11, 2015

Call for Workshops: CGO 2015

Submitted by Christophe Dubach
http://www.cgo.org/
CGO 2015

*** Call for Workshops and Tutorials ***

February 7-11, 2015 – San Francisco Bay Area

http://www.cgo.org/

The 2015 ACM/IEEE International Symposium on Code Generation and
Optimization (CGO), located in San Francisco Bay Area, is looking for proposals
for co-located workshops and tutorials that will run before the main
conference. Please see the CGO web site for more details: http://www.cgo.org

The deadline for submitting a workshop or tutorial proposal is
September 15, 2014 but interested parties are encouraged to contact the
workshops and tutorial chair as soon as possible.

==== Proposal Submission Guidelines ====

If you wish to organize a workshop or tutorial (1/2 or 1 day), please e-mail a
proposal to christophe.dubach@ed.ac.uk with the following details :

* Title of the workshop or tutorial
* Organizers and their affiliations
* Brief description of topics to be covered
* Expected duration; i.e., 1/2 day or full day
* Expected attendance (stats from previous years are ideal)
* URL of workshop/tutorial information (if available)
* Any special requirements the workshop or tutorial may have

One free registration will be made available per workshop/tutorial accepted
(could be used for one of the organizers or for one invited speaker)

==== Important Dates ====

* Proposal Submission : September 15, 2014
* Notification : October 1, 2014
* Workshop/Tutorial date : February 7-8, 2015

==== Workshop and Tutorial Chair ====

Christophe Dubach, christophe.dubach@ed.ac.uk

Start: February 7, 2015
End: February 11, 2015
Venue: San Francisco Bay Area

Call for Papers: PPoPP 2015

Submitted by Antoniu Pop
http://ppopp15.soe.ucsc.edu/
20th ACM SIGPLAN Symposium on Principles and Practice of Parallel
Programming (PPoPP’15)
February 2015 – San Francisco Bay Area

PPoPP is the forum for leading work on all aspects of parallel
programming, including foundational and theoretical aspects,
techniques, languages, compilers, runtime systems, tools, and
practical experiences. In the context of the symposium, “parallel
programming” encompasses work on concurrent and parallel systems
(multicore, multithreaded, heterogeneous, clustered systems,
distributed systems, grids, clouds, and large scale machines). Given
the rise of parallel architectures into the consumer market (desktops,
laptops, and mobile devices), PPoPP is particularly interested in work
that addresses new parallel workloads, techniques, and tools that
attempt to improve the productivity of parallel programming, and work
towards improved synergy with such emerging architectures. Specific
topics of interest include (but are not limited to):
+ Parallel programming theory and models
+ Formal analysis and verification
+ Parallel programming languages
+ Compilers and runtime systems for parallel and heterogeneous systems
+ Task-parallel libraries
+ Parallel application frameworks
+ Software productivity for parallel programming
+ Middleware for parallel systems
+ Performance analysis, debugging and optimization
+ Development, analysis, or management tools
+ Parallel algorithms
+ Parallel applications
+ Concurrent data structures
+ Synchronization and concurrency control
+ Software engineering for parallel programs
+ Fault tolerance for parallel systems
+ Software for heterogeneous architectures
+ Programming tools for parallel and heterogeneous systems
+ Parallelism in non-scientific workloads: web servers, search,
analytics, cloud computing

Papers should report on original research relevant to parallel
programming, and should contain enough background materials to make
them accessible to the entire parallel programming research community.

Papers describing experiences should indicate how they illustrate
general principles; papers about parallel programming foundations
should indicate how they relate to practice. Poster submissions should
meet similar criteria for originality and relevance, but may present
emerging ideas or results that are not yet sufficiently developed for
a full paper.

All submissions must be made electronically through the conference web
site. Abstracts must include contact information, the full list of
authors and their affiliations, and a description (100-400 words) of
the anticipated content of the paper. Full paper submissions must be
in PDF formatted for US lettersize paper. They must not exceed 10
pages (all inclusive) in standard ACM two-column conference format
(preprint mode, with page number). Templates for ACM format are
available for Microsoft Word, and LaTeX at
http://www.sigplan.org/authorInformation.htm (use the 9 pt
template). Over-length submissions will not be accepted. Submissions
will be judged on correctness, relevance, originality, significance,
and clarity.

Paper submission is double-blind to reduce reviewer bias against or
for authors or institutions. Thus, the submissions cannot include
author names, institutions or hints based on references to prior
work. If authors are extending their own work, they need to reference
and discuss the past work in third person, as if they were extending
someone else’s research. We realize that for some papers it will still
reveal authorship, but as long as an effort was made to follow these
guidelines, the submission will not be penalized. Authors must
identify any conflicts-of-interest with PC members and external review
committee members, as defined here:
http://www.sigplan.org/review_policies.htm (ACM SIGPLAN policy).

Poster submissions must conform to the same format restrictions, but
may not exceed 2 pages in length. Paper submissions that are not
accepted for regular presentations will automatically be considered
for posters; authors who do not want their paper considered for the
poster session should indicate this in their abstract
submission. Two-page summaries of posters will be included in the
conference proceedings.

PPoPP 2015 will be co-located with HPCA 2015 and CGO 2015 in the San
Francisco Bay Area (exact location to be announced shortly). Authors
should carefully consider the difference in focus of the conferences
when deciding where to submit a paper.

Important dates:
Abstract submission: September 5, 2014
Full paper submission: September 12, 2014
Author response period: October 28-30, 2014 (Tentative)
Notification of acceptance: November 10, 2014

General Chair
Albert Cohen, INRIA

Program Chair
David Grove, IBM Research

Start: February 7, 2015
End: February 11, 2015
Venue: San Francisco Bay Area

Call for Participation: HPCA 2015

Submitted by Michael Taylor
http://darksilicon.org/hpca

2015 IEEE International Symposium on High Performance
Computer Architecture (HPCA)

Bay Area, California
Feb 7-11, 20015
 

HPCA is a top-tier computer architecture conference,
and will have many industry and academic participants.

We have pulled together a program of 60 talks,
almost 30 workshops and tutorials, co-organized
with CGO and PPoPP, and three excellent keynote speakers.

We hope to see you there!

http://darksilicon.org/hpca

Early Registration Deadline: January 11
 

Start: February 7, 2015
End: February 11, 2015
Venue: Bay Area, California, US

Call for Participation: HPCA 2015

Submitted by Michael Taylor
http://darksilicon.org/hpca

2015 IEEE International Symposium on High Performance
Computer Architecture (HPCA)

San Francisco Airport Marriott Waterfront Hotel
San Francisco Bay Area, California, USA
Feb 7-11, 20015
 

EARLY REGISTRATION DEADLINE: January 11
Early hotel reservation rate ($179): Expires shortly after reg deadline.
 

HPCA is a premier annual computer architecture conference sponsored
by the Computer Society of the Institute of Electrical and Electronics
Engineers (IEEE CS). It will bring together researchers, academics,
and industrial engineers from all over the world. It provides an
international forum for these experts to promote, share, and discuss
various issues and developments in the growing field of High
Performance Computer Architecture.

We have pulled together a program of 60 talks, almost 30 workshops
and tutorials, co-organized with CGO and PPoPP, and three excellent
keynote speakers.

http://darksilicon.org/hpca
 

Start: February 7, 2015
End: February 11, 2015
Venue: San Francisco Airport Marriott Waterfront Hotel

Call for Participation: CGO 2015

Submitted by Aaron Smith
http://www.cgo.org

2015 IEEE/ACM International Symposium on Code Generation and
Optimization (CGO)

San Francisco Airport Marriott Waterfront
Feb 7-11, 2015
 

CGO brings together researchers and practitioners working at the interface of
hardware and software on a wide range of optimization and code generation
techniques and related issues.

CGO 2015 is located with ACM PPoPP and IEEE HPCA in the San Francisco Bay Area.

There are 24 full papers and over 30 co-located workshops and tutorials.

http://cgo.org/cgo2015/conference/cgo-2015-accepted-papers-list/

http://cgo.org/cgo2015/conference/workshops-and-tutorials/

Travel grants are available for all students. Apply now!

http://cgo.org/cgo2015/attend-cgo/travel-support-for-eligible-students/

IMPORTANT DATES:
Conference Dates: February 9-11, 2015
Workshops and Tutorials: February 7-8, 2015
Early Registration Deadline: January 11, 2015
 

Start: February 7, 2015
End: February 11, 2015
Venue: San Francisco Airport Marriott Waterfront