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December 21, 2013

Call for Papers: ASAP 2014

Submitted by Haohuan Fu

25th IEEE International Conference on
Application-specific Systems, Architectures and Processors
18-20 June 2014, IBM Research – Zurich, Switzerland

Important Dates

- Abstract Due: 7 February 2014
- Paper Submission: 14 February 2014
- Notification of Acceptance: 1 April 2014
- Conference: 18-20 June 2014

Quick Links

- Conference
- Call for Papers
- Submission site:

The ASAP 2014 conference will be organized by IBM Research – Zurich
and the Swiss Federal Institute of Technology Zurich (ETH).
The conference will cover the theory and practice of application-specific
systems, architectures and processors. The 2014 conference will build
upon traditional strengths in areas such as computer arithmetic,
cryptography, compression, signal and image processing, network processing,
reconfigurable computing, and all types of hardware accelerators.
We especially encourage submissions in the following areas:

– Big data analytics: extracting and correlating information from large-scale
semi-structured and unstructured data using application-specific systems.

– Scientific computing: architectures and algorithms that address scientific
applications requiring significant computing power and design customization
(bioinformatics, climate modeling, astrophysics, seismology, etc.).

– Industrial computing: systems and architectures for providing high-
throughput or low latency in various industrial computing applications.

– System security: cryptographic hardware architectures, security processors,
countermeasures against side-channel attacks, and secure cloud computing.

– Heterogeneous systems: applications and platforms that exploit heterogeneous
computing resources, including FPGAs, GPUs, or CGRAs.

– Design space exploration: methods for customizing and tuning application-
specific architectures to improve efficiency and productivity.

– Platform-specific architectures: novel architectures for exploiting specific
compute domains such as smartphones, tablets, and data centers, particularly
in the context of energy efficiency.


ASAP 2014 will accept 8-page (US letter-size pages, double column) full papers
for oral presentations, 4-page short papers for short oral or poster
presentations, with a single-blind review process. Full papers may have a
maximum of two extra pages at a fee of USD 100 per page.

Submissions to ASAP 2014 must use the double-column IEEE conference
proceedings format. The only accepted file format is PDF. An online submission
page is available on the ASAP 2014 website and includes detailed guidelines and
links to formatting templates. Selected papers from ASAP 2014 will be
invited for publication in a special issue of the Journal of Signal Processing

Conference Venue

The conference is hosted at

IBM Research – Zurich
Säumerstrasse 4
CH-8803 Rüschlikon (Switzerland)

Conference Organization

General Chair:
Kubilay Atasu, IBM Research – Zurich, Switzerland

General Co-Chair:
Melissa Smith, Clemson University, USA

Program Co-Chairs:
Haohuan Fu, Tsinghua University, China
David Thomas, Imperial College London, UK

Industrial chair:
Christoph Hagleitner, IBM Research – Zurich, Switzerland

Finance chair:
Andreas Doering, IBM Research – Zurich, Switzerland

Publication chair:
Esam El-Araby, Catholic University of America, USA

Publicity co-chairs:
Jason Bakos, University of South Carolina, USA
Dirk Koch, University of Manchester, UK
Kentaro Sano, Tohoku University, Japan

Please direct questions about the program and the submission process to
Haohuan Fu ( and David Thomas (

Start: December 21, 2013
End: June 21, 2014

May 19, 2014

Call For Papers: HIPS: 19th International Workshop on High-Level Parallel Programming Models and Supportive Environments

Submitted by Tristan Vanderbruggen
The 19th HIPS workshop, to be held as a full-day meeting on May 19, 2014 at the
IPDPS 2014 conference in Phoenix, focuses on high-level programming of
multiprocessors, compute clusters, and massively parallel machines. Like
previous workshops in the series, which was established in 1996, this event
serves as a forum for research in the areas of parallel applications, language
design, compilers, runtime systems, and programming tools. It provides a timely
and lightweight forum for scientists and engineers to present the latest ideas
and findings in these rapidly changing fields. In our call for papers, we
especially encouraged innovative approaches in the areas of emerging
programming models for large-scale parallel systems and many-core architectures.

Topics of interest to the HIPS workshop include but are not limited to:
– New programming languages and constructs for exploiting parallelism and
– Experience with and improvements for existing parallel languages and
run-time environments such as MPI, OpenMP, Cilk, UPC, Co-array Fortran,
X10, and Chapel
– Parallel compilers, programming tools, and environments
– (Scalable) tools for performance analysis, modeling, monitoring, and
– OS and architectural support for parallel programming and debugging
– Software and system support for extreme scalability including fault
– Programming environments for heterogeneous multicore systems and
accelerators such as GPUs, FPGAs, Cells, and MICs

Important dates

Paper submission: January 14, 2014
Author notification: February 14, 2014
Camera-ready: February 28, 2014

Workshop Chair

John Cavazos, University of Delaware – Newark, DE

Steering Committee

Rudolf Eigenmann, Purdue University – West Lafayette, IN
Michael Gerndt, Technische Universitat – Munchen, Germany
Frank Mueller, North Carolina State University – Raleigh, NC
Craig Rasmussen, University of Oregon – Eugene, OR
Martin Schulz, Lawrence Livermore National Laboratory – Livermore, CA

Program Committee

Tarek Abdelrahman, University of Toronto – Toronto
Greg Bronevetsky, Lawrence Livermore National Laboratory – Livermore, CA
Brad Chamberlain,Cray – Seattle, WA
Alastair Donaldson, Imperial College – London, United Kingdom
Franz Franchetti, Carnegie Mellon University – Pittsburgh, PA
Benedict Gaster, Qualcomm
Hakan Grahn, Blekinge Institute of Technology, Sweden
Christos Kartsaklis, Oak Ridge National Laboratory – Oak Ridge, TN
Jaejin Lee, Seoul National University – Seoul, Korea
Paul Kelly, Imperial College – London, United Kingdom
Andrew Lumsdaine, Indiana University – Bloomington, IN
Tim Mattson, Intel Corp. – DuPont, WA
Kathryn Mohror, Lawrence Livermore National Laboratory – Livermore, CA
Matthias S. Mueller, RWTH Aachen University- Aachen, Germany
Stephen Olivier, University of North Carolina – Chapel Hill, NC
Antoniu Pop, University of Manchester – Manchester, United Kingdom
Philip Roth, Oak Ridge National Laboratory – Oak Ridge, TN
Michael Spear, Lehigh University – Bethlehem, PA
Nathan Tallent, Pacific Northwest National Laboratory – Richland, WA
Zheng (Eddy) Zhang, Rutgers University – New Brunswick, NJ

Start: May 19, 2014
End: May 19, 2014
Venue: Phoenix, Arizona, USA

May 20, 2014

Call for Papers: Computing Frontiers 2014

Submitted by Mohamed Zahran

ACM International Conference on Computing Frontiers 2014 (CF’14)
May 20 – 22, 2014, Cagliari, Italy

Computing Frontiers represents an engaged, collaborative
community of researchers who are excited about transformational
technologies in the field of computing. We are presently on the
cusp of several revolutions, including new memory technologies,
networking technologies, algorithms for handling large-scale data,
power-saving and energy-efficient solutions for data centers,
systems solutions for cloud computing, and many, many more.
Boundaries between the state-of-the-art and revolutionary innovation
constitute the computing frontiers that must be pushed forward to
advance science, engineering, and information technology.
Before revolutionary materials, devices, and systems enter the
mainstream, early research must be performed using far-reaching
projections of the future state of technologies.

Computing Frontiers is a gathering for people to share and discuss
such work, focusing on a wide spectrum of advanced technologies and
radically new solutions relevant to the development of the whole
spectrum of computer systems, from embedded to high-performance

Submissions deadline: January 18, 2014
Notification: February 28, 2014
Camera-Copy Papers Due: March 15, 2014


We seek contributions that push the envelope in a wide range of
computing topics, ranging from more traditional research in
architecture and systems to new technologies and devices. We seek
contributions on novel computing paradigms, computational models,
algorithms, application paradigms, development environments,
compilers, operating environments, computer architecture,
hardware substrates, and memory technologies. We are also
interested in emerging fields that may not fit within traditional

* Algorithms and Models of Computing
approximate and inexact computing, quantum and probabilistic

* Big Data
analytics, machine learning, search and representation, system

* System Complexity Management
cloud systems, datacenters, computational neuroscience,
biologically-inspired architectures

* Computers and Society
education, health and cost/energy-efficient design, smart cities,
emerging markets

* Security
architecture and systems support for protection against malicious

* Limits on Technology Scaling and Moore’s Law
defect- and variability-tolerant designs, graphene and other
novel materials, nanoscale design, optoelectronics, dark silicon

* Uses of Technology Scaling
3D stacked technology, challenges of manycore designs,
PCM’s, novel memory architectures, mobile devices

* Compiler technologies
novel techniques to push the envelope on new technologies,
applications, hardware/software integrated solutions, advanced

* Networking
technology and protocols, bandwidth management, social networks,
internet of things


Authors are invited to submit full papers or posters to the main
conference. Full papers and poster abstracts must be submitted
through the conference paper submission site. Full papers should
not exceed 10 double-column pages in standard ACM conference format.
Poster abstracts should not exceed two pages in the same format.
These limits include figures, tables, and references. Abstracts
for accepted posters will be published in the proceedings and in
the ACM Digital Library (note that authors of these works retain
their copyright rights to publish more complete versions later).
As per ACM guidelines, at least one of the authors of accepted
papers is required to register for the conference.


Computing Frontiers 2014 Chairs

General Chair: Pedro Trancoso, University of Cyprus, CY
Program Chairs: Diana Franklin, University of California at Santa Barbara, US
Sally A. McKee, Chalmers University of Technology, SE
Finance Chair: Carsten Trinitis, TUM, DE/Univ. of Bedfordshire, UK
Local Arrangements Chair:
Francesca Palumbo, University of Cagliari, IT
Poster Chair: Hubertus Franke, IBM, US
Publicity Chairs:
Mohamed Zahran, New York University, US
Rui Hou, Institute of Computing Technology, CN
Publication Chair:
Roberto Gioiosa, Pacific Northwest National Lab, US
Web Chair: Josef Weidendorfer, TU Muenchen, DE

Program Committee Members

Bridget Benson California Polytechnic University,
San Luis Obispo, US
Haibo Chen Shanghai Jiao Tong University, CN
David Black-Schaffer Uppsala University, SE
Marcelo Cintra Intel, DE
Hadi Esmailzadeh Georgia Tech, US
Hubertus Franke IBM, US
Michael Franz University of California at Irvine, US
Maria Gini University of Minnesota, US
Dimitris Gizopoulos University of Athens, GR
Torsten Hoefler ETH Zurich, CH
Rui Hou Institute of Computing Technology, CN
Koji Inoue Kyushu University, JP
Engin Ipek University of Rochester, UK
Mahmut Kandemir Penn State University, US
Ryan Kastner University of California at San Diego, US
Gokcen Kestor Pacific Northwest National Laboratory, US
John Kim KAIST, KR
Cetin Koc University of California at Santa Barbara, US
Gabriel Loh AMD Research, US
Guoping Long Institute of Software, CN
Mauro Migliardi University of Padua, IT
Katerina Mitrokotsa Chalmers University of Technology, SE
Dimitrios Nikolopulos Queen’s University of Belfast, IR
Magnus Sjaelander Florida State University, US
Leonel Sousa Universidade Tecnica de Lisboa, PT
Lingjia Tang University of Michigan, US
Michela Taufer University of Delaware, US
Gary Tyson Florida State University, US
Carole-Jean Wu Arizona State University, US
Jin Xiong Institute of Computing Technology, CN
Zhibin Yu Shenzhen Institutes of Advanced Technology, CN

Computing Frontiers 2014 Steering Committee

Monica Alderighi, INAF, IT
Paolo Faraboschi, HP, ES
Hubertus Franke, IBM, US
John Feo, Pacific Northwest National Lab, US
Georgi Gaydadjiev, Chalmers University of Technology, SE
Alex Heinecke, TU Muenchen, DE
Paul H. J. Kelly, Imperial College London, UK
Sally A. McKee, Chalmers University of Technology, SE
Valentina Salapura, IBM TJ Watson, US
Pedro Trancoso, University of Cyprus, CY
Carsten Trinitis, TUM, DE/Univ. of Bedfordshire, UK
Oreste Villa, NVIDIA Architecture Research, US

Start: May 20, 2014
End: May 22, 2014
Venue: Cagliari, Italy

Call for Participation: Computing Frontiers’14

Submitted by Mohamed Zahran
ACM International Conference on Computing Frontiers 2014

May 20 – 22, 2014, Cagliari, Italy
Early registration (for special rate) till April 11, 2014

Computing Frontiers represents an engaged, collaborative community of
researchers who are excited about transformational technologies in the field of
computing. We are presently on the cusp of several revolutions, including new
memory technologies, networking technologies, algorithms for handling
large-scale data, power-saving and energy-efficient solutions for data centers,
systems solutions for cloud computing, and many, many more. Boundaries between
the state-of-the-art and revolutionary innovation constitute the computing
frontiers that must be pushed forward to advance science, engineering, and
information technology. Before revolutionary materials, devices, and systems
enter the mainstream, early research must be performed using far-reaching
projections of the future state of technologies.
Computing Frontiers is a gathering for people to share and discuss such work,
focusing on a wide spectrum of advanced technologies and radically new
solutions relevant to the development of the whole spectrum of computer
systems, from embedded to high-performance computing.

Start: May 20, 2014
End: May 22, 2014
Venue: Cagliari, Italy

June 2, 2014

Call for Papers: 30th International Conference on Massive Storage Systems and Technology (MSST 2014)

Submitted by Thomas Schwarz SJ
Abstracts Deadline March 4, 2014
Paper Submission: March 9, 2014
Notifications: April 7, 2014
Final papers due: May 2, 2014
Research Track: June 5 – 6, 2014
Papers published in: IEEE Xplore

The 30th International Conference on Massive Storage systems and
Technologies (MSST 2014) will have IEEE as a technical co-sponsor
and will be held at Santa Clara University in the midst of Silicon Valley.
The conference offers a full week dedicated to storage technology. As
on previous occasions, the conference will include a two-day research
track of peer-reviewed papers on the design, analysis, and
implementation of and experience with storage systems. Published
papers will be indexed by IEEE and appear in IEEE Xplore.

We encourage the submission of research papers on the
implementation, design, and analysis of file and storage systems.
Specific areas of interest for the MSST
2014 Research Track include (but are not limited to):

Performance modeling and analysis of storage systems
Experiences with real-world systems and data storage challenges
Management of new and upcoming storage technologies
Cloud storage systems and global-scale storage
Exascale storage architecture and design
Evaluation of networked storage architectures
Data protection and recovery
Data archiving
Storage in virtualized environments
Storage systems modeling and evaluation
Techniques for building extremely scalable and distributed
storage systems
Parallel and distributed file systems
Scalable metadata management
Storage security, privacy, and provenance
Long-term data preservation and management
Disk and Flash based cold storage systems
File systems for cold storage
File systems for shingled magnetic recording hard disk
File systems for solid state disk drives
New solid state disk APIs: Object storage, key value store,
memory mapping …
Phase change memory based storage class memory
devices and systems

As is traditional, MSST will have short and full papers. Short
papers are to be 4 – 6 pages in length, whereas full papers are
8 – 14 pages in length. Accepted full papers will be presented in a
30 minute session, short papers will be presented in a poster session
with short (7 minutes) presentations. All papers will be published
by IEEE Xplore and indexed by IEEE.

Details about the submission process and rules as well as the conference
organization will be published at the conference website:

The submission process will be managed by easychair at

Start: June 2, 2014
End: June 6, 2014
Venue: Santa Clara University

June 10, 2014

Call for Papers: SYSTOR 2014

Submitted by Eliezer Dekel
We invite you to submit original and innovative papers to SYSTOR 2014.
The 7th ACM International Systems and Storage Conference.
The conference will take place between June 10–12, 2013 in Haifa, Israel.

Start: June 10, 2014
End: June 12, 2014
Venue: Haifa, Israel

June 12, 2014

Call for Papers: TRUST’14 @ PLDI’14

Submitted by Grigori Fursin
on Reproducible Research Methodologies
and New Publication Models in Computer Engineering

June 12,2014, Edinburgh, UK
(co-located with PLDI 2014)

It becomes excessively challenging or even impossible to capture,
share and accurately reproduce experimental results in computer
engineering for fair and trustable evaluation and future
improvement. This is often due to ever rising complexity of the
design, analysis and optimization of computer systems, increasing
number of ad-hoc tools, interfaces and techniques, lack of
a common experimental methodology, and lack of simple and unified
mechanisms, tools and repositories to preserve and exchange
knowledge apart from numerous publications where reproducibility
is oaten not even considered. This SIGPLAN workshop is intended
to become an interdisciplinary forum for academic and industrial
researchers, practitioners and developers in computer engineering
to discuss challenges, ideas, experience, trustable and
reproducible research methodologies, practical techniques, tools
and repositories to:

* capture, preserve, formalize, systematize, exchange and improve
knowledge and experimental results including negative ones
* describe and catalog whole experimental setups with all related
material including algorithms, benchmarks, codelets, datasets,
tools, models and any other artifact
* validate and verify experimental results by the community
* develop common research interfaces for existing or new tools
* develop common experimental frameworks and repositories
* share rare hardware and computational resources for
experimental validation
* deal with variability and rising amount of experimental data
using statistical analysis, data mining, predictive modeling and
other techniques
* implement previously published experimental scenarios
(auto-tuning, run-time adaptation) using common infrastructure
* implement open access to publications and data (particularly
discussing intellectual property IP and legal issues)
* improve reviewing process
* enable interactive articles

==== Important Dates ====

* Abstract submission deadline: March 7, 2014 (AoE)
* Paper submission deadline: March 14, 2014 (AoE)
* Author notification: April 14, 2014
* Final paper version: May 2, 2014
* Workshop: June 12, 2014

==== Workshop organizers ====

* Grigori Fursin (INRIA, France)
* Bruce Childers, Alex K.Jones and Daniel Mosse
(University of Pittsburgh, USA)

==== Program Committee ====

* Jose Nelson Amaral (University of Alberta, Canada)
* Calin Cascaval (Qualcomm, USA)
* Jack Davidson (University of Virginia, USA)
* Evelyn Duesterwald (IBM, USA)
* Lieven Eeckhout (Ghent University, Belgium)
* Eric Eide (University of Utah, USA)
* Sebastian Fischmeister (University of Waterloo, Canada)
* Michael Gerndt (TU Munich, Germany)
* Christophe Guillon (STMicroelectronics, France)
* Shriram Krishnamurthi (Brown University, USA)
* Hugh Leather (University of Edinburgh, UK)
* Anton Lokhmotov (ARM, UK)
* Mikel Lujan (University of Manchester, UK)
* David Padua (University of Illinois at Urbana-Champaign, USA)
* Christoph Reichenbach
(Johann-Wolfgang Goethe Universitat Frankfurt, Germany)
* Arun Rodrigues (Sandia National Laboratories, USA)
* Reiji Suda (University of Tokyo, Japan)
* Sid Touati (INRIA, France)
* Jesper Larsson Traff (Vienna University of Technology, Austria)
* Petr Tuma (Charles University, Czech Republic)
* Jan Vitek (Purdue University, USA)
* Vladimir Voevodin (Moscow State University, Russia)
* Vittorio Zaccaria (Politecnico di Milano, Italy)
* Xiaoyun Zhu (VMware, USA)

==== Paper Submission Guidelines ====

We invite papers in three categories (please use these prefixes
for your submission title):

* T1: Extended abstracts should be at most 3 pages long
(excluding bibliography). We welcome preliminary and exploratory
work, presentation of related tools and repositories
in development, experience reports, and wild & crazy ideas.
* T2: Full papers should be at most 6 pages long (excluding
bibliography). Papers in this category are expected to have
relatively mature content.
* T3: Papers validating and sharing past research on design and
optimization of computer systems published in relevant
conferences. These papers should be at most 6 pages long
(excluding bibliography).

Submissions should be in PDF formatted with double
column/single-spacing using 10pt fonts and printable on US letter
or A4 sized paper. All papers will be peer-reviewed. Accepted
papers can be published online on the conference website that
will not prevent later publication of extended papers.
We currently arrange proceedings to be published in the ACM
Digital Library.

Easychair submission website:

==== Some related projects and initiatives ====

* Conference Artifact Evaluation

* HiPEAC thematic session on making computer engineering a science:

* ADAPT panel on reproducible research methodologies and new
publication models (January 2014):

* Collective Mind technology for collaborative, systematic and
reproducible computer engineering:

* cTuning technology to crowdsource auto-tuning
and combine with machine learning (2006-2011):

* OCCAM project for reproducible computer architecture simulation:

* Evaluate project:

* Artifact evaluation at OOSPLA’13:

* Artifact evaluation at PLDI’14:

* CARE tool from STMicroelectronics
(Comprehensive Archiver for Reproducible Execution)

==== Sponsors ====


Start: June 12, 2014 9:00 am
End: June 12, 2014 2:00 pm
Venue: Edinburgh, UK

June 13, 2014

Call for Papers: MSPC 2014

Submitted by Milind Kulkarni
ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
MSPC 2014
June 13, 2014, Edinburgh, Scotland
(co-located with PLDI 2014)

PC Chairs: Milind Kulkarni (
Tim Harris (

Workshop website:


Memory continues to be a major bottleneck in almost all computing systems. It
is becoming more so as more cores and agents are sharing parts of the memory
system and as applications that run on the cores are becoming increasingly
data intensive. Continuing the tradition of eight previous successful
incarnations, MSPC 2014 will provide a forum for publishing and discussing all
aspects of memory performance and correctness on a variety of systems
(multi-core, desktop, embedded, server/cloud, high-performance computing,
sensor, etc) and related software and hardware innovations at various levels
of the technology stack. We invite new submissions that tackle issues in
memory system performance, efficiency, correctness, and dependability in both
hardware and software layers. Example areas of interest include but are not
limited to the following:

* Hardware, software, and hybrid techniques for better memory performance,
correctness, reliability, efficiency
* Memory hierarchy design for chip multiprocessors (CMPs)
* Emerging memory technologies (e.g., Phase Change Memory, MRAM)
* Characterization and analysis of memory systems performance
* Insightful experimental evaluation and analysis of memory-intensive
* Static and dynamic techniques for understanding and improving memory
performance and efficiency
* Managed memory and garbage collection optimizations
* Hardware and software techniques for ensuring memory safety and detecting
memory-related bugs
* Hardware and software memory models and their impact on programmability and
* Memory system issues in accelerator-based computing (e.g., GPGPU)
* Memory system issues in embedded computers and tiny devices
* Prefetching, compression, latency tolerance techniques for memory
* Memory power and energy management techniques
* Memory reliability management techniques
* Software, hardware, and hybrid approaches are encouraged.

In addition, we solicit papers from practitioners describing problems and
experiences with memory performance and correctness in specific application


We encourage the submission of not-fully-polished but provocative short papers
(6—8 pages; 8 pages maximum) or position abstracts (1-2 pages; 2 pages
maximum). Paper submissions should use standard ACM SIGPLAN conference format
(10pt), available at Copies of
accepted papers will be made available at the workshop and published in the
ACM digital library. Submitted papers must not be simultaneously under review
for any other conference or journal, and authors should point out any
substantial overlap with their previously published or currently submitted


Papers due: March 10, 2014 (11:59 AOE)
Notification of acceptance: April 28, 2014
Final papers due: May 19, 2014

Start: June 13, 2014
End: June 13, 2014
Venue: Edinburgh, Scotland, UK

June 14, 2014

Call for Papers: ISCA 2014

Submitted by Natalie Enright Jerger
The International Symposium on Computer Architecture is the premier forum
for new ideas and experimental results in computer architecture. The conference
specifically seeks particularly forward-looking and novel submissions. Papers
are solicited on a broad range of topics, including (but not limited to):

Processor, memory, and storage systems architecture
Parallel and multicore systems
Data-center scale computing
Architectures for handheld and mobile devices
Application-specific, reconfigurable, or embedded architectures
Accelerator-based architectures
Architectures for security and virtualization
Power and energy efficient architectures
Interconnection networks
Instruction, thread, and data-level parallelism
Dependable architectures
Architectural support for programming productivity
Network processor and router architectures
Architectures for emerging technologies and applications
Effect of circuits and technology on architecture
Architecture modeling and simulation methodology
Performance evaluation and measurement of real systems

Abstract Deadline: November 14, 2013, 11:59PM EST
Final Paper Deadline: November 21, 2013, 11:59PM EST
Rebuttal Period: February 11-14, 2014
Author Notification: March 7, 2014

** Program Chair:

Steve Keckler, NVIDIA/University of Texas at Austin

** Program Committee:

David Albonesi Cornell
David I. August Princeton University
Todd Austin University of Michigan
David Brooks Harvard
Doug Burger Microsoft
Doug Carmean Intel
John Carter IBM Research
Derek Chiou Microsoft/UT-Austin
Fred Chong UC-Santa Barbara
Al Davis University of Utah
Pradeep Dubey Intel
Sandhya Dwarkadas University of Rochester
Yoav Etsion Technion
Boris Grot University of Edinburgh
Rajiv Gupta UC-Riverside
David Hansquine Qualcomm
Mark D. Hill University of Wisconsin-Madison
Wen-mei Hwu University of Illinois
Stefanos Kaxiras Uppsala University
Hyesoon Kim Georgia Tech
John Kim KAIST
Martha Kim Columbia
Ronny Krashinsky NVIDIA
James Laudon Google
Alvin Lebeck Duke
Hsien-Hsin Lee Georgia Tech
Srilatha Manne AMD
Nacho Navarro U. Politecnica de Catalunya
Scott Rixner Rice
Simha Sethumadhavan Columbia
Ed Suh Cornell
Olivier Temam INRIA
Mohit Tiwari UT-Austin
Brian Towles DE Shaw Research
Dean Tullsen UC San Diego
Uri Weiser Technion
David Wentzlaff Princeton University
Carole-Jean Wu Arizona State University
Yuan Xie Pennsylvania State University
Sudhakar Yalamanchili Georgia Tech
Lixin Zhang Chinese Academy of Sciences
Craig Zilles University of Illinois

Organizing Committee:

** General Co-Chairs
Pen-Chung Yew, University of Minnesota
Antonia Zhai, University of Minnesota

** Workshop Co-Chairs
David Wentzlaff, Princeton University
Nuwan Jayasena, AMD Research

** Tutorial Co-Chairs
Martha Kim, Columbia University
Debbie Marr, Intel

** Finance Chair
Yuan Xie, Pennsylvania State University

** Industry Liaison Co-Chairs
Hyesoon Kim, Georgia Institute of Technology
Samantika Subramaniam, Intel

** Local Arrangements Chair
John Sartori, University of Minnesota

** Web Chair
Omer Khan, University of Connecticut

** Publicity Co-Chairs
Chia-Lin Yang, National Taiwan University
Natalie Enright Jerger, University of Toronto
Lieven Eeckhout, Ghent University

** Registration Chair
Ulya Karpuzcu, University of Minnesota

** Proceedings Chair
Eric Chung, Microsoft Research

** Travel Award Chair
James Tuck, NC State University

** Submission Chair
Paul Gratz, Texas A&M University

** Steering Committee
Mark Horowitz, Stanford University
David Kaeli, Northeastern University
Shih-Lien Lu, Intel
Avi Mendelson, Technion
Margaret Martonosi, Princeton University
Yale Patt, University of Texas at Austin
Joseph Torrellas, University of Illinois
David Wood, University of Wisconsin

Start: June 14, 2014
End: June 18, 2014

Call for Papers: Workshop on Neuromorphic Architectures (NeuroArch) @ ISCA 2014

Submitted by Hadi Esmaeilzadeh
Workshop on Neuromorphic Architectures (NeuroArch)

Saturday, June 14th, 2014
(held in conjunction with ISCA 2014)
Minneapolis, MN, USA


The first workshop on Neuromorphic Architectures (NeuroArch) aims at exploring
novel ideas and research opportunities in design, programming, and application
of neuromorphic and brain-inspired accelerators. In the current realm of
processor design, where energy and power constraint has shifted the designs
toward heterogeneity, hardware neural networks are emerging as candidate
accelerators with attractive characteristics and broad application scope.

In addition to the power-efficiency and fault tolerance of neural accelerators,
we are at the junction of time where: As technology scales down to the atomic
levels, the increasing process variability causes the designers to pay a high
tax in performance and efficiency to provide fault-free designs; the intrinsic
robustness of neural networks may lead to fault-tolerant accelerators. Novel
neural network algorithms such as Deep Belief Networks outperform many
alternative machine learning algorithms across a broad set of applications.
Significant progress in neuroscience sheds light on the operating principles of
biological neural networks, which can thus be partially replicated in hardware.
The landscape of computing has changed toward providing a more personalized and
more targeted experience for the users, thus increasing the importance of
applications that require learning.

Therefore, we believe it is imperative and timely for the computer architecture
community and the design of next generation computing systems to explore and
research neural models of computing.


To this end, NeuroArch invites research papers and talks on topics including
but not limited to: Hardware design for biologically or mathematically inspired
neural networks Applications of hardware neural networks Advanced technologies
and devices for neural hardware design (3D, memristors, …) Programming models
and environments for neural accelerators

NeuroArch 2014 will include both invited talks and peer-reviewed papers.
Peer-reviewed papers will not be published in a proceedings; therefore,
submitting to NeuroArch will not preclude future publication opportunities.
However, papers and presentation slides will be made available online with the
authors’ approval.


Paper Submission: April 1st, 2014
Author Notification: April 15th, 2014


Paper submissions are limited to two-page extended abstracts. Please use the
formatting guidelines from the main conference (see

Please send a PDF version of your paper to and

Submissions may optionally be blind (authors can choose whether to include
names on the submitted PDF; this option will be relevant if the organizing
committee decides to query the opinion of an external reviewer).


Daniel Ben Dayan-Rubin, Intel Labs, ICRI, Israel
Hadi Esmaeilzadeh, Georgia Tech
Abdullah Muzahid, University of Texas at San Antonio
Emre Neftci, UCSD
Olivier Temam, Inria

For any question related to the workshop organization, please contact and

Start: June 14, 2014
End: June 14, 2014
Venue: Minneapolis, MN, USA