Submitted by Narayan Desai
http://www.cs.huji.ac.il/~feit/parsched/jsspp13/

17th WORKSHOP ON JOB SCHEDULING STRATEGIES FOR PARALLEL PROCESSING (JSSPP)
in conjunction with IPDPS
Boston, USA, May 24, 2013

The JSSPP workshop addresses all scheduling aspects of parallel
processing.

Large parallel systems have been in production for over 15 years.
Initially, they were primarily used in scientific computing. But with
the advance of Cloud computing and new processor paradigms such as
multi-core systems and reconfigurable architectures, scheduling in
parallel systems has grown in relevance and scope, significantly
extending its original focus. JSSPP has evolved with the area and now
fully covers parallel scheduling for commercial environments while
still maintaining strong interest in its traditional areas: scientific
computing, supercomputing and cluster platforms.

From its very beginning, JSSPP has strived to balance practice and
theory in its program. This combination provides a rich environment
for technical debate about scheduling approaches including both
academic researchers as well as participants from industry. JSSPP is a
high-visibility workshop, which has been ranking repeatedly in the top
10% of Citeseer’s venue impact list. JSSPP solicits papers that belong
to any of the following topics, although papers on other themes that
are relevant in the context of JSSPP are welcome as well: Performance
evaluation of scheduling approaches, including methodology,
benchmarks, and metrics. Design of, and experience with, scheduling
approaches for production systems. Workloads on parallel processing
systems, including characterization, classification, and modeling.
Consideration of additional constraints in scheduling systems, like
job priorities, accounting, load estimation, and quality of service
guarantees. Scaling and composition of very large scheduling systems.
Interaction between schedulers on different levels, like processor
level as well as whole single- or even multi-owner systems. Impact of
scheduling strategies on application performance, user friendliness,
cost efficiency, and energy efficiency.

==========
Submission dates and guidelines
DEADLINE: February 17, 2013
NOTIFICATION: March 20, 2013

Papers should be no longer than 20 single-spaced pages, 10pt font,
including figures and references. All papers in scope will be reviewed
by at least three members of the program committee. All submissions
must follow the LNCS format, see the instructions at Springer’s web
site:

http://www.springer.com/computer/lncs?SGWID=0-164-7-72376-0

Files must be submitted electronically in PDF format and must be
formatted for 8.5×11 inch paper. Submission procedures can be found at
the workshop’s homepage: http://www.cs.huji.ac.il/~feit/parsched/

Papers can be submitted via EDAS:

https://www.edas.info/newPaper.php?c=13633&track=27403

==========
Goals Continuing the tradition started at IPPS’95, the workshop is
intended to attract people from academia, industry, computing centers,
national laboratories, Cloud and Grid initiatives, and parallel
computer vendors to address scheduling in parallel systems, and
attempt to resolve often conflicting goals expressed by system owners.
The workshop intends to achieve a balance between – reports of current
practices in the entire range of parallel systems, – proposals of
novel schemes that have not yet been tested in a real environment, and
- realistic models and their analysis.

==========
Registration Registration will be part of the IPDPS process and is
handled by the IEEE. For details, see the IPDPS web site

http://www.ipdps.org/

==========
Proceedings Interim proceedings containing a collection of the papers
presented will be distributed at the workshop in electronic form. It
is planned to also publish a post-workshop proceedings in the Springer
Lecture Notes on Computer Science series, as was done in previous
years (pending approval from Springer).

==========
Workshop organizers
Walfredo Cirne, Google
Narayan Desai, Argonne National Laboratory

Program Committee
Henri Casanova, University of Hawaii at Manoa
Julita Corbalan, Technical University of Catalonia
Dick Epema, Delft University of Technology
Gilles Fedak, INRIA
Dror G. Feitelson, The Hebrew University
Liana Fong, IBM T. J. Watson Research Center
Eitan Frachtenberg, Facebook
Alfredo Goldman, USP
Allan Gottlieb, NYU
Alexandru Iosup, Delft University of Technology
Morris Jette, SchedMD LLC
Rajkumar Kettimuthu, Argonne National Lab
Dalibor Klusáček, Masaryk University
Zhiling Lan, Illinois Institute of Technology
Bill Nitzberg, Altair
David Oppenheimer, Google
Uwe Schwiegelshohn, TU Dortmund University
Mark Squillante, IBM Thomas J. Watson Research Center
Wei Tang, Argonne National Laboratory
Dan Tsafrir, Technion – Israel Institute of Technology
Ramin Yahyapour, GWDG – University Göttingen

Henri Casanova, University of Hawaii at Manoa
Julita Corbalan, Technical University of Catalunya
Dick Epema, Delft University of Technology
Dror G. Feitelson, The Hebrew University
Ian Foster, Argonne National Laboratory
Alfredo Goldman, University of Sao Paulo
Allan Gottlieb, New York University
Morris Jette, SchedMD
Rajkumar Kettimuthu, Argonne National Lab
Derrick Kondo, INRIA
Zhiling Lan, Illinois Institute of Technology
Virginia Lo, University of Oregon
Satoshi Matsuoka, Tokyo Institute of Technology
Jose Moreira, IBM T.J. Watson Research Center
Bill Nitzberg, Altair Engineering
Mark Squillante, IBM Thomas J. Watson Research Center
Dan Tsafrir, Technion
John Wilkes, Google
Ramin Yahyapour, The University of Göttingen

Submitted by Kubilay Atasu
http://asap-conference.org

ASAP 2013
Abstract due: February 8, 2013
Paper due: February 15, 2013

24th IEEE International Conference on
Application-specific Systems, Architectures and Processors
5-7 June 2013
Washington D.C., USA

The conference will cover the theory and practice of
application-specific systems, architectures and processors.
The 2013 conference will build upon traditional strengths
in areas such as computer arithmetic, cryptography,
compression, signal and image processing, network processing,
reconfigurable computing, application-specific instruction-set
processors, and hardware accelerators. We especially encourage
submissions in the following areas:
* Bioinformatics and computational biology – life sciences
present a host of interesting problems that can benefit from
application-specific solutions
* Computational finance – the financial community has significant
needs for high performance computing
* Big data analytics – extracting and correlating information from
large scale unstructured data using application-specific systems
* Architecturally diverse systems – systems that use heterogeneous
computing resources including FPGAs, GPUs, and CGRAs
* Architectural and system level design space exploration and
customization techniques for improving the design efficiency
* Architectures for emerging platforms, such as smartphones,
tablets, and data centers, with emphasis on energy efficiency

Guidelines for Submission:
ASAP will accept 8-page full papers for oral presentation,
4-page short papers for short oral or poster presentation.
All submissions should be written in the English language.
An online submission link will be available on the ASAP 2013
website starting in early January. Papers should use the
IEEE formatting template linked at the submission page.

Conference Committee:
General Chair:
Tarek El-Ghazawi, The George Washington University, USA
General Co-Chair:
Alan George, UoF, USA
Program Chair:
Melissa Smith, Clemson University, USA
Program Co-Chair:
Kubilay Atasu, IBM Research – Zurich, Switzerland

Important Dates:
* Abstract Due – February 8, 2013
* Paper Due – February 15, 2013
* Notification of Acceptance – March 15, 2013
* Camera Ready Paper – April 5, 2013
* Conference – June 5-7 2013

Submitted by Joseph Sloan
http://aer-workshop.org
International Workshop on Algorithmic and Application Error Resilience
AER 2013

Held in conjunction with the
27th International Conference on Supercomputing (ICS 2013)

June 10th, 2013
Eugene, Oregon, USA

http://aer-workshop.org

CALL FOR PAPERS
—————
Circuit and logic variability from process scaling is leading to significant
reliability problems in future systems. The increasingly stringent power
constraints on system designs are making prior hardware and software-based
fault tolerance approaches impractical due to their heavy reliance on redundant,
worst-case, and conservative designs. Instead, algorithm-based approaches
provide applications the flexibility to adapt to inherent application error
tolerances and leverage the patterns of higher level abstractions.

SUBMISSIONS
———–
The AER workshop, to be held as a full-day meeting at the ICS 2013 conference
in Eugene, Oregon, focuses on techniques, approaches, and principles for
algorithmic and application error resilience.

Topics of Interest:
* Algorithm design principles for error resilience
* Algorithmic error resilience implementations
* Techniques for massively parallel resilient applications
* Application fault detection and correction
* Hardware fault and application error models
* Application error resilience analysis and case studies
* Tools for analyzing application vulnerability to errors
* Optimizations for exploiting error resilience
* System design and automation

The AER workshop proceedings will be published electronically along with the
ICS conference proceedings via the ACM Digital Library. Submitted manuscripts
should be formatted using the ACM SIG proceedings alternate format
(http://www.acm.org/sigs/publications/proceedings-templates). The maximum
length is 8 pages. All papers must be in English. Please visit the workshop
website for further instructions and the submission link
(http://aer-workshop.org).

IMPORTANT DATES
—————
Submission deadline: May 1st, 2013
Author notification: May 20th, 2013

WORKSHOP CHAIRS:
—————-
Greg Bronevetsky, Lawrence Livermore National Laboratory, USA
Joseph Sloan, University of Illinois at Urbana-Champaign, USA

PROGRAM COMMITTEE
—————–
Rakesh Kumar, UIUC
Zizhong Chen, UC Riverside
John Daly, DoD
Pedro Diniz, University of Southern California
Jack Dongarra, University of Tennessee
Marc Casas-Guix, LLNL
Ganesh Gopalkrishnan, University of Utah
Nathan DeBardeleben, LANL
Mike Heroux, Sandia

WEBSITE
——-
http://aer-workshop.org

Submitted by Girish Venkatasubramanian
http://www.ideal.ece.ufl.edu/wivosca/

Seventh Annual
Workshop on the Interaction amongst
Virtualization, Operating Systems, and Computer Architecture
( WIVOSCA 2013 )

http://www.ideal.ece.ufl.edu/wivosca

Held in Conjunction with the
40th Annual International Symposium on Computer Architecture
( ISCA – 40 )

Workshop Overview and Topics
~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Operating systems (OS) constitute a major software component
and are essential to any computing system. Commercial and
server workloads such as online transaction processing,
database, file/e-mail servers involve significant OS-level
activity. The interactions between OS and emerging
architectures (e.g. homogeneous and heterogeneous chip
multiprocessors, simultaneous multithreading systems) /
technology (e.g. hardware-assisted virtualization) are
projected to continuously increase. In addition, the use of a
wide variety of virtualization techniques, ranging from
application-level virtualization to full-system virtualization,
for providing application portability, managing power and
performance, providing QoS guarantees and to effectively use the
power of emerging architectures, has become prominent.

To optimize system
performance/power/reliability/security, it is important to
facilitate efficient interaction and cooperation amongst the
three constantly evolving components – OS, virtualization and
computer architecture.

This workshop focuses on characterizing, modeling, and
optimizing the interaction between OS and hardware in the
light of emerging architecture paradigms, workloads, and
computing technology. Topics of particular interest include,
but are not limited to:

* Architectural support for OS functionality and services
* Architectural support for virtual machines and hypervisors
* Hardware acceleration of OS and Virtualization services
* OS and Virtualization support for emerging computer architectures
* Implications of virtualization on OS design
* Effect of OS/Virtualization on emerging architectures
* System software-aware microarchitecture design
* Leveraging OS/Virtualization to optimize reliability/thermal/power
* Frameworks and tools for full-system simulation
* Characterization of OS/Virtualization activity in emerging workloads
* Performance, power, dependability, and security in OS/Virtualization
* OS/Virtualization -intensive benchmark suites
* Evaluation of the interaction/interference among OS/user
* Mitigation of OS and Virtualization related execution bottlenecks
* Architecture and Virtualization issues in data centers
* Architecture and Virtualization support for cloud computing

Furthermore, the workshop aims at providing a forum for
researchers, engineers, and students from academia and
industry to discuss their latest research in
virtualization, computer architecture and OS, to bring
their ideas and research problems to the attention of
others, and to obtain valuable and instant feedback from
fellow researchers.

Workshop Co-Organizers
~~~~~~~~~~~~~~~~~~~~~~
Tao Li, University of Florida (taoli@ece.ufl.edu)
James Poe, Miami Dade College (jpoe@mdc.edu)
Girish Venkatasubramanian, Intel (girish.venkatasubramanian@intel.com)

Important Dates
~~~~~~~~~~~~~~~

* Abstract Submission: April 12, 2013
* Paper Submission: April 19, 2013
* Author Notification: May 10, 2013
* Camera-ready Version: May 17, 2013

Please feel free to visit our website for more information
as well as links to previous WIOSCA workshops:

http://www.ideal.ece.ufl.edu/wivosca

Submitted by Augusto Vega
http://researcher.ibm.com/project/2259

The “power wall” has forced chip and system architects to design
with smaller margins between nominal and worst-case operating
points. Dynamic power and thermal management control loops have
already become an integral part of chip and system design. New
research papers in wearout and general reliability management have
recently been published. These new generation management protocols
have, however, opened up other sources of concern: e.g. control loop
stability and robustness of the management protocols. The potential
security holes exposed by the integrated control loops and system
safety issues triggered by potential violations of power or thermal
limits are other areas of concern. We seek to motivate the research
community into adopting a holistic approach to mitigating the power
wall and the concomitant reliability-security wall.

We have coined the term “Energy-Secure System Architectures” to
cover the range of research being pursued within industry and
academia in order to ensure robust and secure functionality, while
meeting the energy-related constraints of the emerging “green
computing” era. This segmented tutorial/workshop offering, composed
of lectures provided by experts in the areas of power/thermal
management, reliability and security, provides a comprehensive view
of the hardware and software aspects of Energy-Secure System
Architectures.
This is the third year of the offering of this workshop.