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October 1, 2014

Call for Papers: IEEE Transactions on Computers Special Issue on Transparent Computing

Submitted by Jimmy Cuo
*** We apologize if you receive multiple copies **********
Special Issue in IEEE Transactions on Computers on “Transparent Computing”

At 2012 Intel Developer Forum, San Francisco, Renee James, senior Vice
President and General Manager of Intels Software Services Group, delivered a
keynote speech “Next Era of Computing: Transparent Computing”, in which she
pointed out that “(transparent computing) represents for us the direction
that we believe we need to go as an industry. And it’s the next step really
beyond ubiquitous computing.”

The basic idea behind transparent computing is simple: give developers just
one basic platform on which to develop their applications, and make it
possible for these applications to run on any other platform. A formal model
of transparent computing has been proposed, which is a cloud-style paradigm.
As described by James, transparent computing “is really about allowing
experiences to seamlessly cross across different platforms, both
architectures and operating system platform boundaries”. The key idea of
transparent computing is to logically separate hardware and software
(including operating systems) and to separate computation and memory.
Specifically, all the required software and data are centralized on central
servers, and streamed to the clients on demand to carry out the computing
tasks leveraging the local CPU and memory resources. Compared with other
cloud computing models, transparent computing has the following desired
features: (1) user and application transparency; (2) heterogeneous OS
support; (3) streaming delivery; (4) supports of various devices; and (5)
enhanced security.

Transparent computing has proposed new challenges in the research of
computer software and systems:

From user’s perspectives:
_ user transparency (in paradigms, systems, applications, and services);
_ user machine’s efficiency and security;
_ privacy protection and system reliability; and
_ local resource scheduling and management.

From system’s perspectives:
_ standardized software-hardware interface;
_ device and user virtualization;
_ data consistence and security;
_ multiple-user system performance; and
_ operating system modularization.

This journal Special Issue in the IEEE Transaction on Computers will provide
the scientific community a dedicated forum for discussing new research and
development in transparent computing. The Special Issue invites original
research papers that make significant contributions to the state-of-the-art
that advance the fundamental understanding, technologies, concepts, and
applications in transparent computing.

Open for Submissions in ScholarOne Manuscripts: October 31, 2014
Closed for Submission: November 30, 2014
Results of First Round of Review: January 25, 2015
Submission of Revised Manuscripts: February 20, 2015
Results of Second Round of Review: March 15, 2015
Publication Materials Due: March 31, 2015

Prospective authors are invited to submit their manuscripts electronically
after the open for submissions date, adhering to the IEEE Transactions on
Computers guidelines at

Please submit your papers through the online system
( and be sure to select the special
issue or special section name. Manuscripts should not be published or
currently submitted for publication elsewhere. Please submit only full
papers intended for review, not abstracts, to the ScholarOne portal. If
requested, abstracts should be sent by e-mail to the Guest Editors directly.

Jianer Chen, Texas A&M University, USA,
Yaoxue Zhang, Central South University, P.R. China,

Start: October 1, 2014
End: November 30, 2014

November 7, 2014

Call for Papers: Special Issue on Optimization of Parallel Scientific Applications with Accelerated HPC

Submitted by Javier Garcia
International Journal of Computers & Electrical Engineering

Call for Papers: Special Issue on Optimization of Parallel Scientific
Applications with Accelerated HPC


Since 2011, the most powerful supercomputers systems
ranked in the Top500 list have been hybrid systems composed
of thousands of nodes that includes CPUs and accelerators,
as Xeon Phi and GPUs. Programming and deploying applications
on those systems is still a challenge due to complexity of the
system and the need to mix several programming interfaces
(MPI, CUDA, Intel Xeon Phi) in the same application. This special
issue is aimed at exploring the state of the art of developing applications
in accelerated massive HPC architectures, including practical issues
of hybrid usage models with MPI, OpenMP, and other accelerators
programming models. The idea is to publish novel work on the use
of available programming interfaces (MPI, CUDA, Intel Xeon Phi)
and tools for code development, application performance optimizations,
application deployment on accelerated systems, as well as the
advantages and limitations of accelerated HPC systems. Experiences
with real-world applications, including scientific computing, numerical
simulations, healthcare, energy, data-analysis, etc. are also encouraged.

The topics of specific interest for this Special Issue include the following:

Hybrid and heterogeneous programming with MPI and accelerators.
Performance evaluation of scientific applications based on accelerators.
Automatic performance tuning of scientific applications with accelerators.
Integrating accelerators on existing HPC run-times and middlewares.
Energy efficient HPC solutions based on accelerators.
Storage cache solutions based on SSD accelerators.
Real-world scientific and engineering applications using accelerated HPC.


Submitted papers must be written in English and must describe
original research that has not been published, and is not currently
under review by other journals or for conferences. The papers should
be submitted via journal’s submission website and should adhere to
standard formatting requirements. The author guidelines for preparation
of manuscripts are available online. Manuscripts should be no longer
than 20 pages, including the title page, abstract, or references. All
manuscripts and any supplementary material should be submitted
through the Elsevier Editorial System (EES) at the location indicated.
The authors must choose the Article Type “SI-hpc” at the time of

The special issue will invite extended versions of the best papers
of ESAA 2014, “International Workshop on Enhancing Parallel
Scientific Applications with Accelerated HPC” at the EuropMPI/Asia
2014 on September 2014 in Kyoto, but it is also open to other authors.
For work that has been published previously in the workshop or conference,
it is required that submissions to the special issue have at least 30%
new content/contribution. Each submission will be peer-reviewed to
ensure a very high quality of papers selected for the Special Issue.


Submission of papers: November 1st 2014
Communication of first round of review results: January 15th 2015
Submission of revised manuscript: February 15th 2015
Notification of acceptance: April 1st 2015
Final paper due: May 1st 2015
Publication date: August 2015


Jesus Carretero,
Universidad Carlos III de Madrid, Spain

Javier Garcia-Blas,
Universidad Carlos III de Madrid, Spain

Maya Neytcheva,
Uppsala University, Sweden

Start: November 7, 2014
End: November 7, 2014

November 14, 2014

Call for Papers: ASPLOS SRC 2015

Submitted by Onur Mutlu
ACM Student Research Competition

Important Dates
Abstract submission: 11:59pm CST Friday November 14, 2014
Acceptance notification: 11:59pm CST Friday January 16, 2015
Poster Session for Accepts: Monday March 16, 2015
Presentations for Finalists: Monday March 16, 2015

ASPLOS is the premier forum for multidisciplinary systems research
spanning computer architecture and hardware, programming languages and
compilers, operating systems and networking, as well as applications
and user interfaces. The 2015 conference will be held in Istanbul,
Turkey, a city where two continents meet on the blue waters of the
Bosphorus to offer an abundance of unique natural, historical,
cultural, and culinary experiences.

The 20th International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS) invites
participation in the ACM Student Research Competition (SRC). Sponsored
by ACM and Microsoft Research, the SRC is a forum for undergraduates
and graduate students to share their research results, exchange ideas,
and improve their communication skills while competing for
prizes. Students accepted to participate in the SRC are entitled to a
travel grant (up to $500) to help cover travel expenses. The top 3
undergraduate and graduate winners will receive all of the following

1. Monetary prizes of $500, $300, and $200, respectively.

2. An award medal (gold, silver or bronze) and a two-year
complimentary ACM membership with a subscription to ACM’s Digital

3. The names of the winners and their placement will be posted on the
ACM SRC web site.

4. In addition, the first place winner in each category
(undergraduate, graduate) will receive an invitation to participate in
the SRC Grand Finals, an on-line round of competitions among the first
place winners of individual conference-hosted SRCs. The top three
graduate and undergraduate Grand Finalists will receive an additional
$500, $300, and $200, respectively, along with Grand Finalist medals
(gold, silver, bronze). Grand Finalists and their advisors will be
invited to the Annual ACM Awards Banquet for an all-expenses-paid
trip, where they will be recognized for their accomplishments, along
with other prestigious ACM award winners, including the winner of the
Turing Award.

The SRC consists of two rounds: a poster session and a presentation
session. A panel of judges will select a number of finalists from the
poster session, who will be invited to the presentation session at
ASPLOS 2015 and compete for the prizes. The evaluation will be
concentrated on the quality of both visual and oral presentation, the
research methods, and the significance of contribution. You can find
more information on the ACM Student Research Competition site

A participant in the SRC must meet all following conditions:

* The participant must submit an up to 800-word abstract outlining the
content of a poster that is going to be presented during the

* The abstract must include the poster title, author names,
affiliations, and the name of the academic advisor.

* It should describe the research problem, motivation and background,
techniques and results, and the prospect for clearly and concisely
conveying the work in a poster format.

* It should state the novelty and contributions of the work

* The submission deadline is November 14th, 2014 at 23:59 CST.

* The abstract must have not appeared before. Novelty is one of the
criteria for selection.

* The abstract and the poster must be authored solely by the

* The participant can be from anywhere in the world, but must be an
ACM student member, and must maintain an undergraduate or graduate
student status as of November 14, 2014.

* In your submission, please indicate whether you are an undergraduate
or a graduate student.

* You may join ACM prior to entering. Basic student membership is $19
per year or less

For each accepted SRC poster, a one-page extended abstract in the ACM
format will be included in the ASPLOS 2015 conference proceedings. The
content, however, can be included in a future submission to other
conferences or journals.

For questions regarding the submission process, or for additional
information, clarifications, or questions, please contact the ACM
Student Research Competition Co-chairs, Eren Kursun
( and Gurhan Kucuk (

The ACM Student Research Competition at ASPLOS 2015 is sponsored by
the ACM and Microsoft Research.

Start: November 14, 2014
End: November 14, 2014
Venue: Istanbul, Turkey

November 25, 2014

Call for Papers: VEE 2015

Submitted by Angela Demke Brown

VEE’15: 11th ACM international conference on Virtual Execution Environments
Co-located with ASPLOS 2015
March 14-15, 2015
Istanbul, Turkey

Tuesday, November 25, 2014 (11:59pm, PST)

The 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution
Environments (VEE’15) brings together researchers and practitioners from
different computer systems domains to interact and share ideas in order to
advance the state of the art of virtualization and broaden its applicability.

VEE’15 accepts both full-length and short papers. Both types of submissions are
reviewed to the same standards and differ primarily in the scope of the ideas
expressed. Short papers are limited to half the space of full-length papers.
The program committee will not accept a full paper on the condition that it is
cut down to fit in a short paper slot, nor will it invite short papers to be
extended to full length. Submissions will be considered only in the category
in which they are submitted.

We invite authors to submit original papers related to virtualization across
all layers of the software stack down to the microarchitectural level.
Topics of interest include (but are not limited to):
– virtualization support for programs and programmers;
– architecture support for virtualization;
– operating system support for virtualization;
– compiler and programming language support for virtualization;
– runtime system support for virtualization;
– virtual I/O, storage, and networking;
– memory management;
– management technologies for virtual environments;
– performance analysis and debugging for virtual environments;
– virtualization technologies applied to specific problem domains such as
cloud, HPC, realtime, power management, and security.

Submission Deadline: Tuesday, November 25, 2014 (11:59pm, PST)
Author Rebuttal: Friday – Saturday, January 23 – 24, 2015
Author Notification: Wednesday, January 28, 2015
Camera-ready Deadline: Thursday, February 12, 2015 (11:59pm, PST)

Ada Gavrilovska (Georgia Institute of Technology)

Angela Demke Brown (University of Toronto)
Bjarne Steensgaard (Microsoft Research)

Jonathan Appavoo (Boston University)
Haibo Chen (Shanghai Jiao Tong University)
Dilma Da Silva (Texas A&M University)
Amer Diwan (Google)
Daniel Frampton (Microsoft Research)
David Gregg (Trinity College Dublin)
David Grove (IBM Research)
Vishakha Gupta (Intel)
Tomas Kalibera (Purdue University)
Kenichi Kourai (Kyushu Institute of Technology)
Priya Nagpurkar (IBM Research)
Donald Porter (Stony Brook University)
Jennifer Sartor (Ghent University)
Ravi Soundararajan (VMWare)
Gael Thomas (LIP6)
Timothy Wood (GWU)

Start: November 25, 2014
End: November 25, 2014

December 10, 2014

Call for Papers: Performance and Power Issues in Multi/Many Core Architecture

Submitted by Hitoshi OI
Performance and Power Issues in Multi/Many Core Architecture,
a special session in International Symposium on Integrated Circuits
(ISIC) 2014, Singapore, December 10 to 12, 2014

Call for papers:

This special session is aimed to attract the interests
of people working in various aspects of multi/many core
architecture, from the circuit level to the application level,
stimulate the discussion and share and exchange their experiences
and knowledge.

Topics of interests for the special session include
(but not limited to):

– Performance and power-efficiency optimization,
– Heterogeneous multi/many core: architectural design
and run-time support,
– Parallelization libraries and tools,
– Performance and power consumption modeling methodologies,
– Design strategies for performance and power-efficiency in
circuit, architecture and software levels,
On-chip interconnect: architecture, protocol and routing,
– Memory hierarchy architecture and protocol.

Important Dates:

5/15: Title and abstract submission
(send by email to p2m2ca at
6/1: Full paper submission
(use the Paper Upload page of ISIC 2014 )
9/1: Notification of Paper Acceptance
10/15: Submission of Final Manuscript Papers

Organizing Members:

Hitoshi Oi, University of Aizu (JP)
Joao Pedro Pedroso, University of Porto (PT)
Ines Dutra, University of Porto (PT)
Xiongfei Liao, Intel (MY)
Senthilkumar Jayapal, Intel (MY)
Jorge Chavez, Cinvestav (MX)
Amilcar Meneses, Cinvestav (MX)
Yao-Min Cheng, Oracle (US)

For more information, please refer to
ISIC 2014 web site
or send email to p2m2ca at

Start: December 10, 2014
End: December 12, 2014
Venue: Singapore

December 13, 2014

Call for Papers: Workshop on Near-Data Processing

Submitted by Boris Grot

Co-located with MICRO-47
Cambridge, UK

Paper submissions due: Friday October 17, 2014
Notification: Tuesday November 4th, 2014
Final Paper Due: Monday December 8th, 2014

Computing in large-scale systems is shifting away from the traditional
compute-centric model to a much more data-centric one. This transition is
driven by the evolving nature of what computing comprises, no longer dominated
by the execution of arithmetic and logic calculations but instead dominated by
large data volume and the cost of moving data to the locations where
computations are performed. Data movement impacts performance,
energy-efficiency and reliability. These trends are leading to changes in the
computing paradigm driven by the notion of moving computation to the data in a
so-called Near-Data Processing approach, which seeks to perform computations
in the most appropriate location based on where data resides and what needs to
be done with it.

This workshop is intended to bring together experts from academia and industry
to share advances in the development of Near-Data Processing systems
principles, with emphasis on large-scale systems. Topics of interest include
but are not limited to:
- Analysis of applications illustrating the potential for Near-Data Processing
- System and software architectures for Near-Data Processing
- Programming models for distributed and heterogeneous infrastructures
driven by location of the data
- Processing/Memory/Storage architectures and microarchitectures for Near-Data
- Performance evaluation of Near-Data Processing systems and subsystems
- Energy-efficiency and reliability analysis and evaluation of Near-Data

Two kinds of papers are invited:
- Technical papers (4-6 pages) with preliminary results.
- Position papers (3 pages maximum) on directions for research and development.


Rajeev Balasubramonian , University of Utah
Boris Grot , University of Edinburgh
Jaime Moreno , IBM TJ Watson Research Center
Ravi Nair , IBM TJ Watson Research Center


Rajeev Balasubramonian , University of Utah
Boris Grot , University of Edinburgh
Jeff Draper , USC/ISI
Ron Dreslinski, University of Michigan
Maya Gokhale , Lawrence Livermore National Laboratory
Nuwan Jayasena, AMD Research
Jaime Moreno , IBM TJ Watson Research Center
Arrvindh Shriraman , Simon Fraser University

Further details and submission instructions available at

Start: December 13, 2014
End: December 13, 2014
Venue: Cambridge, UK

Call for Participation: MICRO-47

Submitted by Ronald Dreslinski

The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47)
December 13-17, 2014
Cambridge, UK

Micro-47 registration portal is live NOW.
You can take advantage of early bird registration until Nov. 12!

The International Symposium on Microarchitecture (MICRO) is the premier forum
for the presentation and discussion of new ideas in microarchitecture,
compilers, hardware/software interfaces, and design of advanced computing
and communication systems. The goal of MICRO is to bring together researchers
in the fields of microarchitecture, compilers, and systems for technical
exchange. The MICRO community has enjoyed having close interaction between
academic researchers and industrial designers ­ we aim to continue and
strengthen this longstanding tradition at the 47th MICRO in Cambridge, England.

On behalf of the Micro47 organization team, we look forward to seeing you
in Cambridge.

Start: December 13, 2014
End: December 17, 2014
Venue: Cambridge, UK

January 14, 2015

Call for Participation: RISC-V Workshop and Bootcamp

Submitted by Krste Asanovic

1st RISC-V Workshop and Boot Camp

January 14-15, 2015
Monterey, CA, USA

RISC-V (pronounced “risk-5″) is a new instruction set architecture
(ISA) that was originally designed to support computer architecture
research and education, but which we now hope will become a standard
open architecture for industry implementations. RISC-V was originally
developed in the Computer Science Division of the EECS Department at
the University of California, Berkeley, but has been made freely
available open-source under the BSD license for anyone to use.

The goals of this workshop are to inform the community of recent
activity in the various RISC-V projects underway around the globe and
to build consensus on future steps in the RISC-V project, while the
bootcamp provides an opportunity to learn about the existing RISC-V
infrastructure from the RISC-V development team. The workshop and
bootcamp will feature demos of multiple RISC-V silicon tapeouts as
well as FPGA board designs and associated software tools.

Space will be limited, so please register early!

Early Bird registration ends December 1.

Start: January 14, 2015
End: January 15, 2015
Venue: Monterey, CA

January 15, 2015

Call for Tutorials and Workshops: ISPASS 2015

Submitted by Kelly Shaw
ISPASS 2015 Call for Tutorial and Workshop Proposals

Call for Tutorial Proposals

Tutorial proposals are solicited for ISPASS-2015. Tutorials will be
held on March 29 in Philadelphia, PA.

Proposals for both half- and full-day tutorials are solicited on any
topic that is relevant to the ISPASS audience. Tutorials that focus on
workload characterization and analysis tools and techniques that
enable research across layers of the computational stack are strongly

In previous years, tutorials seeking to achieve any of the following
goals have been particularly successful:
* Describe an important piece of research/experimental infrastructure.
* Educate the community on an emerging topic.

Submission deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

Proposals should provide the following information:
* Title of the tutorial
* Presenter(s) and contact information
* Proposed duration (full day, half day)
* 1-2 paragraph abstract suitable for tutorial publicity
* 1 paragraph biography per presenter suitable for tutorial publicity
* Short description (for evaluation). This should include:
– Tutorial scope and objectives
– Topics to be covered
– Target audience
– If the tutorial has been held previously, the location
(i.e., conference), date, and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton ( with the subject
“ISPASS 2015 Tutorial Proposal”. Submissions will be acknowledged via


Call for Workshop Proposals

Workshop proposals are solicited for ISPASS-2015. Workshops will be
held on March 29 in Philadelphia, PA.

Proposals related to power/performance analysis and workload
characterization as it relates to computer architecture, operating
systems, programming languages/compilers in current and emerging areas
such as datacenters and cloud computing, systems based on non-volatile
memory technologies, mobile technologies, large scale data analysis,
smart infrastructure, and extreme scale computing are encouraged.

Submission Deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

Please include in your proposal:
* Title of the workshop
* Organizers and their affiliations
* Sample call for papers
* Duration – Half-Day or Full Day
* If the workshop was previously held, the location
(conference), date, and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton ( with the subject
“ISPASS 2015 Workshop Proposal”. Submissions will be acknowledged via

Start: January 15, 2015
End: January 15, 2015

January 16, 2015

Call for Papers: IEEE Micro Special Issue on Heterogeneous Computing

Submitted by Lieven Eeckhout
Call for Papers: IEEE Micro Special Issue on Heterogeneous Computing

Guest Co-Editors:
Dean Tullsen (UCSD)
Ravishankar Iyer (Intel)

Submissions due: Jan 16, 2015
Publication date: July-August 2015

Heterogeneity is widely accepted as a fruitful avenue to improve
performance and power/energy/thermal-efficiency in the face of continued
technology miniaturization (Moore’s Law) and slowed supply voltage
reduction (end of Dennard scaling). Heterogeneity comes in many flavors
ranging from Systems-on-Chip (SoCs) with specialized hardware accelerators,
to hybrid CPU/GPU architectures, to single-ISA heterogeneous multi-cores
with different core types, to multi-ISA heterogeneous multi-cores in which
different core types implement different Instruction-Set Architectures (ISA).
Architects have explored and built heterogeneous architectures
across a broad spectrum of computing devices including embedded systems,
mobile devices, datacenters, and High-Performance Computing (HPC)
supercomputers. While the performance and power/energy opportunities
have been outlined, important challenges are yet to be studied regarding
architecture, accelerators, hardware/software interface, run-time support,
compilation, programming models, and performance evaluation. The goal of
this Special Issue is to present the latest state-of-the-art results
in the broad area of heterogeneous computing systems.

Areas of interest include, but are not limited to:
- Heterogeneous architectures, including:

  • o System-on-Chip (SoC) with accelerators
  • o CPU/GPU systems
  • o Single-ISA heterogeneous multi-cores
  • o Multi-ISA heterogeneous multi-cores

- Roadmaps and commercial trends in heterogeneous architectures
- Trade-offs in performance, power, energy, thermal, reliability, code
portability and programmability due to heterogeneity
- Case studies of heterogeneous architectures in embedded system design,
mobile computing, HPC, data centers, etc.
- Accelerator architectures and interfaces
- Platform support for heterogeneous and accelerator architectures
- Hardware/software interactions on heterogeneous architectures, including
OS scheduling and compilation
- Programming models and runtime support for heterogeneous architectures
- Workloads particularly suited for heterogeneity
- Performance evaluation of heterogeneous architectures
- Experiences with real heterogeneous platforms

Submission procedure:
Log onto IEEE CS Manuscript Central
( and submit your manuscript.
Please direct questions to the IEEE Micro magazine assistant
( regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and
PDF. Manuscripts should not exceed 5,000 words including references, with
each average-size figure counting as 150 words toward this limit.
Please include all figures and tables, as well as a cover page with author
contact information (name, postal address, phone, fax, and e-mail address)
and a 200-word abstract. Submitted manuscripts must not have been
previously published or currently submitted for publication elsewhere, and
all manuscripts must be cleared for publication. All previously published
papers must have at least 30% new content compared to any conference (or
other) publication. Accepted articles will be edited for structure, style,
clarity, and readability. For more information, please visit
the IEEE Micro Author Center

Important dates:
Initial submissions due: Jan 16, 2015
Author notification: March 2, 2015
Revised papers due: March 20, 2015
Final version due: April 23, 2015
Publication timeframe: July-August 2015

Contact the Guest Co-Editors Dean Tullsen ( and
Ravi Iyer (, or the Editor-in-Chief
Lieven Eeckhout (

Start: January 16, 2015
End: January 16, 2015