Calendar of Events

Event List Calendar
iCal Import

November 1, 2014

Call for Papers: IJPP Special Issue on Workload Optimized Systems

Submitted by Parijat Dube

Springer International Journal of Parallel Programming (IJPP)
Special Issue on Workload Optimized Systems


The slowdown in Moore’s Law makes it increasingly important to optimize
systems around specific workloads. Such workload optimized systems have
hardware and/or software specifically designed to run well for a particular
workload or workload class. Such systems include, but are not limited to
traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory
accelerators, I/O accelerators, hybrid systems, and IT appliances. This
workload optimized system approach contrasts to the broad general purpose
direction of computing over many decades. The workload optimized systems
approach is growing in importance, as we see in systems from cellphones to
tablets to routers to game machines to Top500 supercomputers, and IT
appliances such as IBM’s DataPower and Netezza, and Oracle’s Exadata. The
goal of this special issue is to foster awareness in industry and academic
community on workload optimized systems and to expose cross hw/sw stack
unique systems and software research challenges associated with such
systems. All submitted papers are subject to the same review process as those
papers accepted for publication in the regular issues. The special issue seeks
original papers on a range of topics related to workload optimized systems
including, but not limited to

- GPUs, FPGAs, ASIC Accelerators
- Memory and I/O accelerators
- Network accelerators
- Storage optimized systems
- System level accelerators
- IT Appliances
- Systems in specific domains like analytics, cloud, cognitive, mobile etc.
- Converged/Hybrid/Heterogeneous systems
- Cross hardware/software stack design and optimization
- Programming models for workload optimized systems
- Measurements and Experimentation
- Workload characterization and profiling
- Performance modeling and optimization
- Workload scheduling and orchestration
- Runtime management systems
- Industrial Experiences

Manuscript due: March 27, 2015
First decision notification: June 5, 2015
Revision due: July 10, 2015
Final decision notification: August 14, 2015
Final version due: September 11, 2015

Authors are encouraged to submit high-quality, original work that
has neither appeared in, nor is under consideration by, other
journals. All papers will be reviewed following standard reviewing
procedures for the Journal.
Papers must be prepared in accordance with the Journal guidelines:

Manuscripts must be submitted to:
Choose “S.I.: Workload Optimized Systems” as the article type.

Erik Altman, IBM Research, Yorktown Heights, NY.
Parijat Dube, IBM Research, Yorktown Heights, NY.


Start: November 1, 2014
End: October 1, 2015

July 8, 2015

Call For Papers: IA^3 2015

Submitted by Antonino Tumeo

5th Workshop on Irregular Applications: Architectures and Algorithms (IA^3)
in conjunction with SC’15
Austin, TX, USA
November 15, 2015

Irregular applications span a broad range of applications with unpredictable
memory access patterns, control structures, and/or network transfers. They
typically use pointer-based data structures such as graphs and trees, often
present fine-grained synchronization and communication, and generally
operate on very large data sets. They have a significant degree of latent
parallelism, which however is difficult to exploit due to their complex
behavior. Current high performance architectures rely on data locality and
regular computation to tolerate access latencies, and often do not cope
well with the requirements of these applications. Furthermore, irregular
applications are difficult to scale on current supercomputing machines,
due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields,
such as social network analysis, bioinformatics, semantic graph databases,
bioinformatics, Computer Aided Design (CAD) and computer security. Many
of these application areas also process massive sets of unstructured data,
which keep growing exponentially. Addressing the issues of irregular
applications on current and future architectures will become critical to
solve the scientific challenges of the next few years.

This workshop seeks to explore solutions for supporting efficient execution
of irregular applications in the form of new features at the level of the
micro- and system-architecture, network, languages and libraries, runtimes,
compilers, analysis, algorithms. Topics of interest, of both theoretical and
practical significance, include but are not limited to:

- Micro- and System-architectures
- Network and memory architectures
- Heterogeneous, custom and emerging architectures (GPUs, FPGAs,
multi- and many-cores, processors-in-memory)
- Modeling, simulation and evaluation of architectures
- Innovative algorithmic techniques
- Parallelization techniques and data structures
- Approaches for managing massive unstructured datasets
- Languages and programming models
- Library and runtime support
- Compiler and analysis techniques
- High performance data analytics, including graph databases

Besides regular papers, papers describing work-in-progress or incomplete
but sound, innovative ideas related to the workshop theme are also
encouraged. We solicit both 8-page regular papers and 4-page position

Abstract submission: 17 August 2015
Position or full paper submission: 24 August 2015
Notification of acceptance: 2 October 2015
Camera-ready position and full papers: 9 October 2015
Workshop: 15 November 2015

All submissions should be in double-column, single-spaced letter format, using
9-point size fonts, with at least one-inch margins on each side. Submitted manuscripts
may not exceed eight pages in length for regular papers and four pages for position
papers including figures, tables and references.
Submission site:

The proceedings of the workshop will be published in cooperation with ACM SIGHPC.

Workshop chairs:
Antonino Tumeo, Pacific Northwest National Laboratory,
John Feo, Context Relevant,
Oreste Villa, NVIDIA Research,

Program Committee:
Scott Beamer, University of California Berkeley, US
David Brooks, Harvard University, US
Vito Giovanni Castellana, Pacific Northwest National Laboratory, US
Georgi Gaydadjiev, Chalmers University, SWE
Maya Gokhale, Lawrence Livermore National Laboratory, US
John Leidel, Texas Tech University, US
Kamesh Madduri, Penn State University, US
Richard Murphy, Micron, US
Onur Mutlu, Carnegie Mellon University, US
Walid Najjar, University of California Riverside, US
Jacob Nelson, University of Washington, US
Kunle Olukotun, Stanford University, US
Timothy Mattson, Intel, US
Gianluca Palermo, Politecnico di Milano, ITA
Fabrizio Petrini, IBM TJ Watson, US
Keshav Pingali, University of Texas Austin, US
Sébastien Rumley, Columbia University, US
Erik Saule, University of Carolina Charlotte, US
John Shalf, Lawrence Berkeley National Laboratory, US
Michela Taufer, University of Delaware, US
Pedro Trancoso, University of Cyprus, CYP

Start: July 8, 2015
End: August 24, 2015
Venue: Austin

August 6, 2015

Call For Papers: NAS 2015

Submitted by Resit Sendag

10th IEEE International Conference on Networking, Architecture and Storage (NAS)
Boston, Massachusetts, USA
August 6-7, 2015

Sponsored by IEEE Computer Society’s Technical Committees on Computer
Architecture (TCCA), Parallel Processing (TCPP) and Distributed Processing

– Paper Submission: April 3, 2015
– Notification: May 20, 2015
– Camera-Ready Copy: June 29, 2015

The International Conference on Networking, Architecture, and Storage (NAS)
provides a high-quality international forum to bring together researchers and
practitioners from academia and industry to discuss cutting-edge research on
networking, high-performance computer architecture, and parallel and
distributed data storage technologies. NAS 2015 will expose participants to the
most recent developments in the interdisciplinary areas.

Authors are invited to submit previously unpublished work for possible
presentation at the conference. Papers should be submitted for double-blind
review. The program committee will nominate best papers for recognition in the
three conference topic areas. All papers will be evaluated based on their
novelty, fundamental insight, experimental evaluation, and potential for long
-term impact; new-idea papers are encouraged. All accepted papers will be
published in IEEE digital library.

Papers are solicited in fields that include, but are not limited to, the

- Processor, cache, memory system architectures
- Parallel and multi-core architectures
- GPU architecture and programming
- Data-center scale architectures
- Architecture for handheld or mobile devices
- Accelerator-based architectures
- Application-specific, reconfigurable or embedded architectures
- HW/SW co-design and tradeoffs
- Power and energy efficient architectures and techniques
- Effects of circuits and emerging technology on architecture
- Cloud and grid computing
- Architecture, networking or storage modeling and simulation methodologies
- Non-volatile memory technologies
- Mobile and wireless networks
- Ad hoc and sensor networks
- Network security
- Network information theory
- Software defined networking
- Network applications and services
- Network architecture and protocols
- Virtual and overlay networks
- Network modeling and measurement
- Storage management
- Storage performance and scalability
- File systems, object-based storage
- Energy-aware storage
- SSD architecture and applications
- Parallel I/O
- Cloud storage
- Storage virtualization and security
- Software defined storage
- Big Data infrastructure
- Big Data services and analytics

General Chair
– Resit Sendag (U of Rhode Island)
Program Co-Chairs:
– Jun Wang (U of Central Florida)
– Iris Bahar (Brown U)
Vice Program Chairs:
– Networking: Weikuan Yu (Auburn U) & Haiying Shen (Clemson U)
– Architecture: Martin Herbordt (Boston U) & Tali Moreshet (Boston U)
– Storage: Xiaosong Ma(Qatar Comp Ins & NC State) & Ali Butt(Virginia Tech)
Local Arrangements Chair:
– Ningfang Mi (Northeastern U)
Publications Chair:
– Gus Uht (U of Rhode Island)
Registration Chair:
– Yan Sun (U of Rhode Island)
Finance Chair:
– Yan Luo (U of Massachussetts-Lowell)
Industry Liaison Chair:
– Ming Zhang (EMC)
Publicity Co-chairs:
– Chengsheng Xie (Huazhong U Sci. Tech)
– André Brinkmann (Universitat Mainz)
– Ramon Bertran (IBM)
– Alper Buyuktosunoglu (IBM)
Submission Chair:
– Xunchao Chen (U of Central Florida)
Web Chair:
– Ibrahim Burak Karsli (U of Rhode Island)
Steering Committee
– Xubin He (Virginia Commonwealth U)
– Changsheng Xie(Huazhong U of Sci.Tech)
– André Brinkmann (U Mainz)
– Jian Li (IBM Austin Research Lab)
– Tao Li (University of Florida)
– Marco D Santambrogio (Politec. Milano)
– Hongbin Sun (Xi’An Jiaotong U)

Networking Track
– Weikuan Yu, Auburn University (co-chair)
– Haiying Shen, Clemson University (co-chair)
– Sarp Oral, Oak Ridge National Lab
– Shane Canon, Lawrence Berkeley National Lab
– Richard Graham, Mellanox
– Amith R Mamidala, IBM
– Jian Tan, IBM
– Ronald Brightwell, Sandia National Lab
– Gerald F II Lofstead, Sandia National Lab
– Wenjun Wu, Beihang University
– Jia Rao, University of Colorado Cold Springs
– Seung-Jong Park, Louisiana State University
– Xin Yuan, Florida State University
– Saad Biaz, Auburn University
– Kang Chen, Clemson University
– Yaohang Li, Old Dominion University
– Shan Lin, Temple University
– Chuan Yue, University of Colorado Colorado Springs
– Mengjun Xie, University of Arkansas at Little Rock
– Lei Yu, Georgia State University
– Yang Guo, Bell Labs
– Yongning Tang, Illinois State University
– Fangzhe Chang, Bell Labs, Alcatel-Lucent
– Feng Deng, Clemson University
– Weichen Liu, Chongqing University
– Zhi Wang, Tsinghua University
– Xiaojun Hei, Huazhong University of Science and Technology
– Yuan He, Hong Kong University of Science and Technology
– Di Wu, Sun Yat-Sen University
– Liudong Xing, University of Massachusetts Dartmouth
– Gang Zhou, College of William and Mary
– Jiangyi Hu, Devry University
– Junwei Cao, Tsinghua University
– Wenzhong Li, Nanjing University
– Surendar Chandra, EMC Data Protection and Availability Division
– Wei Zhang, Hong Kong University of Science and Technology
– Yao Liu, SUNY Binghamton
– Chiu Tan, Temple University
– Kyoungwon Suh, Illinois State University
Architecture Track
– Martin Herbordt, Boston University (co-chair)
– Tali Moreshet, Boston University (co-chair)
– Lide Duan , University of Texas at San Antonio
– Cesare Ferri , Marvel
– Mark Hempstead , Drexel University
– Ajay Joshi , Boston University
– Dong Li , Qualcomm
– Xiaoyao Liang , Shanghai Jiao Tong University
– Yan Luo , University of Massachusetts Lowell
– Vijay Nagarajan , University of Edinburgh
– Gi-Ho Park , Sejong University
– Dmitry Ponomarev , SUNY
– Kelly Shaw , University of Richmond
– Magnus Sjalander, Uppsala University
– Bharat Sukhwani, IBM
– Radu Teodorescu , Ohio-State University
– Jing Wang , Capital Normal University
– Jason Xue , City University of Hong Kong
– Zhibin Yu , Shenzhen Institute of Advanced Technology
– Jidong Zhai , Tsinghua University
– Dongyuan Zhan , AMD
– Chuanjun Zhang , Intel
– Wei Zhang , Virginia Commonwealth University
– Ping Zhou , Intel
– Zhichun Zhu , University of Illinois at Chicago
Storage Track
– Ali Butt, Virginia Tech (co-chair)
– Xiaosong Ma, Qatar Comp Res Inst and NC State (co-chair)
– Youngjae Kim, Oak Ridge National Laboratory
– Gary Liu, Oak Ridge National Laboratory
– Fei Meng, North Carolina State University and PureStorage
– Xing Wu, Amazon
– Xuanhua Shi, Huazhong University of Science and Technology
– Zhe Zhang, Cloudera
– Sudharshan Vazhkuda, ORNL
– Shuibing He, IIT
– Yong Chen, TTU
– Suren Byna, LBL
– Medha Bhadkamkar, Symantec Research Labs
– Avani Wildani, Salk Institute
– Min Li, IBM TJ Watson Research Center
– Aayush Gupta, IBM Almaden Research Center
– Lei Tian, Tintri
– Tao Xie, San Diego State University
– Song Jiang, Wayne State University
– Abhishek Chandra, University of Minnesota
– Jay Lofstead, Sandia National Laboratories
– Jinho Hwang, IBM Research
– Yifeng Zhu, University of Maine
– Xiao Qin, Auburn University
– Douglas Thain, University of Notre Dame
– Alan Sussman, University of Maryland
– Peter Varman, Rice University
– Nitin Agrawal, NEC Labs
– Fang Zheng, IBM T.J. Watson Research Center
– Qingdong Wang, University of Central Florida/Huizhou University

Start: August 6, 2015
End: August 7, 2015
Venue: Boston, MA

Call for Participation: NAS 2015

Submitted by Ramon Bertran

The IEEE International Conference on Networking, Architecture, and Storage (NAS 2015)
Boston, MA, USA
August 6-7, 2015

NAS provides a high-quality international forum to bring together researchers
and practitioners from academia and industry to discuss cutting-edge research
on networking, high-performance computer architecture, and parallel and
distributed data storage technologies. This year, NAS will be held in the Park
Plaza Hotel in downtown Boston, MA during August 6-7, 2015.

Early registration deadline: July 8th, 2015
Hotel reservation deadline: July 6th, 2015

NAS registration web site:

Hotel Reservation web site:


Conference Program:
Final program for the main conference is ready!

Keynote Speakers:
Scott Klasky, Oak Ridge National Laboratory
David Brooks, Harvard University

Complete details at

Start: August 6, 2015
End: August 7, 2015
Venue: Boston

August 26, 2015

Call for Participation: Hot Interconnects 2015

Submitted by Torsten Hoefler

23rd International Symposium on High Performance Interconnects
Oracle Santa Clara Agnews Campus
Santa Clara, California
August 26-28, 2015 (following Hot Chips)

Early Registration: Ends at 11:59 PM (PDT), July 31st, 2015
Last Day for Refunds: 11:59 PM (PDT), August 12, 2015.

Come join us for the 23rd annual IEEE Symposium on High-Performance
Interconnects (Hot Interconnects), to be held August 26-27 (with
tutorials on August 28), 2015, generously hosted by Oracle at the
historic Oracle Agnews Campus, Santa Clara, California.

Hot Interconnects (HotI) is the premier international forum for
researchers and developers of state- of-the-art hardware and
software architectures and implementations for interconnection
networks of all scales, ranging from multi-core on-chip
interconnects to those within systems, clusters, data centers, and
clouds. This yearly conference is attended by leaders in industry
and academia, creating a wealth of opportunities to interact with
individuals at the forefront of this field.

This year’s Hot Interconnects features keynotes from Oracle’s Vice
President of Hardware Development Rick Heatherington, and David
Meyer, the CTO and Chief Scientist of Brocade Communications. There
will be a great lineup of exciting talks, Intel will be discussing
their upcoming OmniPath technology, Facebook will discuss their
efforts in interconnects and VMWare will talk about NFV.

A panel “HPC vs. Datacenter Networks” discussing the intersection
of HPC networking technologies and Data center networking from
experts in both areas from world-leading companies and institutions
will provide a lively debate on what each group can learn from each
other and areas in which they are already converging.

There will be four technical paper sessions covering the cutting
edge in interconnect research and development on cross-cutting
issues spanning computer systems, networking technologies, and
communication protocols for high-performance interconnection
networks. This conference is directed particularly at new and
exciting technology and product innovations in these areas.

Building on last year’s successful technical program comprising
keynotes, technical sessions, and panels on networking for
data centers and high-performance computing, the 2015 edition of Hot
Interconnects will be located at Oracle Agnews Campus in Santa
Clara, CA. This year’s conference focuses on HPC Interconnects and
their use in traditional and non-traditional applications. We hope
you can join us.

A preliminary program and additional conference details are available

Fabrizio Petrini, IBM T.J. Watson

Technical Program Chairs:
Ada Gavrilovska, Georgia Tech
Ryan Grant, Sandia National Laboratories

Tutorial Chair:
Vikram Dham, Kamboi Technologies

Publication Chair:
Luca Valcarenghi, Scuola Superior Sant’Anna

Awards Chair:
Xin Huang, Cyan

Finance Chairs:
Madeleine Glick, University of Arizona
Xinyu Que, IBM T.J. Watson

Registration Chair:
Charlie Perkins, Huawei

Media Chair:
Torsten Hoefler, ETH Zurich

Local Arrangements Chair:
Don Draper, Oracle

Natalia Berezneva

Steering Committee:
Allen Baum, Mill Computing
Keren Bergman, Columbia University
Raj Channa, RBC Capital Markets
Lily Jow, Hewlett Packard
Mark Laubach, Broadcom
John Lockwood, Algo-Logic Systems
Fabrizio Petrini, IBM T.J. Watson
Dan Pitt, Open Networking Foundation

Start: August 26, 2015
End: August 28, 2015
Venue: Santa Clara, CA, USA

September 1, 2015

Call for Papers: ParCo2015 Edinburgh

Submitted by Mark Sawyer
The University of Edinburgh is hosting the International Conference on Parallel
Computing (ParCo) from 1 – 4 September 2015. This is the latest in the series
of biennial ParCo conferences that started in Berlin, 1983. This makes ParCo
one of the longest running international conferences on parallel computing.
Over the years, the conference has established itself as the foremost platform
for exchanging know-how on the newest parallel computing strategies,
technologies,methods, and tools.

The Call for Papers can be found here:

Aims and Scope
The aim of the conference is to give an overview of the state of the art of the
developments, applications, and future trends in parallel computing for the
whole range of platforms. The conference addresses all aspects of parallel
computing, including applications, hardware and software technologies as well
as languages and development environments.

Topic Areas:

Section 1: Algorithms

Design, analysis, and implementation of parallel algorithms in science and
engineering, focusing on issues such as

- Scalability and speedup
- Efficient utilization of the memory hierarchy
- Communication and synchronization
- Data Management and Exploration
- Energy Efficiency.

The parallel computing aspects should be emphasized.

Section 2: Software and Architectures

Software engineering for developing and maintaining parallel software, including

- Parallel programming languages, compilers, and environments
- Tools and techniques for generating reliable and efficient parallel code
- Testing and debugging techniques and tools
- Best practices of parallel computing on multicore, manycore, and stream

Software, architectures and operating systems for all types of parallel
computers may be considered, including multicores, GPU accelerators, FPGA
reconfigurable systems, high-end machines and cloud computing.

Section 3: Applications

The application of parallel computing to solve all types of business,
industrial, scientific, and engineering problems using high-performance
computing technologies, in particular:

- Applications of high-end computers, including exascale
- Applications of multicore / manycore processors
- Applications for heterogeneous systems, including FPGAs, GPUs, etc.
- Cloud and Grid computing applications
- Data intensive (Big Data) analytics and applications.


The scientific programme consists of invited and contributed papers as well as
mini-symposia covering special topics.Papers are presented in parallel sessions
with 20 minutes available per presentation, with an additional five minutes for
discussion.A special session for young researchers as well as an industrial
session and an exhibition are planned.

Contributions :


Contributed papers in English are called for. Extended abstracts of at least
two pages should be submitted in electronic form by 28 February 2015.
Proposals are to be submitted in .pdf-format.

Abstracts should clearly describe the contents of the proposed paper. The
relevance and originality of the contribution must be described and the most
important references included.

At most five relevant keywords must be supplied. Also indicate the preferred
topic area (section 1, 2 or 3) from the list given above.

Submission of paper proposals:

Paper proposals can be submitted using ConfTool at Authors are required to register with the
system before they can enter their proposals.

Full (draft) papers of accepted proposals are due by 31 July 2015.


Proposals for organising a mini-symposium are called for. Such proposals should

- The proposed title of the symposium
- The name and affiliation(s) of the organiser(s)
- A short outline of the contents
- The planned number of papers.

Proposals for organising a mini-symposium can be submitted by 31 March 2015
to the conference office. For any questions about the organisation of a
mini-symposium please contact the conference office.


Extended abstracts of papers: 28 Feb 2015
Proposals for mini-symposia: 31 Mar 2015
Notification of acceptance for presentation at conference: 15 May 2015
Submission of full (draft) papers: 31 Jul 2015
Notification of inclusion of full papers in the proceedings: 30 Sep 2015


The conference proceedings will be published after the conference.

An invitation to authors to present a paper at the conference is based on an
extended abstract or draft paper. Thus, the presentation of a paper at the
conference does not imply an automatic acceptance of the presented paper for
publication in the conference proceedings. All papers presented at the
conference will be refereed at or after the conference. Only accepted papers
will be published.

All papers presented as part of mini-symposia will be considered for
publication in the proceedings. This will be done in liaison with
the organiser(s) of the respective mini-symposium.

Conference Organisation:

ParCo2015 is organised by the non-profit foundation ParCo Conferences in
cooperation with The University of Edinburgh, Scotland, UK.

Conference Committee Chair Gerhard Joubert (Germany/Netherlands)
Program Committee Chair: Mark Parsons (UK)
Organising Committee Chairs: Hugh Leather (UK), Mark Sawyer (UK)
Finance Chair: Frans Peters (Netherlands)


Start: September 1, 2015
End: September 4, 2015
Venue: Edinburgh, UK

Call for Papers: Workshop on Embedded Multicore Systems

Submitted by Kuan-Ching Li

The 2015 International Workshop on Embedded Multicore Systems (ICPP-EMS’2015)
Beijing, China
September 1-4, 2015

to be held in conjunction with
The 44th International Conference on Parallel Processing (ICPP’2015)


Embedded systems with Multicore designs are of major focuses from both
industry and academia. While embedded Multicore systems will look to
play an important role ahead for system designs, many challenging
issues remain. Applications, programming models, architecture designs,
emerging memory architectures, and software tools all need to help for
the advance of embedded Multicore computing ahead.

The 2015 International Workshop on Embedded Multicore Systems
(ICPP-EMS 2015) will bring researchers and experts together to present
and discuss the latest developments and technical solutions concerning
various aspects of embedded Multicore computing.

ICPP-EMS 2015 seeks original unpublished papers focusing on emerging
applications, embedded compilers, embedded memory and architecture
design, DSP/GPU systems, ESLs, embedded Multicore programming models,
and WCET analysis. Moreover, ICPP-EMS 2015 also welcomes
work-in-progress, case studies, visionary idea, new application
challenges, and industrial practice studies.

Topics of Interest
- Memory Architectures for embedded Multicore systems
- Design for emerging embedded memory systems
- Compilers for DSP processors
- Embedded Multicore processors
- Compilers for heterogeneous embedded Multicore systems.
- Programming models for embedded Multicore systems
- Signal processing on embedded Multicore systems
- Multimedia signal processing algorithms on embedded Multicore systems
- Multimedia applications on embedded Multicore systems
- Human-computer interaction on Multicore systems
- Augmented reality applications on Multicore systems
- Software for Multicore, GPU, and embedded architectures
- VM for embedded systems
- 3D IC and Multicore architectures
- Real-time system designs for embedded Multicore environments
- Compiler for low-power
- ESL designs for embedded Multicore systems
- Applications for Automobile electronics of Multicore designs
- Embedded OS designs and performance tuning tools
- Hardware/Software co-design framework
- Embedded devices + cloud computing framework
- Compiler for worst-case execution time analysis
- Formal method for embedded systems

Papers should present original research and should provide sufficient
background material to make them accessible to the community. Full
paper submissions should not exceed 8 pages in standard IEEE
conference format. Papers should be submitted electronically, through

Best and selected papers presented in the workshop will be invited to
appear published in Special Issues of International Journal of
Embedded Systems (IJES), International Journal of High Performance
Computing and Networking (IJHPCN) and International Journal of
Computational​ ​Science and Engineering (IJCSE), Inderscience publishers.

Submission due date: May 1, 2015
Notification date: June 05, 2015
Camera Ready due date: June 20, 2015
ICPP Conference dates: September 1-4, 2015

General Chairs
Kuan-Ching Li, Providence University, Taiwan
Cho-Li Wang, The University of Hong Kong, Hong Kong
Wen Zhi Chen, Zhejiang University, China

Program Chairs
Chen Liu, Clarkson University, USA
Bing Guo, Sichuan University, China
Albert Cohen, INRIA, France

Steering Committee
Jenq Kuen Lee, National Tsing-Hua University, Taiwan
Pen-Chung Yew, University of Minnesota, USA
Roy Ju, Mediatek, USA

International Liaison
Barbara Chapman, University of Houston, USA
Jean-Luc Gaudiot, Univ. of California – Irvine, USA
Shang-Hong Lai, National Tsing-Hua University, Taiwan
Qingguo Zhou, Lanzhou University, China

For additional information, please send your email to PC co-chair
Prof. Chen Liu (

Start: September 1, 2015
End: September 4, 2015
Venue: Beijing, China

Call for Papers: ParaFPGA 2015

Submitted by Erik D’Hollander

Parallel Computing with FPGAs (ParaFPGA 2015)
A Mini-Symposium held in conjunction with ParCo 2015
Edinburgh, UK

Conference date: 1-4 September 2015
Submission deadline : 1 June 2015

ParaFPGA2015 is a Mini-Symposium organized in conjunction with the
Biennial Parallel Computing conference ParCo2015, to be held in
Edinburgh, Scotland, UK on 1-4 September 2015.


ParaFPGA focuses on parallel techniques for using FPGAs as
accelerator in high performance computing areas such as
supercomputing, embedded systems and big data computing.

Field Programmable Gate Arrays emerge as powerful building blocks for
High Performance Systems. The freedom to build tailored
architectures with extremely low power is one of the key milestones
on the path to exascale computing. Recently the major industrial
players invested heavily in high-level synthesis tools and
established well known programming paradigms to facilitate the march
towards programmable hardware. In addition, the famous memory wall
has been alleviated by incorporating processing cores inside the FPGA

Of special interest are design methods, heterogeneous architectures
and algorithms optimized for execution on FPGAs. Design methods
include optimizing the resource utilization, development time and
high-level synthesis tools. Heterogeneous architectures encompass
multi-FPGAs, FPGAs with CPU cores and systems combining FPGAs, GPUs
and CPUs. Algorithms ready-made for FPGAs range from streaming
applications to fast dynamic reconfiguration and feature a
substantial performance increase.

Researchers and practitioners are invited to submit novel
contributions in the areas of high-level synthesis, dynamic
reconfiguration and high performance applications. Papers are
invited on a wide variety of topics related but not limited to:

– optimizing throughput of streaming applications
– non-uniform memory partitioning and data reuse
– heterogeneous on-chip processor and programmable logic codesign
– scalability of multi-core with multi-FPGA architectures
– OpenCL for FPGA applications
– evaluating performance metrics for high-level synthesis
– high-level synthesis techniques and case studies
– high-level partial and dynamic reconfiguration
– performance-driven resource and area optimization

Authors are invited to submit a full paper of maximum 10 pages or an
extended abstract of minimal 4 pages. The approved contributions
will be presented at the conference and the accepted full papers are
published in the ParCo 2015 proceedings. Details regarding the
format, presentation and paper submission are given on the author
guidelines page.

Submission deadline : 1 June 2015
Notification of acceptance : 15 July 2015
Final papers due : 15 August 2015

Steering committee:
- Gerhard Joubert, Conference Committee Chair
- Frans Peters, Finance Chair

Mini-Symposium committee:
- Dirk Stroobandt, Ghent University, Symposium chair
- Erik D’Hollander, Ghent University, Program committee chair
- Abdellah Touhafi, Brussels University, Program committee co-chair

Program committee:
- Abbes Amira, University of the West of Scotland, UK
- Georgi Gaydadjiev, Chalmers University of Technology
- Mike Hutton, Altera, USA
- Tsutomu Maruyama, University of Tsukuba, Japan
- Dionisios Pnevmatikos, Technical University of Crete, Greece
- Viktor Prasanna, University of Southern California, USA
- Mazen A. R. Saghir, Texas A&M University, Qatar
- Donatella Sciuto, Politecnico di Milano, Italy
- Sascha Uhrig, Technical University of Dortmund, Germany
- Sotirios G. Ziavras, New Jersey Institute of Technology, USA


Start: September 1, 2015
End: September 4, 2015
Venue: Edinburgh, UK

Call for Papers: JPDC Special Issue on Energy Efficient Multi-Core and Many-Core Systems

Submitted by Amir Rahmani

Special Issue on Energy Efficient Multicore and Manycore Systems
The Journal of Parallel and Distributed Computing (Elsevier)

Recent trends in the microprocessor industry have important ramifications for
the design of the next generation of high-performance as well as embedded
parallel and network-based systems. By increasing number of cores, it is
possible to improve the performance while keeping the power consumption at the
bay. This trend has reached the deployment stage in parallel and network-based
systems ranging from small ultramobile devices to large telecommunication
servers. It is expected that the number of cores in these systems increases
dramatically in the near future. For such systems, energy efficiency is one of
the primary design constraints. The cessation of Dennard scaling and the dark
silicon phenomenon have limited recent improvements in transistor speed and
energy efficiency, resulting in slowed improvements in multi-core and many-core
systems. Consequently, architectural innovation has become crucial to achieve
performance and efficiency gains. New technologies that combine different types
of cores or similar cores with different computation capabilities can result in
a better match between the workload and the execution hardware improving
overall system energy efficiency. In addition, multi-core and many-core systems
need to be able to reconfigure themselves adaptively by monitoring their own
condition and the surrounding environment in order to adapt themselves to
different scenarios and performance-power requirements. Runtime monitoring
becomes crucial in the near future parallel and distributed multicore systems
due to increase in thermal issues as well as due to the need for various
adaptive managements.

This special issue addresses all aspects of energy-efficient computing in parallel
and distributed multi-core and many-core systems. Topics of interest include:
- Power and thermal estimation, analysis, optimization, and management
techniques for hardware and software systems
- Energy- and thermal aware application mapping and scheduling
- Energy- and thermal-aware dark silicon system design and optimization
- Energy-efficient heterogeneous system architecture
- Programming models, tools, languages and compilers to support energy-
aware computing
- Low-power monitor and sensor circuits
- Energy Efficient defect/fault tolerance, testing, and reliability
- Aging aware design, energy- and thermal-related reliability issues
- Energy-efficient off-chip/on-chip communication architectures including
- 3D architectures, integration and synthesis
- Energy-proportional systems
- Energy-efficient memory architectures and technologies (e.g. coherence
- Formal methods for modeling, design and verification of energy efficient
parallel and network-based systems
- Application analysis and parallelization for energy-efficient design
- Cases studies of parallel and network-based systems demonstrating
energy-efficient implementation as well as emerging applications and design

- Hannu Tenhunen, Royal Institute of Technology, Sweden (
- Alexander V. Veidenbaum, University of California, Irvine, USA (
- Jose L. Ayala, Complutense University of Madrid, Spain (
- Pasi Liljeberg, University of Turku, Finland (
- Amir Rahmani, University of Turku, Finland (

Manuscript due: September 1st, 2015
Acceptance/rejection notification: November 15th, 2015
2nd round check: January 15th, 2016
Final manuscript due: March 15th, 2016

Submitted manuscripts will be reviewed according to the peer review policy of
Information Sciences as available on-line at
Previously published conference papers should be clearly stated by the authors
and an explanation should be provided how such papers have been extended to
be considered for this special issue. Manuscripts should be formatted and be
submitted online according to the instructions for Information Sciences at

Authors should make sure to select the correct special issue by selecting
“SI: E2MC2” in the Article Type step.

Start: September 1, 2015
End: September 1, 2015

September 2, 2015

Call for Papers: FPL 2015

Submitted by Kubilay Atasu

25th International Conference on Field Programmable Logic and
Applications (FPL2015)

The Royal Institution
London, UK
September 2-4, 2015

The International Conference on Field Programmable Logic and Applications (FPL)
is the first and the largest conference covering the rapidly growing area of
field-programmable logic. During the past 25 years, many of the advances in
reconfigurable system architectures, applications, processors, electronic
design automation (EDA) methods and tools have been first published in the
proceedings of the FPL conference series. The objective of FPL is to bring
together researchers and practitioners from both academia and industry from
around the world to share their insight into the frontiers of field-
programmable logic and its applications.

The 25th FPL Conference will take place at the Royal Institution, London, UK,
during September 2 – 4, 2015. Tutorials and associated workshops are offered on
August 31, September 1 and 4. A new angle of FPL 2015 is power efficient and
self-aware FPGA accelerators and heterogeneous computing platforms for High
Performance Computing, embedded systems and cyber physical systems. Highlights
of FPL 2015 will include keynotes from academia and industry.

FPL 2015 will offer the following FIVE CONFERENCE TRACKS:

- Heterogeneous computing: multi/manycores, FPGAs, GPUs and DSPs
- Low power architectures
- Fault tolerant architectures
- Security and cryptography for FPGA Design
- 2.5D and 3D architectures
- Advanced on-chip interconnect technologies
- Analog and mixed-signal arrays
- Emerging technologies

- Aerospace, automotive and industry automation
- Bioinformatics & medical systems
- Communications, software defined networking and Internet-of-Things
- Finance, HPC and database acceleration
- Big data analytics
- Embedded & cyber physical systems
- Signal processing and SDR
- Benchmarks for FPGA designs

- System-level design tools
- High-level synthesis
- Hardware / software co-design
- Logic optimization and technology mapping
- Optimizations for power efficiency
- Packing, Placement and routing
- Rapid prototyping and emulation
- Testing, debugging and verification
- Open-source tools

- Self-awareness in FPGA-based systems
- Self-adaptive architectures and design techniques
- Virtualization of reconfigurable hardware
- Runtime resource management
- Partial reconfiguration

- Surveys on reconfigurable logic architectures and design techniques
- Deployment of FPGAs in new application domains
- Roadmap of reconfigurable computing platforms
- Teaching courses and tutorials

Abstract Submission Deadline (mandatory): March 27, 2015
Full Paper Submission Deadline: April 3, 2015
Acceptance Notification: June 5, 2015
Camera-ready and Author Registration: June 26, 2015
Submission Instructions on:


General Chairs
Peter Cheung, Imperial College London, UK
Wayne Luk, Imperial College London, UK

Programme Chair
Cristina Silvano, Politecnico di Milano, IT

Track Chairs
Architectures and Technology
Jason H. Anderson, University of Toronto, CA
Applications and Benchmarks
Dirk Koch, University of Manchester, UK
Design Methods and Tools
Dirk Stroobandt, Ghent University, BE
Self-aware and Adaptive Systems
Marco Platzner, Paderborn University, DE
Surveys, Trends and Education
Walid Najjar, University of California at Riverside, US

Workshop & Tutorial Chairs
Guy Gogniat, Université de Bretagne-Sud, FR
Bob Stewart, University of Strathclyde, UK

Panel Chairs
Michael Huebner, Ruhr-Universitåt Bochum, DE
Simon Moore, University of Cambridge, UK

PhD Forum Chairs
Dimitrios Soudris, National TU of Athens, GR
Andy Tyrrell, University of York, UK

Demo Night & Project Presentation Chairs
Koen Bertels, TU Delft, NL
Jose Nunez-Yanez, University of Bristol, UK

Proceedings Chair
Walter Stechele, TU München, DE

Steering Committee
Jürgen Becker, KIT Karlsruhe, DE
Koen Bertels, TU Delft, NL
Eduardo Boemo, Univ. Autónoma de Madrid, ES
João M. P. Cardoso, Universidade do Porto, PT
Peter Y.K. Cheung, Imperial College London, UK
Martin Danek, Daiteq, CZ
Apostolos Dollas, TU of Crete, GR
Fabrizio Ferrandi, Politecnico di Milano, IT
Manfred Glesner, TU Darmstadt, DE
John Gray, Consultant, UK
Reiner Hartenstein, TU Kaiserslautern, DE
Andreas Herkersdorf, TU München, DE
Udo Kebschull, Goethe University Frankfurt, DE
Wayne Luk, Imperial College London, UK
Patrick Lysaght, Xilinx, Inc., US
Jari Nurmi, Tampere University of Technology, FI
Lionel Torres, University of Montpellier II, FR
Jim Tørresen, University of Oslo, NO

Start: September 2, 2015
End: September 4, 2015
Venue: The Royal Institution, London, UK