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January 15, 2014

Call for Tutorial and Workshop Proposals: ISPASS 2015

Submitted by Kelly Shaw
http://www.ispass.org/

ISPASS 2015 Tutorials and Workshops
2015 IEEE International Symposium on Performance Analysis of
Systems and Software (ISPASS)
 

CALL FOR TUTORIAL PROPOSALS
 

Tutorial proposals are solicited for ISPASS-2015. Tutorials will be
held on March 29 in Philadelphia, PA.

Proposals for both half- and full-day tutorials are solicited on any
topic that is relevant to the ISPASS audience. Tutorials that focus on
workload characterization and analysis tools and techniques that
enable research across layers of the computational stack are strongly
encouraged.

In previous years, tutorials seeking to achieve any of the following
goals have been particularly successful:
- Describe an important piece of research/experimental infrastructure.
- Educate the community on an emerging topic.

IMPORTANT DATES
Submission deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

SUBMISSION PROCEDURES
Proposals should provide the following information:
- Title of the tutorial
- Presenter(s) and contact information
- Proposed duration (full day, half day)
- 1-2 paragraph abstract suitable for tutorial publicity
- 1 paragraph biography per presenter suitable for tutorial publicity
- Short description (for evaluation). This should include:
  o Tutorial scope and objectives
  o Topics to be covered
  o Target audience
  o If the tutorial has been held previously, the location
    (i.e., conference), date, and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton (adhilton@ee.duke.edu) with the subject
“ISPASS 2015 Tutorial Proposal”. Submissions will be acknowledged via
e-mail.
 

CALL FOR WORKSHOP PROPOSALS
 

Workshop proposals are solicited for ISPASS-2015. Workshops will be
held on March 29 in Philadelphia, PA.

Proposals related to power/performance analysis and workload
characterization as it relates to computer architecture, operating
systems, programming languages/compilers in current and emerging areas
such as datacenters and cloud computing, systems based on non-volatile
memory technologies, mobile technologies, large scale data analysis,
smart infrastructure, and extreme scale computing are encouraged.

IMPORTANT DATES
Submission Deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

SUBMISSION PROCEDURES
Please include in your proposal:
- Title of the workshop
- Organizers and their affiliations
- Sample call for papers
- Duration: Half-Day or Full Day
- If the workshop was previously held, the location (conference), date,
and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton (adhilton@ee.duke.edu) with the subject
“ISPASS 2015 Workshop Proposal”. Submissions will be acknowledged via
e-mail.
 

Start: January 15, 2014
End: January 15, 2015

November 1, 2014

Call for Papers: IEEE Computer Special Issue on Irregular Applications

Submitted by Antonino Tumeo
http://www.computer.org/portal/web/computingnow/cocfp8

IEEE Computer Special issue on Irregular Applications

Full paper submission deadline: 1 February 2015
Publication date: August 2015
 

The broad class of irregular applications is characterized by unpredictable
memory access patterns, control structures, and/or network transfers. These
applications typically use pointers or linked list–based data structures
such as graphs, unbalanced trees, and unstructured grids. Their complex
behavior makes it difficult to fully exploit their significant latent
parallelism. In addition to performance concerns, dataset size presents a
challenge in emerging irregular applications because they often operate
on massive amounts of unstructured heterogeneous data that is
usually difficult to partition.

Current high-performance architectures rely on data locality as well as regular
computations, structured data, and easily partitionable datasets; consequently,
they do not cope well with the computational and data requirements of
irregular applications. Furthermore, scaling on current supercomputing machines
is problematic, because of limits associated with fine-grained communication and
synchronization. These applications exist in well established and emerging
fields such as: CAD; bioinformatics; semantic graph databases; machine
learning; analysis of social, transportation, communication, and other types of
networks; and computer security. Addressing the many system-related issues
posed by irregular applications on current and future system architectures
is critical to solving future scientific challenges.

This special issue seeks to explore solutions for supporting the efficient
design, development, and execution of irregular applications. Practical
and theoretical topics of interest include but are not limited to:

- Micro- and system-level architectures;
- Network and memory architectures;
- Many-core, hybrid, heterogeneous, and custom architectures
(tiled processors, GPUs, FPGAs);
- Modeling, evaluation, and characterization of architectures for
memory-intensive and irregular applications;
- Innovative algorithmic techniques;
- Combinatorial (graph) algorithms and their applications;
- Languages and programming models;
- Library and runtime support;
- Compiler and analysis techniques; and
- Case studies of irregular applications (for example,
semantic graph databases, data mining, security, bioinformatics).

Articles focused on approaches that span multiple levels of the stack
— ideally providing application-specific, end-to‐end solutions — are of
particular interest. Articles should provide context for their contributions
with respect to existing solutions as well as potential commercial impact.

GUEST EDITORS
Antonino Tumeo (antonino.tumeo@pnnl.gov), PNNL
John Feo (john.feo@pnnl.gov), PNNL

SUBMISSION GUIDELINES
Paper submissions are due 1 February 2015.

Only technical articles describing previously unpublished, original,
state-of-the-art research, and not currently under review by a conference
or a journal will be considered. Articles should be understandable to a
broad audience of computer science and engineering professionals,
avoiding a focus on theory, mathematics, jargon, and abstract concepts.
All manuscripts are subject to peer review on both technical merit and
relevance to Computer’s readership. Accepted papers will be professionally
edited for content and style.

For author guidelines and information on how to submit a manuscript,
visit http://www.computer.org/portal/web/peerreviewmagazines/computer.

Start: November 1, 2014
End: February 1, 2015

Call for Papers: IJPP Special Issue on Workload Optimized Systems

Submitted by Parijat Dube
http://www.springer.com/10766

Springer International Journal of Parallel Programming (IJPP)
Special Issue on Workload Optimized Systems

 

The slowdown in Moore’s Law makes it increasingly important to optimize
systems around specific workloads. Such workload optimized systems have
hardware and/or software specifically designed to run well for a particular
workload or workload class. Such systems include, but are not limited to
traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory
accelerators, I/O accelerators, hybrid systems, and IT appliances. This
workload optimized system approach contrasts to the broad general purpose
direction of computing over many decades. The workload optimized systems
approach is growing in importance, as we see in systems from cellphones to
tablets to routers to game machines to Top500 supercomputers, and IT
appliances such as IBM’s DataPower and Netezza, and Oracle’s Exadata. The
goal of this special issue is to foster awareness in industry and academic
community on workload optimized systems and to expose cross hw/sw stack
unique systems and software research challenges associated with such
systems. All submitted papers are subject to the same review process as those
papers accepted for publication in the regular issues. The special issue seeks
original papers on a range of topics related to workload optimized systems
including, but not limited to

- GPUs, FPGAs, ASIC Accelerators
- Memory and I/O accelerators
- Network accelerators
- Storage optimized systems
- System level accelerators
- IT Appliances
- Systems in specific domains like analytics, cloud, cognitive, mobile etc.
- Converged/Hybrid/Heterogeneous systems
- Cross hardware/software stack design and optimization
- Programming models for workload optimized systems
- Measurements and Experimentation
- Workload characterization and profiling
- Performance modeling and optimization
- Workload scheduling and orchestration
- Runtime management systems
- Industrial Experiences

IMPORTANT DATES
Manuscript due: March 27, 2015
First decision notification: June 5, 2015
Revision due: July 10, 2015
Final decision notification: August 14, 2015
Final version due: September 11, 2015

SUBMISSIONS
Authors are encouraged to submit high-quality, original work that
has neither appeared in, nor is under consideration by, other
journals. All papers will be reviewed following standard reviewing
procedures for the Journal.
Papers must be prepared in accordance with the Journal guidelines:

http://www.springer.com/10766.

Manuscripts must be submitted to: http://IJPP.edmgr.com.
Choose “S.I.: Workload Optimized Systems” as the article type.

GUEST EDITORS
Erik Altman, IBM Research, Yorktown Heights, NY. ealtman@us.ibm.com
Parijat Dube, IBM Research, Yorktown Heights, NY. pdube@us.ibm.com

 

Start: November 1, 2014
End: October 1, 2015

January 14, 2015

Call for Participation: RISC-V Workshop and Bootcamp

Submitted by Krste Asanovic
http://riscv.org/workshop/

1st RISC-V Workshop and Boot Camp

January 14-15, 2015
Monterey, CA, USA

RISC-V (pronounced “risk-5″) is a new instruction set architecture
(ISA) that was originally designed to support computer architecture
research and education, but which we now hope will become a standard
open architecture for industry implementations. RISC-V was originally
developed in the Computer Science Division of the EECS Department at
the University of California, Berkeley, but has been made freely
available open-source under the BSD license for anyone to use.

The goals of this workshop are to inform the community of recent
activity in the various RISC-V projects underway around the globe and
to build consensus on future steps in the RISC-V project, while the
bootcamp provides an opportunity to learn about the existing RISC-V
infrastructure from the RISC-V development team. The workshop and
bootcamp will feature demos of multiple RISC-V silicon tapeouts as
well as FPGA board designs and associated software tools.

Space will be limited, so please register early!

Early Bird registration ends December 1.

Start: January 14, 2015
End: January 15, 2015
Venue: Monterey, CA

Call for Papers: SPAA 2015

Submitted by Jeremy Fineman
http://www.spaa-conference.org

27th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2015)
June 13-15, 2015
Portland, Oregon, USA
 

This year, SPAA will be in the Federated Computing Research Conference (FCRC).
General FCRC information is available at http://fcrc.acm.org.

IMPORTANT DATES:
Submission deadlines:
- Abstract: January 14, 11:59pm EST
- Full versions: January 16, 11:59pm EST
Rebuttal period: March 4-5
Notification: March 23
Camera-ready: April 21

Contributed papers are sought in all areas of parallel algorithms and
architectures, encompassing any computation system that can perform multiple
operations or tasks simultaneously. Topics of interest include, but are not
limited to:

- parallel and distributed algorithms
- parallel and distributed data structures
- green computing & power-efficient architectures
- management of massive data sets
- parallel complexity theory
- parallel and distributed architectures
- multi-core architectures
- instruction level parallelism and VLSI
- compilers and tools for concurrent programming
- supercomputing architecture and computing
- transactional memory hardware and software
- game theory and collaborative learning
- routing and information dissemination
- resource management and awareness
- peer-to-peer systems
- mobile, ad-hoc, and sensor networks
- robustness, self-stabilization, and security
- synergy of parallelism in algorithms, programming, and architecture

Conference presentations will have two formats:

Regular presentations will be allotted a 25-minute talk and up to 10
pages in the proceedings. This format is intended for contributions
reporting original research, submitted exclusively to this conference.

Brief announcements will be allotted a 10-minute talk and a 2-page
abstract in the proceedings. This format is a forum for brief
communications, which may be published later in other conferences.

Every regular paper is eligible for the best paper award. The program
committee may decline to make this award or may split the award among
multiple papers.

SUBMISSIONS
Authors of contributed papers are encouraged to submit their manuscript
electronically. To submit electronically, visit http://www.spaa-conference.org
for instructions. This is the preferred method of submission. Authors unable
to submit electronically should contact the program chair Kunal Agrawal at
kunal@wustl.edu to receive instructions on how to proceed.

Submissions for regular presentations should include an introduction
understandable to a nonspecialist including motivation and previous work, and
a technical exposition directed to a specialist. A submission should not
exceed 10 double-column pages in 9-point font, including figures, tables, and
references. More details may be supplied in a clearly marked appendix to
be read at the discretion of the program committee. A submission for brief
announcements should be no longer than two double-column pages in 9-point
font.

Rebuttal Period:
There will be a rebuttal period in which the authors can point out
misunderstandings or comment on critical questions that PC members may have.
The rebuttal period will take place on March 4-5.

PROGRAM COMMITTEE
Umut Acar, Carnegie Mellon University
Grey Ballard, Sandia National Labs
Petra Berenbrink, Simon Fraser University
Dave Dice, Oracle Labs
Jeremy Fineman, Georgetown University
Pierre Fraigniaud, University of Paris 7
Seth Gilbert, National University of Singapore
Rachid Guerraoui, EPFL
MohammadTaghi HajiAghayi, University of Maryland
Maurice Herlihy, Brown University
Martin Hoefer, MPI Saarbrücken
Peter Kling, University of Pittsburgh
Bradley Kuzsmaul, MIT
Angelina Lee, Washington University in St. Louis
Ryan Newton, Indiana University
Gopal Pandurangan, University of Houston
Michael Spear, Lehigh University
Cliff Stein, Columbia University
Kanat Tangwongsan, Mahidol University
Sivan Toledo, Tel Aviv University
Uzi Vishkin, University of Maryland

CONFERENCE COMMITTEE
Program Chair: Kunal Agrawal, Washington University in St. Louis
General Chair: Guy Blelloch, Carnegie Mellon University
Secretary: Christian Scheideler, University of Paderborn
Treasurer: David Bunde, Knox College
Publicity Chair: Jeremy Fineman, Georgetown University
 

Start: January 14, 2015 1:00 am
End: January 16, 2015 11:45 pm
Venue: Portland, Oregon

January 15, 2015

Call for Tutorials and Workshops: ISPASS 2015

Submitted by Kelly Shaw
http://www.ispass.org
ISPASS 2015 Call for Tutorial and Workshop Proposals

Call for Tutorial Proposals

Tutorial proposals are solicited for ISPASS-2015. Tutorials will be
held on March 29 in Philadelphia, PA.

Proposals for both half- and full-day tutorials are solicited on any
topic that is relevant to the ISPASS audience. Tutorials that focus on
workload characterization and analysis tools and techniques that
enable research across layers of the computational stack are strongly
encouraged.

In previous years, tutorials seeking to achieve any of the following
goals have been particularly successful:
* Describe an important piece of research/experimental infrastructure.
* Educate the community on an emerging topic.

IMPORTANT DATES
Submission deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

SUBMISSION PROCEDURES
Proposals should provide the following information:
* Title of the tutorial
* Presenter(s) and contact information
* Proposed duration (full day, half day)
* 1-2 paragraph abstract suitable for tutorial publicity
* 1 paragraph biography per presenter suitable for tutorial publicity
* Short description (for evaluation). This should include:
– Tutorial scope and objectives
– Topics to be covered
– Target audience
– If the tutorial has been held previously, the location
(i.e., conference), date, and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton (adhilton@ee.duke.edu) with the subject
“ISPASS 2015 Tutorial Proposal”. Submissions will be acknowledged via
e-mail.

*******************************************************************************

Call for Workshop Proposals

Workshop proposals are solicited for ISPASS-2015. Workshops will be
held on March 29 in Philadelphia, PA.

Proposals related to power/performance analysis and workload
characterization as it relates to computer architecture, operating
systems, programming languages/compilers in current and emerging areas
such as datacenters and cloud computing, systems based on non-volatile
memory technologies, mobile technologies, large scale data analysis,
smart infrastructure, and extreme scale computing are encouraged.

IMPORTANT DATES
Submission Deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

SUBMISSION PROCEDURES
Please include in your proposal:
* Title of the workshop
* Organizers and their affiliations
* Sample call for papers
* Duration – Half-Day or Full Day
* If the workshop was previously held, the location
(conference), date, and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton (adhilton@ee.duke.edu) with the subject
“ISPASS 2015 Workshop Proposal”. Submissions will be acknowledged via
e-mail.

Start: January 15, 2015
End: January 15, 2015

January 16, 2015

Call for Papers: IEEE Micro Special Issue on Heterogeneous Computing

Submitted by Lieven Eeckhout
http://www.computer.org/portal/web/computingnow/micro
Call for Papers: IEEE Micro Special Issue on Heterogeneous Computing

Guest Co-Editors:
Dean Tullsen (UCSD)
Ravishankar Iyer (Intel)

Submissions due: Jan 16, 2015
Publication date: July-August 2015

Heterogeneity is widely accepted as a fruitful avenue to improve
performance and power/energy/thermal-efficiency in the face of continued
technology miniaturization (Moore’s Law) and slowed supply voltage
reduction (end of Dennard scaling). Heterogeneity comes in many flavors
ranging from Systems-on-Chip (SoCs) with specialized hardware accelerators,
to hybrid CPU/GPU architectures, to single-ISA heterogeneous multi-cores
with different core types, to multi-ISA heterogeneous multi-cores in which
different core types implement different Instruction-Set Architectures (ISA).
Architects have explored and built heterogeneous architectures
across a broad spectrum of computing devices including embedded systems,
mobile devices, datacenters, and High-Performance Computing (HPC)
supercomputers. While the performance and power/energy opportunities
have been outlined, important challenges are yet to be studied regarding
architecture, accelerators, hardware/software interface, run-time support,
compilation, programming models, and performance evaluation. The goal of
this Special Issue is to present the latest state-of-the-art results
in the broad area of heterogeneous computing systems.

Areas of interest include, but are not limited to:
- Heterogeneous architectures, including:

  • o System-on-Chip (SoC) with accelerators
  • o CPU/GPU systems
  • o Single-ISA heterogeneous multi-cores
  • o Multi-ISA heterogeneous multi-cores

- Roadmaps and commercial trends in heterogeneous architectures
- Trade-offs in performance, power, energy, thermal, reliability, code
portability and programmability due to heterogeneity
- Case studies of heterogeneous architectures in embedded system design,
mobile computing, HPC, data centers, etc.
- Accelerator architectures and interfaces
- Platform support for heterogeneous and accelerator architectures
- Hardware/software interactions on heterogeneous architectures, including
OS scheduling and compilation
- Programming models and runtime support for heterogeneous architectures
- Workloads particularly suited for heterogeneity
- Performance evaluation of heterogeneous architectures
- Experiences with real heterogeneous platforms

Submission procedure:
Log onto IEEE CS Manuscript Central
(https://mc.manuscriptcentral.com/micro-cs) and submit your manuscript.
Please direct questions to the IEEE Micro magazine assistant
(micro-ma@computer.org) regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and
PDF. Manuscripts should not exceed 5,000 words including references, with
each average-size figure counting as 150 words toward this limit.
Please include all figures and tables, as well as a cover page with author
contact information (name, postal address, phone, fax, and e-mail address)
and a 200-word abstract. Submitted manuscripts must not have been
previously published or currently submitted for publication elsewhere, and
all manuscripts must be cleared for publication. All previously published
papers must have at least 30% new content compared to any conference (or
other) publication. Accepted articles will be edited for structure, style,
clarity, and readability. For more information, please visit
the IEEE Micro Author Center
(http://www2.computer.org/portal/web/peerreviewmagazines/acmicro).

Important dates:
Initial submissions due: Jan 16, 2015
Author notification: March 2, 2015
Revised papers due: March 20, 2015
Final version due: April 23, 2015
Publication timeframe: July-August 2015

Questions?
Contact the Guest Co-Editors Dean Tullsen (tullsen@ucsd.edu) and
Ravi Iyer (ravishankar.iyer@intel.com), or the Editor-in-Chief
Lieven Eeckhout (lieven.eeckhout@ugent.be).

Start: January 16, 2015
End: January 16, 2015

January 19, 2015

Call for Papers: HIPEAC 2015

Submitted by Gennady Pekhimenko
http://www.hipeac.net/conference

10th International Conference on High-Performance Embedded
Architectures and Compilers

January 19-21, 2015
Amsterdam, The Netherlands

http://www.hipeac.net/conference

IMPORTANT DATE:
Paper deadline: June 1, 2014

Sponsored by:
HiPEAC Compilation & Architecture
Seventh Framework Programme

Description:
The HiPEAC conference is the premier European forum for
experts in computer architecture, programming models,
compilers and operating systems for embedded and
general-purpose systems.

The 10th HiPEAC conference will take place in Amsterdam,
The Netherlands from Monday, January 19 to Wednesday, January
21, 2015. Associated workshops, tutorials, special sessions,
several large poster session and an industrial exhibition will
run in parallel with the conference. The three day event
attracts about 500 delegates each year.

Paper selection is done by ACM TACO, the ACM Transactions on
Architecture and Code Optimization. Prospective authors submit
their original papers to ACM TACO at any time before the paper
deadline of June 1, 2014 to benefit from two rounds of reviews
before the conference paper track cut-off date which is
November 15, 2014.

See below for detailed information about the new publication
model called ACM TACO 2.0.

Topics of interest include, but are not limited to:
* Processor, memory, and storage systems architecture
* Parallel, multi-core and heterogeneous systems
* Interconnection networks
* Architectural support for programming productivity
* Power, performance and implementation efficient designs
* Reliability and real-time support in processors, compilers
and run-time systems
* Application-specific processors, accelerators and
reconfigurable processors
* Architecture and programming environments for GPU-based
computing
* Simulation and methodology
* Architectural and run-time support for programming languages
* Programming models, frameworks and environments for exploiting
parallelism
* Compiler techniques
* Feedback-directed optimization
* Program characterization and analysis techniques
* Dynamic compilation, adaptive execution, and continuous
profiling/optimization
* Binary translation/optimization
* Code size/memory footprint optimizations

GENERAL CHAIRS
Andy D. Pimentel, University of Amsterdam
Stephan Wong, Delft University of Technology

PROGRAM CHAIR
Onur Mutlu, Carnegie Mellon University

WORKSHOPS & TUTORIALS CHAIRS
Diana Göhringer, Ruhr-Universität Bochum
Sascha Uhrig, TU Dortmund

PUBLICITY CHAIRS
Sorin Cotofana, Delft University of Technology
Antonio Beck, UFRGS
Chao Wang, USTC
Gennady Pekhimenko, Carnegie Mellon Univ.

POSTER & EXHIBITION CHAIR
Koen De Bosschere, Ghent University

SPONSOR CHAIR
Albert Cohen, INRIA

INDUSTRIAL SESSION CHAIR
Daniel Gracia Pérez, Thales

FINANCE CHAIR
Vicky Wandels, Ghent University

WEB AND REGISTRATIONS CHAIR
Eneko Illarramendi, Ghent University

LOCAL ARRANGEMENTS COMMITTEE
Andy D. Pimentel, University of Amsterdam
Stephan Wong, Delft University of Technology
Clemens Grelck, University of Amsterdam
Todor Stefanov, University of Leiden
Zaid Al-Ars, Delft University of Technology

*****************************************************************
ACM TACO 2.0 Publication Model:
Over the last three years ACM TACO has optimized its
internal review processes. Today, the average turnaround
time from submission to first response is 46 days and 95%
of the manuscripts get a response within 2 months. For
revised manuscripts, the review process goes even faster.
In 2013, most accepted manuscripts went through two rounds
of reviews to reach a final decision only 5 months after
submission. Accepted manuscripts are immediately uploaded
in the ACM digital library. Hence, excellent manuscripts
can make it from submission to publication in about three
months; papers needing a major revision are published after
6 months. We call this “ACM TACO 2.0”

ACM TACO 2.0 now has a review cycle and an acceptance rate
which is competitive with the best ACM conferences, but
without the inconvenient non-negotiable submission deadlines,
and with the advantage of being able to revise a paper based
on the detailed review reports by carefully selected
reviewers, and of being published as soon as it is accepted.
On top of that, authors of original work papers get an open
invitation to present their paper at the yearly HiPEAC
conference, which is the premier European network event on
topics central to ACM TACO, attended by more than 500
scientists.

ACM TACO interim Editor-in-Chief
Prof. Koen De Bosschere

ACM TACO Senior Editor
Prof. Per Stenström

Start: January 19, 2015
End: January 21, 2015
Venue: Amsterdam, The Netherlands

Call for Papers: HiPEAC 2015

Submitted by Gennady Pekhimenko
http://www.hipeac.net/conference
Call for Papers – HIPEAC 2015

10th International Conference on High-Performance Embedded
Architectures and Compilers

January 19-21, 2015
Amsterdam, The Netherlands

http://www.hipeac.net/conference

IMPORTANT DATE:
Paper deadline: June 1, 2014

Sponsored by:
HiPEAC Compilation & Architecture
Seventh Framework Programme

Description:
The HiPEAC conference is the premier European forum for
experts in computer architecture, programming models,
compilers and operating systems for embedded and
general-purpose systems.

The 10th HiPEAC conference will take place in Amsterdam,
The Netherlands from Monday, January 19 to Wednesday, January
21, 2015. Associated workshops, tutorials, special sessions,
several large poster session and an industrial exhibition will
run in parallel with the conference. The three day event
attracts about 500 delegates each year.

Paper selection is done by ACM TACO, the ACM Transactions on
Architecture and Code Optimization. Prospective authors submit
their original papers to ACM TACO at any time before the paper
deadline of June 1, 2014 to benefit from two rounds of reviews
before the conference paper track cut-off date which is
November 15, 2014.

See below for detailed information about the new publication
model called ACM TACO 2.0.

Topics of interest include, but are not limited to:
* Processor, memory, and storage systems architecture
* Parallel, multi-core and heterogeneous systems
* Interconnection networks
* Architectural support for programming productivity
* Power, performance and implementation efficient designs
* Reliability and real-time support in processors, compilers
and run-time systems
* Application-specific processors, accelerators and
reconfigurable processors
* Architecture and programming environments for GPU-based
computing
* Simulation and methodology
* Architectural and run-time support for programming languages
* Programming models, frameworks and environments for exploiting
parallelism
* Compiler techniques
* Feedback-directed optimization
* Program characterization and analysis techniques
* Dynamic compilation, adaptive execution, and continuous
profiling/optimization
* Binary translation/optimization
* Code size/memory footprint optimizations

GENERAL CHAIRS
Andy D. Pimentel, University of Amsterdam
Stephan Wong, Delft University of Technology

PROGRAM CHAIR
Onur Mutlu, Carnegie Mellon University

WORKSHOPS & TUTORIALS CHAIRS
Diana Göhringer, Ruhr-Universität Bochum
Sascha Uhrig, TU Dortmund

PUBLICITY CHAIRS
Sorin Cotofana, Delft University of Technology
Antonio Beck, UFRGS
Chao Wang, USTC
Gennady Pekhimenko, Carnegie Mellon Univ.

POSTER & EXHIBITION CHAIR
Koen De Bosschere, Ghent University

SPONSOR CHAIR
Albert Cohen, INRIA

INDUSTRIAL SESSION CHAIR
Daniel Gracia Pérez, Thales

FINANCE CHAIR
Vicky Wandels, Ghent University

WEB AND REGISTRATIONS CHAIR
Eneko Illarramendi, Ghent University

LOCAL ARRANGEMENTS COMMITTEE
Andy D. Pimentel, University of Amsterdam
Stephan Wong, Delft University of Technology
Clemens Grelck, University of Amsterdam
Todor Stefanov, University of Leiden
Zaid Al-Ars, Delft University of Technology

ACM TACO 2.0 Publication Model:
Over the last three years ACM TACO has optimized its
internal review processes. Today, the average turnaround
time from submission to first response is 46 days and 95%
of the manuscripts get a response within 2 months. For
revised manuscripts, the review process goes even faster.
In 2013, most accepted manuscripts went through two rounds
of reviews to reach a final decision only 5 months after
submission. Accepted manuscripts are immediately uploaded
in the ACM digital library. Hence, excellent manuscripts
can make it from submission to publication in about three
months; papers needing a major revision are published after
6 months. We call this “ACM TACO 2.0”

ACM TACO 2.0 now has a review cycle and an acceptance rate
which is competitive with the best ACM conferences, but
without the inconvenient non-negotiable submission deadlines,
and with the advantage of being able to revise a paper based
on the detailed review reports by carefully selected
reviewers, and of being published as soon as it is accepted.
On top of that, authors of original work papers get an open
invitation to present their paper at the yearly HiPEAC
conference, which is the premier European network event on
topics central to ACM TACO, attended by more than 500
scientists.

ACM TACO interim Editor-in-Chief
Prof. Koen De Bosschere

ACM TACO Senior Editor
Prof. Per Stenström

Start: January 19, 2015
End: January 21, 2015
Venue: Amsterdam, The Netherlands

Call for Papers: Workshop on Exploiting Silicon Photonics for Energy-efficient High Performance Computing (SiPhotonics’2015)

Submitted by Jose M. Garcia
http://www.hipeac.net/2015/amsterdam/workshops/siphotonics
Call for Papers: 2nd International Workshop on Exploiting Silicon Photonics for energy-efficient high performance computing (SiPhotonics’2015),
19-21 January, 2015 Amsterdam, The Netherlands

Associated with the 10th HiPEAC conference on High Performance and Embedded
Architecture and Compilers (http://www.hipeac.net/2015/amsterdam/).
*****************************************************************************

Goal of the Workshop:

With Exascale systems on the horizon, we will be ushering in an era with
power and energy consumption as the primary concerns for scalable computing.
To achieve viable high performance, revolutionary methods are required with a
stronger integration among hardware features, system software and
applications.

The main purpose of this workshop is to promote further research interests
and activities on Silicon Photonics and related topics in the perspective of
its adoption in future high performance systems and, in general, within
future computing systems (from servers/workstations down to embedded
devices). In fact, Silicon Photonics poses in itself crucial challenges and
interesting design tradeoffs for being deployed in future computer systems
effectively, also in integration with other technologies. Furthermore, the
unique features of photonics (e.g. extreme low-latency, end-to-end
transmission, high bandwidth density) have the potential to constitute a
discontinuity element able to modify the expected shape of future computer
systems from the design point of view and also from the programmability
and/or runtime management perspectives.

Summarizing, silicon photonics can bring innovations and benefits into
current and foreseeable computing systems directly, due to their intrinsic
features, but also indirectly enabling the evolution towards architectures,
runtime and resource management approaches that maximize the photonic raw
technological opportunities and lead to more efficient overall designs,
otherwise impossible.

This workshop aims to increase the synergy from a complete range of
perspectives, from raw technology issues and solutions up to studies at the
overall system level of modern multi-/many-core systems, both from academic
and industrial researchers working in this area. We are interested in
experimental, systems-related, and work-in-progress papers in all aspects of
the Silicon Photonics technology at all levels of development.

To emphasize both the fundamental impact of silicon photonic technologies on
future system and interconnection network architectures and, conversely, the
driving forces of practical and economically viable system-level design,
requirements and constraints on the underlying technologies, this year the
SiPhotonics and INA-OCMC Workshops will be held in a federated fashion. We
plan to organize joint keynote presentations and a panel discussion with
experts from both fields on topics of interest to both communities. This way,
we intend to foster the exchange of ideas and increase collaboration between
these highly complementary workshops. The paper submission and review
processes will, however, still be run independently by each workshop.

Topics of interest:

Authors are invited to submit high quality papers representing original work
from both the academia and industry in (but not limited to) the following
topics:

- Photonics in the memory hierarchy and I/O of computing systems, QoS
management and performance analysis. On-chip and inter-chip approaches
- Emerging challenges and solutions for on-chip interconnections, runtime and
programmability for future homogeneous/heterogeneous CMPs
- Interaction of photonic features and opportunities with chip-multiprocessor
architectural features, runtime and operating system
- Addressing thermal-/energy- and power-related issues
- Solving the requirements of multiple heterogeneous parallel applications
- Simulation, validation and verification
- Synergies and tradeoffs between photonic and electronic network
technologies
- Low-level technological improvements and implications (e.g. integrated
lasers, modulation and detection technologies, microring resonators) for
computer system communication
- Industrial practices and case studies

Submission guidelines:

Prospective authors should submit electronically a full paper in English in
PDF format. Submitted papers must represent original unpublished research
that is not currently under review for any other conference or journal.

All manuscripts will be reviewed and will be judged on correctness,
originality, technical strength, significance, quality of presentation, and
interest and relevance to the workshop attendees.

They should be formatted according to the IEEE Conference proceedings format
- http://www.ieee.org/conferences_events/conferences/publishing/templates.html
(IEEEtran, double-column, 10pt), not exceeding 8 pages including figures and
references.

Submissions can be made through the submission web site at the IEEE CPS Web-
based paper submission site.
Publication:

Informal proceedings will be provided in an USB stick to all participants
including all material relevant to the conference and the related events.

The proceedings of the workshop will be published by the IEEE Computer
Society’s Conference Publishing Services (CPS)
http://www.computer.org/portal/web/cscps/home. Conference proceedings will be
indexed by the IEEE Xplore Digital Library. An extended version of the best
papers of the SiPhotonics be invited to submit extended article versions to a
special issue of one of the ISI-indexed high-quality journals in this field
(Concurrency and Computation: Practice and Experience from Wiley was last
edition journal).

Registration: Authors of accepted papers are expected to register and present their papers at the conference.

Important dates:

Paper submission deadline: November 15, 2014
Notification of acceptance: November 30, 2014
Camera-ready paper due: December 13, 2014
Conference: 19th – 21th January 2015

Co-chairs:

José M. García, University of Murcia, Spain.
Sandro Bartolini, University of Siena, Italy

Program committee:

Keren Bergman Columbia University
Giovanna Calo Politecnico di Bari
José M. Cecilia Catholic University of Murcia
Yawen Chen Otago University
Ricardo Fernández-Pascual University of Murcia
Pierfrancesco Foglia University of Pisa
Antonio Garcia-Guirado ARM Norway – NTNU
Paolo Grani University of Siena
Huaxi Gu Xidian University
Timothy Jones University of Cambridge
Kostas Katrinis IBM Ireland
Sébastien Le Beux Lyon Institute of Nanotechnology (INL)
Xavier Martorell Barcelona Supercomputing Center (BSC) & UPC
Gokhan Memik Northwestern University
Sergei Mingaleev VPIphotonics
Takahiro Nakamura Photonics Electronics Technology Research
Sudeep Pasricha Colorado State University
Luca Ramini University of Ferrara
Oded Raz COBRA Research Institute (Eindhoven University of Technology)
Marco Romagnoli CNIT
José Luis Sánchez University of Castilla-La Mancha
Laurent Schares IBM TJ Watson
Philip M. Watts University College London

Contacts:

Prof. José M. García
Departamento de Ingeniería y Tecnología de Computadores
University of Murcia, Spain.
email: jmgarcia[at]ditec.um.es
Tel.: +34 868 884819 Fax: +34 868 884151

Ing. Sandro Bartolini, PhD
Dipartimento di Ingegneria dell’Informazione e Scienze Matematiche
University of Siena, Italy
E-mail: bartolini[at]dii.unisi.it
Tel: +39 0577 234850 Fax: +39 0577 233609

Start: January 19, 2015
End: January 19, 2015
Venue: Amsterdam, The Netherlands