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October 1, 2014

Call for Papers: IEEE Transactions on Computers Special Issue on Transparent Computing

Submitted by Jimmy Cuo

Call for Papers: Special Issue in IEEE Transactions on Computers on “Transparent Computing”

At 2012 Intel Developer Forum, San Francisco, Renee James, senior Vice
President and General Manager of Intels Software Services Group, delivered a
keynote speech “Next Era of Computing: Transparent Computing”, in which she
pointed out that “(transparent computing) represents for us the direction
that we believe we need to go as an industry. And it’s the next step really
beyond ubiquitous computing.”

The basic idea behind transparent computing is simple: give developers just
one basic platform on which to develop their applications, and make it
possible for these applications to run on any other platform. A formal model
of transparent computing has been proposed, which is a cloud-style paradigm.
As described by James, transparent computing “is really about allowing
experiences to seamlessly cross across different platforms, both
architectures and operating system platform boundaries”. The key idea of
transparent computing is to logically separate hardware and software
(including operating systems) and to separate computation and memory.
Specifically, all the required software and data are centralized on central
servers, and streamed to the clients on demand to carry out the computing
tasks leveraging the local CPU and memory resources. Compared with other
cloud computing models, transparent computing has the following desired
features: (1) user and application transparency; (2) heterogeneous OS
support; (3) streaming delivery; (4) supports of various devices; and (5)
enhanced security.

Transparent computing has proposed new challenges in the research of
computer software and systems:

From user’s perspectives:
_ user transparency (in paradigms, systems, applications, and services);
_ user machine’s efficiency and security;
_ privacy protection and system reliability; and
_ local resource scheduling and management.

From system’s perspectives:
_ standardized software-hardware interface;
_ device and user virtualization;
_ data consistence and security;
_ multiple-user system performance; and
_ operating system modularization.

This journal Special Issue in the IEEE Transaction on Computers will provide
the scientific community a dedicated forum for discussing new research and
development in transparent computing. The Special Issue invites original
research papers that make significant contributions to the state-of-the-art
that advance the fundamental understanding, technologies, concepts, and
applications in transparent computing.

Open for Submissions in ScholarOne Manuscripts: October 31, 2014
Closed for Submission: November 30, 2014
Results of First Round of Review: January 25, 2015
Submission of Revised Manuscripts: February 20, 2015
Results of Second Round of Review: March 15, 2015
Publication Materials Due: March 31, 2015

Prospective authors are invited to submit their manuscripts electronically
after the open for submissions date, adhering to the IEEE Transactions on
Computers guidelines at

Please submit your papers through the online system
( and be sure to select the special
issue or special section name. Manuscripts should not be published or
currently submitted for publication elsewhere. Please submit only full
papers intended for review, not abstracts, to the ScholarOne portal. If
requested, abstracts should be sent by e-mail to the Guest Editors directly.

Jianer Chen, Texas A&M University, USA,
Yaoxue Zhang, Central South University, P.R. China,

Start: October 1, 2014
End: November 30, 2014

November 1, 2014

Call for Papers: IEEE Computer Special Issue on Irregular Applications

Submitted by Antonino Tumeo

IEEE Computer Special issue on Irregular Applications

Full paper submission deadline: 1 February 2015
Publication date: August 2015

The broad class of irregular applications is characterized by unpredictable
memory access patterns, control structures, and/or network transfers. These
applications typically use pointers or linked list–based data structures
such as graphs, unbalanced trees, and unstructured grids. Their complex
behavior makes it difficult to fully exploit their significant latent
parallelism. In addition to performance concerns, dataset size presents a
challenge in emerging irregular applications because they often operate
on massive amounts of unstructured heterogeneous data that is
usually difficult to partition.

Current high-performance architectures rely on data locality as well as regular
computations, structured data, and easily partitionable datasets; consequently,
they do not cope well with the computational and data requirements of
irregular applications. Furthermore, scaling on current supercomputing machines
is problematic, because of limits associated with fine-grained communication and
synchronization. These applications exist in well established and emerging
fields such as: CAD; bioinformatics; semantic graph databases; machine
learning; analysis of social, transportation, communication, and other types of
networks; and computer security. Addressing the many system-related issues
posed by irregular applications on current and future system architectures
is critical to solving future scientific challenges.

This special issue seeks to explore solutions for supporting the efficient
design, development, and execution of irregular applications. Practical
and theoretical topics of interest include but are not limited to:

- Micro- and system-level architectures;
- Network and memory architectures;
- Many-core, hybrid, heterogeneous, and custom architectures
(tiled processors, GPUs, FPGAs);
- Modeling, evaluation, and characterization of architectures for
memory-intensive and irregular applications;
- Innovative algorithmic techniques;
- Combinatorial (graph) algorithms and their applications;
- Languages and programming models;
- Library and runtime support;
- Compiler and analysis techniques; and
- Case studies of irregular applications (for example,
semantic graph databases, data mining, security, bioinformatics).

Articles focused on approaches that span multiple levels of the stack
— ideally providing application-specific, end-to‐end solutions — are of
particular interest. Articles should provide context for their contributions
with respect to existing solutions as well as potential commercial impact.

Antonino Tumeo (, PNNL
John Feo (, PNNL

Paper submissions are due 1 February 2015.

Only technical articles describing previously unpublished, original,
state-of-the-art research, and not currently under review by a conference
or a journal will be considered. Articles should be understandable to a
broad audience of computer science and engineering professionals,
avoiding a focus on theory, mathematics, jargon, and abstract concepts.
All manuscripts are subject to peer review on both technical merit and
relevance to Computer’s readership. Accepted papers will be professionally
edited for content and style.

For author guidelines and information on how to submit a manuscript,

Start: November 1, 2014
End: February 1, 2015

Call for Papers: IJPP Special Issue on Workload Optimized Systems

Submitted by Parijat Dube

Springer International Journal of Parallel Programming (IJPP)
Special Issue on Workload Optimized Systems


The slowdown in Moore’s Law makes it increasingly important to optimize
systems around specific workloads. Such workload optimized systems have
hardware and/or software specifically designed to run well for a particular
workload or workload class. Such systems include, but are not limited to
traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory
accelerators, I/O accelerators, hybrid systems, and IT appliances. This
workload optimized system approach contrasts to the broad general purpose
direction of computing over many decades. The workload optimized systems
approach is growing in importance, as we see in systems from cellphones to
tablets to routers to game machines to Top500 supercomputers, and IT
appliances such as IBM’s DataPower and Netezza, and Oracle’s Exadata. The
goal of this special issue is to foster awareness in industry and academic
community on workload optimized systems and to expose cross hw/sw stack
unique systems and software research challenges associated with such
systems. All submitted papers are subject to the same review process as those
papers accepted for publication in the regular issues. The special issue seeks
original papers on a range of topics related to workload optimized systems
including, but not limited to

- GPUs, FPGAs, ASIC Accelerators
- Memory and I/O accelerators
- Network accelerators
- Storage optimized systems
- System level accelerators
- IT Appliances
- Systems in specific domains like analytics, cloud, cognitive, mobile etc.
- Converged/Hybrid/Heterogeneous systems
- Cross hardware/software stack design and optimization
- Programming models for workload optimized systems
- Measurements and Experimentation
- Workload characterization and profiling
- Performance modeling and optimization
- Workload scheduling and orchestration
- Runtime management systems
- Industrial Experiences

Manuscript due: March 27, 2015
First decision notification: June 5, 2015
Revision due: July 10, 2015
Final decision notification: August 14, 2015
Final version due: September 11, 2015

Authors are encouraged to submit high-quality, original work that
has neither appeared in, nor is under consideration by, other
journals. All papers will be reviewed following standard reviewing
procedures for the Journal.
Papers must be prepared in accordance with the Journal guidelines:

Manuscripts must be submitted to:
Choose “S.I.: Workload Optimized Systems” as the article type.

Erik Altman, IBM Research, Yorktown Heights, NY.
Parijat Dube, IBM Research, Yorktown Heights, NY.


Start: November 1, 2014
End: October 1, 2015

November 25, 2014

Call for Papers: VEE 2015

Submitted by Angela Demke Brown

VEE’15: 11th ACM international conference on Virtual Execution Environments
Co-located with ASPLOS 2015
March 14-15, 2015
Istanbul, Turkey

Tuesday, November 25, 2014 (11:59pm, PST)

The 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution
Environments (VEE’15) brings together researchers and practitioners from
different computer systems domains to interact and share ideas in order to
advance the state of the art of virtualization and broaden its applicability.

VEE’15 accepts both full-length and short papers. Both types of submissions are
reviewed to the same standards and differ primarily in the scope of the ideas
expressed. Short papers are limited to half the space of full-length papers.
The program committee will not accept a full paper on the condition that it is
cut down to fit in a short paper slot, nor will it invite short papers to be
extended to full length. Submissions will be considered only in the category
in which they are submitted.

We invite authors to submit original papers related to virtualization across
all layers of the software stack down to the microarchitectural level.
Topics of interest include (but are not limited to):
– virtualization support for programs and programmers;
– architecture support for virtualization;
– operating system support for virtualization;
– compiler and programming language support for virtualization;
– runtime system support for virtualization;
– virtual I/O, storage, and networking;
– memory management;
– management technologies for virtual environments;
– performance analysis and debugging for virtual environments;
– virtualization technologies applied to specific problem domains such as
cloud, HPC, realtime, power management, and security.

Submission Deadline: Tuesday, November 25, 2014 (11:59pm, PST)
Author Rebuttal: Friday – Saturday, January 23 – 24, 2015
Author Notification: Wednesday, January 28, 2015
Camera-ready Deadline: Thursday, February 12, 2015 (11:59pm, PST)

Ada Gavrilovska (Georgia Institute of Technology)

Angela Demke Brown (University of Toronto)
Bjarne Steensgaard (Microsoft Research)

Jonathan Appavoo (Boston University)
Haibo Chen (Shanghai Jiao Tong University)
Dilma Da Silva (Texas A&M University)
Amer Diwan (Google)
Daniel Frampton (Microsoft Research)
David Gregg (Trinity College Dublin)
David Grove (IBM Research)
Vishakha Gupta (Intel)
Tomas Kalibera (Purdue University)
Kenichi Kourai (Kyushu Institute of Technology)
Priya Nagpurkar (IBM Research)
Donald Porter (Stony Brook University)
Jennifer Sartor (Ghent University)
Ravi Soundararajan (VMWare)
Gael Thomas (LIP6)
Timothy Wood (GWU)

Start: November 25, 2014
End: November 25, 2014

December 10, 2014

Call for Papers: Performance and Power Issues in Multi/Many Core Architecture

Submitted by Hitoshi OI
Performance and Power Issues in Multi/Many Core Architecture,
a special session in International Symposium on Integrated Circuits
(ISIC) 2014, Singapore, December 10 to 12, 2014

Call for papers:

This special session is aimed to attract the interests
of people working in various aspects of multi/many core
architecture, from the circuit level to the application level,
stimulate the discussion and share and exchange their experiences
and knowledge.

Topics of interests for the special session include
(but not limited to):

– Performance and power-efficiency optimization,
– Heterogeneous multi/many core: architectural design
and run-time support,
– Parallelization libraries and tools,
– Performance and power consumption modeling methodologies,
– Design strategies for performance and power-efficiency in
circuit, architecture and software levels,
On-chip interconnect: architecture, protocol and routing,
– Memory hierarchy architecture and protocol.

Important Dates:

5/15: Title and abstract submission
(send by email to p2m2ca at
6/1: Full paper submission
(use the Paper Upload page of ISIC 2014 )
9/1: Notification of Paper Acceptance
10/15: Submission of Final Manuscript Papers

Organizing Members:

Hitoshi Oi, University of Aizu (JP)
Joao Pedro Pedroso, University of Porto (PT)
Ines Dutra, University of Porto (PT)
Xiongfei Liao, Intel (MY)
Senthilkumar Jayapal, Intel (MY)
Jorge Chavez, Cinvestav (MX)
Amilcar Meneses, Cinvestav (MX)
Yao-Min Cheng, Oracle (US)

For more information, please refer to
ISIC 2014 web site
or send email to p2m2ca at

Start: December 10, 2014
End: December 12, 2014
Venue: Singapore

December 13, 2014

Call for Papers: Workshop on Near-Data Processing

Submitted by Boris Grot

Co-located with MICRO-47
Cambridge, UK

Paper submissions due: Friday October 17, 2014
Notification: Tuesday November 4th, 2014
Final Paper Due: Monday December 8th, 2014

Computing in large-scale systems is shifting away from the traditional
compute-centric model to a much more data-centric one. This transition is
driven by the evolving nature of what computing comprises, no longer dominated
by the execution of arithmetic and logic calculations but instead dominated by
large data volume and the cost of moving data to the locations where
computations are performed. Data movement impacts performance,
energy-efficiency and reliability. These trends are leading to changes in the
computing paradigm driven by the notion of moving computation to the data in a
so-called Near-Data Processing approach, which seeks to perform computations
in the most appropriate location based on where data resides and what needs to
be done with it.

This workshop is intended to bring together experts from academia and industry
to share advances in the development of Near-Data Processing systems
principles, with emphasis on large-scale systems. Topics of interest include
but are not limited to:
- Analysis of applications illustrating the potential for Near-Data Processing
- System and software architectures for Near-Data Processing
- Programming models for distributed and heterogeneous infrastructures
driven by location of the data
- Processing/Memory/Storage architectures and microarchitectures for Near-Data
- Performance evaluation of Near-Data Processing systems and subsystems
- Energy-efficiency and reliability analysis and evaluation of Near-Data

Two kinds of papers are invited:
- Technical papers (4-6 pages) with preliminary results.
- Position papers (3 pages maximum) on directions for research and development.


Rajeev Balasubramonian , University of Utah
Boris Grot , University of Edinburgh
Jaime Moreno , IBM TJ Watson Research Center
Ravi Nair , IBM TJ Watson Research Center


Rajeev Balasubramonian , University of Utah
Boris Grot , University of Edinburgh
Jeff Draper , USC/ISI
Ron Dreslinski, University of Michigan
Maya Gokhale , Lawrence Livermore National Laboratory
Nuwan Jayasena, AMD Research
Jaime Moreno , IBM TJ Watson Research Center
Arrvindh Shriraman , Simon Fraser University

Further details and submission instructions available at

Start: December 13, 2014
End: December 13, 2014
Venue: Cambridge, UK

Call for Participation: MICRO-47

Submitted by Ronald Dreslinski

The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47)
December 13-17, 2014
Cambridge, UK

Micro-47 registration portal is live NOW.
You can take advantage of early bird registration until Nov. 12!

The International Symposium on Microarchitecture (MICRO) is the premier forum
for the presentation and discussion of new ideas in microarchitecture,
compilers, hardware/software interfaces, and design of advanced computing
and communication systems. The goal of MICRO is to bring together researchers
in the fields of microarchitecture, compilers, and systems for technical
exchange. The MICRO community has enjoyed having close interaction between
academic researchers and industrial designers ­ we aim to continue and
strengthen this longstanding tradition at the 47th MICRO in Cambridge, England.

On behalf of the Micro47 organization team, we look forward to seeing you
in Cambridge.

Start: December 13, 2014
End: December 17, 2014
Venue: Cambridge, UK

January 14, 2015

Call for Participation: RISC-V Workshop and Bootcamp

Submitted by Krste Asanovic

1st RISC-V Workshop and Boot Camp

January 14-15, 2015
Monterey, CA, USA

RISC-V (pronounced “risk-5″) is a new instruction set architecture
(ISA) that was originally designed to support computer architecture
research and education, but which we now hope will become a standard
open architecture for industry implementations. RISC-V was originally
developed in the Computer Science Division of the EECS Department at
the University of California, Berkeley, but has been made freely
available open-source under the BSD license for anyone to use.

The goals of this workshop are to inform the community of recent
activity in the various RISC-V projects underway around the globe and
to build consensus on future steps in the RISC-V project, while the
bootcamp provides an opportunity to learn about the existing RISC-V
infrastructure from the RISC-V development team. The workshop and
bootcamp will feature demos of multiple RISC-V silicon tapeouts as
well as FPGA board designs and associated software tools.

Space will be limited, so please register early!

Early Bird registration ends December 1.

Start: January 14, 2015
End: January 15, 2015
Venue: Monterey, CA

Call for Papers: SPAA 2015

Submitted by Jeremy Fineman

27th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2015)
June 13-15, 2015
Portland, Oregon, USA

This year, SPAA will be in the Federated Computing Research Conference (FCRC).
General FCRC information is available at

Submission deadlines:
- Abstract: January 14, 11:59pm EST
- Full versions: January 16, 11:59pm EST
Rebuttal period: March 4-5
Notification: March 23
Camera-ready: April 21

Contributed papers are sought in all areas of parallel algorithms and
architectures, encompassing any computation system that can perform multiple
operations or tasks simultaneously. Topics of interest include, but are not
limited to:

- parallel and distributed algorithms
- parallel and distributed data structures
- green computing & power-efficient architectures
- management of massive data sets
- parallel complexity theory
- parallel and distributed architectures
- multi-core architectures
- instruction level parallelism and VLSI
- compilers and tools for concurrent programming
- supercomputing architecture and computing
- transactional memory hardware and software
- game theory and collaborative learning
- routing and information dissemination
- resource management and awareness
- peer-to-peer systems
- mobile, ad-hoc, and sensor networks
- robustness, self-stabilization, and security
- synergy of parallelism in algorithms, programming, and architecture

Conference presentations will have two formats:

Regular presentations will be allotted a 25-minute talk and up to 10
pages in the proceedings. This format is intended for contributions
reporting original research, submitted exclusively to this conference.

Brief announcements will be allotted a 10-minute talk and a 2-page
abstract in the proceedings. This format is a forum for brief
communications, which may be published later in other conferences.

Every regular paper is eligible for the best paper award. The program
committee may decline to make this award or may split the award among
multiple papers.

Authors of contributed papers are encouraged to submit their manuscript
electronically. To submit electronically, visit
for instructions. This is the preferred method of submission. Authors unable
to submit electronically should contact the program chair Kunal Agrawal at to receive instructions on how to proceed.

Submissions for regular presentations should include an introduction
understandable to a nonspecialist including motivation and previous work, and
a technical exposition directed to a specialist. A submission should not
exceed 10 double-column pages in 9-point font, including figures, tables, and
references. More details may be supplied in a clearly marked appendix to
be read at the discretion of the program committee. A submission for brief
announcements should be no longer than two double-column pages in 9-point

Rebuttal Period:
There will be a rebuttal period in which the authors can point out
misunderstandings or comment on critical questions that PC members may have.
The rebuttal period will take place on March 4-5.

Umut Acar, Carnegie Mellon University
Grey Ballard, Sandia National Labs
Petra Berenbrink, Simon Fraser University
Dave Dice, Oracle Labs
Jeremy Fineman, Georgetown University
Pierre Fraigniaud, University of Paris 7
Seth Gilbert, National University of Singapore
Rachid Guerraoui, EPFL
MohammadTaghi HajiAghayi, University of Maryland
Maurice Herlihy, Brown University
Martin Hoefer, MPI Saarbrücken
Peter Kling, University of Pittsburgh
Bradley Kuzsmaul, MIT
Angelina Lee, Washington University in St. Louis
Ryan Newton, Indiana University
Gopal Pandurangan, University of Houston
Michael Spear, Lehigh University
Cliff Stein, Columbia University
Kanat Tangwongsan, Mahidol University
Sivan Toledo, Tel Aviv University
Uzi Vishkin, University of Maryland

Program Chair: Kunal Agrawal, Washington University in St. Louis
General Chair: Guy Blelloch, Carnegie Mellon University
Secretary: Christian Scheideler, University of Paderborn
Treasurer: David Bunde, Knox College
Publicity Chair: Jeremy Fineman, Georgetown University

Start: January 14, 2015 1:00 am
End: January 16, 2015 11:45 pm
Venue: Portland, Oregon

January 15, 2015

Call for Tutorials and Workshops: ISPASS 2015

Submitted by Kelly Shaw
ISPASS 2015 Call for Tutorial and Workshop Proposals

Call for Tutorial Proposals

Tutorial proposals are solicited for ISPASS-2015. Tutorials will be
held on March 29 in Philadelphia, PA.

Proposals for both half- and full-day tutorials are solicited on any
topic that is relevant to the ISPASS audience. Tutorials that focus on
workload characterization and analysis tools and techniques that
enable research across layers of the computational stack are strongly

In previous years, tutorials seeking to achieve any of the following
goals have been particularly successful:
* Describe an important piece of research/experimental infrastructure.
* Educate the community on an emerging topic.

Submission deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

Proposals should provide the following information:
* Title of the tutorial
* Presenter(s) and contact information
* Proposed duration (full day, half day)
* 1-2 paragraph abstract suitable for tutorial publicity
* 1 paragraph biography per presenter suitable for tutorial publicity
* Short description (for evaluation). This should include:
– Tutorial scope and objectives
– Topics to be covered
– Target audience
– If the tutorial has been held previously, the location
(i.e., conference), date, and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton ( with the subject
“ISPASS 2015 Tutorial Proposal”. Submissions will be acknowledged via


Call for Workshop Proposals

Workshop proposals are solicited for ISPASS-2015. Workshops will be
held on March 29 in Philadelphia, PA.

Proposals related to power/performance analysis and workload
characterization as it relates to computer architecture, operating
systems, programming languages/compilers in current and emerging areas
such as datacenters and cloud computing, systems based on non-volatile
memory technologies, mobile technologies, large scale data analysis,
smart infrastructure, and extreme scale computing are encouraged.

Submission Deadline: Thursday, January 15th, 2015
Notification: Friday, January 30th, 2015

Please include in your proposal:
* Title of the workshop
* Organizers and their affiliations
* Sample call for papers
* Duration – Half-Day or Full Day
* If the workshop was previously held, the location
(conference), date, and number of attendees

Proposals should take the form of a PDF document and be submitted via
e-mail to Andrew Hilton ( with the subject
“ISPASS 2015 Workshop Proposal”. Submissions will be acknowledged via

Start: January 15, 2015
End: January 15, 2015