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February 17, 2016

Call for Papers: Multi-Core and Many-Core Systems for Embedded Computing

Submitted by Amir Rahmani
http://www.pdp2016.org/SS9.html

Multi-Core and Many-Core systems for EMbedded Computing (MC)3
Special session in PDP 2016
Crete, Greece
17-19 Feb. 2016
 

This special session addresses all aspects of multi-core and many-core embedded
systems design. It presents new ideas in the multi-core field such as theory
and modeling, scalable and fault tolerant design approaches and frameworks,
algorithms, software, tools and applications, analysis and comparison, design
techniques and emerging implementations.

The proceedings of the special session will be published together with the
proceedings of PDP 2016 by the IEEE Computer Society, which are available
worldwide through the IEEE Xplore Digital Library. An extended version of the
best papers of the MC3 be invited to submit extended article versions to one of
the ISI-indexed high-quality journals.

Authors are invited to submit high quality papers representing original work
from both the academia and industry in (but not limited to) the following
topics:
- Design space exploration and design methodology for embedded multi-core and
many-core systems
- Specification and Formal modeling of embedded multi-core and many-core systems
- Multi-core/many-core embedded system design challenges
- Parallel programming and software for embedded multi- and many-core systems
- Memory management
- 3D architectures, integration and synthesis for embedded multi-core and many-
core systems
- On-chip communication architectures and networks-on-chip for embedded systems
- Heterogeneous multi-core and many-core architectures
- Hardware/software co-design
- Simulation, validation and verification
- Test and Fault Tolerance
- QoS management and performance analysis
- Multi-core and many-core cyber-physical systems
- Programming languages and compilers
- Thermal-, energy-, and power-aware architectures
- Monitoring and reconfiguration
- System prototyping
- Industrial practices and case studies

IMPORTANT DATES:
Deadline for paper submission: 6th September 2015
Acceptance notification: 19th October 2015

SPECIAL SESSION CHAIRS:
- Hannu Tenhunen (KTH Royal Institute of Technology, Sweden)
- Axel Jantsch (Vienna University of Technology, Austria)
- Pasi Liljeberg (University of Turku, Finland)
- Amir-Mohammad Rahmani (University of Turku, Finland)

Start: February 17, 2016
End: February 19, 2016
Venue: Crete, Greece

March 6, 2016

Call for Papers: Non-Volatile Memories Workshop 2016

Submitted by Steven Swanson
http://nvmw.ucsd.edu

7th Annual Non-Volatile Memories Workshop 2016
March 6-8, 2016
 

The 7th Annual Non-Volatile Memories Workshop (NVMW 2016) provides a unique
showcase for outstanding research on solid state, non-volatile memories. It
features a “vertically integrated” program that includes presentations on
devices, data encoding, systems architecture, and applications related to these
exciting new data storage technologies. Last year’s workshop (NVMW 2015)
included 40 speakers from top universities, industrial research labs, and device
manufacturers and attracted nearly 230 attendees. NVMW 2016 will build
on this success.

The organizing committee is soliciting presentations on any topic related
to non-volatile, solid state memories, including:
- Characterization of commercial or experimental memory devices.
- Advances in non-volatile memory-based storage systems.
- Operating system and file system designs for non-volatile memories.
- Security and reliability of solid-state storage systems.
- Non-volatile memories applications such as databases, NoSQL, and
big-data systems.

The goal is to facilitate the exchange of the latest ideas, insights, and
knowledge that can propel future progress. To that end, presentations may
include new results or work that has already been published during the 18
months prior to the submission deadline. In lieu of printed proceedings, we
will post the slides and extended abstracts of the presentations online.
Presentation of new work at the workshop does not preclude future publication.

SUBMISSION GUIDELINES:
Workshop submissions should be in the form of a 2-page presentation abstract.
Submissions will be evaluated on the basis of impact, novelty, and general
interest.

IMPORTANT DATES:
Submission deadline: November 20, 2015
Notification of acceptance: January 26, 2016

Further details on abstract submission, technical program, tutorials,
travel, social program, and travel grant will be provided on this website.

Start: March 6, 2016
End: March 9, 2016
Venue: San Digeo, CA

March 12, 2016

Call for Papers: CGO 2016

Submitted by Bjoern Franke
http://cgo.org/cgo2016/

2016 IEEE/ACM International Symposium on Code Generation
and Optimization (CGO)

co-located with HPCA, PPoPP, CC, and EuroLLVM
Barcelona, Spain
March 12-18, 2016
 

The International Symposium on Code Generation and Optimization (CGO) provides
a premier venue to bring together researchers and practitioners working at the
interface of hardware and software on a wide range of optimization and code
generation techniques and related issues. The conference spans the spectrum
from purely static to fully dynamic approaches, and from pure software-based
methods to specific architectural features and support for code generation and
optimization.

Original contributions are solicited on, but not limited to, the following
topics:

Code Generation, Translation, Transformation, and Optimization
- For performance, energy, virtualization, portability, security or reliability
concerns, and architectural support.
- Efficient execution of dynamically typed and higher-level languages.
- Optimization and code generation for emerging programming models, platforms,
domain-specific languages.
- Dynamic/static, profile-guided, feedback-directed, and machine learning based
optimization.

Static, Dynamic, and Hybrid Analysis
- For performance, energy, memory locality, throughput or latency, security,
reliability, or functional debugging.
- Program characterization methods.
- Efficient profiling and instrumentation techniques; architectural support.
- Novel and efficient tools.

Compiler design, practice and experience
- Compiler abstraction and intermediate representations.
- Vertical integration of language features, representations, optimizations,
and runtime support for parallelism.
- Solutions that involve cross-layer (HW/OS/VM/SW) design and integration.
- Deployed dynamic/static compiler and runtime systems for general purpose,
embedded system and Cloud/HPC platforms.

Parallelism, heterogeneity, and reconfigurable architectures
- Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA.
- Compiler-support for vectorization, thread extraction, task scheduling,
speculation, transaction, memory management, data distribution and
synchronization.

Authors should carefully consider the difference in focus with the co-located
conferences when deciding where to submit a paper. CGO will make the
proceedings freely available via the ACM DL platform during the period from two
weeks before to two weeks after the conference. This option will facilitate
easy access to the proceedings by conference attendees, and it will also enable
the community at large to experience the excitement of learning about the
latest developments being presented in the period surrounding the event itself.

Authors of accepted papers will be invited to formally submit their supporting
materials to the Artifact Evaluation process. The Artifact Evaluation process
is run by a separate committee whose task is to assess how the artifacts
support the work described in the papers. This submission is voluntary and will
not influence the final decision regarding the papers. Papers that go through
the Artifact Evaluation process successfully will receive a seal of approval
printed on the papers themselves. Additional information is available on the
CGO AEC web page.
Authors of accepted papers are encouraged to make these materials publicly
available upon publication of the proceedings, by including them as “source
materials” in the ACM Digital Library.

IMPORTANT DATES
Abstract Submission: September 12, 2015
Paper Submission: September 18, 2015
Author Response Period: October 28-30, 2015
Notification to Authors: November 8, 2015
Artifact Submission: November 20, 2015
Artifact Decision: December 22, 2015

ORGANIZING COMMITTEE
General Chair:
Björn Franke (U. of Edinburgh)

Programme Chairs:
Fabrice Rastello (Inria)
Youfeng Wu (Intel)

Programme Committee:
Erik Altman (IBM)
Saman Amarasinghe (MIT)
Edson Borin (U. of Campinas)
Florian Brandner (ENSTA)
Derek Bruening (Google)
Vugranam C. Sreedhar (IBM)
Wenguang Chen (Tsinghua U.)
Mila Dalla Preda (U. of Verona)
Evelyn Duesterwald (IBM)
Guang Gao (U. of Delaware)
Antonio Gonzalez (UPC/Intel)
Christophe Guillon (STmicroelectronics)
Sebastian Hack (U. of Saarland)
Ben Hardekopf (UCSB)
Wei-Chung Hsu (National Chiao Tung U.)
Robert Hundt (Google)
Chris J Newburn (Intel)
Vijay Janapa Reddi (U. of Texas)
Alexandra Jimborean (Uppsala)
Alain Ketterlin (U. Louis Pasteur)
Jaejin Lee (Seoul National U.)
Mary Lou Soffa (U. of Virginia)
Scott Mahlke (U. of Michigan)
Vineeth Mekkat (Intel)
John Mellor-Crummey (Rice U.)
Soo-mook Moon (Seoul National U.)
Tipp Moseley (Google)
Dorit Nuzman (Intel)
Michael O’Boyle (U. of Edinburgh)
Ramesh Peri (Intel)
Keshav Pingali (U. of Texas)
Louis-Noel Pouchet (Ohio State U.)
Aaron Smith (Microsoft)
Cheng Wang (Intel)
Chenggang Wu (ICT)
Jingling Xue (U. of New South Wales)
Qing Yi (U. of Colorado)
Antonia Zhai (U. of Minnesota)

Finance Chair:
Christophe Dubach (U. of Edinburgh)

Workshop and Tutorials Chair:
Jeronimo Castrillon (TU Dresden)

Student Travel Chair:
Ronald Mak (San Jose State U.)

Sponsors Chair:
Tobias Edler von Koch (Qualcomm)

Website Chair:
Tom Spink (U. of Edinburgh)

Artifact Evaluation Chairs:
Grigori Fursin (cTuning Foundation)
Bruce Childers (U. of Pittsburgh)

Steering Committee:
Kim Hazelwood (Yahoo Labs)
Robert Hundt (Google)
Scott Mahlke (Michigan)
Jason Mars (Michigan)
Kunle Olukotun (Stanford)
Vijay Janapa Reddi (U. of Texas)
Olivier Temam (Google) — Chair

Start: March 12, 2016
End: March 18, 2016
Venue: Barcelona, Spain

Call for Proposals: Workshops and Tutorials at HPCA 2016

Submitted by Carole-Jean Wu
http://hpca22.site.ac.upc.edu/index.php/conference/call-for-workshops-and-tutorials/

Workshops and Tutorials at HPCA 2016
Barcelona, Spain
March 12-13, 2016

The 2016 IEEE International Symposium on High-Performance Computer
Architecture (HPCA 2016) is seeking proposals for workshops and tutorials
to accompany the conference. Workshops and tutorials will be held on
Saturday-Sunday, March 12-13, and may be a half day or a full day in
length. We encourage members of the community to consider submitting
proposals for workshops and tutorials that bring together researchers and
practitioners working on research topics of significant current interest to
the HPCA community.

Prospective workshop and tutorial organizers are invited to submit
proposals in pdf of no more than two pages to the workshop and tutorials
chair Carole-Jean Wu, via email carole-jean.wu@asu.edu.

IMPORTANT DATES
– Deadline for submission: September 14, 2015, 11:59 PM EDT
– Notification of acceptance: October 14, 2015

SUBMISSION GUIDELINES

For workshops, please include in your proposal:
– Title of the workshop
– Organizers and their affiliations
– Sample call for papers, including the workshop’s main topics and URL
– Expected duration of the workshop: 1/2 day or full day
– For previously held workshops, the number of papers and attendees at
the last workshop.

For tutorials, please include in your proposal:
– Title of the tutorial
– Organizers, presenters, and their affiliations
– Abstract of the tutorial, including objectives, target audience, and
prerequisite knowledge
– List of topics to be covered and URL to the tutorial web page
– Expected duration of the tutorial: 1/2 day or full day
– For previously held tutorials, the location (i.e., which conference), date,
and number of attendees at the last tutorial.

Selection committee:
The workshop proposals will be evaluated by members of the HPCA 2016
organizing committee.

Sponsored by the IEEE Computer Society TC on Computer Architecture.

Start: March 12, 2016
End: March 13, 2016
Venue: Barcelona, Spain

HPCA 2016: Call for Papers, Workshops and Tutorials

Submitted by Augusto Vega
http://hpca22.site.ac.upc.edu/

22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA 2016)
collocated with PPoPP and CGO
Barcelona, Spain
March 12-16 2016
 

CALL FOR PAPERS:
The IEEE International Symposium on High-Performance Computer Architecture
(HPCA) provides a high-quality forum for scientists and engineers to present
their latest research findings in this rapidly changing field. Authors are
invited to submit papers on all aspects of high-performance computer
architecture.

Topics of interest include, but are not limited to:
– Processor, cache, and memory architectures
– Parallel computer architectures
– Multicore architectures
– Impact of technology on architecture
– Power-efficient architectures and techniques
– Dependable/secure architectures
– High-performance I/O systems
– Embedded and reconfigurable architectures
– Interconnect and network interface architectures
– Architectures for cloud-based HPC and data centers
– Innovative hardware/software trade-offs
– Impact of compilers and system software on architecture
– Performance modeling and evaluation
– Architectures for emerging technology and applications

SUBMISSION GUIDELINES
Authors should submit an abstract by Friday, September 4, 2015, 5pm EDT. They
should submit the full version of the paper by Friday, September 11, 2015,
5pm EDT. No requests for extensions will be granted. The full version should
be a PDF file that follows the submission guidelines, which will be available
at the submission website. Papers should be submitted for double-blind review.
We anticipate selecting a Best Paper award. All papers will be evaluated based
on their novelty, fundamental insights, experimental evaluation, and potential
for long-term impact.

IMPORTANT DATES
Abstract submission deadline: 4 September 2015, 5pm EDT
Paper submission deadline: 11 September 2015, 5pm EDT
Rebuttal period: 28-30 October 2015
Paper notification of acceptance: 9 November 2015

 
CALL FOR WORKSHOPS & TUTORIALS:
The IEEE International Symposium on High-Performance Computer Architecture
(HPCA) is seeking proposals for workshops and tutorials to accompany the
conference. Workshops and tutorials will be held on Saturday-Sunday, March
12-13, and may be a half day or a full day in length. We encourage members of
the community to consider submitting proposals for workshops and tutorials
that bring together researchers and practitioners working on research topics
of significant current interest to the HPCA community. Prospective workshop
and tutorial organizers are invited to submit proposals in PDF of no more
than two pages to the workshop and tutorials chair Carole-Jean Wu, via email
carole-jean.wu@asu.edu.

IMPORTANT DATES:
– Deadline for submission: 14 September 2015, 11:59pm EDT
– Notification of acceptance: 14 October 2015

For workshops, please include in your proposal:

– Title of the workshop
– Organizers and their affiliations
– Sample call for papers, including the workshop’s main topics and URL
– Expected duration of the workshop: 1/2 day or full day
– For previously held workshops, the number of papers and attendees at the
last workshop

For tutorials, please include in your proposal:

– Title of the tutorial
– Organizers, presenters, and their affiliations
– Abstract of the tutorial, including objectives, target audience, and
prerequisite knowledge
– List of topics to be covered and URL to the tutorial web page
– Expected duration of the tutorial: 1/2 day or full day
– For previously held tutorials, the location (i.e., which conference),
date, and number of attendees at the last tutorial

Selection committee:

The workshop proposals will be evaluated by members of the HPCA 2016
organizing committee. Sponsored by the IEEE Computer Society TC on Computer
Architecture.

Start: March 12, 2016
End: March 16, 2016
Venue: Barcelona, Spain

Call for Papers: HARSH 2016

Submitted by Augusto Vega
http://www.harsh-workshop.org/

Workshop on Highly-Reliable Power-Efficient Embedded Designs (HARSH 2016)
in conjunction with HPCA, CGO, and PPoPP 2016
Barcelona, Spain
March 12, 2016
 

IMPORTANT DATES:
– Submission deadline: Jan 22, 2016
– Notification of acceptance: Feb 8, 2016
– Final paper submission: Feb 26, 2016
– Workshop date: Mar 12, 2016

HARSH 2016 will provide a unique forum for the discussion of the challenges in
the design and operation of harsh environment-capable embedded processors.

Nowadays, embedded chips are deployed almost everywhere, from mobile phones to
on-board electronics in automobiles and satellites. Different from
conventional microprocessor designs, the operation conditions of embedded
processors are severely constrained by the environment. For example, in
aerospace applications, the computer installed on Mars rover “Curiosity” has
to tolerate extreme space radiation and temperatures, operate at low power,
and provide enough computation capability to perform mission-critical tasks.
Embedded designs for Unmanned Aerial Vehicles (UAVs) also encounter extremely
challenging design requirements. Despite their tight power budget, UAV chips
demand significant throughput for real-time high-speed image processing. In
the context of oil and gas exploration and extraction, embedded processors can
be found even on the drill string itself, to process sensor inputs in real
time while withstanding high temperatures and humidity levels.

To guarantee reliability across these drastically diverse environments, the
design and operation of embedded processors should not be solely confined to
the chip but traverse different layers in the computing system, involving
firmware, operating system, applications, as well as power management units
and communication interfaces. The goal of HARSH 2016 is to facilitate the
exchange of the latest ideas, insights, and knowledge related to all critical
aspects of new-generation harsh environment-capable embedded processors,
including micro-architectural approaches, cross-stack hardware/software
techniques, and emerging challenges and opportunities. We hope to attract a
group of interdisciplinary researchers from academia, industry, and government
research labs.

In addition to the presentation of selected paper submissions, keynote
speakers will be invited to kick-off the workshop sessions and a “Best Paper”
award will be presented at the conclusion of the workshop. To encourage
discussion between participants, HARSH 2016 will organize dedicated programs
for discussion between presenters and the audience.

Topics of interest include but are not limited to:

(1) Architecture design and implementation for highly-reliable power-efficient
embedded processors:
– Architectural approaches for reliability assurance under very-low power
budgets
– Availability, soft-error tolerance and recovery issues
– Highly-reliable cache/memory hierarchies
– Massive heterogeneous processing capabilities
– Power management techniques
– Very-low power, reliable real-time processing
– Specialized accelerator architectures and unique designs
– Reusable and/or reconfigurable embedded designs
– Packaging and cooling

(2) Cross-stack hardware/software techniques:
– Cross-stack approaches for reliability assurance under very-low power
budgets
– Reliability- and power-aware operating systems, compilers, workload
managers, firmware and other software
– Workload analysis and optimization for reliable low-power embedded
systems

(3) Applications:
– Aerospace: unmanned aerial vehicles (UAVs), planetary rovers and space
probes, satellites, avionic systems, etc.
– Medical support: lifesaving monitors, portable medical devices, high-end
imaging systems, etc.
– Oil and gas exploration and extraction
– Aerial surveillance
– Disaster search, rescue, and relief
– Novel applications for highly-reliable low-power embedded chips

SUBMISSION GUIDELINES:
Papers reporting original research results pertaining to the above and related
topics are solicited. Full paper manuscripts must be in English of up to 6
pages (using the IEEE two-column format). The on-line submission site is
EasyChair. If web submission is not possible, please contact the program
co-chairs for alternate arrangements.

ORGANIZING COMMITTEE:
– Augusto Vega (IBM Research)
– Xuan (Silvia) Zhang (Washington University in St. Louis)
– David Brooks (Harvard University)
– Alper Buyuktosunoglu (IBM Research)
– Pradip Bose (IBM Research)

Start: March 12, 2016
End: March 12, 2016
Venue: Barcelona (Spain)

Call for Participation: HPCA 2016

Submitted by Augusto Vega
http://hpca22.site.ac.upc.edu/

22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA)
collocated with PPoPP-2016 and CGO-2016
Barcelona, Spain
March 12-16 2016
 

IMPORTANT DATES:
– Travel grant application deadline: January 31, 2016, 11:59pm (GMT+0)
– Early registration deadline: February 3, 2016

The International Symposium on High-Performance Computer Architecture provides
a high-quality forum for scientists and engineers to present their latest
research findings in this rapidly-changing field. HPCA-22 will be held in
conjunction with the 21st ACM SIGPLAN Symposium on Principles and Practice of
Parallel Programming (PPoPP-2016) and the 14th International Symposium on Code
Generation and Optimization (CGO-2016).

Conference program, workshops and tutorials, registration and lodging
information are all available at the conference website.

Start: March 12, 2016
End: March 16, 2016
Venue: Barcelona, Spain

March 13, 2016

Call for Papers: Sensor to Cloud Architectures Workshop

Submitted by Govind Sreekar Shenoy
https://sites.google.com/site/scaw16/home

Sensor to Cloud Architectures Workshop (SCAW-2016)
in conjunction with HPCA 2016
Barcelona, Spain
March 13, 2016
 

IMPORTANT DATES:
Paper submission deadline: January 8, 2016 (23:59 PST)
Author notification: January 18, 2016
Final paper submission: February 19, 2016
Workshop: March 13, 2016

The computer industry is witnessing an inflection point – ‘Internet of things
combined with Cloud Analytics’ – which has implications from end (sensor
devices) to end (cloud architectures). Many technologies come together
contributing to this major inflection point: Computing platforms getting
smaller (e.g. handheld devices, wearables), richer (e.g. image and language
understanding) and broader (i.e. reaching the masses via Internet of Things).
Sensors operating in constrained environments connected through intelligent
gateways and cloud backend creates a very complex environment for the
operators, system integrators, and developers of this new emerging technology.
Discovering and managing sensor devices; collecting, cleaning and storing
discoverable data; normalizing, aggregating and analyzing the data for insights
and actions; managing the security and privacy of the data, enforcing the
access privileges and trusted execution environments – all these are required
to make this revolution happen.

The research challenges in IoT platforms are multi-fold:
- providing rich functionality and wider power/performance range for sensor devices
- attempting to cover a broad range of applications that can be migrated
from cloud to gateways and sensor devices
- enabling a scalable and modular cloud architecture that provides the
required real-time and uptime capabilities
- providing a rich software programming environment that eases the challenge
of developing applications on end to end platforms consisting of elements
ranging from sensors to gateways to cloud.

The goal of this workshop is to bring together academic researchers and
industry practitioners to discuss future IoT sensor-to- cloud architectures
including sensors, gateways and cloud architectures.

Topics of interest include, but are not restricted to, the following:

1) Sensors, Actuators, Gateway & Controllers Architectures:
- Architectures for wearable and IOT devices
- Heterogeneity in Cores, Frequency, Cache, Memory
- Power, Performance, Energy optimizations
- SoCs, CPU/GPU, CPU/GPGPU architectures
- Ultra-Low Power Core Micro-architectures
- Fabrics / Network-on-chip, Cache/Memory Hierarchies
- HW Support for Heterogeneity, Programmability, Modularity
- Simulation / Emulation Methodologies
- Protocols and abstraction layers (MQTT, CoAP, REST, …)

2) Cloud Architecture:
- Data Center Architectures for IoT
- Edge/Fog computing, Dynamic Cloud-gateway-device offloads
- Workload partitioning between heterogeneous cores and accelerators
- BigData Frameworks (Hadoop, Spark, Flink, …)
- Heterogeneous Datacenters (FPGA, GPU, Accelerators)
- Machine Learning Algorithms & Applications, Graph processing,
Deep Neural Networks
- Batch, streaming and distributed Analytics
- Design Patterns and Application Programming frameworks

3) Emerging Workloads and Use cases:
- Wearable and IOT use cases and workloads
- Speech/Image recognition and understanding, Cognitive computing
- Personal Assistants, Predictive/Prescriptive Analytics, Robotics
- Workload Analysis for power/performance/energy optimization and
acceleration
- Performance Monitoring and Simulation, Architecture analysis

4) Novel Accelerator Designs:
- Specialized Accelerator Architectures and Designs
- Machine Learning, Neural Network and Graph Processing accelerators
- Domain-Specific Programmable/Configurable Accelerators
- Accelerator Interfaces for Programmability
- Development Environments for Accelerator Design

SUBMISSION GUIDELINES:
Interested authors are encouraged to submit extended abstracts (1-2 pages)
or short papers (6 pages) by email to the organizing chairs. The deadline for
submission is January 8, 2016.

ORGANIZERS:
Ramesh Illikkal, Intel
Ravi Iyer, Intel
Murali Emani, University of Edinburgh
Govind Sreekar Shenoy, University of Edinburgh

Start: March 13, 2016
End: March 13, 2016
Venue: Barcelona

March 17, 2016

Call for Papers: ANCS 2016

Submitted by Haowei Yuan
http://www.ancsconf.org

The 12th ACM/IEEE Symposium on Architectures for Networking and
Communications Systems (ANCS 2016)

co-located with NSDI 2016
Santa Clara, CA, USA
March 17-18, 2016
 

IMPORTANT DATES:
Paper registration and abstract: November 2, 2015
Submission deadline: November 9, 2015
Author notification: December 21, 2015

ANCS is the premier forum for presenting and discussing original research that
explores the relationship between the algorithms and architectures of data
communication networks and the hardware and software elements from which these
networks are built. This includes both experimental and theoretical analysis.
To recognize and foster the increasing importance of research into the
co-design of computer and network systems, the conference also places an
emphasis on systems issues arising from the interaction of computer and network
architectures.

Topics of interest include, but are not limited to:
- System design for future network architectures
- Router and switch architectures
- High-speed networking algorithms and mechanisms
- Software Defined Networking systems
- Network Functions Virtualization architectures
- Virtualized infrastructure architectures and systems
- Architectures for data centers
- Converged router, server, and storage platforms
- Host-network interface issues
- Techniques and systems for large-scale data analysis
- Wireless network hardware and related software, including software
radios
- Information-centric network architectures, platforms, and mechanisms
- Network security architectures and security anchor/enhancement devices
- Network measurement techniques, architectures, and devices
- Scalable programming and application frameworks
- High-performance and high-function network processing platforms
- Power- and size-optimized computer and communications platforms
- Hardware accelerators and offload engines
- Single-chip networking elements, e.g., multicore, NPU, FPGA, TCAM,
custom ASIC
- Network-on-Chip architectures and applications
- Memory architectures and technologies for packet, state and table
storage.

IMPORTANT DATES:
- Abstract registrations deadline: Nov 2, 2015 at 11:59 PM PT (US).
- Full paper submission deadline: Nov 9, 2015 at 11:59 PM PT (US).
- Notification of acceptance: December 21, 2015

SUBMISSION GUIDELINES:
ANCS 2016 will use single-blind reviewing, so submitted papers should include
the authors’ names. All papers must be submitted electronically via the
submission site: http://www.ancsconf2016.org/.

Submit papers using a 10pt font on 12pt leading formatted for printing on
Letter-sized (8.5″ by 11″) paper. Paper text blocks must follow ACM guidelines:
double-column, with each column 9.25″ by 3.33″, 0.33″ space between columns.
Each column must contain no more than 55 lines of text. The template can be
found at: ACM Manuscript Templates for Conference Proceedings:

http://www.acm.org/sigs/publications/proceedings-templates

This year ANCS welcomes submissions of long and short papers. Long papers are
the more traditional and complete form to present technical work, and should be
no more than 12 pages (excluding references). Long papers may also be extended
versions of previously-published short preliminary papers (such as workshop
papers), as long as they are in accordance with published SIGCOMM policy. Short
papers are the preferred vehicle for contributions whose novelty and impact
show the same technical excellence, and whose description fits within 6 pages
(excluding references). Short papers will be reviewed with a more open mind
towards criticizing the scope of evaluation or broadness of topics impacted
than the long papers. Note that position papers, critiques of networking
research, and ideas that are not yet fully complete or evaluated are not a good
fit for ANCS. Papers accompanied by nondisclosure agreement requests will not
be considered nor ever disclosed.

We encourage submissions containing original ideas that are relevant to the
scope of ANCS. Like other conferences, ANCS requires that papers not be
submitted simultaneously to any other conferences or publications; that
submissions not be previously published in peer-reviewed conferences; and that
accepted papers not be subsequently published elsewhere. Papers describing work
that was previously published in a peer-reviewed workshop are allowed, if the
authors clearly describe what significant new content has been included.

All submissions will be treated as confidential prior to publication in the
proceedings; rejected submissions will be permanently treated as confidential.

SPONSORED BY:
- ACM Special Interest Group on Computer Architecture (SIGARCH)
- ACM Special Interest Group on Communications (SIGCOMM)
- IEEE Computer Society Tech. Committee on Computer Architecture (TCCA)

ORGANIZING COMMITTEE:
General Chair:
Patrick Crowley (Washington University in St. Louis, USA)

Program Chairs:
Luigi Rizzo, Università di Pisa, Italy
Laurent Mathy, Université de Liège, Belgium

Start: March 17, 2016
End: March 18, 2016
Venue: Santa Clara

March 29, 2016

Call for Papers: SELSE 2016

Submitted by William H. Robinson
http://www.selse.org/

The 12th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2016)
Austin, TX, USA
March 29 – 30, 2016
 

IMPORTANT DATES:
- Register an abstract: December 14, 2015
- Paper submission: January 4, 2016
- Authors notification: February 23, 2016
- Camera-ready submission: March 8, 2016

The growing complexity and shrinking geometries of modern manufacturing
technologies are making high-density, low-voltage devices increasingly
susceptible to the influences of electrical noise, process variation,
transistor aging, and the effects of natural radiation. The system-level
impact of these errors can be far- reaching. Growing concern about
intermittent errors, unstable storage cells, and the effects of aging are
influencing system design, and failures in memories account for a significant
fraction of costly product returns. Emerging logic and memory device
technologies introduce several reliability challenges that need to be
addressed to make these technologies viable. Additionally, reliability is a
key issue for large-scale systems, such as those in data centers and cloud
computing infrastructure.

The SELSE workshop provides a forum for discussion of current research and
practice in system-level error management. Participants from industry and
academia explore both current technologies and future research directions.
SELSE is soliciting papers that address the system-level effects of errors
from a variety of perspectives: architectural, logical, circuit-level, and
semiconductor processes. Case studies are also solicited.

Key areas of interest are (but not limited to):
- Technology trends and the impact on error rates.
- New error mitigation techniques.
- Characterizing the overhead and design complexity of error
mitigation techniques.
- Case studies describing the tradeoff analysis for reliable systems.
- Experimental data on failures in current and emerging technologies.
- System-level models: derating factors and validation of error
models.
- Error handling protocols (higher-level protocols for robust system
design).
- Characterization of reliability of systems deployed in the field and
mitigation of issues.
- Software-level impact of hardware failures.
- Software frameworks for resilience.

SUBMISSION GUIDELINES:
Authors are requested to register to submit a paper by December 14, 2015. The
paper submission deadline is January 4, 2016. Papers will be considered for
both oral and poster presentation, and all accepted submissions will be
distributed to SELSE participants. Authors will be notified by February 23,
2016. Final papers are due on March 8, 2016.

Additional information and guidelines for submission are available at
http://www.selse.org. Submissions and final papers should be in PDF following
IEEE two-column transactions format that does not exceed six printed pages of
text; the bibliography does not count against this page limit. Papers are not
made available through IEEE, and authors retain the copyright of their work.
Authors may optionally choose to make their presentations available online at
the workshop web site. Authors of papers selected for the DSN Best-of-SELSE
session will have the option to work with the DSN publications committee to
prepare the camera-ready versions for the DSN workshop proceedings.

There will be a special session at the 46th Annual IEEE/IFIP Conference on
Dependable Systems and Networks (DSN) in Toulouse, France dedicated for the
best papers of SELSE 2016. The selected SELSE papers will have the opportunity
to be presented in the special session and published in the DSN workshop
proceedings.

ORGANIZING COMMITTEE:
General Chairs:
Helia Naeimi, Intel
Dan Alexandrescu, iRoC

Program Chairs:
Sudhanva Gurumurthi, IBM/University of Virginia
Mattan Erez, The University of Texas at Austin

Finance Chairs:
Siva Hari, NVIDIA
Daniel Lowell, AMD

Publicity Chairs:
William H. Robinson, Vanderbilt University
Paolo Rech, UFRGS
Yiannakis Sazeides, University of Cyprus

Documents Chairs:
Mehdi Tahoori, Karlsruhe Institute of Technology
Mojtaba Ebrahimi, Karlsruhe Institute of Technology

Austin Industry Liaison:
Indrani Paul, AMD

Webmaster:
Marios Kleanthous, Mesoyios College

Local Arrangements Chair:
Vijay Janapa Reddi, The University of Texas at Austin

Advisors to the Committee:
Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD
Adrian Evans, iRoC

Start: March 29, 2016
End: March 30, 2016
Venue: Austin, TX, USA