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November 1, 2014

Call for Papers: IJPP Special Issue on Workload Optimized Systems

Submitted by Parijat Dube
http://www.springer.com/10766

Springer International Journal of Parallel Programming (IJPP)
Special Issue on Workload Optimized Systems

 

The slowdown in Moore’s Law makes it increasingly important to optimize
systems around specific workloads. Such workload optimized systems have
hardware and/or software specifically designed to run well for a particular
workload or workload class. Such systems include, but are not limited to
traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory
accelerators, I/O accelerators, hybrid systems, and IT appliances. This
workload optimized system approach contrasts to the broad general purpose
direction of computing over many decades. The workload optimized systems
approach is growing in importance, as we see in systems from cellphones to
tablets to routers to game machines to Top500 supercomputers, and IT
appliances such as IBM’s DataPower and Netezza, and Oracle’s Exadata. The
goal of this special issue is to foster awareness in industry and academic
community on workload optimized systems and to expose cross hw/sw stack
unique systems and software research challenges associated with such
systems. All submitted papers are subject to the same review process as those
papers accepted for publication in the regular issues. The special issue seeks
original papers on a range of topics related to workload optimized systems
including, but not limited to

- GPUs, FPGAs, ASIC Accelerators
- Memory and I/O accelerators
- Network accelerators
- Storage optimized systems
- System level accelerators
- IT Appliances
- Systems in specific domains like analytics, cloud, cognitive, mobile etc.
- Converged/Hybrid/Heterogeneous systems
- Cross hardware/software stack design and optimization
- Programming models for workload optimized systems
- Measurements and Experimentation
- Workload characterization and profiling
- Performance modeling and optimization
- Workload scheduling and orchestration
- Runtime management systems
- Industrial Experiences

IMPORTANT DATES
Manuscript due: March 27, 2015
First decision notification: June 5, 2015
Revision due: July 10, 2015
Final decision notification: August 14, 2015
Final version due: September 11, 2015

SUBMISSIONS
Authors are encouraged to submit high-quality, original work that
has neither appeared in, nor is under consideration by, other
journals. All papers will be reviewed following standard reviewing
procedures for the Journal.
Papers must be prepared in accordance with the Journal guidelines:

http://www.springer.com/10766.

Manuscripts must be submitted to: http://IJPP.edmgr.com.
Choose “S.I.: Workload Optimized Systems” as the article type.

GUEST EDITORS
Erik Altman, IBM Research, Yorktown Heights, NY. ealtman@us.ibm.com
Parijat Dube, IBM Research, Yorktown Heights, NY. pdube@us.ibm.com

 

Start: November 1, 2014
End: October 1, 2015

July 14, 2015

Call for papers: ACM e-Energy 2015

Submitted by Vincenzo Mancuso
Preliminary Call for Papers

ACM e-Energy 2015

Bangalore, India

June 2015 (Exact date TBC)

As countries round the world rally to reduce their carbon emissions
in the face of rising energy costs, there is a growing need to
research computing and communication technologies that will support
smarter and more sustainable energy solutions (e.g., Smart Grid).
Such technologies, measure, monitor and control energy systems
(e.g., micro-grids and electric vehicles); inform and shape human
demand; aid in the prediction, deployment, storage and control
of energy resources; and determine how utilities, generators,
regulators, and consumers measure, analyze, and collectively control
system elements. In turn, the exponential growth in the deployment
of communication and computing technologies has made them large-scale
energy consumers. Therefore, new architectures, technologies and
systems are being developed and deployed to make computing and
networked system more energy efficient.

The Sixth International Conference on Future Energy Systems
(ACM e-Energy), to be held in Bangalore, India in June 2015,
aims to be the premier venue for researchers working in the
broad areas of computing and communication for smart energy
systems (including the smart grid), and in energy efficient
computing and communication systems. By bringing together
researchers from a range of disciplines in a high-quality
single-track conference with significant opportunities for
individual and small-group interaction, it will serve as a major
forum for presentations and discussions that will shape the
future of this area.

We solicit high-quality papers in the areas of computing and
communication for the Smart Grid and energy-efficient computing
and communications. We welcome submissions describing theoretical
advances as well as system design, implementation and
experimentation. ACM e-Energy is committed to a fair, timely, and
thorough review process providing authors of submitted papers with
sound and detailed feedback.

Topics covered:

—————

. Advances in monitoring and control of smart homes and buildings

. Sensing, monitoring, control, and management of energy systems

. Energy-efficient computing and communication, including
energy-efficient data centers

. The impact of storage integration on the smart grid

. Electric Vehicle monitoring and control

. Distribution and transmission network control techniques

. Microgrid and distributed generation management and control

. Modeling, control, and architectures for renewable energy
generation resources

. Smart grid communication architectures and protocols

. Privacy and security of smart grid infrastructure

. Innovative pricing and incentives for demand-side management

. Novel technologies to enhance reliability and robustness of
energy systems

. HCI for energy monitoring, management, and awareness

. User studies and behavioral change enabled by computing and
communication technologies

. Data analytics for the smart grid and energy-efficient systems

Submissions:

————

Two type of contributions are solicited:

. Full papers, up to 12 pages in ACM double-column format, should
present original theoretical and/or experimental research in any of
the areas listed above that has not been previously published,
accepted for publication, or is not currently under review by
another conference or journal.

.. Poster/demo descriptions, up to 2 pages in ACM double-column
format showcasing works-in-progress; accepted posters/demos will
be presented at the conference. Topics of interest are the same
as research topics listed above. Preference will be given to
posters/demos where the primary contribution is from one or
more students.

Papers will be judged in terms of technical quality and originality.

Important Dates: (TBC)

———————–

Submission Deadline: January 2015

Reviews and Notification: March-April 2015

Conference: June 2015

General Co-Chairs:

—————

Shivkumar Kalyanaraman (IBM Research, AUS)

Deva P. Seetharam (IBM Research, INDIA)

TPC Co-chairs:

————–

Mani Srivastava (UCLA)

Sarvapali (Gopal) Ramchurn ( U. Southampton)

Start: July 14, 2015
End: July 17, 2015

July 22, 2015

Call for Papers: ISLPED 2015

Submitted by Andreas Burg
http://www.islped.org/2015/index.html

International Symposium on Low Power Electronics and Design
July 22 – July 24, 2015
Rome, Italy
 

IMPORTANT DATES
Technical Paper Submission Deadline:
- Abstract registration by Feb 22, 2015
- Full paper by March 1, 2015
Invited Talk, Panel, and Embedded Tutorial Proposals Deadline: April 1, 2015
Notification of Paper Acceptance: May 1, 2015
Submission of Camera-Ready Papers: June 1, 2015

For more information or general queries, please email islped@islped.org.
Follow us on Twitter: http://twitter.com/islped

Sponsored by the IEEE Circuits and Systems Society (CASS) and the ACM Special
Interest Group on Design Automation (SIGDA).

The International Symposium on Low Power Electronics and Design (ISLPED) is
the premier forum for presentation of innovative research in all aspects of
low power electronics and design, ranging from process technologies and
analog/digital circuits, simulation and synthesis tools, system-level
design and optimization, to system software and applications. Specific
topics include, but are not limited to, the following three main tracks
and sub-areas:

1. Technology, Circuits, and Architecture

1.1. Technologies
Low-power technologies for Device, Interconnect, Logic, Memory,
2.5/3D, Cooling, Harvesting, Sensors, Optical, Printable, Biomedical,
Battery, and Alternative energy storage devices.

1.2. Circuits
Low-power digital circuits for Logic, Memory, Reliability, Clocking,
Power gating, Resiliency, Near-threshold and Sub-threshold,
Variability, and Digital assist schemes; Low-power analog/mixed-signal
circuits for Wireless, RF, MEMS, AD/DA Converters, I/O, PLLs/DLLS,
Imaging, DC-DC converters, and Analog assist schemes.

1.3. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, Processor cores
(compute, graphics and other special purpose cores), Cache, Memory,
Arithmetic/Signal processing, Cryptography, Variability, Asynchronous
design, and Nonconventional computing.

2. CAD, Systems, and Software

2.1. CAD Tools and Methodologies
CAD tools and methodologies for low-power and thermal-aware design
addressing power estimation, optimization, reliability and variation impact
on power, and power-down approaches at all levels of design abstraction:
physical, circuit, gate, register transfer, behavioral, and algorithm.

2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design and platforms
for microprocessors, DSPs, embedded systems, FPGAs, ASICs, SoCs,
heterogeneous computing, data-center power delivery and cooling, and
system-level power implications due to reliability and variability.

2.3. Software and Applications
Energy-efficient, energy-aware, and thermal-aware system software and
application design including scheduling and management, power
optimizations through HW/SW interactions, and emerging low power
applications such as approximate and brain-inspired computing, the
Internet-of-Things (IoT), wearable computing, body-area/in-body networks,
and wireless sensor networks.

3. Industrial Design Track (New Initiative for 2015)

3.1. Industry Perspectives
For the first time, ISLPED’15 solicits papers for an “Industrial Design” track
to reinforce interaction between the academic research community and
industry. Industrial Design track papers have the same submission deadline
as regular papers and should focus on similar topics, but are expected to
provide a complementary perspective to academic research by focusing on
challenges, solutions, and lessons learnt while implementing industrial-
scale designs. In addition to purely hardware-focused papers, papers
describing power optimizations through an interaction of hardware and
software are also welcome.

Submissions should be full-length papers of up to 6 pages (PDF format,
double-column, US letter size, using the IEEE Conference format, available at

http://www.ieee.org/conferences_events/conferences/publishing/templates.html),

including all illustrations, tables, references, and an abstract of no more
than 250 words. Submissions must be anonymous. Submissions exceeding 6 pages
or identifying the authors, either directly or through explicit references to
their prior work, will be automatically rejected. More information on paper
submission can be found at http://www.islped.org.

Submitted papers must describe original work that has not been
published/accepted or currently under review by another journal, conference,
symposium, or workshop at the same time. Accepted papers will be published in
the Symposium Proceedings and included in IEEE Xplore and the ACM Digital
Library. ISLPED’15 will present two Best Paper Awards based on the ratings of
reviewers and a panel of judges.

There will be several invited talks by industry and academic thought leaders
on key issues in low power electronics and design. The Symposium may also
include embedded tutorials to provide attendees with the necessary background
to follow recent research results, as well as panel discussions on future
directions in low power electronics and design.

Proposals for invited talks, embedded tutorials, and panels should be sent by
email to the ISLPED’15 Technical Program Co-Chairs, Vijay Raghunathan
(vr@purdue.edu) and Ruchir Puri (ruchir@us.ibm.com) by the deadline listed
above.

ORGANIZING COMMITTEE AND SYMPOSIUM OFFICERS:

General Co-Chairs:
Luca Benini, Univ. of Bologna, luca.benini@unibo.it
Renu Mehra, Synopsys, renu@synopsys.com
Mauro Olivieri, Sapienza Univ., olivieri@diet.uniroma1.it

Program Co-Chairs:
Ruchir Puri, IBM, ruchir@us.ibm.com
Vijay Raghunathan, Purdue Univ., vr@purdue.edu

Local Arrangement Chair:
Alessandro Trifiletti, Sapienza Univ., alessandro.trifiletti@diet.uniroma1.it

Industry Liaison:
David Garrett, Broadcom, garrettd@broadcom.com

Publicity Co-Chairs:
Andreas Burg, EPFL, andreas.burg@epfl.ch
Deming Chen, UIUC, dchen@illinois.edu

Publication Chair:
Paul Wesling, IEEE, p.wesling@ieee.org

Industrial Design Track Co-Chairs:
Edith Beigne, CEA-Leti, edith.beigne@cea.fr
Juergen Karmann, Infineon, juergen.karmann@infineon.com

Design Contest Co-Chairs:
Alberto Macii, Politecnico di Torino, alberto.macii@polito.it
Hiroki Matsutani, Keio University, matutani@arc.ics.keio.ac.jp

Treasurer:
Yu Wang, Tsinghua University, yu-wang@mail.tsinghua.edu.cn

Web Chair:
Theo Theocharides, Univ. of Cyprus, ttheocharides@ucy.ac.cy

Local Staff:
Francesco Menichelli, Sapienza Univ.
Antonio Mastrandrea, Sapienza Univ.
Zia Abbas Zaidi, Sapienza Univ.
Usman Khalid, Sapienza Univ.
Monica Coppola, FREEnergy
 

Start: July 22, 2015
End: July 24, 2015
Venue: Rome, Italy

Call for Papers: ISLPED 2015 (Extended Deadline for Abstracts: Mar 1)

Submitted by Andreas Burg
http://www.islped.org/2015/index.html

International Symposium on Low Power Electronics and Design (ISLPED)
http://www.islped.org Rome, Italy
July 22 – July 24, 2015
 

IMPORTANT DATES:
Abstract Registration Deadline (extended): March 1st, 2015
Full paper submission Deadline: March 8th, 2015
Invited Talk, Panel, and Embedded Tutorial Proposals Deadline: April 1, 2015
Notification of Paper Acceptance: May 1, 2015
Submission of Camera-Ready Papers: June 1, 2015

Sponsored by the IEEE Circuits and Systems Society (CASS) and the ACM Special
Interest Group on Design Automation (SIGDA).

The International Symposium on Low Power Electronics and Design (ISLPED) is the
premier forum for presentation of innovative research in all aspects of low
power electronics and design, ranging from process technologies and
analog/digital circuits, simulation and synthesis tools, system-level design
and optimization, to system software and applications. Specific topics include,
but are not limited to, the following three main tracks and sub-areas:

1. Technology, Circuits, and Architecture

1.1. Technologies
Low-power technologies for Device, Interconnect, Logic, Memory,
2.5/3D, Cooling, Harvesting, Sensors, Optical, Printable, Biomedical,
Battery, and Alternative energy storage devices.

1.2. Circuits
Low-power digital circuits for Logic, Memory, Reliability, Clocking,
Power gating, Resiliency, Near-threshold and Sub-threshold,
Variability, and Digital assist schemes; Low-power analog/mixed-signal
circuits for Wireless, RF, MEMS, AD/DA Converters, I/O, PLLs/DLLS,
Imaging, DC-DC converters, and Analog assist schemes.

1.3. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, Processor cores
(compute, graphics and other special purpose cores), Cache, Memory,
Arithmetic/Signal processing, Cryptography, Variability, Asynchronous
design, and Nonconventional computing.

2. CAD, Systems, and Software

2.1. CAD Tools and Methodologies
CAD tools and methodologies for low-power and thermal-aware design
addressing power estimation, optimization, reliability and variation impact
on power, and power-down approaches at all levels of design abstraction:
physical, circuit, gate, register transfer, behavioral, and algorithm.

2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design and platforms
for microprocessors, DSPs, embedded systems, FPGAs, ASICs, SoCs,
heterogeneous computing, data-center power delivery and cooling, and
system-level power implications due to reliability and variability.

2.3. Software and Applications
Energy-efficient, energy-aware, and thermal-aware system software and
application design including scheduling and management, power
optimizations through HW/SW interactions, and emerging low power
applications such as approximate and brain-inspired computing, the
Internet-of-Things (IoT), wearable computing, body-area/in-body networks,
and wireless sensor networks.

3. Industrial Design Track (New Initiative for 2015)

3.1. Industry Perspectives
For the first time, ISLPED’15 solicits papers for an “Industrial Design” track
to reinforce interaction between the academic research community and
industry. Industrial Design track papers have the same submission deadline
as regular papers and should focus on similar topics, but are expected to
provide a complementary perspective to academic research by focusing on
challenges, solutions, and lessons learnt while implementing industrial-
scale designs. In addition to purely hardware-focused papers, papers
describing power optimizations through an interaction of hardware and
software are also welcome.

SUBMISSION INSTRUCTIONS:
Submissions should be full-length papers of up to 6 pages (PDF format, double-
column, US letter size, using the IEEE Conference format, available at

http://www.ieee.org/conferences_events/conferences/publishing/templates.html),

including all illustrations, tables, references, and an abstract of no more
than 250 words. Submissions must be anonymous. Submissions exceeding 6
pages or identifying the authors, either directly or through explicit references to
their prior work, will be automatically rejected. More information on paper
submission can be found at http://www.islped.org.

Submitted papers must describe original work that has not been
published/accepted or currently under review by another journal, conference,
symposium, or workshop at the same time. Accepted papers will be submitted to
the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’15 will
present two Best Paper Awards based on the ratings of reviewers and a panel of
judges.

There will be several invited talks by industry and academic thought
leaders on key issues in low power electronics and design. The Symposium
may also include embedded tutorials to provide attendees with the necessary
background to follow recent research results, as well as panel discussions
on future directions in low power electronics and design. Proposals for
invited talks, embedded tutorials, and panels should be sent by email to
the ISLPED’15 Technical Program Co-Chairs, Vijay Raghunathan (vr@purdue.edu)
and Ruchir Puri (ruchir@us.ibm.com) by the deadline listed above.

ORGANIZING COMMITTEE:
General Co-Chairs:
Luca Benini, Univ. of Bologna
Renu Mehra, Synopsys
Mauro Olivieri, Sapienza Univ.

Program Co-Chairs:
Ruchir Puri, IBM, ruchir@us.ibm.com
Vijay Raghunathan, Purdue Univ.

Local Arrangement Chair:
Alessandro Trifiletti, Sapienza Univ.

Industry Liaison:
David Garrett, Broadcom

Publicity Co-Chairs:
Andreas Burg, EPFL
Deming Chen, UIUC
Baris Taskin, Drexel University

Publication Chair:
Paul Wesling, IEEE

Industrial Design Track Co-Chairs:
Edith Beigne, CEA-Leti
Juergen Karmann, Infineon

Design Contest Co-Chairs:
Alberto Macii, Politecnico di Torino
Hiroki Matsutani, Keio University

Treasurer:
Yu Wang, Tsinghua University

Web Chair:
Theo Theocharides, Univ. of Cyprus

Local Staff:
Francesco Menichelli, Sapienza Univ.
Antonio Mastrandrea, Sapienza Univ.
Zia Abbas Zaidi, Sapienza Univ.
Usman Khalid, Sapienza Univ.
Monica Coppola, FREEnergy
 

Start: July 22, 2015
End: July 24, 2015
Venue: Rome, Italy

Call for Participation: ISLPED 2015 (early registration deadline: June 5)

Submitted by Andreas Burg
http://www.islped.org/

International Symposium on Low Power Electronics and Design (ISLPED’15)
Rome, Italy
July 22-24, 2015
 

ISLPED is the world’s premier event on low power design.
It is sponsored by the IEEE Circuits and Systems Society and the
ACM Special Interest Group on Design Automation.

The technical program comprises paper presentations in the areas of:
1.1 Technologies
1.2 Circuits
1.3 Logic & Architecture
2.1 CAD & Methodologies,
2.2 Systems & Platforms,
2.3 Software & Applications,
3.1 Industrial Perspectives

Besides the paper presentations, the program also features three high-profile
keynotes (A. Sangiovanni-Vincentelli — UC Berkeley, USA;
J. Pineda De Givez — NXP, Netherlands; N. Shanbhag — UIUC, USA),
An Industry Reception Dinner (July 22nd),
A Banquet Gala Dinner (July 23rd),
A free Co-Located Workshop and Tutorial (July 24th) on Ultra-Low Power
Environmental Monitoring, Security, and Health (ULPESH)

Early registration is available until June 5, 2015.

For more information and registration, visit: http://www.islped.org/

Start: July 22, 2015
End: July 24, 2015
Venue: Rome, Italy

July 26, 2015

Call for Papers: HotPower’15

Submitted by Christos Kozyrakis
https://engineering.purdue.edu/~hotpower/

The 7th Workshop on Power-Aware Computing and Systems (HotPower’15)

The 7th Workshop on Power-Aware Computing and Systems will be co-located
with the 25th ACM Symposium on Operating Systems Principles (SOSP) on
October 4, 2015. HotPower’15 is sponsored by USENIX, the Advanced
Computing Systems Association.

HotPower provides a forum to present the latest research and to debate
directions, challenges, and novel ideas about building energy-efficient
systems, including both traditional platforms ranging from smartphones to
datacenters, and emerging platforms such as implantable devices and Internet
of Things (IoT). Researchers and practitioners coming from diverse fields such
as computer architecture, systems and networking, measurement and modeling,
language and compiler design, mobile computing, and embedded systems will
have the opportunity to interact with one another, explore cross-cutting ideas,
and develop new perspectives from the interactions.

The workshop seeks submissions of early-stage research and novel ideas that
will generate interesting discussion, e.g., unconventional, promising ideas
with early results. Submissions about first-hand experience, lessons,
challenges and problems from building and operating real-world systems are
also welcome.

Topics of interest in energy-efficient computing include but are not limited
to:
- Energy-efficiency measurements & benchmarking
- Power-performance trade-offs
- Reliability and power management
- Software optimizations & application design
- Run-time adaptation, scheduling, feedback control
- Power-aware computer architecture
- Energy efficient processors, networks, and storage
- Server & datacenter design
- Mobile and embedded systems, IOTs
- Innovative wearable & mobile devices
- System-level optimization, cross-layer coordination
- Renewable energy sources & energy storage
- Sustainability and life-cycle analysis

IMPORTANT DATES:
Paper Submission Deadline: July 26, 2015
Notification of Paper Acceptance: August 14, 2015
Camera Ready: August 30, 2015

Start: July 26, 2015
End: July 26, 2015

July 27, 2015

Call for Papers: ASAP 2015

Submitted by Vaughn Betz
http://www.eecg.toronto.edu/asap2015

The 2015 IEEE International Conference on Application-Specific
Architectures, Systems, and Processors (ASAP)

Toronto, Canada
July 27-29, 2015
 

IMPORTANT DATES:
Abstract Submission: February 27, 2015
Paper Due: March 6, 2015
Notification: May 15, 2015
Conference: July 27-29, 2015

CONFERENCE OVERVIEW:
The 26th IEEE International Conference on Application-specific
Systems, Architectures and Processors 2015 (ASAP 2015) takes place
July 27-29, 2015 at the University of Toronto in Toronto, Canada. The
conference will cover the theory and practice of application-specific
systems, architectures and processors. The 2015 conference will build
upon traditional strengths in areas such as computer arithmetic,
cryptography, compression, signal and image processing, network
processing, reconfigurable computing, application-specific
instruction-set processors, and hardware accelerators. We especially
encourage submissions in the following areas:

- Big data analytics: extracting and correlating information from
large-scale semi-structured and unstructured data using
application-specific systems.
- Scientific computing: architectures and algorithms that address
applications requiring significant computing power and customization
(bioinformatics, climate modeling, astrophysics, seismology, etc.).
- Industrial computing: systems and architectures for providing high-
throughput or low latency in various industrial computing
applications.
- System security: cryptographic hardware architectures, security
processors, countermeasures against side-channel attacks, and secure
cloud computing.
- Heterogeneous systems: applications and platforms that exploit
heterogeneous computing resources, including FPGAs, GPUs, or CGRAs.
- Design space exploration: methods for customizing and tuning
application- specific architectures to improve efficiency and
productivity.
- Platform-specific architectures: novel architectures for exploiting
specific compute domains, such as smartphones, tablets, and data
centers, particularly in the context of energy efficiency.

SUBMISSION GUIDELINES:
ASAP 2015 will accept 8-page full papers for oral presentations,
4-page short papers for short oral or poster presentations, with a
single-blind review process.

Submissions to ASAP 2015 must use the double-column IEEE conference
proceedings format. The only accepted file format is PDF. An online
submission page will be made available on the ASAP 2015 website and
will include detailed guidelines and links to formatting templates.

ORGANIZING COMMITTEE:

General Chair:
Jason Anderson, University of Toronto

Program Co-Chairs:
Deshanandh Singh, Altera Corp.
Hayden So, University of Hong Kong

Finance Chair:
Warren Gross, McGill University

Publicity Chair:
Vaughn Betz, University of Toronto

Web Chair:
Hiren Patel, University of Waterloo

Publications Chair:
Yuko Hara-Azumi, Tokyo Inst. of Tech.

Industry Chair:
Soojung Ryu, Samsung Electronics
 

Start: July 27, 2015
End: July 29, 2015
Venue: Toronto, ON, Canada

Call for Participation: ASAP 2015

Submitted by Vaughn Betz
http://www.eecg.toronto.edu/asap2015/

The 2015 IEEE International Conference on Application-Specific
Architectures, Systems, and Processors (ASAP)

University of Toronto Faculty Club
Toronto, Canada
July 27-29, 2015
 

EARLY REGISTRATION DEADLINE: June 30, 2015

The 26th IEEE International Conference on Application-specific
Systems, Architectures and Processors 2015 (ASAP 2015) takes place
July 27-29, 2015 at the University of Toronto in Toronto, Canada.

ASAP is a premiere IEEE conference covering all aspects of
application-specific computing, including systems, architectures,
processors, and design methodologies/tools.

The conference sessions will be held at the University of Toronto
Faculty Club, which is reknown for its collection of Canadian Art.

KEYNOTE TALKS
- Arvind, Massachusetts Institute of Technology
- Derek Chiou, Microsoft and the University of Texas at Austin

PROGRAM
The conference will include 21 full and 11 short papers with oral
presentation on topics ranging from customized domain-specific
processor architectures, computer security/cryptography, application
acceleration, design methods and tools, and fault tolerance. The oral
presentations are complemented by 18 poster paper presentations. The
advanced program and information about the keynote speakers
is posted on the conference website.

In addition to the technical program, ASAP 2015 will offer ample
opportunities for professional networking and socializing, including
an opening-day patio wine reception, and a banquet sunset cruise of
the beautiful Toronto islands and harbour.

ORGANIZING COMMITTEE
General Chair:
Jason Anderson, University of Toronto

Program Co-Chairs:
Hayden So, University of Hong Kong
Deshanandh Singh, Altera Corp.

Finance Chair:
Warren Gross, McGill University

Publicity Chair:
Vaughn Betz, University of Toronto

Web Chair:
Hiren Patel, University of Waterloo

Publications Chair:
Yuko Hara-Azumi, Tokyo Inst. of Tech.

Industry Chairs:
Soojung Ryu, Samsung Electronics
Qiang Wang, Huawei America

Start: July 27, 2015
End: July 29, 2015
Venue: Toronto, ON, Canada

August 6, 2015

Call For Papers: NAS 2015

Submitted by Resit Sendag
http://www.nas-conference.org/

10th IEEE International Conference on Networking, Architecture and Storage (NAS)
Boston, Massachusetts, USA
August 6-7, 2015

Sponsored by IEEE Computer Society’s Technical Committees on Computer
Architecture (TCCA), Parallel Processing (TCPP) and Distributed Processing
(TCDP).

IMPORTANT DATES:
– Paper Submission: April 3, 2015
– Notification: May 20, 2015
– Camera-Ready Copy: June 29, 2015

The International Conference on Networking, Architecture, and Storage (NAS)
provides a high-quality international forum to bring together researchers and
practitioners from academia and industry to discuss cutting-edge research on
networking, high-performance computer architecture, and parallel and
distributed data storage technologies. NAS 2015 will expose participants to the
most recent developments in the interdisciplinary areas.

Authors are invited to submit previously unpublished work for possible
presentation at the conference. Papers should be submitted for double-blind
review. The program committee will nominate best papers for recognition in the
three conference topic areas. All papers will be evaluated based on their
novelty, fundamental insight, experimental evaluation, and potential for long
-term impact; new-idea papers are encouraged. All accepted papers will be
published in IEEE digital library.

Papers are solicited in fields that include, but are not limited to, the
following:

- Processor, cache, memory system architectures
- Parallel and multi-core architectures
- GPU architecture and programming
- Data-center scale architectures
- Architecture for handheld or mobile devices
- Accelerator-based architectures
- Application-specific, reconfigurable or embedded architectures
- HW/SW co-design and tradeoffs
- Power and energy efficient architectures and techniques
- Effects of circuits and emerging technology on architecture
- Cloud and grid computing
- Architecture, networking or storage modeling and simulation methodologies
- Non-volatile memory technologies
- Mobile and wireless networks
- Ad hoc and sensor networks
- Network security
- Network information theory
- Software defined networking
- Network applications and services
- Network architecture and protocols
- Virtual and overlay networks
- Network modeling and measurement
- Storage management
- Storage performance and scalability
- File systems, object-based storage
- Energy-aware storage
- SSD architecture and applications
- Parallel I/O
- Cloud storage
- Storage virtualization and security
- Software defined storage
- Big Data infrastructure
- Big Data services and analytics

ORGANIZATION COMMITTEE
General Chair
– Resit Sendag (U of Rhode Island)
Program Co-Chairs:
– Jun Wang (U of Central Florida)
– Iris Bahar (Brown U)
Vice Program Chairs:
– Networking: Weikuan Yu (Auburn U) & Haiying Shen (Clemson U)
– Architecture: Martin Herbordt (Boston U) & Tali Moreshet (Boston U)
– Storage: Xiaosong Ma(Qatar Comp Ins & NC State) & Ali Butt(Virginia Tech)
Local Arrangements Chair:
– Ningfang Mi (Northeastern U)
Publications Chair:
– Gus Uht (U of Rhode Island)
Registration Chair:
– Yan Sun (U of Rhode Island)
Finance Chair:
– Yan Luo (U of Massachussetts-Lowell)
Industry Liaison Chair:
– Ming Zhang (EMC)
Publicity Co-chairs:
– Chengsheng Xie (Huazhong U Sci. Tech)
– André Brinkmann (Universitat Mainz)
– Ramon Bertran (IBM)
– Alper Buyuktosunoglu (IBM)
Submission Chair:
– Xunchao Chen (U of Central Florida)
Web Chair:
– Ibrahim Burak Karsli (U of Rhode Island)
Steering Committee
– Xubin He (Virginia Commonwealth U)
– Changsheng Xie(Huazhong U of Sci.Tech)
– André Brinkmann (U Mainz)
– Jian Li (IBM Austin Research Lab)
– Tao Li (University of Florida)
– Marco D Santambrogio (Politec. Milano)
– Hongbin Sun (Xi’An Jiaotong U)

PROGRAM COMMITTEE
Networking Track
– Weikuan Yu, Auburn University (co-chair)
– Haiying Shen, Clemson University (co-chair)
– Sarp Oral, Oak Ridge National Lab
– Shane Canon, Lawrence Berkeley National Lab
– Richard Graham, Mellanox
– Amith R Mamidala, IBM
– Jian Tan, IBM
– Ronald Brightwell, Sandia National Lab
– Gerald F II Lofstead, Sandia National Lab
– Wenjun Wu, Beihang University
– Jia Rao, University of Colorado Cold Springs
– Seung-Jong Park, Louisiana State University
– Xin Yuan, Florida State University
– Saad Biaz, Auburn University
– Kang Chen, Clemson University
– Yaohang Li, Old Dominion University
– Shan Lin, Temple University
– Chuan Yue, University of Colorado Colorado Springs
– Mengjun Xie, University of Arkansas at Little Rock
– Lei Yu, Georgia State University
– Yang Guo, Bell Labs
– Yongning Tang, Illinois State University
– Fangzhe Chang, Bell Labs, Alcatel-Lucent
– Feng Deng, Clemson University
– Weichen Liu, Chongqing University
– Zhi Wang, Tsinghua University
– Xiaojun Hei, Huazhong University of Science and Technology
– Yuan He, Hong Kong University of Science and Technology
– Di Wu, Sun Yat-Sen University
– Liudong Xing, University of Massachusetts Dartmouth
– Gang Zhou, College of William and Mary
– Jiangyi Hu, Devry University
– Junwei Cao, Tsinghua University
– Wenzhong Li, Nanjing University
– Surendar Chandra, EMC Data Protection and Availability Division
– Wei Zhang, Hong Kong University of Science and Technology
– Yao Liu, SUNY Binghamton
– Chiu Tan, Temple University
– Kyoungwon Suh, Illinois State University
Architecture Track
– Martin Herbordt, Boston University (co-chair)
– Tali Moreshet, Boston University (co-chair)
– Lide Duan , University of Texas at San Antonio
– Cesare Ferri , Marvel
– Mark Hempstead , Drexel University
– Ajay Joshi , Boston University
– Dong Li , Qualcomm
– Xiaoyao Liang , Shanghai Jiao Tong University
– Yan Luo , University of Massachusetts Lowell
– Vijay Nagarajan , University of Edinburgh
– Gi-Ho Park , Sejong University
– Dmitry Ponomarev , SUNY
– Kelly Shaw , University of Richmond
– Magnus Sjalander, Uppsala University
– Bharat Sukhwani, IBM
– Radu Teodorescu , Ohio-State University
– Jing Wang , Capital Normal University
– Jason Xue , City University of Hong Kong
– Zhibin Yu , Shenzhen Institute of Advanced Technology
– Jidong Zhai , Tsinghua University
– Dongyuan Zhan , AMD
– Chuanjun Zhang , Intel
– Wei Zhang , Virginia Commonwealth University
– Ping Zhou , Intel
– Zhichun Zhu , University of Illinois at Chicago
Storage Track
– Ali Butt, Virginia Tech (co-chair)
– Xiaosong Ma, Qatar Comp Res Inst and NC State (co-chair)
– Youngjae Kim, Oak Ridge National Laboratory
– Gary Liu, Oak Ridge National Laboratory
– Fei Meng, North Carolina State University and PureStorage
– Xing Wu, Amazon
– Xuanhua Shi, Huazhong University of Science and Technology
– Zhe Zhang, Cloudera
– Sudharshan Vazhkuda, ORNL
– Shuibing He, IIT
– Yong Chen, TTU
– Suren Byna, LBL
– Medha Bhadkamkar, Symantec Research Labs
– Avani Wildani, Salk Institute
– Min Li, IBM TJ Watson Research Center
– Aayush Gupta, IBM Almaden Research Center
– Lei Tian, Tintri
– Tao Xie, San Diego State University
– Song Jiang, Wayne State University
– Abhishek Chandra, University of Minnesota
– Jay Lofstead, Sandia National Laboratories
– Jinho Hwang, IBM Research
– Yifeng Zhu, University of Maine
– Xiao Qin, Auburn University
– Douglas Thain, University of Notre Dame
– Alan Sussman, University of Maryland
– Peter Varman, Rice University
– Nitin Agrawal, NEC Labs
– Fang Zheng, IBM T.J. Watson Research Center
– Qingdong Wang, University of Central Florida/Huizhou University

Start: August 6, 2015
End: August 7, 2015
Venue: Boston, MA

September 1, 2015

Call for Papers: ParCo2015 Edinburgh

Submitted by Mark Sawyer
http://www.parco.org
The University of Edinburgh is hosting the International Conference on Parallel
Computing (ParCo) from 1 – 4 September 2015. This is the latest in the series
of biennial ParCo conferences that started in Berlin, 1983. This makes ParCo
one of the longest running international conferences on parallel computing.
Over the years, the conference has established itself as the foremost platform
for exchanging know-how on the newest parallel computing strategies,
technologies,methods, and tools.

The Call for Papers can be found here: http://parco.org/call_for_papers.html

Aims and Scope
——————–
The aim of the conference is to give an overview of the state of the art of the
developments, applications, and future trends in parallel computing for the
whole range of platforms. The conference addresses all aspects of parallel
computing, including applications, hardware and software technologies as well
as languages and development environments.

Topic Areas:

Section 1: Algorithms

Design, analysis, and implementation of parallel algorithms in science and
engineering, focusing on issues such as

- Scalability and speedup
- Efficient utilization of the memory hierarchy
- Communication and synchronization
- Data Management and Exploration
- Energy Efficiency.

The parallel computing aspects should be emphasized.

Section 2: Software and Architectures

Software engineering for developing and maintaining parallel software, including

- Parallel programming languages, compilers, and environments
- Tools and techniques for generating reliable and efficient parallel code
- Testing and debugging techniques and tools
- Best practices of parallel computing on multicore, manycore, and stream
processors

Software, architectures and operating systems for all types of parallel
computers may be considered, including multicores, GPU accelerators, FPGA
reconfigurable systems, high-end machines and cloud computing.

Section 3: Applications

The application of parallel computing to solve all types of business,
industrial, scientific, and engineering problems using high-performance
computing technologies, in particular:

- Applications of high-end computers, including exascale
- Applications of multicore / manycore processors
- Applications for heterogeneous systems, including FPGAs, GPUs, etc.
- Cloud and Grid computing applications
- Data intensive (Big Data) analytics and applications.

Programme

The scientific programme consists of invited and contributed papers as well as
mini-symposia covering special topics.Papers are presented in parallel sessions
with 20 minutes available per presentation, with an additional five minutes for
discussion.A special session for young researchers as well as an industrial
session and an exhibition are planned.

Contributions :

Papers:

Contributed papers in English are called for. Extended abstracts of at least
two pages should be submitted in electronic form by 28 February 2015.
Proposals are to be submitted in .pdf-format.

Abstracts should clearly describe the contents of the proposed paper. The
relevance and originality of the contribution must be described and the most
important references included.

At most five relevant keywords must be supplied. Also indicate the preferred
topic area (section 1, 2 or 3) from the list given above.

Submission of paper proposals:

Paper proposals can be submitted using ConfTool at
https://www.conftool.net/parco2015/. Authors are required to register with the
system before they can enter their proposals.

Full (draft) papers of accepted proposals are due by 31 July 2015.

Mini-Symposia:

Proposals for organising a mini-symposium are called for. Such proposals should
give:

- The proposed title of the symposium
- The name and affiliation(s) of the organiser(s)
- A short outline of the contents
- The planned number of papers.

Proposals for organising a mini-symposium can be submitted by 31 March 2015
to the conference office. For any questions about the organisation of a
mini-symposium please contact the conference office.

Deadlines

Extended abstracts of papers: 28 Feb 2015
Proposals for mini-symposia: 31 Mar 2015
Notification of acceptance for presentation at conference: 15 May 2015
Submission of full (draft) papers: 31 Jul 2015
Notification of inclusion of full papers in the proceedings: 30 Sep 2015

Proceedings:

The conference proceedings will be published after the conference.

An invitation to authors to present a paper at the conference is based on an
extended abstract or draft paper. Thus, the presentation of a paper at the
conference does not imply an automatic acceptance of the presented paper for
publication in the conference proceedings. All papers presented at the
conference will be refereed at or after the conference. Only accepted papers
will be published.

All papers presented as part of mini-symposia will be considered for
publication in the proceedings. This will be done in liaison with
the organiser(s) of the respective mini-symposium.

Conference Organisation:

ParCo2015 is organised by the non-profit foundation ParCo Conferences in
cooperation with The University of Edinburgh, Scotland, UK.

Conference Committee Chair Gerhard Joubert (Germany/Netherlands)
Program Committee Chair: Mark Parsons (UK)
Organising Committee Chairs: Hugh Leather (UK), Mark Sawyer (UK)
Finance Chair: Frans Peters (Netherlands)

Contact
e-Mail: parco-2015@ed.ac.uk
Website: http://www.parco.org

Start: September 1, 2015
End: September 4, 2015
Venue: Edinburgh, UK