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August 6, 2014

Call for Papers: The 9th IEEE International Conference on Networking, Architecture, and Storage (NAS 2014)

Submitted by Jianhui Yue
http://www.nas-conference.org/
The 9th IEEE International Conference on Networking, Architecture,
and Storage (NAS 2014) will be held from August 6 − 8, 2014 in
Tianjin, China. It will serve as an international forum to bring
together researchers and practitioners from academia and industry
to discuss cutting-edge research on networking, high-performance
computer architecture, and parallel and distributed data storage
technologies.

Topics (Topics of interest include but are not limited to the list as follow)
- Virtual and overlay networks
- Network applications and services
- Ad hoc and sensor networks
- Networks and protocols
- Network architectures
- Processor architectures
- Cache and memory systems
- Parallel computer architectures
- Impact of technology on architecture
- Network information theory & network coding
- Network modeling and measurement
- Power and energy efficient architectures and techniques
- Storage management
- Storage performance and scalability
- File systems, object-based storage and block storage
- Energy-aware storage
- Architecture and applications of solid state disks
- Cloud storage
- Storage visualization
- HW/SW co-designs&trade-offs

Important Dates
- Deadline for Paper Submission: March 21st, 2014
- Notification of Paper Acceptance: May 19th, 2014
- Camera-ready Paper and Author Registration: June 9th, 2014

Submission
NAS 2014 invites authors to submit original and unpublished work.
All accepted papers will be included in the IEEE digital library
and indexed by EI. (IEEE sponsorship is pending approval.)

Start: August 6, 2014
End: August 8, 2014
Venue: Tianjian, China

August 11, 2014

Call For Papers: ISLPED 2014

Submitted by Jose L. Ayala
http://www.islped.org

La Jolla, CA, USA
Aug. 11 – Aug. 13, 2014

The International Symposium on Low Power Electronics and Design (ISLPED) is the
premier forum for presentation of recent advances in all aspects of low power
design and technologies, ranging from process and circuit technologies,
simulation and synthesis tools, to system level design and optimization.
Specific topics include, but are not limited to, the following two main areas,
each with three sub-areas:

1. Technology, Circuits, and Architecture

1.1. Technologies
Emerging Low-power technologies for Device, Interconnect, Logic, Memory,
2.5/3D,
Cooling, Harvesting, Sensors, Optical, Printable, Biomedical, Battery, and
Alternative energy storage devices.

1.2. Circuits
Low-power digital circuits for Logic, Memory arrays, Reliability, Clocking,
Power gating, Resiliency, NearThreshold Voltage (NTV), Sub-threshold,
Variability, and Digital assist schemes; Low-power analog/mixed-signal circuits
for Wireless, RF, MEMS, AD/DA Converters, I/O circuits, PLLs/DLLS, Imaging, DC
DC converters, and Analog assist schemes.

1.3. Logic and Architecture
Low-power logic and microarchitectures for SoC designs, Processor cores
(compute, graphics and other special purpose cores), Register file, Cache,
Memory, Arithmetic/Signal processing, Encryption, Variability, Asynchronous
design, and Non-conventional computing.

2. CAD, Systems, and Software

2.1. CAD Tools and Methodologies
CAD tools and methodologies for low-power and thermalaware design addressing
power estimation, optimization, reliability and variation impact on power, and
power-down approaches at all design levels: physical, circuit, gate, RTL,
behavioral, and algorithmic.

2.2. Systems & Platform
Low-power, power-aware, and thermal-aware system design and platforms for
microprocessors, DSP, embedded systems, FPGA, ASIC, SoC, heterogeneous
computing, novel systems, data-center power delivery and cooling, and system
level power implications due to reliability and variability.

2.3. Software & Applications
Energy-efficient, energy-aware, and thermal-aware software and application
design including scheduling and management, reliability and variability
optimizations, and emerging low power applications like approximate and
braininspired computing, low power distributed body-area/inbody networks, and
sensor networks.

Submissions on new topics: emerging technologies, architectures/platforms, and
applications are particularly encouraged.

TECHNICAL PAPER SUBMISSIONS DEADLINE: Abstract registration: Feb 28, 2014; Full
paper: March 7, 2014
Submissions should be full-length papers of up to 6 pages (double-column, ACM
SIG Proceedings format, available at
http://www.acm.org/sigs/publications/proceedings-templates), including all
illustrations, tables, references and an abstract of no more than 100 words.
Papers exceeding the six-page limit will not be reviewed. Submission must be
anonymous: papers identifying the authors and/or with explicit references to
their prior work will be automatically rejected. Electronic submission in pdf
format only via the web is required. More information on electronic submission
to ISLPED’14 can be found at http://www.islped.org.

Submitted papers must describe original work that will not be announced or
published prior to the Symposium and that is not being considered or under
review by another conference at the same time. Accepted papers will be
presented
in one of two parallel tracks: one focusing on architectures, circuits and
technologies, the other on design tools and systems and software design for low
power. Notification of paper acceptance will be mailed by April 28, 2014 and
the
camera-ready version of the paper will be due by June 2, 2014. Accepted papers
will be published in the Symposium Proceedings and included in the ACM Digital
Library. Authors of a few selected papers from the Symposium will also be given
an opportunity to submit enhanced versions of their papers for publication in a
special issue of a reputed journal. ISLPED’14 will present two Best Paper
Awards based on the ratings of reviewers and an invited panel of judges.

INVITED TALK, PANEL, AND TUTORIAL PROPOSALS DEADLINE: Received by: March 14,
2014

There will be several invited talks by industry and academic thought leaders on
key issues in low power electronics and design. All invited talks will be in
plenary sessions. The Symposium may also include embedded tutorials to provide
attendees with the necessary background to follow recent research results, as
well as panel discussions on future directions and design/technology
alternatives in low power electronics and design. Proposals for invited talks,
embedded tutorials, and the panel should be sent to the Technical Program Co

Chairs:

Renu Mehra
Synopsys
renu@synopsys.com

Muhammad M. Khellah
Intel
muhammad.m.khellah@intel.com

EXHIBITION REQUESTS DEADLINE: Received by: April 28, 2014

People from Industry or Academia interested in exhibiting at ISLPED’14 should
contact the symposium General Co-Chairs.

Start: August 11, 2014
End: August 13, 2014
Venue: La Jolla, CA, USA

August 25, 2014

Call for Papers: TASUS 2014

Submitted by Jesus Carretero
http://www.arcos.inf.uc3m.es/~tasus/
TASUS 2014: TECHNIQUES AND APPLICATIONS FOR SUSTAINABLE ULTRASCALE
COMPUTING SYSTEMS.

The ever-increasing data and processing requirements of applications
from various domains are constantly pushing for dramatic increases in
computational and storage capabilities. Today, we have
reached a point where computer systems’ growth cannot be addressed
anymore in an incremental way, due to the huge challenges lying ahead, in
particular scalability, energy barrier, data management, programmability,
and reliability.

Ultrascale computing systems (UCS) are envisioned as a
large-scale complex system joining parallel and distributed
computing systems, maybe located
at multiple sites, that cooperate to provide solutions to the
users. As a growth of two or three orders of magnitude of today’s
computing systems is expected, including systems with unprecedented
amounts of heterogeneous hardware, lines of source code, numbers
of users, and volumes of data, sustainability is critical to ensure the
feasibility of those systems. Due to those needs, currently there is an
emerging cross-domain interaction between high-performance in clouds or
the adoption of distributed programming paradigms, such as Map-Reduce,
in scientific applications, the cooperation between HPC and
distributed system communities still poses many challenges towards
building the ultrascale
systems of the future. Especially in unifying the services to deploy
sustainable applications portable to HPC systems, multi-clouds,
data centers, and big data.

TASUS workshop focuses on the software side, aiming at bringing
together researchers from academia and industry interested in the design,
implementation, and evaluation of services and system software
mechanisms to improve sustainability in ultrascale computing systems
with a holistic approach.

Topics:

We are looking for original high quality research and position papers
on applications, services, and system software for sustainable ultrascale
systems. Topics of interest include:

- Existing and emerging designs to achieve sustainable ultrascale systems.
- High-level parallel programming tools and programmability
techniques to improve applications sustainability on ultrascale
platforms. (model driven, refactoring, dynamic code generation, unified
services, middlewares, …).
- Synergies among emerging programming models and run-times
from HPC, distributed systems, and big data communities to provide
sustainable execution models (increased productivity, transparency,
elasticity, …).
- New energy efficiency techniques for monitoring, analyzing, and
modeling ultrascale systems, including energy efficiency metrics for
multiple resources (computing, storage, networking) and sites.
- Eco-design of ultrascale components and applications, with
special emphasis on energy-aware software components that help
users to shape energy issues for their applications.
- Sustainable resilience and fault-tolerant mechanisms that can
cooperate throughout the whole software stack to handle errors.
- Fault tolerance techniques in partitioned global address space
(e.g. PGAS, MPI, hybrid) and federated cooperative environments.
- Data management optimization techniques through cross layer
adaptation of the I/O stack to provide global system information to
improve data locality.
- Enhanced data management lifecycle on scalable architectures
combining HPC and distributed computing (clouds and data centers).
- Experiences with applications, high-level algorithms, and services
amenable to ultrascale systems.

Important dates:

· Workshop papers due: May 30, 2014

· Workshop author notification: July 4, 2014

· Workshop early registration: July 25, 2014
· Workshop camera-ready papers due: October 3, 2014

Committees

Workshop Organizers:
Prof. Jesus Carretero. University Carlos III of Madrid. Spain.
Dr. Laurent Lefevre. INRIA, ENS of Lyon. France
Prof. Gudula Rünger. Technical University of Chemnitz. Germany.
Prof. Domenico Talia. Universitá della Callabria. Italy.

Start: August 25, 2014
End: August 25, 2014
Venue: Porto, Portugal

October 21, 2014

Call for Papers: Dynamic Languages Symposium

Submitted by Edd Barrett
http://www.dynamic-languages-symposium.org/dls-14/
Dynamic Languages Symposium 2014
October 21, 2014

Co-located with SPLASH 2014, Portland, OR, USA

The 10th Dynamic Languages Symposium (DLS) at SPLASH 2014 is the premier
forum for researchers and practitioners to share knowledge and research on
dynamic languages, their implementation, and applications. The influence of
dynamic languages — from Lisp to Smalltalk to Python to Javascript — on
real-world practice, and research, continues to grow.

DLS 2014 invites high quality papers reporting original research, innovative
contributions, or experience related to dynamic languages, their
implementation, and applications. Accepted papers will be published in the
ACM Digital Library, and freely available for 2 weeks before and after the
event itself. Areas of interest include but are not limited to:

* Innovative language features and implementation techniques
* Development and platform support, tools
* Interesting applications
* Domain-oriented programming
* Very late binding, dynamic composition, and run-time adaptation
* Reflection and meta-programming
* Software evolution
* Language symbiosis and multi-paradigm languages
* Dynamic optimization
* Hardware support
* Experience reports and case studies
* Educational approaches and perspectives
* Semantics of dynamic languages

Submissions

Submissions should not have been published previously nor be under review at
other events. Research papers should describe work that advances the current
state of the art. Experience papers should be of broad interest and should
describe insights gained from substantive practical applications. The program
committee will evaluate each contributed paper based on its relevance,
significance, clarity, length, and originality.

Papers are to be submitted electronically at
http://www.easychair.org/conferences?conf=dls14 in PDF format. Submissions
must be in the ACM format (see http://www.sigplan.org/authorInformation.htm)
and not exceed 12 pages. Authors are reminded that brevity is a virtue.

DLS 2014 will run a two-phase reviewing process to help authors make their
final papers the best that they can be. After the first round of reviews,
papers will be rejected, conditionally accepted, or unconditionally accepted.
Conditionally accepted papers will be given a list of issues raised by
reviewers. Authors will then submit a revised version of the paper with a
cover letter explaining how they have / why they have not addressed these
issues. The reviewers will then consider the cover letter and revised paper
and recommend final acceptance / rejection.

Important dates

Submissions: June 8 2014 (FIRM DEADLINE)
First phase notification: July 14 2014
Revisions due: August 4 2014
Final notification: August 11 2014
Camera ready: August 15 2014
DLS: October 21 2014

Programme chair

Laurence Tratt, King’s College London, UK
e-mail: dls14@easychair.org

Publicity chair

Edd Barrett, King’s College London, UK

Programme committee

Gilad Bracha, Google, US
Jonathan Edwards, MIT, US
Robert Hirschfeld, Hasso-Plattner-Institut Potsdam, DE
Roberto Ierusalimschy, PUC-Rio, BR
Sergio Maffeis, Imperial College London, UK
Stefan Marr, INRIA, FR
Oscar Nierstrasz, University of Bern, CH
James Noble, Victoria University of Wellington, NZ
Shriram Krishnamurthi, Brown University, US
Chris Seaton, University of Manchester, UK
Nikolai Tillmann, Microsoft Research, US
Sam Tobin-Hochstadt, Indiana University, US
Jan Vitek, Purdue University, US
Christian Wimmer, Oracle Labs, US
Peng Wu, IBM Research, US

Start: October 21, 2014
End: October 21, 2014
Venue: Portland, OR, USA

October 26, 2014

Call for Papers: IEEE International Symposium on Workload Characterization

Submitted by Jian Li
http://www.iiswc.org/iiswc2014/index.html
IISWC-2014
October 26 (Sun) – 28 (Tue), 2014
Raleigh, North Carolina, USA

CALL FOR PAPERS 

Important Dates

Abstracts Submission : April 18, 2014   
Paper Submission : April 25, 2014   
Acceptance Notification : June 17, 2014 

This symposium is dedicated to the understanding and characterization of
workloads that run on all types of computing systems. New applications and
programming paradigms continue to emerge rapidly as the diversity and
performance of computers increase. On one hand, improvements in computing
technology are usually based on a solid understanding and analysis of existing
workloads. On the other hand, computing workloads evolve and change with
advances in microarchitecture, compilers, programming languages, and networking
communication technologies. Whether they are smart phones and deeply embedded
systems at the low end or massively parallel systems at the high end, the
design of future computing machines can be significantly improved if we
understand the characteristics of the workloads that are expected to run on
them. This symposium will focus on characterizing and understanding emerging
applications in consumer, commercial and scientific computing.

General Chair
  Huiyang Zhou, North Carolina State University
 
Program Chair 
  Lixin Zhang, Inst of Comp Tech, Chinese Academy of Sciences
  Lingjia Tang, University of Michigan
 
Workshop/Tutorial Chair
  Lisa Hsu, Qualcomm
 
Finance Chair
  Carole-Jean Wu, Arizona State University
 
Local Arrangements Chair
  James Tuck, North Carolina State University
 
Publications Chair
  Mark Hempstead, Drexel University
 
Publicity Chair
  Jian Li, IBM Research
 
Registration Chair
  Xin Fu, University of Kansas
 
Submissions Chair
  TBA
 
Web Chair
  Yi Yang, NEC Laboratories America
Topics of Interest
We solicit papers in all areas related to characterization of computing
system workloads. Topics of interest include (but are not limited to):
 
Characterization of applications in areas including
o Search engines, e-commerce, web services, databases, file/application servers
o Embedded, mobile, multimedia, real-time, 3D-Graphics, gaming, telepresence
o Life sciences, bioinformatics, scientific computing, finance, forecasting
o Machine Learning, Analytics, Data mining
o Security, reliability, biometrics
o Grid and Cloud computing
o Emerging big data applications
Characterization of OS, Virtual Machine, middleware and library behavior
o Virtual machines, Websphere, .NET, Java VM, databases
o Graphics libraries, scientific libraries
Characterization of system behavior, including
o Operating system and hypervisor effects and overheads
o Hardware accelerators (GPGPU, XML, crypto, etc)
o User behavior and system-user interaction
o Impacts of scale-up and scale-out of systems, applications, and inputs
o Instrumentation methodologies for workload verification and characterization
o Techniques for accurate analysis/measurement of production systems
Implications of workloads in design issues, such as
o Power management, reliability, security, performance
o Processors, memory hierarchy, I/O, and networks
o Design of accelerators, FPGA’s, GPU’s, etc.
o Novel architectures (non-Von-Neumann)
Benchmark creation, analysis, and evaluation issues, including
o Multithreaded benchmarks, benchmark cloning
o Profiling, trace collection, synthetic traces
o Validation of benchmarks
Analytical and abstract modeling of program behavior and systems
Emerging and future workloads
o Transactional memory workloads; workloads for multi/many-core systems
o Stream-based computing workloads; web2.0/internet workloads;
cyber-physical workloads
 
For further information, please contact the General or Program Chair:
   General Chair
         Huiyang Zhou, NC State University ( hzhou@ncsu.edu )
    Program Chair
         Lixin Zhang, Institute of Computing Technology,
Chinese Academy of Sciences    (zhanglixin@ict.ac.cn)
         Lingjia Tang, University of Michigan    (lingjia@umich.edu)

Start: October 26, 2014
End: October 28, 2014
Venue: Raleigh, North Carolina, USA

Call for Papers: IEEE International Symposium on Workload Characterization 2014

Submitted by Jian Li
http://www.iiswc.org/iiswc2014/index.html
IISWC-2014
October 26 (Sun) – 28 (Tue), 2014
Raleigh, North Carolina, USA

CALL FOR PAPERS 

Important Dates

Abstracts Submission : April 25, 2014   
Paper Submission : May 2, 2014   
Acceptance Notification : June 17, 2014 

This symposium is dedicated to the understanding and characterization of
workloads that run on all types of computing systems. New applications and
programming paradigms continue to emerge rapidly as the diversity and
performance of computers increase. On one hand, improvements in computing
technology are usually based on a solid understanding and analysis of existing
workloads. On the other hand, computing workloads evolve and change with
advances in microarchitecture, compilers, programming languages, and networking
communication technologies. Whether they are smart phones and deeply embedded
systems at the low end or massively parallel systems at the high end, the
design of future computing machines can be significantly improved if we
understand the characteristics of the workloads that are expected to run on
them. This symposium will focus on characterizing and understanding emerging
applications in consumer, commercial and scientific computing.

General Chair
  Huiyang Zhou, North Carolina State University
 
Program Chair 
  Lixin Zhang, Institute of Computing Technology, Chinese Academy
of Science
  Lingjia Tang, University of Michigan
 
Workshop/Tutorial Chair
  Lisa Hsu, Qualcomm
 
Finance Chair
  Carole-Jean Wu, Arizona State University
 
Local Arrangements Chair
  James Tuck, North Carolina State University
 
Publications Chair
  Mark Hempstead, Drexel University
 
Publicity Chair
  Jian Li, IBM Research
 
Registration Chair
  Xin Fu, University of Kansas
 
Submissions Chair
  TBA
 
Web Chair
  Yi Yang, NEC Laboratories America

Topics of Interest
We solicit papers in all areas related to characterization of computing system
workloads. Topics of interest include (but are not limited to):
 
Characterization of applications in areas including
o Search engines, e-commerce, web services, databases, file/application servers
o Embedded, mobile, multimedia, real-time, 3D-Graphics, gaming, telepresence
o Life sciences, bioinformatics, scientific computing, finance, forecasting
o Machine Learning, Analytics, Data mining
o Security, reliability, biometrics
o Grid and Cloud computing
o Emerging big data applications

Characterization of OS, Virtual Machine, middleware and library behavior
o Virtual machines, Websphere, .NET, Java VM, databases
o Graphics libraries, scientific libraries

Characterization of system behavior, including
o Operating system and hypervisor effects and overheads
o Hardware accelerators (GPGPU, XML, crypto, etc)
o User behavior and system-user interaction
o Impacts of scale-up and scale-out of systems, applications, and inputs
o Instrumentation methodologies for workload verification and characterization
o Techniques for accurate analysis/measurement of production systems

Implications of workloads in design issues, such as
o Power management, reliability, security, performance
o Processors, memory hierarchy, I/O, and networks
o Design of accelerators, FPGA’s, GPU’s, etc.
o Novel architectures (non-Von-Neumann)

Benchmark creation, analysis, and evaluation issues, including
o Multithreaded benchmarks, benchmark cloning
o Profiling, trace collection, synthetic traces
o Validation of benchmarks
o Analytical and abstract modeling of program behavior and systems

Emerging and future workloads
o Transactional memory workloads; workloads for multi/many-core systems
o Stream-based computing workloads; web2.0/internet workloads; cyber-physical
workloads
 
For further information, please contact the General or Program Chair:
   General Chair
         Huiyang Zhou, North Carolina State University   
( hzhou@ncsu.edu )
    Program Chair
         Lixin Zhang, Institute of Computing Technology, Chinese
Academy of Science    (zhanglixin@ict.ac.cn)
         Lingjia Tang, University of Michigan    (lingjia@umich.edu)

Start: October 26, 2014
End: October 28, 2014
Venue: Raleigh, North Carolina, USA

Call for Tutorials & Workshops: IEEE International Symposium on Workload Characterization

Submitted by Jian Li
http://www.iiswc.org/iiswc2014/index.html
Call for Tutorial and Workshop Proposals

IISWC-2014 solicits proposals to be organizes in conjunction with the main
conference, to be held on October 26, 2014 (Sunday).

Tutorial Proposals:

Proposals for both half- and full-day tutorials are solicited on any topic that
is relevant to the IISWC audience. Tutorials that focus on the primary topics of
interest for IISWC are strongly encouraged. Examples of successful formats
include educating the community on tools, or on emerging topics.

Important Dates
Submission deadline: Friday, August 1, 2014
Notification: Friday, August 8, 2014

Submission Procedures
Proposals should provide the following information:
· Title of the tutorial
· List of organizer(s) and presenter(s), including contact information
and short bios
· Tutorial abstract
· Short description (for evaluation). This should include:
o Tutorial scope and objectives,
o Topics to be covered,
o Target audience
· Proposed duration (full day, half day).
· If the tutorial has been held previously, the location (i.e.,
conference), date, and number of attendees.

Proposals should take the form of a PDF document, and be submitted via e-mail to
Lisa Hsu (hsul@qti.qualcomm.com) , with the subject “IISWC 2014 Tutorial
Proposal”. Submissions will be acknowledged via e-mail.

Call for Workshop Proposals

Proposals for half- and full-day workshops are solicited on any topic that is
relevant to the IISWC audience. Proposals relating to power/energy/performance
analysis and workload characterization as relating to computer architecture,
systems, compilers, or programming languages, particularly as related to mobile
computing (either from the mobile side or the servers supporting mobile
computing); datacenters; or the Internet of Things, are encouraged.

Important Dates
Submission deadline: Friday, August 1, 2014
Notification: Friday, August 8, 2014

Submission Procedures
Please include in your proposal
· Title of the workshop
· Organizers and their affiliations
· Sample call for papers
· Duration – Half-Day or Full Day
· If the workshop was previously held, the location (conference), date,
and number of attendees

Proposals should take the form of a PDF document, and be submitted via e-mail to
Lisa Hsu (hsul@qti.qualcomm.com) , with the subject “IISWC 2014 Workshop
Proposal”. Submissions will be acknowledged via e-mail.

Start: October 26, 2014
End: October 26, 2014
Venue: Raleigh, North Carolina, USA

December 10, 2014

Call for Papers: Performance and Power Issues in Multi/Many Core Architecture

Submitted by Hitoshi OI
http://p2m2ca.oslab.biz/
Performance and Power Issues in Multi/Many Core Architecture,
a special session in International Symposium on Integrated Circuits
(ISIC) 2014, Singapore, December 10 to 12, 2014

Call for papers:

This special session is aimed to attract the interests
of people working in various aspects of multi/many core
architecture, from the circuit level to the application level,
stimulate the discussion and share and exchange their experiences
and knowledge.

Topics of interests for the special session include
(but not limited to):

– Performance and power-efficiency optimization,
– Heterogeneous multi/many core: architectural design
and run-time support,
– Parallelization libraries and tools,
– Performance and power consumption modeling methodologies,
– Design strategies for performance and power-efficiency in
circuit, architecture and software levels,
On-chip interconnect: architecture, protocol and routing,
– Memory hierarchy architecture and protocol.

Important Dates:

5/15: Title and abstract submission
(send by email to p2m2ca at oslab.biz)
6/1: Full paper submission
(use the Paper Upload page of ISIC 2014
http://www.isic2014.org/submission/paper-upload )
9/1: Notification of Paper Acceptance
10/15: Submission of Final Manuscript Papers

Organizing Members:

Hitoshi Oi, University of Aizu (JP)
Joao Pedro Pedroso, University of Porto (PT)
Ines Dutra, University of Porto (PT)
Xiongfei Liao, Intel (MY)
Senthilkumar Jayapal, Intel (MY)
Jorge Chavez, Cinvestav (MX)
Amilcar Meneses, Cinvestav (MX)
Yao-Min Cheng, Oracle (US)

For more information, please refer to
ISIC 2014 web site http://www.isic2014.org/
or send email to p2m2ca at oslab.biz

Start: December 10, 2014
End: December 12, 2014
Venue: Singapore

January 19, 2015

Call for Papers: HIPEAC 2015

Submitted by Gennady Pekhimenko
http://www.hipeac.net/conference

10th International Conference on High-Performance Embedded
Architectures and Compilers

January 19-21, 2015
Amsterdam, The Netherlands

http://www.hipeac.net/conference

IMPORTANT DATE:
Paper deadline: June 1, 2014

Sponsored by:
HiPEAC Compilation & Architecture
Seventh Framework Programme

Description:
The HiPEAC conference is the premier European forum for
experts in computer architecture, programming models,
compilers and operating systems for embedded and
general-purpose systems.

The 10th HiPEAC conference will take place in Amsterdam,
The Netherlands from Monday, January 19 to Wednesday, January
21, 2015. Associated workshops, tutorials, special sessions,
several large poster session and an industrial exhibition will
run in parallel with the conference. The three day event
attracts about 500 delegates each year.

Paper selection is done by ACM TACO, the ACM Transactions on
Architecture and Code Optimization. Prospective authors submit
their original papers to ACM TACO at any time before the paper
deadline of June 1, 2014 to benefit from two rounds of reviews
before the conference paper track cut-off date which is
November 15, 2014.

See below for detailed information about the new publication
model called ACM TACO 2.0.

Topics of interest include, but are not limited to:
* Processor, memory, and storage systems architecture
* Parallel, multi-core and heterogeneous systems
* Interconnection networks
* Architectural support for programming productivity
* Power, performance and implementation efficient designs
* Reliability and real-time support in processors, compilers
and run-time systems
* Application-specific processors, accelerators and
reconfigurable processors
* Architecture and programming environments for GPU-based
computing
* Simulation and methodology
* Architectural and run-time support for programming languages
* Programming models, frameworks and environments for exploiting
parallelism
* Compiler techniques
* Feedback-directed optimization
* Program characterization and analysis techniques
* Dynamic compilation, adaptive execution, and continuous
profiling/optimization
* Binary translation/optimization
* Code size/memory footprint optimizations

GENERAL CHAIRS
Andy D. Pimentel, University of Amsterdam
Stephan Wong, Delft University of Technology

PROGRAM CHAIR
Onur Mutlu, Carnegie Mellon University

WORKSHOPS & TUTORIALS CHAIRS
Diana Göhringer, Ruhr-Universität Bochum
Sascha Uhrig, TU Dortmund

PUBLICITY CHAIRS
Sorin Cotofana, Delft University of Technology
Antonio Beck, UFRGS
Chao Wang, USTC
Gennady Pekhimenko, Carnegie Mellon Univ.

POSTER & EXHIBITION CHAIR
Koen De Bosschere, Ghent University

SPONSOR CHAIR
Albert Cohen, INRIA

INDUSTRIAL SESSION CHAIR
Daniel Gracia Pérez, Thales

FINANCE CHAIR
Vicky Wandels, Ghent University

WEB AND REGISTRATIONS CHAIR
Eneko Illarramendi, Ghent University

LOCAL ARRANGEMENTS COMMITTEE
Andy D. Pimentel, University of Amsterdam
Stephan Wong, Delft University of Technology
Clemens Grelck, University of Amsterdam
Todor Stefanov, University of Leiden
Zaid Al-Ars, Delft University of Technology

*****************************************************************
ACM TACO 2.0 Publication Model:
Over the last three years ACM TACO has optimized its
internal review processes. Today, the average turnaround
time from submission to first response is 46 days and 95%
of the manuscripts get a response within 2 months. For
revised manuscripts, the review process goes even faster.
In 2013, most accepted manuscripts went through two rounds
of reviews to reach a final decision only 5 months after
submission. Accepted manuscripts are immediately uploaded
in the ACM digital library. Hence, excellent manuscripts
can make it from submission to publication in about three
months; papers needing a major revision are published after
6 months. We call this “ACM TACO 2.0”

ACM TACO 2.0 now has a review cycle and an acceptance rate
which is competitive with the best ACM conferences, but
without the inconvenient non-negotiable submission deadlines,
and with the advantage of being able to revise a paper based
on the detailed review reports by carefully selected
reviewers, and of being published as soon as it is accepted.
On top of that, authors of original work papers get an open
invitation to present their paper at the yearly HiPEAC
conference, which is the premier European network event on
topics central to ACM TACO, attended by more than 500
scientists.

ACM TACO interim Editor-in-Chief
Prof. Koen De Bosschere

ACM TACO Senior Editor
Prof. Per Stenström

Start: January 19, 2015
End: January 21, 2015
Venue: Amsterdam, The Netherlands

Call for Papers: HiPEAC 2015

Submitted by Gennady Pekhimenko
http://www.hipeac.net/conference
Call for Papers – HIPEAC 2015

10th International Conference on High-Performance Embedded
Architectures and Compilers

January 19-21, 2015
Amsterdam, The Netherlands

http://www.hipeac.net/conference

IMPORTANT DATE:
Paper deadline: June 1, 2014

Sponsored by:
HiPEAC Compilation & Architecture
Seventh Framework Programme

Description:
The HiPEAC conference is the premier European forum for
experts in computer architecture, programming models,
compilers and operating systems for embedded and
general-purpose systems.

The 10th HiPEAC conference will take place in Amsterdam,
The Netherlands from Monday, January 19 to Wednesday, January
21, 2015. Associated workshops, tutorials, special sessions,
several large poster session and an industrial exhibition will
run in parallel with the conference. The three day event
attracts about 500 delegates each year.

Paper selection is done by ACM TACO, the ACM Transactions on
Architecture and Code Optimization. Prospective authors submit
their original papers to ACM TACO at any time before the paper
deadline of June 1, 2014 to benefit from two rounds of reviews
before the conference paper track cut-off date which is
November 15, 2014.

See below for detailed information about the new publication
model called ACM TACO 2.0.

Topics of interest include, but are not limited to:
* Processor, memory, and storage systems architecture
* Parallel, multi-core and heterogeneous systems
* Interconnection networks
* Architectural support for programming productivity
* Power, performance and implementation efficient designs
* Reliability and real-time support in processors, compilers
and run-time systems
* Application-specific processors, accelerators and
reconfigurable processors
* Architecture and programming environments for GPU-based
computing
* Simulation and methodology
* Architectural and run-time support for programming languages
* Programming models, frameworks and environments for exploiting
parallelism
* Compiler techniques
* Feedback-directed optimization
* Program characterization and analysis techniques
* Dynamic compilation, adaptive execution, and continuous
profiling/optimization
* Binary translation/optimization
* Code size/memory footprint optimizations

GENERAL CHAIRS
Andy D. Pimentel, University of Amsterdam
Stephan Wong, Delft University of Technology

PROGRAM CHAIR
Onur Mutlu, Carnegie Mellon University

WORKSHOPS & TUTORIALS CHAIRS
Diana Göhringer, Ruhr-Universität Bochum
Sascha Uhrig, TU Dortmund

PUBLICITY CHAIRS
Sorin Cotofana, Delft University of Technology
Antonio Beck, UFRGS
Chao Wang, USTC
Gennady Pekhimenko, Carnegie Mellon Univ.

POSTER & EXHIBITION CHAIR
Koen De Bosschere, Ghent University

SPONSOR CHAIR
Albert Cohen, INRIA

INDUSTRIAL SESSION CHAIR
Daniel Gracia Pérez, Thales

FINANCE CHAIR
Vicky Wandels, Ghent University

WEB AND REGISTRATIONS CHAIR
Eneko Illarramendi, Ghent University

LOCAL ARRANGEMENTS COMMITTEE
Andy D. Pimentel, University of Amsterdam
Stephan Wong, Delft University of Technology
Clemens Grelck, University of Amsterdam
Todor Stefanov, University of Leiden
Zaid Al-Ars, Delft University of Technology

ACM TACO 2.0 Publication Model:
Over the last three years ACM TACO has optimized its
internal review processes. Today, the average turnaround
time from submission to first response is 46 days and 95%
of the manuscripts get a response within 2 months. For
revised manuscripts, the review process goes even faster.
In 2013, most accepted manuscripts went through two rounds
of reviews to reach a final decision only 5 months after
submission. Accepted manuscripts are immediately uploaded
in the ACM digital library. Hence, excellent manuscripts
can make it from submission to publication in about three
months; papers needing a major revision are published after
6 months. We call this “ACM TACO 2.0”

ACM TACO 2.0 now has a review cycle and an acceptance rate
which is competitive with the best ACM conferences, but
without the inconvenient non-negotiable submission deadlines,
and with the advantage of being able to revise a paper based
on the detailed review reports by carefully selected
reviewers, and of being published as soon as it is accepted.
On top of that, authors of original work papers get an open
invitation to present their paper at the yearly HiPEAC
conference, which is the premier European network event on
topics central to ACM TACO, attended by more than 500
scientists.

ACM TACO interim Editor-in-Chief
Prof. Koen De Bosschere

ACM TACO Senior Editor
Prof. Per Stenström

Start: January 19, 2015
End: January 21, 2015
Venue: Amsterdam, The Netherlands