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November 1, 2014

Call for Papers: IJPP Special Issue on Workload Optimized Systems

Submitted by Parijat Dube
http://www.springer.com/10766

Springer International Journal of Parallel Programming (IJPP)
Special Issue on Workload Optimized Systems

 

The slowdown in Moore’s Law makes it increasingly important to optimize
systems around specific workloads. Such workload optimized systems have
hardware and/or software specifically designed to run well for a particular
workload or workload class. Such systems include, but are not limited to
traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory
accelerators, I/O accelerators, hybrid systems, and IT appliances. This
workload optimized system approach contrasts to the broad general purpose
direction of computing over many decades. The workload optimized systems
approach is growing in importance, as we see in systems from cellphones to
tablets to routers to game machines to Top500 supercomputers, and IT
appliances such as IBM’s DataPower and Netezza, and Oracle’s Exadata. The
goal of this special issue is to foster awareness in industry and academic
community on workload optimized systems and to expose cross hw/sw stack
unique systems and software research challenges associated with such
systems. All submitted papers are subject to the same review process as those
papers accepted for publication in the regular issues. The special issue seeks
original papers on a range of topics related to workload optimized systems
including, but not limited to

- GPUs, FPGAs, ASIC Accelerators
- Memory and I/O accelerators
- Network accelerators
- Storage optimized systems
- System level accelerators
- IT Appliances
- Systems in specific domains like analytics, cloud, cognitive, mobile etc.
- Converged/Hybrid/Heterogeneous systems
- Cross hardware/software stack design and optimization
- Programming models for workload optimized systems
- Measurements and Experimentation
- Workload characterization and profiling
- Performance modeling and optimization
- Workload scheduling and orchestration
- Runtime management systems
- Industrial Experiences

IMPORTANT DATES
Manuscript due: March 27, 2015
First decision notification: June 5, 2015
Revision due: July 10, 2015
Final decision notification: August 14, 2015
Final version due: September 11, 2015

SUBMISSIONS
Authors are encouraged to submit high-quality, original work that
has neither appeared in, nor is under consideration by, other
journals. All papers will be reviewed following standard reviewing
procedures for the Journal.
Papers must be prepared in accordance with the Journal guidelines:

http://www.springer.com/10766.

Manuscripts must be submitted to: http://IJPP.edmgr.com.
Choose “S.I.: Workload Optimized Systems” as the article type.

GUEST EDITORS
Erik Altman, IBM Research, Yorktown Heights, NY. ealtman@us.ibm.com
Parijat Dube, IBM Research, Yorktown Heights, NY. pdube@us.ibm.com

 

Start: November 1, 2014
End: October 1, 2015

August 18, 2015

Call for Papers: IEEE Micro’s Top Picks 2016

Submitted by Dan Sorin
https://sites.google.com/site/ieeemicro/call-for-papers/top-picks-2016—call-for-papers

IEEE Micro’s Top Picks 2016
 

IEEE Micro will publish its yearly “Micro’s Top Picks from the Computer
Architecture Conferences” as its May/June 2016 issue. This issue collects some
of this year’s most significant research papers in computer architecture based
on novelty and potential for long-term impact. Any computer architecture paper
(not a combination of papers) published in the top conferences of 2015
(including MICRO-48) is eligible. IEEE Micro also distinguishes a number of
papers as IEEE Micro Top Pick Honorable Mentions.

IMPORTANT DATES:
Submission Deadline: October 16, 2015 6:00 pm EDT
Author notification: January 29, 2016
Final papers due: February 19, 2016
Publication date: May/June 2016

Top Picks Guest Editors (and Co-Chairs of the Selection Committee):
Milo Martin, Google
Dan Sorin, Duke University

Start: August 18, 2015
End: October 16, 2015

September 1, 2015

Call for Papers: ParCo2015 Edinburgh

Submitted by Mark Sawyer
http://www.parco.org
The University of Edinburgh is hosting the International Conference on Parallel
Computing (ParCo) from 1 – 4 September 2015. This is the latest in the series
of biennial ParCo conferences that started in Berlin, 1983. This makes ParCo
one of the longest running international conferences on parallel computing.
Over the years, the conference has established itself as the foremost platform
for exchanging know-how on the newest parallel computing strategies,
technologies,methods, and tools.

The Call for Papers can be found here: http://parco.org/call_for_papers.html

Aims and Scope
——————–
The aim of the conference is to give an overview of the state of the art of the
developments, applications, and future trends in parallel computing for the
whole range of platforms. The conference addresses all aspects of parallel
computing, including applications, hardware and software technologies as well
as languages and development environments.

Topic Areas:

Section 1: Algorithms

Design, analysis, and implementation of parallel algorithms in science and
engineering, focusing on issues such as

- Scalability and speedup
- Efficient utilization of the memory hierarchy
- Communication and synchronization
- Data Management and Exploration
- Energy Efficiency.

The parallel computing aspects should be emphasized.

Section 2: Software and Architectures

Software engineering for developing and maintaining parallel software, including

- Parallel programming languages, compilers, and environments
- Tools and techniques for generating reliable and efficient parallel code
- Testing and debugging techniques and tools
- Best practices of parallel computing on multicore, manycore, and stream
processors

Software, architectures and operating systems for all types of parallel
computers may be considered, including multicores, GPU accelerators, FPGA
reconfigurable systems, high-end machines and cloud computing.

Section 3: Applications

The application of parallel computing to solve all types of business,
industrial, scientific, and engineering problems using high-performance
computing technologies, in particular:

- Applications of high-end computers, including exascale
- Applications of multicore / manycore processors
- Applications for heterogeneous systems, including FPGAs, GPUs, etc.
- Cloud and Grid computing applications
- Data intensive (Big Data) analytics and applications.

Programme

The scientific programme consists of invited and contributed papers as well as
mini-symposia covering special topics.Papers are presented in parallel sessions
with 20 minutes available per presentation, with an additional five minutes for
discussion.A special session for young researchers as well as an industrial
session and an exhibition are planned.

Contributions :

Papers:

Contributed papers in English are called for. Extended abstracts of at least
two pages should be submitted in electronic form by 28 February 2015.
Proposals are to be submitted in .pdf-format.

Abstracts should clearly describe the contents of the proposed paper. The
relevance and originality of the contribution must be described and the most
important references included.

At most five relevant keywords must be supplied. Also indicate the preferred
topic area (section 1, 2 or 3) from the list given above.

Submission of paper proposals:

Paper proposals can be submitted using ConfTool at
https://www.conftool.net/parco2015/. Authors are required to register with the
system before they can enter their proposals.

Full (draft) papers of accepted proposals are due by 31 July 2015.

Mini-Symposia:

Proposals for organising a mini-symposium are called for. Such proposals should
give:

- The proposed title of the symposium
- The name and affiliation(s) of the organiser(s)
- A short outline of the contents
- The planned number of papers.

Proposals for organising a mini-symposium can be submitted by 31 March 2015
to the conference office. For any questions about the organisation of a
mini-symposium please contact the conference office.

Deadlines

Extended abstracts of papers: 28 Feb 2015
Proposals for mini-symposia: 31 Mar 2015
Notification of acceptance for presentation at conference: 15 May 2015
Submission of full (draft) papers: 31 Jul 2015
Notification of inclusion of full papers in the proceedings: 30 Sep 2015

Proceedings:

The conference proceedings will be published after the conference.

An invitation to authors to present a paper at the conference is based on an
extended abstract or draft paper. Thus, the presentation of a paper at the
conference does not imply an automatic acceptance of the presented paper for
publication in the conference proceedings. All papers presented at the
conference will be refereed at or after the conference. Only accepted papers
will be published.

All papers presented as part of mini-symposia will be considered for
publication in the proceedings. This will be done in liaison with
the organiser(s) of the respective mini-symposium.

Conference Organisation:

ParCo2015 is organised by the non-profit foundation ParCo Conferences in
cooperation with The University of Edinburgh, Scotland, UK.

Conference Committee Chair Gerhard Joubert (Germany/Netherlands)
Program Committee Chair: Mark Parsons (UK)
Organising Committee Chairs: Hugh Leather (UK), Mark Sawyer (UK)
Finance Chair: Frans Peters (Netherlands)

Contact
e-Mail: parco-2015@ed.ac.uk
Website: http://www.parco.org

Start: September 1, 2015
End: September 4, 2015
Venue: Edinburgh, UK

Call for Papers: Workshop on Embedded Multicore Systems

Submitted by Kuan-Ching Li
https://sites.google.com/site/icppems2015/home

The 2015 International Workshop on Embedded Multicore Systems (ICPP-EMS’2015)
Beijing, China
September 1-4, 2015

to be held in conjunction with
The 44th International Conference on Parallel Processing (ICPP’2015)

SUBMISSIONS DUE: May 1, 2015
 

Embedded systems with Multicore designs are of major focuses from both
industry and academia. While embedded Multicore systems will look to
play an important role ahead for system designs, many challenging
issues remain. Applications, programming models, architecture designs,
emerging memory architectures, and software tools all need to help for
the advance of embedded Multicore computing ahead.

The 2015 International Workshop on Embedded Multicore Systems
(ICPP-EMS 2015) will bring researchers and experts together to present
and discuss the latest developments and technical solutions concerning
various aspects of embedded Multicore computing.

ICPP-EMS 2015 seeks original unpublished papers focusing on emerging
applications, embedded compilers, embedded memory and architecture
design, DSP/GPU systems, ESLs, embedded Multicore programming models,
and WCET analysis. Moreover, ICPP-EMS 2015 also welcomes
work-in-progress, case studies, visionary idea, new application
challenges, and industrial practice studies.

Topics of Interest
- Memory Architectures for embedded Multicore systems
- Design for emerging embedded memory systems
- Compilers for DSP processors
- Embedded Multicore processors
- Compilers for heterogeneous embedded Multicore systems.
- Programming models for embedded Multicore systems
- Signal processing on embedded Multicore systems
- Multimedia signal processing algorithms on embedded Multicore systems
- Multimedia applications on embedded Multicore systems
- Human-computer interaction on Multicore systems
- Augmented reality applications on Multicore systems
- Software for Multicore, GPU, and embedded architectures
- VM for embedded systems
- 3D IC and Multicore architectures
- Real-time system designs for embedded Multicore environments
- Compiler for low-power
- ESL designs for embedded Multicore systems
- Applications for Automobile electronics of Multicore designs
- Embedded OS designs and performance tuning tools
- Hardware/Software co-design framework
- Embedded devices + cloud computing framework
- Compiler for worst-case execution time analysis
- Formal method for embedded systems

SUBMISSION
Papers should present original research and should provide sufficient
background material to make them accessible to the community. Full
paper submissions should not exceed 8 pages in standard IEEE
conference format. Papers should be submitted electronically, through
link https://www.easychair.org/conferences/?conf=icppems2015

Best and selected papers presented in the workshop will be invited to
appear published in Special Issues of International Journal of
Embedded Systems (IJES), International Journal of High Performance
Computing and Networking (IJHPCN) and International Journal of
Computational​ ​Science and Engineering (IJCSE), Inderscience publishers.

IMPORTANT DATES
Submission due date: May 1, 2015
Notification date: June 05, 2015
Camera Ready due date: June 20, 2015
ICPP Conference dates: September 1-4, 2015

ORGANIZERS
General Chairs
Kuan-Ching Li, Providence University, Taiwan
Cho-Li Wang, The University of Hong Kong, Hong Kong
Wen Zhi Chen, Zhejiang University, China

Program Chairs
Chen Liu, Clarkson University, USA
Bing Guo, Sichuan University, China
Albert Cohen, INRIA, France

Steering Committee
Jenq Kuen Lee, National Tsing-Hua University, Taiwan
Pen-Chung Yew, University of Minnesota, USA
Roy Ju, Mediatek, USA

International Liaison
Barbara Chapman, University of Houston, USA
Jean-Luc Gaudiot, Univ. of California – Irvine, USA
Shang-Hong Lai, National Tsing-Hua University, Taiwan
Qingguo Zhou, Lanzhou University, China

Contact
For additional information, please send your email to PC co-chair
Prof. Chen Liu (cliu@clarkson.edu).
 

Start: September 1, 2015
End: September 4, 2015
Venue: Beijing, China

Call for Papers: ParaFPGA 2015

Submitted by Erik D’Hollander
http://parafpga2015.elis.ugent.be

Parallel Computing with FPGAs (ParaFPGA 2015)
A Mini-Symposium held in conjunction with ParCo 2015
Edinburgh, UK

Conference date: 1-4 September 2015
Submission deadline : 1 June 2015
 

ParaFPGA2015 is a Mini-Symposium organized in conjunction with the
Biennial Parallel Computing conference ParCo2015, to be held in
Edinburgh, Scotland, UK on 1-4 September 2015.

SCOPE:

ParaFPGA focuses on parallel techniques for using FPGAs as
accelerator in high performance computing areas such as
supercomputing, embedded systems and big data computing.

Field Programmable Gate Arrays emerge as powerful building blocks for
High Performance Systems. The freedom to build tailored
architectures with extremely low power is one of the key milestones
on the path to exascale computing. Recently the major industrial
players invested heavily in high-level synthesis tools and
established well known programming paradigms to facilitate the march
towards programmable hardware. In addition, the famous memory wall
has been alleviated by incorporating processing cores inside the FPGA
fabric.

Of special interest are design methods, heterogeneous architectures
and algorithms optimized for execution on FPGAs. Design methods
include optimizing the resource utilization, development time and
high-level synthesis tools. Heterogeneous architectures encompass
multi-FPGAs, FPGAs with CPU cores and systems combining FPGAs, GPUs
and CPUs. Algorithms ready-made for FPGAs range from streaming
applications to fast dynamic reconfiguration and feature a
substantial performance increase.

Researchers and practitioners are invited to submit novel
contributions in the areas of high-level synthesis, dynamic
reconfiguration and high performance applications. Papers are
invited on a wide variety of topics related but not limited to:

– optimizing throughput of streaming applications
– non-uniform memory partitioning and data reuse
– heterogeneous on-chip processor and programmable logic codesign
– scalability of multi-core with multi-FPGA architectures
– OpenCL for FPGA applications
– evaluating performance metrics for high-level synthesis
– high-level synthesis techniques and case studies
– high-level partial and dynamic reconfiguration
– performance-driven resource and area optimization

SUBMISSION GUIDELINES:
Authors are invited to submit a full paper of maximum 10 pages or an
extended abstract of minimal 4 pages. The approved contributions
will be presented at the conference and the accepted full papers are
published in the ParCo 2015 proceedings. Details regarding the
format, presentation and paper submission are given on the author
guidelines page.

IMPORTANT DATES:
Submission deadline : 1 June 2015
Notification of acceptance : 15 July 2015
Final papers due : 15 August 2015

ORGANIZERS:
Steering committee:
- Gerhard Joubert, Conference Committee Chair
- Frans Peters, Finance Chair

Mini-Symposium committee:
- Dirk Stroobandt, Ghent University, Symposium chair
- Erik D’Hollander, Ghent University, Program committee chair
- Abdellah Touhafi, Brussels University, Program committee co-chair

Program committee:
- Abbes Amira, University of the West of Scotland, UK
- Georgi Gaydadjiev, Chalmers University of Technology
- Mike Hutton, Altera, USA
- Tsutomu Maruyama, University of Tsukuba, Japan
- Dionisios Pnevmatikos, Technical University of Crete, Greece
- Viktor Prasanna, University of Southern California, USA
- Mazen A. R. Saghir, Texas A&M University, Qatar
- Donatella Sciuto, Politecnico di Milano, Italy
- Sascha Uhrig, Technical University of Dortmund, Germany
- Sotirios G. Ziavras, New Jersey Institute of Technology, USA

CONTACT:
e-Mail: parafpga@elis.ugent.be
Website: http://www.parafpga2015.elis.ugent.be
 

Start: September 1, 2015
End: September 4, 2015
Venue: Edinburgh, UK

Call for Papers: JPDC Special Issue on Energy Efficient Multi-Core and Many-Core Systems

Submitted by Amir Rahmani
http://www.journals.elsevier.com/journal-of-parallel-and-distributed-computing/call-for-papers/special-issue-on-energy-efficient-multi-core-and-many-core-s/

Special Issue on Energy Efficient Multicore and Manycore Systems
The Journal of Parallel and Distributed Computing (Elsevier)

Recent trends in the microprocessor industry have important ramifications for
the design of the next generation of high-performance as well as embedded
parallel and network-based systems. By increasing number of cores, it is
possible to improve the performance while keeping the power consumption at the
bay. This trend has reached the deployment stage in parallel and network-based
systems ranging from small ultramobile devices to large telecommunication
servers. It is expected that the number of cores in these systems increases
dramatically in the near future. For such systems, energy efficiency is one of
the primary design constraints. The cessation of Dennard scaling and the dark
silicon phenomenon have limited recent improvements in transistor speed and
energy efficiency, resulting in slowed improvements in multi-core and many-core
systems. Consequently, architectural innovation has become crucial to achieve
performance and efficiency gains. New technologies that combine different types
of cores or similar cores with different computation capabilities can result in
a better match between the workload and the execution hardware improving
overall system energy efficiency. In addition, multi-core and many-core systems
need to be able to reconfigure themselves adaptively by monitoring their own
condition and the surrounding environment in order to adapt themselves to
different scenarios and performance-power requirements. Runtime monitoring
becomes crucial in the near future parallel and distributed multicore systems
due to increase in thermal issues as well as due to the need for various
adaptive managements.

This special issue addresses all aspects of energy-efficient computing in parallel
and distributed multi-core and many-core systems. Topics of interest include:
- Power and thermal estimation, analysis, optimization, and management
techniques for hardware and software systems
- Energy- and thermal aware application mapping and scheduling
- Energy- and thermal-aware dark silicon system design and optimization
- Energy-efficient heterogeneous system architecture
- Programming models, tools, languages and compilers to support energy-
aware computing
- Low-power monitor and sensor circuits
- Energy Efficient defect/fault tolerance, testing, and reliability
- Aging aware design, energy- and thermal-related reliability issues
- Energy-efficient off-chip/on-chip communication architectures including
networks-on-chip
- 3D architectures, integration and synthesis
- Energy-proportional systems
- Energy-efficient memory architectures and technologies (e.g. coherence
protocols)
- Formal methods for modeling, design and verification of energy efficient
parallel and network-based systems
- Application analysis and parallelization for energy-efficient design
- Cases studies of parallel and network-based systems demonstrating
energy-efficient implementation as well as emerging applications and design
framework

GUEST EDITORS:
- Hannu Tenhunen, Royal Institute of Technology, Sweden (hannu@kth.se)
- Alexander V. Veidenbaum, University of California, Irvine, USA (alexv@ics.uci.edu)
- Jose L. Ayala, Complutense University of Madrid, Spain (jayala@ucm.es)
- Pasi Liljeberg, University of Turku, Finland (pakrli@utu.fi)
- Amir Rahmani, University of Turku, Finland (amirah@utu.fi)

IMPORTANT DATES:
Manuscript due: September 1st, 2015
Acceptance/rejection notification: November 15th, 2015
2nd round check: January 15th, 2016
Final manuscript due: March 15th, 2016

SUBMISSIONS:
Submitted manuscripts will be reviewed according to the peer review policy of
Information Sciences as available on-line at www.elsevier.com/locate/ins.
Previously published conference papers should be clearly stated by the authors
and an explanation should be provided how such papers have been extended to
be considered for this special issue. Manuscripts should be formatted and be
submitted online according to the instructions for Information Sciences at

http://www.elsevier.com/journals/information-sciences/0020-0255/guide-for-authors.

Authors should make sure to select the correct special issue by selecting
“SI: E2MC2” in the Article Type step.

Start: September 1, 2015
End: September 1, 2015

September 2, 2015

Call for Papers: FPL 2015

Submitted by Kubilay Atasu
http://www.fpl2015.org

25th International Conference on Field Programmable Logic and
Applications (FPL2015)

The Royal Institution
London, UK
September 2-4, 2015
 

The International Conference on Field Programmable Logic and Applications (FPL)
is the first and the largest conference covering the rapidly growing area of
field-programmable logic. During the past 25 years, many of the advances in
reconfigurable system architectures, applications, processors, electronic
design automation (EDA) methods and tools have been first published in the
proceedings of the FPL conference series. The objective of FPL is to bring
together researchers and practitioners from both academia and industry from
around the world to share their insight into the frontiers of field-
programmable logic and its applications.

The 25th FPL Conference will take place at the Royal Institution, London, UK,
during September 2 – 4, 2015. Tutorials and associated workshops are offered on
August 31, September 1 and 4. A new angle of FPL 2015 is power efficient and
self-aware FPGA accelerators and heterogeneous computing platforms for High
Performance Computing, embedded systems and cyber physical systems. Highlights
of FPL 2015 will include keynotes from academia and industry.

FPL 2015 will offer the following FIVE CONFERENCE TRACKS:

1) ARCHITECTURES AND TECHNOLOGY
- Heterogeneous computing: multi/manycores, FPGAs, GPUs and DSPs
- Low power architectures
- Fault tolerant architectures
- Security and cryptography for FPGA Design
- 2.5D and 3D architectures
- Advanced on-chip interconnect technologies
- Analog and mixed-signal arrays
- Emerging technologies

2) APPLICATIONS AND BENCHMARKS
- Aerospace, automotive and industry automation
- Bioinformatics & medical systems
- Communications, software defined networking and Internet-of-Things
- Finance, HPC and database acceleration
- Big data analytics
- Embedded & cyber physical systems
- Signal processing and SDR
- Benchmarks for FPGA designs

3) DESIGN METHODS AND TOOLS
- System-level design tools
- High-level synthesis
- Hardware / software co-design
- Logic optimization and technology mapping
- Optimizations for power efficiency
- Packing, Placement and routing
- Rapid prototyping and emulation
- Testing, debugging and verification
- Open-source tools

4) SELF-AWARE AND ADAPTIVE SYSTEMS
- Self-awareness in FPGA-based systems
- Self-adaptive architectures and design techniques
- Virtualization of reconfigurable hardware
- Runtime resource management
- Partial reconfiguration

5) SURVEYS, TRENDS AND EDUCATION
- Surveys on reconfigurable logic architectures and design techniques
- Deployment of FPGAs in new application domains
- Roadmap of reconfigurable computing platforms
- Teaching courses and tutorials

IMPORTANT DATES:
Abstract Submission Deadline (mandatory): March 27, 2015
Full Paper Submission Deadline: April 3, 2015
Acceptance Notification: June 5, 2015
Camera-ready and Author Registration: June 26, 2015
Submission Instructions on: www.fpl2015.org

ORGANIZING COMMITTEE

General Chairs
Peter Cheung, Imperial College London, UK
Wayne Luk, Imperial College London, UK

Programme Chair
Cristina Silvano, Politecnico di Milano, IT

Track Chairs
Architectures and Technology
Jason H. Anderson, University of Toronto, CA
Applications and Benchmarks
Dirk Koch, University of Manchester, UK
Design Methods and Tools
Dirk Stroobandt, Ghent University, BE
Self-aware and Adaptive Systems
Marco Platzner, Paderborn University, DE
Surveys, Trends and Education
Walid Najjar, University of California at Riverside, US

Workshop & Tutorial Chairs
Guy Gogniat, Université de Bretagne-Sud, FR
Bob Stewart, University of Strathclyde, UK

Panel Chairs
Michael Huebner, Ruhr-Universitåt Bochum, DE
Simon Moore, University of Cambridge, UK

PhD Forum Chairs
Dimitrios Soudris, National TU of Athens, GR
Andy Tyrrell, University of York, UK

Demo Night & Project Presentation Chairs
Koen Bertels, TU Delft, NL
Jose Nunez-Yanez, University of Bristol, UK

Proceedings Chair
Walter Stechele, TU München, DE

Steering Committee
Jürgen Becker, KIT Karlsruhe, DE
Koen Bertels, TU Delft, NL
Eduardo Boemo, Univ. Autónoma de Madrid, ES
João M. P. Cardoso, Universidade do Porto, PT
Peter Y.K. Cheung, Imperial College London, UK
Martin Danek, Daiteq, CZ
Apostolos Dollas, TU of Crete, GR
Fabrizio Ferrandi, Politecnico di Milano, IT
Manfred Glesner, TU Darmstadt, DE
John Gray, Consultant, UK
Reiner Hartenstein, TU Kaiserslautern, DE
Andreas Herkersdorf, TU München, DE
Udo Kebschull, Goethe University Frankfurt, DE
Wayne Luk, Imperial College London, UK
Patrick Lysaght, Xilinx, Inc., US
Jari Nurmi, Tampere University of Technology, FI
Lionel Torres, University of Montpellier II, FR
Jim Tørresen, University of Oslo, NO
 

Start: September 2, 2015
End: September 4, 2015
Venue: The Royal Institution, London, UK

Call for Papers: FPL 2015

Submitted by Kubilay Atasu
http://www.fpl2015.org/

25th International Conference on Field Programmable Logic and
Applications (FPL2015)

The Royal Institution
London, UK
September 2-4, 2015
 

Please note the following extended deadlines:
- Abstract submission deadline: 27 March 2015 -> 3 April 2015
- Full paper submission deadline: 3 April 2015 -> 10 April 2015
 

The International Conference on Field Programmable Logic and Applications (FPL)
is the first and the largest conference covering the rapidly growing area of
field-programmable logic. During the past 25 years, many of the advances in
reconfigurable system architectures, applications, processors, electronic
design automation (EDA) methods and tools have been first published in the
proceedings of the FPL conference series. The objective of FPL is to bring
together researchers and practitioners from both academia and industry from
around the world to share their insight into the frontiers of field-
programmable logic and its applications.

The 25th FPL Conference will take place at the Royal Institution, London, UK,
during September 2 – 4, 2015. Tutorials and associated workshops are offered on
August 31, September 1 and 4. A new angle of FPL 2015 is power efficient and
self-aware FPGA accelerators and heterogeneous computing platforms for High
Performance Computing, embedded systems and cyber physical systems. Highlights
of FPL 2015 will include keynotes from academia and industry.
FPL 2015 will offer the following 5 conference tracks:

1) Architectures And Technology
2) Applications And Benchmarks
3) Design Methods And Tools
4) Self-aware And Adaptive Systems
5) Surveys, Trends And Education

Additional details and submission Instructions on: www.fpl2015.org
 

Start: September 2, 2015
End: September 4, 2015
Venue: London, UK

September 3, 2015

Call for Papers: Mini-Symposium on Energy and Resilience in Parallel Programming

Submitted by Christos D. Antonopoulos
http://erpp.inf.uth.gr

Mini-Symposium on Energy and Resilience in Parallel Programming (ERPP 2015)
in Conjunction with ParCo 2015
Edinburgh, Scotland, UK
September 3-4 2015
 

ERPP provides a forum to broadly explore the implications of energy and resilience
on the principles and practice of parallel programming. ERPP aims to present original
research that uses energy and resilience as first-class resources in parallel
programming languages, libraries and models and demonstrates how parallel
programming can improve energy-efficiency and resilience of large-scale
computing systems or many-core embedded systems. The minisymposium also
intends to explore how energy and resilience management in hardware or system
software may affect the performance of existing parallel programming environments.

The topics explored by ERPP include but are not limited to:
- Parallel programming abstractions for energy and resilience
- Compiler and runtime support for energy- and resilience-aware execution
- Parallel libraries and auto-tuning for energy and resilience
- Performance of parallel programming languages, libraries and tools in energy-
constrained environments
- Measurement and characterization of resilience in parallel programming
models, languages and libraries
- Measurement and characterization of energy in parallel programming models,
languages and libraries
- New computing paradigms for improving energy and resilience in parallel
programming, such as approximate computing or near-threshold computing

SUBMISSION GUIDELINES:
We call for high-quality, original contributions (in English language) related
to the minisymposium topics. Extended abstracts of at least 4 pages should be
submitted by June 23 2015 and will be published in a book of abstracts. Final,
camera-ready versions of accepted full length papers (up to 10 pages) must be
prepared in October 2015 (after the minisymposium).

IMPORTANT DATES:
June 23, 2015: Submission deadline for extended abstracts
July 17, 2015: Notification of decision
July 31, 2015: Camera-ready of extended abstracts due
October, 2015: Full paper submission

ORGANIZERS:
Dimitrios S. Nikolopoulos, Queen’s University of Belfast
Christos D. Antonopoulos, University of Thessaly, Greece

PROGRAM COMMITTEE:
Kevin Barker, PNNL
Costas Bekas, IBM Research – Zurich
Nikolaos Bellas, Universuty of Thessaly
Kirk Cameron, Virginia Tech
Rong Ge, Marquette University
Dimitris Gizopoulos, University of Athens
Nikos Hardavellas, Northwestern University
Georgios Karakonstantis, Queen’s University of Belfast
Spyros Lalis, University of Thessaly
Dong Li, University of California, Merced
David Lowenthal, University of Arizona
Naoya Maruyama, RIKEN AICS
Kathryn Mohror, LLNL
Enrique S. Quintana-Orti, Universidad Jaume I
Pedro Trancoso, University of Cyprus
Zheng Wang, Lancaster University

Start: September 3, 2015
End: September 4, 2015
Venue: Edinburgh, Scotland, UK

September 11, 2015

Call for Papers: HPCA 2016

Submitted by Jose F. Martinez
The 22nd IEEE International Symposium
on High Performance Computer Architecture (HPCA)

Barcelona, Spain
 

The IEEE International Symposium on High Performance Computer
Architecture (HPCA) provides a high-quality forum for scientists
and engineers to present their latest research findings in this
rapidly changing field. Authors are invited to submit papers on
all aspects of high-performance computer architecture. Topics of
interest include, but are not limited to:

– Processor, cache, and memory architectures
– Parallel computer architectures
– Multicore architectures
– Impact of technology on architecture
– Power-efficient architectures and techniques
– Dependable/secure architectures
– High-performance I/O systems
– Embedded and reconfigurable architectures
– Interconnect and network interface architectures
– Architectures for cloud-based HPC and data centers
– Innovative hardware/software trade-offs
– Impact of compilers and system software on architecture
– Performance modeling and evaluation
– Architectures for emerging technology and applications

Authors should submit an abstract by Friday, September 4, 2015,
5pm EST. They should submit the full version of the paper by
Friday, September 11, 2015, 5pm EST. No requests for extensions
will be granted. The full version should be a PDF file that
follows the submission guidelines that will be available at the
conference website. Papers should be submitted for double-blind
review. We anticipate selecting a Best Paper award. All papers
will be evaluated based on their novelty, fundamental insights,
experimental evaluation, and potential for long-term impact.

ORGANIZING COMMITTEE:
General Co-chairs:
Ramon Canal, U. Politècnica de Catalunya
Antonio González, U. Politècnica de Catalunya

Program Chair:
José Martínez, Cornell U.

Program Committee:

Tor Aamodt, U. of British Columbia
David Albonesi, Cornell U.
Rajeev Balasubramonian, U. of Utah
David Brooks, Harvard U.
Christopher Batten, Cornell U.

Brad Beckmann, AMD
Mainak Chaudhuri, IIT Kanpur
Reetuparna Das, U. of Michigan
Joe Devietti, U. of Pennsylvania
Natalie Enright Jerger, U. of Toronto

Hadi Esmaeilzadeh, Georgia Tech
José Flich, U. Politècnica de València
Boris Grot, U. of Edinburgh
Kim Hazelwood, Yahoo! Labs
James Hoe, Carnegie Mellon U.

Jaehyuk Huh, KAIST
Hillery Hunter, IBM Research
Wen-mei Hwu, U. of Illinois
Engin Ipek, U. of Rochester
Mary Jane Irwin, Penn State U.

Ulya Karpuzcu, U. of Minnesota
Stefanos Kaxiras, Uppsala U.
Jangwoo Kim, POSTECH
Martha Kim, Columbia U.
Nam Sung Kim, U. of Wisconsin

Christos Kozyrakis, Stanford U.
Hsien-Hsin Lee, TSMC
Mikko Lipasti, U. of Wisconsin
Scott Mahlke, U. of Michigan
Srilatha Manne, Cavium Networks

Debbie Marr, Intel
Jason Mars, U. of Michigan
Pablo Montesinos, Qualcomm
Trevor Mudge, U. of Michigan
Mike O’Connor, NVIDIA

Alex Ramirez, NVIDIA
José Renau, U.C. Santa Cruz
Daniel Sanchez, MIT
Karu Sankaralingam, U. of Wisconsin
Yanos Sazeides, U. of Cyprus

Dan Sorin, Duke U.
Per Stenström, Chalmers U.
Viji Srinivasan, IBM Research
Carole-Jean Wu, Arizona State U.
Jun Yang, U. of Pittsburgh

Start: September 11, 2015
End: September 11, 2015
Venue: Barcelona, Spain