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November 1, 2014

Call for Papers: IJPP Special Issue on Workload Optimized Systems

Submitted by Parijat Dube

Springer International Journal of Parallel Programming (IJPP)
Special Issue on Workload Optimized Systems


The slowdown in Moore’s Law makes it increasingly important to optimize
systems around specific workloads. Such workload optimized systems have
hardware and/or software specifically designed to run well for a particular
workload or workload class. Such systems include, but are not limited to
traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory
accelerators, I/O accelerators, hybrid systems, and IT appliances. This
workload optimized system approach contrasts to the broad general purpose
direction of computing over many decades. The workload optimized systems
approach is growing in importance, as we see in systems from cellphones to
tablets to routers to game machines to Top500 supercomputers, and IT
appliances such as IBM’s DataPower and Netezza, and Oracle’s Exadata. The
goal of this special issue is to foster awareness in industry and academic
community on workload optimized systems and to expose cross hw/sw stack
unique systems and software research challenges associated with such
systems. All submitted papers are subject to the same review process as those
papers accepted for publication in the regular issues. The special issue seeks
original papers on a range of topics related to workload optimized systems
including, but not limited to

- GPUs, FPGAs, ASIC Accelerators
- Memory and I/O accelerators
- Network accelerators
- Storage optimized systems
- System level accelerators
- IT Appliances
- Systems in specific domains like analytics, cloud, cognitive, mobile etc.
- Converged/Hybrid/Heterogeneous systems
- Cross hardware/software stack design and optimization
- Programming models for workload optimized systems
- Measurements and Experimentation
- Workload characterization and profiling
- Performance modeling and optimization
- Workload scheduling and orchestration
- Runtime management systems
- Industrial Experiences

Manuscript due: March 27, 2015
First decision notification: June 5, 2015
Revision due: July 10, 2015
Final decision notification: August 14, 2015
Final version due: September 11, 2015

Authors are encouraged to submit high-quality, original work that
has neither appeared in, nor is under consideration by, other
journals. All papers will be reviewed following standard reviewing
procedures for the Journal.
Papers must be prepared in accordance with the Journal guidelines:

Manuscripts must be submitted to:
Choose “S.I.: Workload Optimized Systems” as the article type.

Erik Altman, IBM Research, Yorktown Heights, NY.
Parijat Dube, IBM Research, Yorktown Heights, NY.


Start: November 1, 2014
End: October 1, 2015

March 29, 2015

Call for Papers: FastPath 2015

Submitted by Parijat Dube

FastPath 2015: Fourth International Workshop on Performance Analysis of
Workload Optimized Systems

Co-located with ISPASS 2015
Philadelphia, PA USA
March 29, 2015

The goal of FastPath is to bring together researchers and practitioners
involved in cross-stack hardware/software performance analysis, modeling,
and evaluation of workload optimized systems. With microprocessor clock
speeds being held constant, optimizing systems around specific workloads
is an increasingly attractive means to improve performance.
More precisely, workload optimized systems have hardware
and/or software specifically designed to run well for a
particular application or application class. The types and
components of workload optimized systems vary, but a partial list
includes traditional CPUs assisted with accelerators
(ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators,
hybrid systems, converged infrastructure, and IT appliances.

The importance of workload optimized systems is seen
in their ubiquitous deployment in diverse systems from
cellphones to tablets to routers to game machines to
Top500 supercomputers. Prominent commercial examples of
workload optimized systems include IBM DataPower, IBM Purescale
Application System, IBM Watson, Oracle Exadata, and HP Moonshot Servers.
Exploiting CPU savings and speed-ups offered by workload optimized
systems for application level performance improvement poses several
cross stack hardware and software challenges. These include
developing alternate programming models to exploit massive
parallelism offered by accelerators, designing low-latency,
high-throughput H/W-S/W interfaces,developing techniques to
efficiently map processing logic on hardware, and
cross system stack performance optimization and tuning.
Emerging infrastructure supporting big data analytics,
cognitive computing, large-scale machine learning, mobile computing,
and internet-of-things, further exemplify workload optimized design
at large.

FastPath seeks to facilitate the exchange of ideas on performance analysis
and evaluation of workload optimized systems and seeks papers on a wide
range of topics including, but not limited to:
- Workload characterization and profiling
- Industrial experiences
- GPUs, FPGAs, ASIC accelerators
- Memory, I/O, Storage, Network accelerators
- Hardware/Software co-design
- Workload optimized servers
- Hybrid/Heterogeneous systems
- Measurements and Experimentation
- Analytical techniques
- Performance modeling and prediction
- Performance tooling and optimization
- Programming models for workload optimized systems
- Runtime management systems
- Workload scheduling and orchestration
- Workload optimized clusters in Cloud
- Big Data analytics systems
- Large-scale machine learning systems
- Intelligent/Cognitive systems
- Mobile computing systems
- Converged/integrated infrastructure
- Workload optimized systems from specific domains,
e.g., financial, biological, education, commerce, healthcare.

The authors should submit PDF of a 2-4 page extended abstract by the
submission deadline at

The submission should follow standard format (2-column,
10 to 12-point type, single spaced, 1-inch margins).
Abstracts should provide sufficient detail about the work
and its technical contributions.

Authors of selected abstracts will be invited to present their work
at the workshop. Accepted abstracts will be made available through
the workshop website and hard copies will be provided at the
workshop to the attendees. There are no copyright issues with FastPath,
and thus authors retain the copyright of their work with complete
freedom to submit their work elsewhere.

Submission: March 1, 2015
Author Notification: March 10, 2015
Workshop: March 29, 2015

General Chair:
Erik Altman (IBM)

Program Chairs:
Vijay Janapa Reddi (U-Texas, Austin)
Parijat Dube (IBM)

Web Chair: Augusto Vega (IBM)

David Brooks, Harvard University
Trey Cain, Qualcomm Research
Mike Ferdman, Stony Brook University
Sudhanva Gurumurthi, AMD, University of Virginia
Eric Van Hensbergen, ARM Research
Arrvindh Shriraman, Simon Fraser University
Devesh Tiwari, Oak Ridge National Lab
Sudhakar Yalamanchili, Georgia Tech
Chuanjun Zhang, Intel

Start: March 29, 2015
End: March 29, 2015
Venue: Philadelphia, PA, USA.

Call for Participation: ISPASS 2015

Submitted by Kelly Shaw

2015 IEEE International Symposium on Performance Analysis of Systems
and Software (ISPASS)

Philadelphia, PA USA
March 29-31, 2015

EARLY REGISTRATION DEADLINE: March 1st, 2015 at 5PM Pacific

Online registration:

ISPASS 2015 will be held at the Hyatt Regency Philadelphia at Penn’s Landing.
Please use the following link to register for the hotel:

Note: The hotel registration cutoff is March 7, 2015.

If you require an invitation letter for purposes of a visa application, please
send an email with your name, email address, mailing address, IEEE
member number (if any), the ID of the paper you are presenting (if any) and
a copy of your registration confirmation to Jose Renau, the Program Chair,

The 2015 IEEE International Symposium on Performance Analysis of Systems and
Software is sponsored by the IEEE Computer Society’s Technical Committee on
Internet, Technical Committee on Computer Architecture, and Technical Committee
on Microprogramming and Microarchitecture.

For the conference program and other details, please visit

Start: March 29, 2015
End: March 31, 2015
Venue: Philadelpha, PA

March 31, 2015

Call for Papers: Workshop on Silicon Errors in Logic – System Effects

Submitted by William H. Robinson
Workshop on Silicon Errors in Logic – System Effects (SELSE 2015)
March 31 – April 1, 2015 – Austin, TX

NOTE TO AUTHORS: Paper submission deadlines are earlier than for
previous SELSE workshops.

Important dates:
- Register an abstract: December 8, 2014
- Paper submission: December 15, 2014
- Authors notification: January 30, 2015
- Camera-ready submission: February 18, 2015

The growing complexity and shrinking geometries of modern
manufacturing technologies are making high-density, low-voltage
devices increasingly susceptible to the influences of electrical
noise, process variation, transistor aging, and the effects of natural
radiation. The system-level impact of these errors can be
far-reaching. Growing concern about intermittent errors, unstable
storage cells, and the effects of aging are influencing system design
and failures in memories account for a significant fraction of costly
product returns. Emerging logic and memory device technologies
introduce several reliability challenges that need to be addressed to
make these technologies viable. Finally, reliability is a key issue
for large-scale systems, such as those in data centers. The SELSE
workshop provides a forum for discussion of current research and
practice in system-level error management. Participants from industry
and academia explore both current technologies and future research
directions (including nanotechnology). SELSE is soliciting papers that
address the system-level effects of errors from a variety of
perspectives: architectural, logical, circuit-level, and semiconductor
processes. Case studies are also solicited.

Key areas of interest are (but not limited to):
- Technology trends and the impact on error rates.
- New error mitigation techniques.
- Characterizing the overhead and design complexity of error
mitigation techniques.
- Case studies describing the tradeoffs analysis for reliable systems.
- Experimental silicon failure data.
- System-level models: derating factors and validation of
error models.
- Error handling protocols (higher-level protocols for robust
system design).
- Characterization of reliability of systems deployed in the field and
mitigation of issues.

Authors are requested to register to submit a paper by December 8th,
2014 and to submit their paper for review by December 15th 2014.
Papers will be considered for both oral and poster presentation, and
all accepted submissions will be distributed to SELSE participants.
Authors will be notified by January 30th, 2015. Final papers are due
on February 18th, 2015.

Additional information and guidelines for submission are available at Submissions and final papers should be in PDF
following IEEE two-column conference proceedings format that does not
exceed six printed pages. Papers are not made available through IEEE,
and authors retain the copyright of their work. Authors may optionally
choose to make their presentations available online at the workshop
web site.

Organizing Committee

General Chairs:
Sarah Michalak, Los Alamos National Laboratory
Helia Naeimi, Intel

Program Chairs:
Dimitris Gizopoulos, University of Athens
Sudhanva Gurumurthi, AMD/University of Virginia

Finance Chairs:
Dan Alexandrescu, iROC Technologies
Siva Hari, NVIDIA

Local Arrangements Chair:
Vijay Janapa Reddi, UT-Austin

Publicity Chairs:
Yi-Pin Fang, TSMC
Paolo Rech, UFRGS
William H. Robinson, Vanderbilt University
Yanos Sazeides, University of Cyprus

Documents Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology

Marios Kleanthous, Mesoyios College

Advisors to the Committee:
Adrian Evans, iROC Technologies
Vilas Sridharan, AMD
Alan Wood, Oracle

Start: March 31, 2015
End: April 1, 2015
Venue: Austin, TX

April 3, 2015

Call for Papers: NAS 2015

Submitted by Ramon Bertran

10th IEEE International Conference on Networking, Architecture and Storage (NAS)
Boston, Massachusetts, USA,
August 6-7, 2015

Sponsored by IEEE Computer Society’s Technical Committees on Computer
Architecture (TCCA), Parallel Processing (TCPP) and Distributed Processing

– Paper Submission: April 3, 2015
– Notification: May 20, 2015
– Camera-Ready Copy: June 29, 2015

The International Conference on Networking, Architecture, and Storage (NAS)
provides a high-quality international forum to bring together researchers and
practitioners from academia and industry to discuss cutting-edge research on
networking, high-performance computer architecture, and parallel and distributed
data storage technologies. NAS 2015 will expose participants to the most recent
developments in the interdisciplinary areas.

Authors are invited to submit previously unpublished work for possible
presentation at the conference. Papers should be submitted for double-blind
review. The program committee will nominate best papers for recognition in
the three conference topic areas. All papers will be evaluated based on their
novelty, fundamental insight, experimental evaluation, and potential for
long-term impact; new-idea papers are encouraged. All accepted papers will
be published in IEEE digital library.

Papers are solicited in fields that include, but are not limited to, the
- Processor, cache, memory system architectures
- Parallel and multi-core architectures
- GPU architecture and programming
- Data-center scale architectures
- Architecture for handheld or mobile devices
- Accelerator-based architectures
- Application-specific, reconfigurable or embedded architectures
- HW/SW co-design and tradeoffs
- Power and energy efficient architectures and techniques
- Effects of circuits and emerging technology on architecture
- Cloud and grid computing
- Architecture, networking or storage modeling and simulation methodologies
- Non-volatile memory technologies
- Software defined networking
- Storage performance and scalability
- File systems, object-based storage
- Energy-aware storage
- SSD architecture and applications
- Parallel I/O
- Cloud storage
- Storage virtualization and security
- Software defined storage
- Big Data infrastructure
- Big Data services and analytics

General Chair
– Resit Sendag (U of Rhode Island)
Program Co-Chairs:
– Jun Wang (U of Central Florida)
– Iris Bahar (Brown U)
Vice Program Chairs:
– Networking: Weikuan Yu (Auburn U) and Haiying Shen (Clemson U)
– Architecture: Martin Herbordt (Boston U) and Tali Moreshet (Boston U)
– Storage: Xiaosong Ma (Qatar Computing Res. Inst. & NC State U) and Ali Butt
(Virginia Tech)
Local Arrangements Chair:
– Ningfang Mi (Northeastern U)
Publications Chair:
– Gus Uht (U of Rhode Island)
Registration Chair:
– Yan Sun (U of Rhode Island)
Finance Chair:
– Yan Luo (U of Massachussetts-Lowell)
Industry Liaison Chair:
– Ming Zhang (EMC)
Publicity Co-chairs:
– Chengsheng Xie (Huazhong U Sci. Tech)
– Andre Brinkmann (Universitat Mainz)
– Ramon Bertran (IBM)
– Alper Buyuktosunoglu (IBM)
Submission Chair:
– Xunchao Chen (U of Central Florida)
Web Chair:
– Ibrahim Burak Karsli (U of Rhode Island)
Steering Committee
– Xubin He (Virginia Commonwealth U)
– Changsheng Xie(Huazhong U of Sci.Tech)
– Andre Brinkmann (U Mainz)
– Jian Li (IBM Austin Research Lab)
– Tao Li (University of Florida)
– Marco D Santambrogio (Politec. Milano)
– Hongbin Sun (Xi’An Jiaotong U)

Networking Track
– Weikuan Yu, Auburn University (co-chair)
– Haiying Shen, Clemson University (co-chair)
– Sarp Oral, Oak Ridge National Lab
– Shane Canon, Lawrence Berkeley National Lab
– Richard Graham, Mellanox
– Amith R Mamidala, IBM
– Jian Tan, IBM
– Ronald Brightwell, Sandia National Lab
– Gerald F II Lofstead, Sandia National Lab
– Wenjun Wu, Beihang University
– Jia Rao, University of Colorado Cold Springs
– Seung-Jong Park, Louisiana State University
– Xin Yuan, Florida State University
– Saad Biaz, Auburn University
– Kang Chen, Clemson University
– Yaohang Li, Old Dominion University
– Shan Lin, Temple University
– Chuan Yue, University of Colorado Colorado Springs
– Mengjun Xie, University of Arkansas at Little Rock
– Lei Yu, Georgia State University
– Yang Guo, Bell Labs
– Yongning Tang, Illinois State University
– Fangzhe Chang, Bell Labs, Alcatel-Lucent
– Feng Deng, Clemson University
– Weichen Liu, Chongqing University
– Zhi Wang, Tsinghua University
– Xiaojun Hei, Huazhong University of Science and Technology
– Yuan He, Hong Kong University of Science and Technology
– Di Wu, Sun Yat-Sen University
– Liudong Xing, University of Massachusetts Dartmouth
– Gang Zhou, College of William and Mary
– Jiangyi Hu, Devry University
– Junwei Cao, Tsinghua University
– Wenzhong Li, Nanjing University
– Surendar Chandra, EMC Data Protection and Availability Division
– Wei Zhang, Hong Kong University of Science and Technology
– Yao Liu, SUNY Binghamton
– Chiu Tan, Temple University
– Kyoungwon Suh, Illinois State University
Architecture Track
– Martin Herbordt, Boston University (co-chair)
– Tali Moreshet, Boston University (co-chair)
– Lide Duan , University of Texas at San Antonio
– Cesare Ferri , Marvel
– Mark Hempstead , Drexel University
– Ajay Joshi , Boston University
– Dong Li , Qualcomm
– Xiaoyao Liang , Shanghai Jiao Tong University
– Yan Luo , University of Massachusetts Lowell
– Vijay Nagarajan , University of Edinburgh
– Gi-Ho Park , Sejong University
– Dmitry Ponomarev , SUNY
– Kelly Shaw , University of Richmond
– Magnus Sjalander, Uppsala University
– Bharat Sukhwani, IBM
– Radu Teodorescu , Ohio-State University
– Jing Wang , Capital Normal University
– Jason Xue , City University of Hong Kong
– Zhibin Yu , Shenzhen Institute of Advanced Technology
– Jidong Zhai , Tsinghua University
– Dongyuan Zhan , AMD
– Chuanjun Zhang , Intel
– Wei Zhang , Virginia Commonwealth University
– Ping Zhou , Intel
– Zhichun Zhu , University of Illinois at Chicago
Storage Track
– Ali Butt, Virginia Tech (co-chair)
– Xiaosong Ma, Qatar Computing Research Institute and North Carolina State
University (co-chair)
– Youngjae Kim, Oak Ridge National Laboratory
– Gary Liu, Oak Ridge National Laboratory
– Fei Meng, North Carolina State University and PureStorage
– Xing Wu, Amazon
– Xuanhua Shi, Huazhong University of Science and Technology
– Zhe Zhang, Cloudera
– Sudharshan Vazhkuda, ORNL
– Shuibing He, IIT
– Yong Chen, TTU
– Suren Byna, LBL
– Medha Bhadkamkar, Symantec Research Labs
– Avani Wildani, Salk Institute
– Min Li, IBM TJ Watson Research Center
– Aayush Gupta, IBM Almaden Research Center
– Lei Tian, Tintri
– Tao Xie, San Diego State University
– Song Jiang, Wayne State University
– Abhishek Chandra, University of Minnesota
– Jay Lofstead, Sandia National Laboratories
– Jinho Hwang, IBM Research
– Yifeng Zhu, University of Maine
– Xiao Qin, Auburn University
– Douglas Thain, University of Notre Dame
– Alan Sussman, University of Maryland
– Peter Varman, Rice University
– Nitin Agrawal, NEC Labs
– Fang Zheng, IBM T.J. Watson Research Center
– Qingdong Wang, University of Central Florida/Huizhou University

Start: April 3, 2015
End: April 3, 2015

May 7, 2015

Call for Posters: ANCS 2015

Submitted by Eric Keller

The 11th ACM/IEEE Symposium on Architectures for Networking
and Communications Systems (ANCS 2015)

Oakland, CA, USA
May 7-8, 2015

Poster abstract submission deadline: March 23, 2015
Author notification for posters: March 30, 2015
Camera-ready for poster abstract: April 6, 2015

The poster session will provide a forum for researchers to showcase
their exciting early work. Areas of interest are the same as those
listed for regular papers. Posters need not describe complete work,
but they should have at least preliminary results to report so that
feedback on the ongoing work can be obtained from knowledgeable
conference attendees. We especially encourage student poster
submissions where the student is the first author. Posters will be
evaluated based on their technical merit and innovation as well as
their potential to stimulate interesting discussions and exchange of
ideas. Submissions from both industry and universities are
encouraged. Two-page poster abstracts will be published in the
conference proceedings.

Poster submissions must be formatted according to the ACM/SIG
conference paper format using 9pt font and submitted in PDF
format. The style is identical to that used for main conference
submissions ( except that
poster submissions are limited to no more than 2 pages and use 9pt
font instead of 12pt font. Please email poster abstract submissions
as PDF attachments to:
with the subject line: “ANCS 2015 POSTER SUBMISSION.”

ANCS 2015 Poster Chair
Won So:

Start: May 7, 2015
End: May 8, 2015
Venue: Oakland, CA, USA

May 18, 2015

Call for Papers: Computing Frontiers 2015

Submitted by Kaoutar El Maghraoui

ACM International Conference on Computing Frontiers 2015 (CF’15)
Ischia, Italy
May 18 – 21, 2015

Computing Frontiers represents an engaged, collaborative community
of researchers who are excited about transformational technologies
in the field of computing. We are presently on the cusp of several
revolutions, including new memory technologies, networking
technologies, algorithms for handling large-scale data, power-saving
and energy-efficient solutions for data centers, systems solutions
for cloud computing, new application domains that affect every day
life and many, many more. Boundaries between the state-of-the-art
and revolutionary innovation constitute the computing frontiers that
must be pushed forward to advance science, engineering, and
information technology. Before revolutionary materials, devices,
and systems enter the mainstream, early research must be performed
using far-reaching projections of the future state of technologies.

Computing Frontiers is a gathering for people to share and discuss
such work, focusing on a wide spectrum of advanced technologies and
radically new solutions relevant to the development of the whole
spectrum of computer systems, from embedded to high-performance

This year we are adding Industry Sessions and Workshops that focus
on special topics. These sessions should have a special computing
frontiers focus and can run between 1/2 and a full day.

Workshop / Industry Sessions Proposal Deadline: November 1, 2014
(Extended from October 3, 2014)
Submissions deadline: January 16, 2015
Notification: February 20, 2015
Camera-Copy Papers Due: March 20, 2015

We seek contributions that push the envelope in a wide range of
computing topics, ranging from more traditional research in
architecture and systems to new technologies and devices. We seek
contributions on novel computing paradigms, computational models,
algorithms, application paradigms, development environments,
compilers, operating environments, computer architecture, hardware
substrates, memory technologies and smarter life applications. We
are also interested in emerging fields that may not fit within
traditional categories.

- Algorithms and Models of Computing
approximate and inexact computing, quantum and probabilistic

- Biological Computing Models
brain computing, neural computing, computational neuroscience,
biologically-inspired architectures

- Big Data
analytics, machine learning, search and representation, system

- System Complexity Management
cloud systems, datacenters, exa-scale computing

- Computers and Society
education, health and cost/energy-efficient design, smart cities,
emerging markets

- Security
architecture and systems support for protection against malicious

- Limits on Technology Scaling and Moore’s Law
defect- and variability-tolerant designs, graphene and other
novel materials, nanoscale design, optoelectronics, dark silicon

- Uses of Technology Scaling
3D stacked technology, challenges of manycore designs,
PCM’s, novel memory architectures, mobile devices

- Compiler technologies
novel techniques to push the envelope on new technologies,
applications, hardware/software integrated solutions, advanced

- Networking
technology and protocols, bandwidth management, social networks,
internet of things

- Interdisciplinary Applications
applications that bridge multiple disciplines in interesting ways

- Position Papers, Trend Papers and Crazy Ideas

- Industry Sessions and Workshops
Sessions should have a special computing frontiers focus and can
run between 1/2 and full day. Proposals for Industry Sessions and
Workshops should be sent by e-mail to fpalumbo (AT) by
filling out the form that can be found on the Computing Frontiers

Authors are invited to submit full papers or posters to the main
conference. Full papers and poster abstracts must be submitted
through the conference paper submission site. Full papers should
not exceed 8 double-column pages in standard ACM conference format.
Poster abstracts should not exceed two pages in the same format.
These limits include figures, tables, and references. Our review
process is double-blind. Thus, please remove all identifying
information from the paper submission (also if citing own work).
Abstracts for accepted posters will be published in the proceedings
and in the ACM Digital Library (note that authors of these works
retain their copyright rights to publish more complete versions
later). The best papers from the Computer Frontiers Conference and
Workshops will be invited to be published in special issues of IJPP
or PARCO. As per ACM guidelines, at least one of the authors of
accepted papers is required to register for the conference. Industry
Session and Workshop proposals should be submitted to
fpalumbo (AT) by filling out the form that can be found
on the Computing Frontiers website.

General Chairs:
Claudia Di Napoli, ICAR-CNR, IT
Valentina Salapura, IBM, USA

Program Chairs:
Hubertus Franke, IBM Research, USA
Rui Hou, Institute for Computing Technology,
Chinese Academy of Sciences, PRC

Finance Chair:
Jens Breitbart, TU Munich, DE

Local Arrangements Chair:
Silvia Rossi, Universite degli Studi di Napoli “Federico II”, IT

Poster Chair:
Alexander Heinecke, Intel Parallel Computing Lab, US

Publicity Chairs:
Kun Wang, Microsoft, PRC
Raymond Namyst, University of Bordeaux, FR

Publication Chair:
Michela Taufer, University of Delaware, US

Web Chair:
Kristian Rietveld, Leiden University, NL

Steering Committee:
Monica Alderighi, INAF, IT
Claudia Di Napoli, ICAR-CNR, IT
Hubertus Franke, IBM, US
Diana Franklin, University of California at Santa Barbara, US
Georgi Gaydadijev, Chalmers University, SE
Alexander Heinecke, Intel Parallel Computing Lab, US
Paul Kelly, Imperial College, GB
Sally A. McKee, Chalmers University of Technology, SE
Krishna Palem, Rice University, US / Nanyang Technological University, SG
Francesca Palumbo, University of Cagliari, IT
Valentina Salapura, IBM, US
Pedro Trancoso, University of Cyprus, CY
Carsten Trinitis, TU Munich, DE
Eli Upfal, Brown University, US
Josef Weidendorfer, TU Munich, DE

Start: May 18, 2015
End: May 21, 2015
Venue: Ischia, Italy

May 25, 2015

Call for Papers: RAW 2015

Submitted by Joao MP Cardoso

22nd Reconfigurable Architectures Workshop (RAW 2015)
Hyderabad, India
May 25, 2015

The 22nd Reconfigurable Architectures Workshop (RAW 2015)
will be held in Hyderabad, India in May 2015. RAW 2015 is
associated with the 29th Annual International Parallel &
Distributed Processing Symposium (IPDPS 2015) and is
sponsored by the IEEE Computer Society Technical Committee
on Parallel Processing. The workshop is one of the
major meetings for researchers to present ideas, results,
and on-going research on both theoretical and practical
advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized
by the ability of underlying hardware architectures or
devices to rapidly alter (often on the fly) the functionalities
of their components and the interconnection between them
to suit the problem at hand. The area has a rich theoretical
tradition and wide practical applicability. There are several
commercially available reconfigurable platforms
(FPGAs and coarse-grained devices) and many modern
applications (including embedded systems and HPC) use
reconfigurable subsystems. An appropriate mix of theoretical
foundations and practical considerations, including algorithms,
architectures, applications, technologies and tools,
is essential to fully exploit the possibilities offered
by reconfigurable computing. The Reconfigurable Architectures
Workshop aims to provide a forum for creative and productive
interaction for researchers and practitioners in the area.

Authors are invited to submit manuscripts of original
unpublished research in all areas of reconfigurable systems,
including architectures, algorithms, applications,
software and cross-cutting areas. Topics of interest include,
but are not limited to:

Architectures & Algorithms
- Theoretical Interconnect and Computation Models
- Algorithmic Techniques and Mapping
- Run-Time Reconfiguration Models and Architectures
- Emerging Technologies (optical models, 3D Interconnects, devices)
- Bounds and Complexity Issues
- Analog Arrays

Reconfigurable Systems & Applications
- Reconfigurable accelerators (HPC, Bioinformatics, Multicore environments)
- Embedded systems and Domain-Specific solutions
(Digital Media, Gaming, Automotive applications)
- Distributed Systems & Networks
- Wireless and Mobile Systems
- Emerging applications (Organic Computing, Biology-Inspired Solutions)
- Critical issues (Security, Energy efficiency, Fault-Tolerance)

Software & Tools
- High-Level Design Methods (Hardware/Software co-design, Compilers)
- System Support (Soft processor programming)
- Runtime Support
- Reconfiguration Techniques (reusable artifacts)
- Simulations and Prototyping (performance analysis, verification tools)

All manuscripts will be reviewed by at least three members
of the program committee. Submissions should be a complete
manuscript or, in special cases, may be a summary of relevant
work. The manuscript should be not exceed 8 single-spaced,
double-column pages using 10-point size font on
8.5X11 inch pages (IEEE conference style) including
references, figures and tables. A submission link will be
provided on this site by November 2014. Submitted papers
should not have appeared in or be under consideration
for a different workshop, conference or journal.
It is also expected that all accepted papers (regular or poster)
will be presented at the workshop by one of the authors.

IEEE CS Press will publish the IPDPS symposium and workshop
abstracts as a printed volume.
The complete symposium and workshop proceedings will also be published
by IEEE CS Press as a CD-ROM disk and be available
in the IEEE Digital Library.

Submission deadline: January 6, 2015
Decision notification: February 1, 2015
Camera-Ready papers due: February 14, 2015

Start: May 25, 2015
End: May 25, 2015
Venue: Hyderabad, India

Call for Papers: Workshop on Large-Scale Parallel Processing

Submitted by Darren J. Kerbyson

Workshop on Large-Scale Parallel Processing
to be held in conjunction with
IEEE International Parallel and Distributed Processing Symposium
Hyderabed, India
May 25th, 2015

SUBMISSION DEADLINE: January 16th 2015

The workshop on Large-Scale Parallel Processing is a forum that
focuses on computer systems that utilize thousands of processors
and beyond. Large-scale systems, referred to by some as
extreme-scale and Ultra-scale, have many important research
aspects that need detailed examination in order for their
effective design, deployment, and utilization to take place.
These include handling the substantial increase in multi-core
on a chip, the ensuing interconnection hierarchy, communication,
and synchronization mechanisms. Increasingly this is becoming an
issue of co-design involving performance, power and reliability
aspects. The workshop aims to bring together researchers from
different communities working on challenging problems in this
area for a dynamic exchange of ideas. Work at early stages of
development as well as work that has been demonstrated in
practice is equally welcome.

Of particular interest are papers that identify and analyze novel
ideas rather than providing incremental advances in the following

- LARGE-SCALE SYSTEMS : exploiting parallelism at large-scale,
the coordination of large numbers of processing elements,
synchronization and communication at large-scale, programming
models and productivity

novel systems, the use of processors in memory (PIMS),
parallelism in emerging technologies, future trends.

- MULTI-CORE : utilization of increased parallelism on a single
chip (MPP on a chip such as the Cell and GPUs), the possible
integration of these into large-scale systems, and dealing with
the resulting hierarchical connectivity.

- MONITORING, ANALYSIS AND MODELING : tools and techniques for
gathering performance, power, thermal, reliability, and other
data from existing large scale systems, analyzing such data
offline or in real time for system tuning, and modeling of
similar factors in projected system installations.

- ENERGY MANAGEMENT: Techniques, strategies, and experiences
relating to the energy management and optimization of
large-scale systems.

- APPLICATIONS : novel algorithmic and application methods,
experiences in the design and use of applications that scale to
large-scales, overcoming of limitations, performance analysis
and insights gained.

- WAREHOUSE COMPUTING: dealing with the issues in advanced
datacenters that are increasingly moving from co-locating many
servers to having a large number of servers working cohesively,
impact of both software and hardware designs and optimizations
to achieve best cost-performance efficiency.

Results of both theoretical and practical significance will be
considered, as well as work that has demonstrated impact at
small-scale that will also affect large-scale systems. Work may
involve algorithms, languages, various types of models, or

Papers should not exceed eight single-space pages (including
figures, tables and references) using a 12-point font on 8.5×11
inch pages. Submissions in PostScript or PDF should be made
using EDAS ( Informal enquiries can be made to Submissions will be judged on correctness,
originality, technical strength, significance, presentation
quality and appropriateness. Submitted papers should not have
appeared in or under consideration for another venue.

Submission deadline: January 16th 2015
Notification of acceptance: February 14th 2015
Camera-Ready Papers due: February 28th 2015

Darren J. Kerbyson, Pacific Northwest National Laboratory
Ram Rajamony, IBMa Austin Research Lab
Charles Weems,University of Massachusetts

Johnnie Baker,Kent State University
Alex Jones, University of Pittsburgh
H.J. Siegel, Colorado State University
Guangming Tan, ICT, Chinese Academy of Sciences
Lixin Zhang, ICT, Chinese Academy of Sciences

Pavan Balaji, Argonne National Laboratory, USA
Kevin J. Barker, Pacific Northwest National Laboratory
Laura Carrington, San Diego Supercomputer Center, USA
I-Hsin Chung, IBM T.J. Watson Research Lab, USA
Tim German, Los Alamos National Laboratory, USA
Georg Hager, University of Erlangen, Germany
Simon Hammond, Sandia National Laboratory, USA
Martin Herbordt, Boston University, USA
Kalapriya Kannan, IBM Research, India
Daniel Katz, University of Chicago, USA
Celso Mendes, University of Illinois Urbana-Champagne
Bernd Mohr,Forschungszentrum Juelich, Germany
Ankur Narang, IBM Research, India
Phil Roth, Oak Ridge National Laboratory, USA
Jose Sancho, Barcelona Supercomputer Center, USA
Gerhard Wellein, University of Erlangen, Germany
Ulrike Yang, Lawrence Livermore National Laboratory, USA

Ankur Narang, IBM Research India

Kalapriya Kannan, IBM Research India

Start: May 25, 2015
End: May 29, 2015
Venue: Hyderabad

May 26, 2015

Call for Papers: SYSTOR 2015

Submitted by Doron Chen

The 8th ACM International Systems and Storage Conference (SYSTOR 2015)
Haifa, Israel
May 26-28, 2015

Paper submission deadline: March 5, 2015

SYSTOR has a broad scope, promoting experimental and practical computer
systems research encompassing the following topics:

- Operating systems, computer architecture, and their interactions
- Distributed, parallel, and cloud systems
- Networked, mobile, wireless, peer-to-peer, and sensor systems
- Runtime systems and compiler/programming-language support
- File and storage systems
- Security, privacy, and trust
- Virtualization
- Embedded and real-time systems
- Fault tolerance, reliability, and availability
- Deployment, usage, and experience
- Performance evaluation and workload characterization

- Full & short paper submission: March 5, 2015
- Highlights paper submission: April 30, 2015
- Paper notification: April 5, 2015
- Camera-ready submission: April 17, 2015
- Poster submission: April 30, 2015
- Poster notification: May 11, 2015

SYSTOR is a home for high-quality international systems research of a
practical nature and welcomes both academic and industrial contributions. We
solicit paper submissions in three separate categories:

- Full papers: should report original, previously unpublished high-
quality research, and be at most 10 pages of content, including everything
except references, which may use additional pages. The program committee
will review all submitted papers. Accepted papers will be presented at the
conference and included in the conference proceedings, to be published by
the ACM.

- Short papers: should report original, previously unpublished work for
which a full paper may not be suitable. Short paper submissions may report
on smaller ideas; unconventional ideas that are still in a preliminary stage
of development; interesting negative results; experimental (in)validation of
previous findings; controversial positions that challenge common wisdom; and
fresh approaches for addressing old problems. Short papers may be at most 5
pages, excluding references. They will undergo the same review process as
full papers. If accepted, short papers will be allocated a shorter talk slot
during the conference and will also be published in the conference

- Highlight papers: should contain exciting research results that have
been accepted to a recent top-tier systems conference or journal. A small
sub-committee will briefly review these submissions and will select the
most suitable ones for SYSTOR. The corresponding presentations will then be
“replayed” at SYSTOR for the benefit of the local community. A highlight
paper submission should include the full citation of the published or
accepted paper and a link to it. Accepted submissions will not be published
in the proceedings.

SYSTOR 2015 will host distinguished keynote speakers, a poster session, and
several social events at the conference. Our goal is to provide an excellent
forum for interaction across the systems community: international, academic,
and industrial, for both students and more established members.

Additional details can be found at:

Gernot Heiser (NICTA and UNSW, Australia)
Idit Keidar (Technion)

Dalit Naor (IBM Research)

David Breitgand (IBM Research)

Michael Factor (IBM Research)

Ethan Miller (University of California Santa Cruz)
Liuba Shrira (Brandeis University)
Dan Tsafrir (Technion)
Yaron Wolfsthal (IBM Research)
Erez Zadok (Stony Brook University)

Start: May 26, 2015
End: May 28, 2015
Venue: Haifa, Israel