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November 1, 2015

Call for Proposals: ISCA Workshops and Tutorials

Submitted by Boris Grot

Workshops and Tutorials at ISCA 2016
Seoul, Korea
June 18-19, Workshops and Tutorials
June 20-22, Main Conference


Please send workshop proposals to by December 14, 2015.
Proposers will be notified of workshop decisions by January 18, 2016.

All workshop proposals should include the following information:
- Title of the workshop
- Organizers and their affiliations
- Description of main objectives
- Sample call for papers, including the workshop’s main topics
- Expected duration of the workshop; i.e., 1/2 day, full day, or 2 days
- If the workshop has been held before, the location (i.e., which conference),
date, the number of published papers and attendees at the last occurrence



Please send tutorial proposals to by December 14, 2015.
Proposers will be notified of workshop decisions by January 18, 2016.

All tutorial proposals should include the following information:
- Title of the tutorial
- List of organizers and presenters, including their affiliations and short bios
- Abstract of the tutorial, including main objectives
- A list of topics to be covered, including format (e.g., talks, demos, etc),
target audience, and pre-requisite knowledge
- Expected duration of the tutorial (i.e., 1/2 day, full day, or 2 days)
- If the tutorial has been held before, the location (i.e., which conference),
date, the number of published papers and attendees at the last occurrence

Start: November 1, 2015
End: December 14, 2015

November 23, 2015

Call for Papers: VEE 2016

Submitted by Don Porter

12th ACM International Conference on Virtual Execution Environments (VEE’16)
co-located with ASPLOS 2016
Atlanta, Georgia, USA
April 2-3, 2016

- Abstract deadline: Monday, November 23, 2015 (11:59PM EST)
- Full paper deadline: Monday, November 30, 2015 (11:59pm, EST)
- Author response period: Tuesday-Wednesday, January 26-27, 2016
- Author notification: Friday, February 5, 2016
- Conference: Saturday-Sunday, April 2-3, 2016

Virtualization has a central role in modern systems. It constitutes a key
aspect in a wide range of environments, from small mobile computing devices to
large-scale data centers and computational clouds. Virtualization techniques
encompass the underlying hardware, the operating system, and the runtime
system. Although these layers have different design and implementation
techniques, the fundamental challenges and insights tend to be similar.

VEE’16 brings together researchers and practitioners from different computer
systems domains to interact and share ideas in order to advance the state of
the art of virtualization and broaden its applicability. VEE’16 accepts both
full-length and short papers. Both types of submissions are reviewed to the
same standards and differ primarily in the scope of the ideas expressed. Short
papers are limited to half the space of full-length papers. The program
committee will not accept a full paper on the condition that it is cut down to
fit in a short paper slot, nor will it invite short papers to be extended to
full length. Submissions will be considered only in the category in which they
are submitted.

We invite authors to submit original papers related to virtualization
across all layers of the software stack down to the microarchitectural
level. Topics of interest include (but are not limited to):
- virtualization support for programs and programmers;
- architecture support for virtualization;
- operating system support for virtualization;
- compiler and programming language support for virtualization;
- runtime system support for virtualization;
- virtual I/O, storage, and networking;
- memory management;
- managed runtimes and virtual machines;
- management technologies for virtual environments;
- performance analysis and debugging for virtual environments;
- security and virtual environments;
- virtualization in cloud computing;
- virtualization technologies applied to specific problem domains
- such as HPC, realtime, and power management.

General Chair:
Vishakha Gupta-Cledat (Intel Research)

Program Co-chairs:
Don Porter (Stony Brook University)
Vivek Sarkar (Rice University)

Program Committee:
Jonathan Appavoo, Boston University
Tzi-Cker Chieuh, Industrial Technology Research Institute, Taiwan
John Criswell, University of Rochester
Dilma Da Silva, Texas A&M University
Julian Dolby, IBM Thomas J. Watson Research Center
Bjoern Franke, University of Edinburgh
Soo-Mook Moon, Seoul National University
Guilherme Ottoni, Facebook
Kevin Pedretti, Sandia National Laboratories
Don Porter, Stony Brook University (co-chair)
Behnam Robatmili, Qualcomm Research
Chris Rossbach, VMware Research and The University of Texas at Austin
Vivek Sarkar, Rice University (co-chair)
Mark Silberstein, Technion—Israel Institute of Technology
Mary Lou Soffa, University of Virginia
Malgorzata Steinder, IBM Research
Priyanka Tembey, VMware
Peng Wu, Huawei America Lab

Start: November 23, 2015
End: November 30, 2015
Venue: Atlanta, GA

December 5, 2015

Call for Workshops and Tutorials at MICRO 2015 (submission deadline: July 10)

Submitted by Bipin Rajendran

Workshops and Tutorials at MICRO-48
Waikiki, Hawaii, USA
Dec 5-6, 2015

Submission Deadline: July 10, 2015
Notification Date: July 17, 2015

Proposals should be one to two pages and must include the following
1. Title of the Workshop / Tutorial
2. Organizers and their affiliations (including short bios)
3. Expected duration of the workshop/tutorial; i.e., half day or full day
4. If the workshop/tutorial was previously held, provide the location
(i.e., which conference), date, number of published papers (if any), and
number of attendees at the last event
5. If workshop proposal, provide sample call for papers, including the
workshop main topics
6. If tutorial proposal, provide the abstract of the tutorial

Submit workshop proposal (1 to 2 pages) to Aamer Jaleel
Submit tutorial proposal (1 to 2 pages) to Christopher Hughes

Start: December 5, 2015
End: December 6, 2015
Venue: Waikiki, Hawaii, USA

Call for Papers: 1st GPU Warp/Wavefront Scheduling Championship

Submitted by Adwait Jog

1st GPU Warp/Wavefront Scheduling Championship (GPU-WSC)
in conjunction with MICRO 2015
Waikiki, Hawaii
December 5 or 6, 2015

The workshop on computer architecture competitions is a forum for holding
contests to evaluate computer architecture research topics. This workshop
is organized around a competition for scheduling algorithms for Graphics
Processing Units (GPUs). This 1st GPU Warp/Wavefront Scheduling Championship
(GPU-WSC) invites contestants to submit their GPU scheduler design to
participate in this competition. The contestants must develop algorithms to
optimize multiple metrics (e.g., IPC, cache miss-rates, memory bandwidth
utilization, hardware overheads etc.) on a common evaluation framework
provided by the organizing committee.

Phase-1 Submission: Oct 5, 2015
Notification of Acceptance for Phase 1: Nov 2, 2015
Phase-2 Submission: Nov 16, 2015.
Championship Dates: Dec 5 or Dec 6, 2015

There are two following phases in the entire championship process:

Phase 1
1) Write-up Submission:
Interested participants are invited to submit a write-up describing
their GPU Warp scheduler design. This write-up must clearly
demonstrate the idea, motivation, design trade-offs, and estimate the
hardware overheads of their proposed scheduler. In addition, write-up
should provide details on the evaluation methodology and impact of
their proposed scheduler on four metrics: 1) IPC, 2) L1 miss-rates
(all three caches: data, texture, constant), 3) L2 miss-rates, and 4)
DRAM bandwidth utilization, in comparison to the Greedy-then-Oldest
(GTO) GPU Warp Scheduler. The comparison results should be described
in the paper with the help of clearly visible graphs. Please use
GPGPU-Sim (Version 3.2.2). — open-source GPU evaluation platform.
More details are on the championship website.

Note that, the primary metric to rank schedulers is performance (IPC).
In case performance of two schedulers are fairly close, we will use
secondary metrics such as miss-rates, bandwidth utilization, and
hardware overheads for breaking the ties.

The Program Committee chaired by the organizers will review the
submitted write-ups. The submission will be evaluated based on the
novelty, presentation of the results, and effectiveness of the
proposed scheduler on different metrics. Novelty is not a strict
requirement, for example, a contestant may submit his/her previously
published design or make incremental enhancements to a previously
proposed design.

2) File Submission:
The authors are required to submit source code, configuration files,
output result files (dump the simulator output to a file), and a diff
of your code with the unmodified GPGPU-Sim version 3.2.2.

Phase 2
The authors of the accepted write-ups will be required to submit their
final write-ups along with the updated files. In this phase, authors
have an option to incrementally revise their scheduler design to
become more competitive. We expect these changes to be only related to
some optimizations with regard to their scheduler design. A complete
change in the scheduler design is not acceptable.

1) Evaluation of Schedulers
The submitted files will be tested by the organizers on the
applications recommended by us (see Simulation Infrastructure section
below). The organizers also plan to include some applications in the
testing set that may not be known apriori to the contestants. The
final ranking of the schedulers will be based on performance (IPC). In
case performance of two schedulers are fairly close, we will use
secondary metrics such as miss-rates, bandwidth utilization, and
hardware overheads for breaking the ties.

2) Incentives
The winner(s) will receive a trophy commemorating his/her triumph (OR
some other prize to be determined later). Authors of all the accepted
write-ups will also be invited to present their papers at the
workshop. All source code, final write-ups, and ranking results will
be made publicly available through this website.

Please use GPGPU-Sim (Version 3.2.2). — open-source GPU evaluation
platform. More details are on the championship website.

Phase-1 Submission: Please use the standard LaTeX or Word ACM
templates. Write-up length should not exceed 6 pages. Email your
write-up to all the organizers by the Phase-1 deadline. Also,
submission of files is mandatory.

Phase-2 Submission: Please use the standard LaTeX or Word ACM
templates. Final Write-up length should not exceed 8 pages. Email your
final write-up to all the organizers by the Phase-2 deadline.

Workshop chairs:
Adwait Jog, College of William and Mary (Email:
Onur Kayiran, AMD Research (Email:
Tim Rogers, Purdue (Email:

Program Committee:

Steering Committee:
Alaa R. Alameldeen (Intel)
Hyesoon Kim (Georgia Tech)
Moin Qureshi (Georgia Tech)

Please contact the organizers with regard to any questions regarding
the championship.

Start: December 5, 2015
End: December 6, 2015
Venue: MICRO 2015, Waikiki, Hawaii

Call for Papers: 3rd Workshop on Near-Data Processing

Submitted by Boris Grot

3rd Workshop on Near-Data Processing (WoNDP)
in conjunction with MICRO’15
Waikiki, Hawaii, USA
December 5 or 6, 2015

Computing in large-scale systems is shifting away from the traditional
compute-centric model successfully used for many decades into one that is much
more data-centric. This transition is driven by the evolving nature of what
computing comprises, no longer dominated by the execution of arithmetic and
logic calculations but instead becoming dominated by large data volume and the
cost of moving data to the locations where computations are performed. Data
movement impacts performance, power efficiency and reliability, three
fundamental components of a system. These trends are leading to changes in the
computing paradigm, in particular the notion of moving computation to the data
in a so-called Near-Data Processing approach, which seeks to perform
computations in the most appropriate location depending on where data resides
and what needs to be extracted from that data. Examples already exist in
systems that perform some computations closer to disk storage, leveraging the
data streaming coming from the disks, filtering the data so that only useful
items are transferred for processing in other parts of the system.
Conceptually, the same principle can be applied throughout a system, by placing
computing resources close to where data is located, and decomposing
applications so that they can leverage such a distributed and potentially
heterogeneous computing infrastructure.

This workshop is intended to bring together experts from academia and industry
to share advances in the development of Near-Data Processing systems
principles, with emphasis on large-scale systems. This is the 3rd edition of
this workshop. The first two editions were held at MICRO 2013 and 2014, and had
over 60 attendees each. The workshop will consist of submitted papers and
invited talks. Topics of interest include but are not limited to

- Analysis of applications illustrating the potential for Near-Data Processing
- System and software architectures for Near-Data Processing
- Programming models for distributed and heterogeneous infrastructures, driven
by location of the data
- Processing/Memory/Storage architectures and microarchitectures for Near-Data
- Performance evaluation of Near-Data Processing systems and subsystems
- Power-efficiency and reliability analysis and evaluation of Near-Data

Two kinds of papers are invited:
1) Technical papers (4-6 pages) with preliminary results.
2) Position papers (3 pages max) on directions for research and development.
Please submit an electronic copy of your paper (in PDF) in two column format
with at least 10pt font. Blind submissions are optional. The selected papers
will be made available online. Publication in WoNDP does not preclude later
publication at regular conferences or journals.

Paper submissions due: October 9, 2015
Notification: November 6th, 2015
Final Paper Due: December 1st, 2015

Rajeev Balasubramonian, University of Utah
Boris Grot, University of Edinburgh
Jaime Moreno, IBM TJ Watson Research Center
Ravi Nair, IBM TJ Watson Research Center

Start: December 5, 2015
End: December 5, 2015

Call for Participation: Tutorial on Building Online Power Models from Real Data

Submitted by Stephan Diestelhorst

Building Online Power Models from Real Data
held at MICRO 2015
Waikiki, Hawaii
December 5, 2015

In this hands-on, interactive tutorial, you will learn how to efficiently
build accurate, run-time power models using real hardware platforms using a
specially built software tool. Starting from the basics of how power is
consumed in a modern system-on-chip through static and dynamic power in the
underlying transistors, we show how activity, voltage and frequency affect the
power consumption.

We will then let you play with a board that we have prepared to be easy to
work with and walk you through practicalities, such as workload selection and
how to get activity information. With the basics from the first section, you
will be able to build your own power model for the test platform quickly.

Once you have built a simple power model for your test board, we will
introduce a surprise workload which we will then use to put the generated
power models through a real-life test: running a workload that was not
anticipated at model construction time. We will even give out prizes for
the ones closest to the real power consumption.

Start: December 5, 2015
End: December 5, 2015
Venue: Waikiki, Hawaii

December 6, 2015

Call for Papers: NoCArc 2015

Submitted by Maurizio Palesi

8th International Workshop on Network on Chip Architectures
in conjunction with IEEE/ACM MICRO-48
Waikiki, Hawaii
December 6, 2015

The goal of NoCArc workshop is to provide a forum for researchers to present
and discuss innovative ideas and solutions related to design and implementation
of multi-core systems on chip. The workshop will focus on issues related to
design, analysis and testing of on-chip networks. The topics of interest for the
workshop include, but are not limited to:

NoC Architecture and Implementation
- Topologies, routing, flow control
- Managing QoS
- Timing, synchronous/asynchronous communication
- Reliability issues
- Design methodologies and tools
- Signaling & circuit design for NoC links
- NoC Analysis and Verification

Power, energy and thermal issues
- Benchmarking and experience with NoC-based systems
- Modeling, simulation, and synthesis
- Verification, debug and test
- Metrics and benchmarks
- NoC Application

Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems
- On-Chip Communication Optimization

Communication efficient algorithms
- Multi/many-core communication workload characterization and
- Energy efficient NoCs and energy minimization
- NoC at System-level

Design of memory subsystem
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and
novel programming models
- Issues related to large-scale systems (datacenters, supercomputers)
with NoC-based systems as building blocks

Emerging NoC Technologies
- Wireless, Optical, and RF
- NoCs for 3D and 2.5D packages

Besides regular papers, papers describing work in progress or
incomplete but sound new innovative ideas related to the workshop
theme are also encouraged.

Both research and application-oriented papers are welcome. All papers
should be submitted electronically by EasyChair. Papers must be in PDF
format and should include title, authors and affiliation, e-mail
address of the contact author. Additional information at

- Abstract submission deadline: September 1, 2015
- Paper submission deadline: September 8, 2015
- Acceptance notification: October 7, 2015
- Camera-ready version due: October 18, 2015

General chairs:
- Maurizio Palesi, Kore University, Italy
- Masoud Daneshtalab, Univ. of Turku, Finland and KTH, Sweden
- Xiaohang Wang, South China University of Technology, China

TPC chairs:
- Masoumeh Ebrahimi, Univ. of Turku, Finland
- Riccardo Locatelli, STMicroelectronics

Start: December 6, 2015
End: December 6, 2015
Venue: Waikiki, Hawaii

Call for Papers: Workshop on Negative Outcomes, Post-mortems, and Experiences

Submitted by Svilen Kanev

Workshop on Negative Outcomes, Post-mortems, and Experiences
in conjunction with MICRO’15
December 6, 2015
Waikiki, Hawaii, USA

Not all research projects end up with positive results. Sometimes ideas that
sound enticing at first run into unexpected complexity, high overheads, or turn
out simply infeasible. Such projects often end up in a proverbial researcher’s
drawer, and the community as a whole is not aware of dead-end or
hard-to-advance research directions. NOPE is a venue that encourages publishing
such results in all their “badness”.

Submission deadline: November 2, 2015

More details at

Start: December 6, 2015
End: December 6, 2015
Venue: Waikiki, Hawaii

Call for Participation: CWWMCA 2015

Submitted by Min LI

Career Workshop for Women and Minorities in Computer Architecture (CWWMCA 2015)
in conjunction with MICRO 2015
Waikiki, Hawaii, USA
December 6, 2015

The CWWMCA Workshop brings together women and under-represented minorities
in academia, industry, and government to promote the recruitment, retention and
progression of women and under-represented groups with research interests in
computer architecture.

The workshop highlights emerging and hot topics in computer architecture, and
provides opportunities for cross-disciplinary research, networking, and career
advice. The program includes a mix of technical presentations and panel
sessions by academic and industry leaders, as well as informal activities to
provide mentoring for students as they get started in their careers. The
workshop also includes a research poster session.

The workshop is generously sponsored by NSF, ACM SIGMICRO, IBM Research
and the MICRO conference.

Thanks to our sponsors, this workshop will be free of charge for the
participating  target demographic of women and minority participants
under-represented in our field, and they will be directly reimbursed for
their registration fees.

Travel grants are available for students and junior faculty/researchers.

For any questions, please contact us at

Start: December 6, 2015
End: December 9, 2015
Venue: Waikiki, Hawaii

December 14, 2015

Call for Papers: Workshop on Low-Power Dependable Computing

Submitted by Abdullah Muzahid

2nd Workshop on Low-Power Dependable Computing (LPDC)
in conjunction with International Green and Sustainable Computing Conference (IGSC)
Las Vegas, Nevada, USA
Dec 14-16, 2015

Submission Deadline: Sept. 15, 2015

Dependable computing is normally achieved through various redundancy (such
as modular, temporal and/or information) techniques at different levels (for
instance, circuit, architecture, runtime, operating systems and software) in
the systems. With the scaled technology size and miniaturization of computing
systems, faults will become more common and it is imperative for most modern
computing systems to deploy various fault-tolerance techniques. On the other
hand, redundancy based fault-tolerance generally has energy implications, which
warrants careful consideration since energy has been promoted to be the
first-class system resource recently.

This workshop aims at establishing a forum for practitioners and researchers
from both industry and academia who work on different aspects of fault
tolerance and system energy efficiency to exchange ideas on how to achieve
low-power dependable computing. To cover a broad range of research related to
energy efficiency and dependable computing, the workshop will consider various
levels (from circuits to software), components (from memory to computation) and
systems (from battery-powered embedded systems to large scale reliable

The topics of interest include (but are not limited to) the following:
- Novel energy-efficient redundant circuit design
- Novel energy-efficient fault-tolerance architecture
- Compilation techniques for redundancy and low-power
- Runtime management for energy-efficiency and fault tolerance
- Scheduling algorithms for energy-efficiency and fault tolerance
- Energy-efficiency tradeoffs for different fault-tolerance techniques
- Low-power reliable memory and storage systems
- Low-power and reliable on-chip communications
- Case study on low-power dependable systems

The workshop invites authors to submit papers in the above mentioned areas that
describe original and unpublished work that are not concurrently under review

The papers submitted to this workshop is limited to be six (6) single-spaced,
double-column pages (with IEEE Computer Society Proceedings Manuscripts style:
11-point fonts and 8.5 x 11 inch), which should include everything (e.g.,
abstract, research description, figures, tables, and references).

All submissions will be reviewed by the program committee. Once a submission
is accepted, at least one author needs to register the conference following the
instructions on IGSC webpage (, and attends the
conference to present the work. Each accepted workshop paper will require a
full IGSC registration at the IEEE member or at the non-member rate (NOT
student rate).

Accepted papers will be published in the workshop proceedings and included in
the IEEE Xplore Digital Library.

Please submit your papers through the following link with EasyChair:

Submission deadline: Aug. 28, 2015
Notification date: Sep. 30, 2015
Final paper due: Oct. 15, 2015

Workshop Chairs:
Tam Chantem (Utah State University, USA)
Dakai Zhu (University of Texas at San Antonio, USA)

Technical Program Committee:
Jian-Jia Chen (TU Dortmund, Germany)
Steven Drager (Air Force Research Lab, USA)
Petru Eles (Linköping University, Sweden)
Alireza Ejlali (Sharif University of Technology, Iran)
Nathan Fisher (Wayne State University, USA)
Yifeng Guo (NetApp. Inc., USA)
Song Han (University of Connecticut, USA)
Houman Homayoun (George Mason University, USA)
Cong Liu (University of Texas at Dallas, USA)
Muhammad Shafique (Karlsruhe Institute of Technology, Germany)
Kaijie Wu (Chongqing University, China)
Xuan Qi (Oracle, USA)
Jun Yi (Amazon, USA)
Zhao Zhang (Iowa State University, USA)
Baoxian Zhao (MicroStrategy Inc, USA)

Start: December 14, 2015
End: December 16, 2015
Venue: Las Vegas