Call for Nominations: 2016 IEEE TCCA Young Computer Architect Award

Submitted by Kunle Olukotun

Submitted by Kunle Olukotun

The 2016 IEEE TCCA Young Computer Architect Award

Nomination deadline: April 15, 2016
 

The IEEE TCCA Young Computer Architect Award recognizes outstanding research
contributions by an individual in the field of Computer Architecture, who
received his/her PhD degree within the last 6 years. The Award will be
presented at the Awards Banquet at the 2016 International Symposium on
Computer Architecture (ISCA). The IEEE Computer Society administers the award.

Eligibility: The award is open to any individual who has completed his/her PhD
degree after April 15, 2010 (within last 6 years). At the discretion of the
awards committee, eligibility may be adjusted for documented family-related or
medical leaves from employment. The winner of the award will be someone who
has made an outstanding, innovative research contribution or contributions to
the field of Computer Architecture.

NOMINATION PROCESS:
Anyone can nominate a candidate (but no self-nominations). The following
information must be provided at the time of nomination:

1. Name/email of person making the nomination.

2. Name/email of candidate for whom the award is recommended.

3. A statement by the nominator (maximum of 500 words long) as to why
the nominee deserves the award. As the award is for outstanding contributions
in research, the statement and supporting letters should address the
contributions and why they are both outstanding and significant.

4. CV of the candidate.

5. The names and email addresses of two persons who the nominator has
contacted to supply supporting letters.

All materials, including the two supporting letters, should be sent to the Chair
of the Selection Committee by April 15, 2016. The award will be presented at
the Awards Banquet of the 43rd International Symposium on Computer
Architecture (ISCA) in Seoul, Korea, June 18-22, 2016.

SELECTION COMMITTEE:
Lieven Eeckhout (Ghent University)
Onur Mutlu (Carnegie Mellon University)
Kunle Olukotun (Stanford University) – Chair (kunle@stanford.edu)

PAST WINNERS:
2015: Prof. Ronald Dreslinski, The University of Michigan, in recognition of
outstanding research contributions in computer architectures for emerging
low-power circuit techniques

2014: Prof. Engin Ipek, The University of Rochester, in recognition of
outstanding research contributions for computer architectures that leverage
emerging technologies

2013: Prof. Luis Ceze, The University of Washington, in recognition of
outstanding research contributions for improving multi-core programmability
and correctness

2012: Prof. Karthikeyan Sankaralingam, The University of Wisconsin, in
recognition of outstanding contributions in the field of computer architecture
in both research and education

2011: Prof. Onur Mutlu, Carnegie Mellon University, in recognition of
outstanding contributions in the field of computer architecture in both
research and education

Available Now: IEEE Micro Special Issue on Near-Data Processing

Submitted by Lieven Eeckhout
http://online.qmags.com/MIC0116?sessionID=6D82D319BF01A05D0C8C0796A&cid=3196036&eid=19756#pg1&mode2

Submitted by Lieven Eeckhout
http://online.qmags.com/MIC0116?sessionID=6D82D319BF01A05D0C8C0796A&cid=3196036&eid=19756#pg1&mode2
IEEE Micro Special Issue on Near-Data Processing

The Jan/Feb 2016 IEEE Micro Special Issue on Near-Data Processing,
guest edited by Rajeev Balasubramonian (University of Utah) and Boris Grot
(University of Edinburgh), is now available. The issue includes expert opinions
and position statements on near-data processing along with in-depth articles.
The issue also features two testimonials on MICRO Test-of-Time Awards.

Call for Nominations: ACM SIGARCH Distinguished Service Award

Submitted by Natalie Enright Jerger
http://www.sigarch.org/awards/acm-sigarch-distinguished-service-award/

Submitted by Natalie Enright Jerger
http://www.sigarch.org/awards/acm-sigarch-distinguished-service-award/

ACM SIGARCH Distinguished Service Award

Nomination Deadline: April 8, 2016
 

This annual award is presented to an individual who has contributed important service to the computer architecture community.

Recipients receive a memento engraved with their name along with a $1000 honorarium. The award is presented by the SIGARCH chair at ISCA during ISCA’s award presentation session. The award recipient also receives up to $2000 towards support for travel costs, including airfare, hotel, and conference registration for ISCA. The recipient is listed with a citation for their award on the SIGARCH Distinguished Service Award web page. The list of past award
recipients is at http://www.sigarch.org/awards/acm-sigarch-distinguished-award-past-winners/

The selection committee consists of 3 or more members and is appointed by the
SIGARCH chair. The committee typically includes recent recipients of the award
and current SIGARCH executive committee members. The committee solicits
nominations from the computer architecture community in a variety of ways
including announcements in SIGARCH’s newsletter and postings on appropriate
newsgroups and websites. The committee considers all external nominations, plus
any internal nominations from members of the committee, in the context of the
nominees’ specific and general service contributions to the computer
architecture community.

NOMINATION PROCESS:

Nominations can be submitted at any time to the committee chair (Norm Jouppi,
jouppi@acm.org). Nominations submitted by April 8th will be considered for this
year’s award. A nomination for the distinguished service award that is not
awarded will remain valid for 3 years.

Each nomination should consist of the following items:
– Name, address, phone number, and email address of the person making the
nomination (the nominator).
– Name, address, phone number, and email address of the candidate for whom
an award is recommended (the nominee).
– A short statement (200-500 words) explaining why the nominee deserves the
award in question.
– Names and email addresses of 4-7 people who the nominator believes will
support the nomination.
– The awards committee will ask some of these people for their opinions.

Self-nominations are not allowed.

The 2016 selection committee is:
– Norman P. Jouppi (chair), Google, jouppi@acm.org
– Trevor Mudge,
 University of Michigan, 
tnm@eecs.umich.edu
– David Brooks,
 Harvard University, dbrooks@eecs.harvard.edu

Call for Papers: IEEE Micro General Interest 2016

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/2016-cfp—general-interest-papers

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/2016-cfp—general-interest-papers

IEEE Micro General Interest 2016

IEEE Micro seeks general-interest submissions for publication in upcoming 2016
issues. The submissions should present the design, performance, or application
of microcomputer and microprocessor systems. Summaries of work in progress
and descriptions of recently completed work are most welcome, as are tutorials
and position statements.

IEEE Micro is a bimonthly magazine of the IEEE Computer Society that reaches
an international audience of computer designers, system integrators, and users.
IEEE Micro publishes 6 to 8-page papers that are slightly less technical and
less quantitative than top-conference and archival journal papers, while being
insightful, slightly more qualitative, with a high tutorial value, and up to
date with current trends. IEEE Micro attracts a broad readership among both
academics and practitioners who want to keep up with new results and trends in
the field of computer architecture.

Areas of interest include, but are not limited to:
– Processor, memory, and storage systems architecture
– Parallel and multicore systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Heterogeneous and accelerator-based architectures
– Neuromorphic computing architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems
– Design of high-performance and low-power chips

SUBMISSION PROCEDURE:
Log onto IEEE CS Manuscript Central (https://mc.manuscriptcentral.com/micro-cs)
and submit your manuscript. Please direct questions to the IEEE Micro magazine
assistant (micro-­ma@computer.org) regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and PDF.
Manuscripts should not exceed 5,000 words including references, with each
average­ size figure counting as 250 words and each average-size table counting
as 150 words toward this limit. Please include all figures and tables, as well
as a cover page with author contact information (name, postal address, phone,
fax, and e­mail address) and a 200­-word abstract. Submitted manuscripts must
not have been previously published or currently submitted for publication
elsewhere, and all manuscripts must be cleared for publication. All previously
published papers must have at least 30% new content compared to any
conference (or other) publication. Accepted articles will be edited for
structure, style, clarity, and readability. For more information, please visit the
IEEE Micro Author Center (http://www2.computer.org/portal/web/peerreviewmagazines/acmicro).

The submission site is continuously open. Papers of general interest appear in
upcoming issues as space allows, or are grouped in the Nov/Dec 2016 issue.

Questions?
Contact the Editor-in-Chief, Lieven Eeckhout, at lieven.eeckhout@ugent.be

Call for Participation: OpenPiton Tutorial

Submitted by David Wentzlaff
http://parallel.princeton.edu/openpiton/ISCA16_tutorial.html

Submitted by David Wentzlaff
http://parallel.princeton.edu/openpiton/ISCA16_tutorial.html

OpenPiton Tutorial
co-located with ISCA 2016
Seoul, S. Korea
June 19, 2016
 

This tutorial will introduce the user to OpenPiton including how to use the
framework to build different designs. The tutorial will introduce the
verification framework (Verilog simulation), how to synthesize an OpenPiton
processor for a Xilinx FPGA board, it will demonstrate booting Linux on an
FPGA version of OpenPiton, it will familiarize users with how to use the
OpenPiton framework to target an ASIC tapeout, and it will show users how to
configure and extend the OpenPiton architecture to enable architecture
research. This tutorial will be hands-on so please bring a laptop.

OpenPiton is an open source framework designed to enable scalable architecture
research prototypes from 1 core to 500 million cores. OpenPiton is the
world’s first open source, general-purpose, multithreaded manycore processor
and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core
with modifications and builds upon it with a scratch-built, scalable uncore
creating a flexible, modern manycore design. In addition, OpenPiton provides
synthesis and backend scripts for ASIC and FPGA to enable other researchers to
bring their designs to implementation. On FPGA, OpenPiton provides a new high
performance memory controller. OpenPiton provides a complete verification
infrastructure of over 8000 tests, is supported by mature software tools, runs
full-stack multiuser Debian Linux, and is written in industry standard
Verilog. Multiple implementations of OpenPiton have been created including a
taped-out 25-core implementation in IBM’s 32nm process and multiple Xilinx
FPGA prototypes.

Available Now: Datacenter Design and Management (Book)

Submitted by Brent Beckley
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=910

Submitted by Brent Beckley
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=910

Datacenter Design and Management

An era of big data demands datacenters, which house the computing
infrastructure that translates raw data into valuable information. This book
defines datacenters broadly, as large distributed systems that perform
parallel computation for diverse users. These systems exist in multiple forms
(private and public) and are built at multiple scales. Datacenter design and
management is multifaceted, requiring the simultaneous pursuit of multiple
objectives. Performance, efficiency, and fairness are first-order design and
management objectives, which can each be viewed from several perspectives.
This book surveys datacenter research from a computer architect’s perspective,
addressing challenges in applications, design, management, server simulation,
and system simulation.

Call For Submissions: Championship Branch Prediction Competition

Submitted by Ronald Dreslinski
http://www.jilp.org/cbp2016/

Submitted by Ronald Dreslinski
http://www.jilp.org/cbp2016/

Championship Branch Prediction Competition
co-located with ISCA 2016
Seoul, South Korea
June 19, 2016
 

The workshop on computer architecture competitions is a forum for holding
competitions to evaluate computer architecture research topics. The fifth
JWAC workshop is organized around a competition for branch prediction
algorithms. The Championship Branch Prediction (CBP) invites contestants
to submit their branch prediction code to participate in this competition.
Contestants will be given a fixed storage budget to implement their best
predictors on a common evaluation framework provided by the organizing
committee. Please see the website for more information.

Submissions Due: May 6, 2016.

Call for Papers: IEEE Micro Special Issue on Security

Submitted by jayvant anantpur

Submitted by jayvant anantpur

IEEE Micro Special Issue on Security

Guest Co-Editors:
Mohit Tiwari, The University of Texas at Austin
Todd Austin: University of Michigan, Ann Arbor

Submissions due: Feb 26, 2016
Publication date: Sept/Oct 2016

Secure, networked systems are the foundation on which the future
healthcare, finances, automotives, and other intelligent services will rest.
Currently deployed systems, from implanted medical devices to voting
machines to mobile phones and data centers, have all been shown to be
vulnerable, and new architectures are required to construct a trustworthy
computing infrastructure.

This Special Issue on Security seeks papers on a range of topics, including but
not limited to:

– Isolation and Access control, Virtualization
– Capabilities
– Information flow control
– Cryptographic primitives
– Side channel and physical access (power, EM, etc.) attacks and defenses
– Attestation and trusted/tamper-proof execution, enclaves, etc.
– Malware detection
– Network processors and deep packet analysis
– Accelerators for security analytics
– Introspection, debugging, root cause analysis
– Secure storage, e.g. using emerging non-volatile memories
– Programming languages and formal design tools for secure architectures
– Metrics and evaluation methodologies for secure architectures
– Secure architectures for domains such as voting machines, medical devices,
automotives, high assurance embedded systems, data centers, and IoT

IMPORTANT DATES:
Initial submissions due: Feb 26, 2016
Initial notifications: April 29, 2016
Revised papers due: May 20, 2016
Final notifications: June 10, 2016
Final versions due: June 24, 2016
Publication date: Sept/Oct 2016

SUBMISSION PROCEDURE:
Log onto IEEE CS Manuscript Central (https://mc.manuscriptcentral.com/micro-cs)
and submit your manuscript. Please direct questions to the IEEE Micro magazine
assistant (micro­-ma@computer.org) regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and PDF.
Manuscripts should not exceed 5,000 words including references, with each
average­-size figure counting as 250 words toward this limit. Please include
all figures and tables, as well as a cover page with author contact information
(name, postal address, phone, fax, and e­mail address) and a 200­-word
abstract. Submitted manuscripts must not have been previously published or
currently submitted for publication elsewhere, and all manuscripts must be
cleared for publication. All previously published papers must have at least 30%
new content compared to any conference (or other) publication. Accepted
articles will be edited for structure, style, clarity, and readability. For
more information, please visit the IEEE Micro Author Center.
(http://www2.computer.org/portal/web/peerreviewmagazines/acmicro).

Questions: Please contact Guest co-Editors Mohit Tiwari
(tiwari@austin.utexas.edu) and Todd Austin (austin@umich.edu), or
Editor-in-Chief Lieven Eeckhout (lieven.eeckhout@ugent.be).

Call for Nominations: ACM SIGARCH Maurice Wilkes Award 2016

Submitted by Margaret Martonosi
http://www.sigarch.org/awards/acm-sigarch-maurice-wilkes-award/

Submitted by Margaret Martonosi
http://www.sigarch.org/awards/acm-sigarch-maurice-wilkes-award/

ACM SIGARCH Maurice Wilkes Award

DEADLINE: MARCH 15, 2016

The award of $2,500 is given annually for an outstanding contribution to
computer architecture made by an individual whose computer-related
professional career (graduate school or full-time employment, whichever began
first) started no earlier than January 1st of the year that is 20 years prior
to the year of the award (At the discretion of the SIGARCH Executive
Committee, eligibility may be adjusted for documented family-related or
medical leaves from employment. Questions about eligibility should be directed
to the SIGARCH Chair (chair_sigarch@acm.org).)

The award is presented annually at the International Symposium on Computer
Architecture Awards Banquet. This year’s recipient will be invited to accept
the award at ISCA 2016.

Nominations should consist of:
1) Name, address, and phone number of person making the nomination.
2) Name and address of candidate for whom the award is recommended.
3) A statement (between 200 and 500 words long) as to why the candidate
deserves the award. Note that since the award is for an outstanding
contribution, the statement and supporting letters should address what the
contribution is and why it is both outstanding and significant.
4) The name(s) and email address(es) or telephone number(s) of others who
agree with the recommendation. Supporting letters from such persons are
useful but not required.
5) A statement regarding the nominee’s specific year of eligibility. That is,
when did they begin their computer-related professional career, and are there
any circumstances for which the 20 years of eligibility should be adjusted?

Please send nominations (preferably electronically) no later than March 15,
2016 to the Chair of the Nominating Committee (martonosi@princeton.edu).

CURRENT AWARDS COMMITTEE:
Margaret Martonosi (chair), Princeton University
Per Stenstrom, Chalmers University of Technology
Babak Falsafi, Ecole Polytechnique Federal de Lausanne

Available Now: IEEE Micro Nov/Dec 2015 Issue

Submitted by Lieven Eeckhout
http://online.qmags.com/MIC1115?sessionID=9DC1CCB1BF00902729BDA8702&cid=3241589&eid=19656#pg1&mode2

Submitted by Lieven Eeckhout
http://online.qmags.com/MIC1115?sessionID=9DC1CCB1BF00902729BDA8702&cid=3241589&eid=19656#pg1&mode2

IEEE Micro’s Nov/Dec 2015 issue is available, and features a number of papers
on a variety of topics, ranging from simulation methodology, reliability,
interconnection networks, to FPGA architectures. The issue also includes two
papers from Cool Chips on an IoT ultra-low-power microcontroller, and a open
framework for studying autonomous vehicles.