Call for Papers: NVMSA 2016

Submitted by Onur Mutlu
https://sites.google.com/a/camelab.org/nvmsa-2016/
April 1, 2016

Submitted by Onur Mutlu
https://sites.google.com/a/camelab.org/nvmsa-2016/

The 4th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)
Daegu, Korea
August 17-19, 2016
 

IMPORTANT DATES:
April 1: Abstract Submission Deadline
April 14: Paper Submission Deadline
June 1: Acceptance notification
June 12: Camera ready
 

Non-Volatile memory (NVM) technologies have demonstrated great potential to
improve many aspects of present and future memory hierarchies, offering high
integration density, larger capacity, zero standby power and good resilience
to soft errors. The recent research progress of various NVMs, e.g., NAND
flash, PCM, STT-RAM, RRAM, FeRAM, etc., have drawn tremendous attentions from
both academia and industry. Besides developing robust and scalable devices,
the unique characteristics of these NVM technologies, such as read-write
asymmetry, stochastic programming behavior, performance-power-nonvolatility
tradeoff, etc., introduce plenty of opportunities and challenges for novel
circuit designs, architectures, system organizations, and management
strategies. There is an urgent need for technology invention, modeling,
analysis, design and application of these NVMs ranging from circuit design to
system design levels.

IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) provides a
fantastic opportunity for global nonvolatile memory researchers from different
communities to discuss and exchange knowledge, ideas, and insights, and to
facilitate the establishment of potential collaborations that can speed up the
progress in the design and application of NVMs. An expanded technical program
will be offered in NVMSA 2016 for the audience from academy and industry. The
organizing committee is soliciting papers on various topics related to NVMs
including (but not limited to):

Device/Circuit design of NVMs
– Emerging Non-volatile Memory Circuit Design
– NVM Device Design
– Error correction for NVMs
– Nonvolatile Logic Circuit Design

NVM Architectures and Systems
– Non-volatile Registers
– Non-volatile Memory Architectures
– Non-volatile Cache Design
– NVM-based Neuromorphic Architectures
– NVM-based Storage

NVM Software
– Operating System Support for NVM
– Compiler Optimization for NVM
– NVM-based File Systems
– NVM-based Storage Software
– NVM-based Databases
– NVM Controller Design

NVM Applications
– In-memory Computing
– NVM for Big Data Analytics
– NVM in Mobile Healthcare Applications
– NVM in Wearable Applications
– NVM and the Internet of Things

The topics of NVMSA cover the research and development advances in both
mainstream and emerging NVMs. The event is designed to foster interaction and
presentation of early results, new ideas and speculative directions. Thus,
NVMSA will combine the presentations of the papers accepted from the regular
submissions as well as a number of invited talks from researchers in academia,
technologists from industry, and case studies on the use of NVMs.
Participating authors are invited to submit six-page manuscripts to the
conference. All accepted papers will be published in the conference
proceedings. Conference content will be submitted for inclusion into IEEE
Xplore as well as other Abstracting and Indexing (A&I) databases.
Extensions of some selected papers will be published in a special issue of The
Journal of Systems Architecture: Embedded Software Design.

Associated Conference: The 22nd IEEE International Conference on
Embedded and Real-Time Computing Systems and Applications (RTCSA 2016)

Call for Nominations: The Rau Award 2016

Submitted by Milagros Lovos
https://www.computer.org/web/awards/rau
February 26, 2016 at 08:00

Submitted by Milagros Lovos
https://www.computer.org/web/awards/rau

The Rau Award

Established in memory of Dr. B. (Bob) Ramakrishna Rau, the award recognizes his
distinguished career in promoting and expanding the use of innovative computer
microarchitecture techniques, including his innovation in compiler technology,
his leadership in academic and industrial computer architecture, and his
extremely high personal and ethical standards.

WHO IS ELIGIBLE?
The candidate will have made an outstanding, innovative contribution or
contributions to microarchitecture, use of novel microarchitectural techniques
or compiler/architecture interfacing. It is hoped, but not required, that the
winner will have also contributed to the computer microarchitecture
community through teaching, mentoring, or community service.

AWARD:
Certificate and a $2,000 honorarium.

PRESENTATION:
This year’s award will be presented at the ACM/IEEE International Symposium
on Microarchitecture (MICRO-49), held in October 15-19, 2016 in Taipei Taiwan.

NOMINATION SUBMISSION:
This award requires 3 endorsements.
Nominations are being accepted electronically through http://www.computer.org/web/awards/rau

PAST RECIPIENT:
Robert P. Colwell – “For contributions to critical analysis of microarchitecture and
the development of the Pentium Pro processor.”

IEEE Computer Society Awards site: www.computer.org/awards
IEEE Computer Society Award Nominations site: http://awards.computer.org/

Call for Papers: MEMSYS 2016

Submitted by Aamer Jaleel
http://www.memsys.io
March 18, 2016

Submitted by Aamer Jaleel
http://www.memsys.io

Memory Systems Conference (MEMSYS)
Washington, DC, USA
 

IMPORTANT DATES:
Submission Deadline: March 18*, 2016
Notification: May 15, 2016
Camera-Ready: July 1, 2016
* There will be an automatic submission extension of one week
 

The memory system has become extremely important recently: memory is slow,
and this is the primary reason that computers don’t run significantly faster than
they do. In large-scale computer installations such as the building-sized
systems powering Google.com, Amazon.com, and the financial sector, memory is
often the largest dollar cost as well as the largest consumer of energy.
Consequently, improvements in the memory system can have significant impact on
the real world, improving power and energy, performance, and/or dollar cost.

Moreover, many of the problems we see in the memory system are
cross-disciplinary in nature—their solution would likely require work at all
levels, from applications to circuits. Thus, while the scope of the problem is
memory, the scope of the solutions will be much wider.

Areas of Interest

Previously unpublished papers containing significant novel ideas and technical
results are solicited. Papers that focus on system, software, and architecture
level concepts, outside of traditional conference scopes, will be preferred
over others (e.g., the desired focus is away from pipeline design, processor
cache design, prefetching, data prediction, etc.). Symposium topics include,
but are not limited to, the following:

– Memory system design from both hardware & software perspectives
– Operating system design for hybrid/nonvolatile memories
– Technologies including PCM, flash, DRAM, STT-RAM, 3DXP, etc.
– Data-movement issues and mitigation techniques
– Interconnects to support large-scale data movement
– Software & application techniques for distributed memories
– Software management techniques
– Near-memory computing
– Memory-centric programming models & compiler techniques
– Memory failure modes and mitigation strategies
– Memory and system security issues

To reiterate, papers that focus on topics outside of traditional conference
scopes will be preferred over others.

SUBMISSION GUIDELINES:
Our primary goal is to showcase interesting ideas that will spark conversation
between disparate groups—to get applications people and operating systems
people and system architecture people and interconnect people and circuits
people to talk to each other. We accept extended abstracts, position papers,
and/or full research papers, and each accepted submission is given a 20-minute
presentation time slot. All accepted papers will be published in the ACM
Digital Library.

Submission formats:
2 page Extended Abstracts
5–6 page Position Papers
10–12 page Research Papers

Conference paper layout, no less than 9pt font in body, two-column, blind
submission, up to 15 pages in length.

All accepted submissions will be presented, published in the ACM Digital
Library, and included in the printed conference proceedings.

Note: Submitting either Extended Abstracts or Position Papers will not
preclude an author from submitting their work, in a longer research format,
to another publication forum at a later date.

ORGANIZERS:
Bruce Jacob, U. Maryland
Kathy Smiley, Memory Systems
Ameen Akel, Micron
James Ang, Sandia National Labs
Yitzhak Birk, Technion
Bruce Childers, U. Pittsburgh
Zeshan Chishti, Intel
Chen Ding, U. Rochester
David Donofrio, Berkeley Lab
Wendy Elsasser, ARM
Maya Gokhale, LLNL
Thuc Hoang, NNSA/DOE
Hillery Hunter, IBM
Mike Ignatowski, AMD
Aamer Jaleel, NVIDIA
David Kaeli, Northeastern
Scott Lloyd, LLNL
Gabriel Loh, AMD
Kenneth Ma, Hynix
Richard Murphy, Micron
Mike O’Connor, NVIDIA
Petar Radojkovic, BSC
David Resnick, Sandia National Labs
Arun Rodrigues, Sandia National Labs
John Shalf, Berkeley Lab
Anouk Van Laer, U. College London
Jeffrey Vetter, Georgia Tech & ORNL
Robert Voigt, Northrop Grumman
David Wang, Inphi
Christian Weis, U. Kaiserslautern
Kenneth Wright, Rambus
Sudhakar Yalamanchili, Georgia Tech

Call for Nominations: Eckert-Mauchly Award

Submitted by Milagros
http://awards.computer.org/
June 18 to June 22, 2016

Submitted by Milagros

http://www.computer.org/web/awards/eckert-mauchly

2016 ACM/IEEE-CS Eckert-Mauchly Award

Deadline: 30 March 2016
 

ACM and the IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which
was initiated in 1979. The award is known as the computer architecture
community’s most prestigious award.

The award recognizes outstanding contributions to computer and digital systems
architecture. It comes with a certificate and a $5,000 honorarium.

The award was named for John Presper Eckert and John William Mauchly, who
collaborated on the design and construction of the Electronic Numerical
Integrator and Computer (ENIAC), the first large-scale electronic computing
machine, which was completed in 1947.

This year’s award will be presented at the 43rd International Symposium on
Computer Architecture (ISCA). ISCA will be held in Seoul, South Korea,
June 18-22, 2016.

NOMINATION GUIDELINES:
– Open to all. Do not need IEEE Membership to nominate.
– This award requires 3 endorsements.
– Self-nominations are not accepted.
Additional details at the award web site. Contact awards@computer.org for
any questions.

Committee Selection Chair:
Antonio Gonzalez, Universitat Politecnica de Catalunya

PAST RECIPIENTS:
2015 Recipient: Norman P. Jouppi, Google
“For pioneering contributions to the design and analysis
of high-performance processors and memory systems.”

2014 Recipient: Trevor Mudge, University of Michigan
“For pioneering contributions to low power computer architecture
and its interaction with technology.”

Call for Papers: NOCS 2016

Submitted by John Kim
http://www.arc.ics.keio.ac.jp/nocs16
August 31 to September 2, 2016

Submitted by John Kim
http://www.arc.ics.keio.ac.jp/nocs16

10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)
Nara, Japan
August 31 – September 2, 2016
 

IMPORTANT DATES:
Abstract registration deadline: February 12, 2016
Full paper submission deadline: February 19, 2016
Notification of acceptance : April 8, 2016
Final version due: May 18, 2016
 

The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip, chip-scale, and multichip
package scale communication technology, architecture, design methods,
applications and systems. NOCS brings together scientists and engineers
working on NoC innovations and applications from inter-related research
communities, including computer architecture, networking, circuits and
systems, packaging, embedded systems, and design automation.

Topics of interest include, but are not limited to:

1. NoC Architecture and Implementation:
– Network architecture (topology, routing, arbitration)
– NoC Quality of Service
– Timing, synchronous/asynchronous communication
– NoC reliability issues
– Network interface issues
– NoC design methodologies and tools
– Signaling & circuit design for NoC links

2. NoC Analysis and Verification:
– Power, energy & thermal issues (at the NoC, un-core and/or system-level)
– Benchmarking & experience with NoC-based hardware
– Modeling, simulation, and synthesis of NoCs
– Verification, debug & test of NoCs
– Metrics and benchmarks for NoCs

3. Novel NoC Technologies:
– New physical interconnect technologies, e.g., carbon nanotubes, wireless
NoCs, through-silicon, etc.
– NoCs for 3D and 2.5D packages
– Package-specific NoC design
– Optical, RF, & emerging technologies for on-chip/in-package interconnects

4. NoC Application:
– Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
– Scalable modeling of NoCs

5. NoC at the Un-Core and System-level:
– Design of memory subsystem (un-core) including memory controllers,
caches, cache coherence protocols & NoCs
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing and
novel programming models
– Issues related to large-scale systems (datacenters, supercomputers)
with NoC-based systems as building blocks

6. On-Chip Communication Optimization:
– Communication efficient algorithms
– Multi/many-core communication workload characterization & evaluation
– Energy efficient NoCs and energy minimization

Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation.

Submitted papers must describe original work that has not been published
before or is under review by another conference or journal at the same time.
Each submission will be checked for any significant similarity to previously
published works or for simultaneous submission to other archival venues, and
such papers will be rejected. Proposals for special sessions, tutorials, and
demos are invited. Paper submissions and demo proposals by industry
researchers or engineers to share their experiences and perspectives are also
welcome.

Please see the detailed submission instructions for paper submissions, special
session, tutorial, and demo proposals on the conference web site.

ORGANIZING COMMITTEE:
General Co-Chairs:
– Hideharu Amano (Keio University, Japan)
– Partha Pratim Pande (Washington State University, USA)

Technical Program Co-Chairs:
– Hiroki Matsutani (Keio University, Japan)
– Sriram Vangal (Intel, USA)

Publicity Co-Chairs:
– John Kim (Korea Advanced Institute of Science and Technology, Korea)
– Turbo Majumder (Intel, USA)
– Maurizio Palesi (Kore University, Italy)

Publication Chair:
– Umit Ogras (Arizona State University, USA)

Industry Chair:
– Yuichiro Ajima (Fujitsu Limited, Japan)

Special Sessions Co-Chairs:
– Michihiro Koibuchi (National Institute of Informatics, Japan)
– Sudeep Pasricha (Colorado State University, USA)

Tutorial Chair:
– Paul Bogdan (University of Southern California, USA)

Finance Chair:
– Ikki Fujiwara (National Institute of Informatics, Japan)

Registration Chair:
– Takashi Nakada (University of Tokyo, Japan)

Local Arrangements Chair:
– Shinya Takamaeda (Nara Institute of Science and Technology, Japan)

Call For Papers: Workshop on Multicore and Rack-scale Systems

Submitted by Boris Grot
http://www.cs.utexas.edu/~mars2016/
February 5, 2016

Submitted by Boris Grot
http://www.cs.utexas.edu/~mars2016/

Workshop on Multicore and Rack-scale Systems (MARS)
co-located with EuroSys 2016
London, UK
April 18, 2016
 

IMPORTANT DATES:
Submission deadline: February 5, 2016
Acceptance Notification: March 9, 2016
Workshop date: April 18, 2016
 

Present and future multi-core architectures pose a variety of challenges for
system developers: non-cache-coherent memory, heterogeneous processing cores
and the exploitation of novel architectural features, such as systems-on-chip
(SoCs), distributed switching fabrics, silicon photonics, and programmable
hardware. In the near future, we expect to see “rack-scale computers” with
1,000s of cores and terabytes of memory, connected with bandwidth and latency
comparable to today’s smaller-scale NUMA servers.

MaRS 2016 is a forum for researchers in the hardware, networking, storage,
operating systems, language runtime and virtual machine communities to present
their experiences with and discuss innovative designs and implementations for
these new architectures.

Topics of interest include, but are not limited to:
– novel multi-core and rack-scale operating system designs,
– System-on-chip (SoC) and Network-on-chip (NoC) designs,
– runtime systems and programming environments for future hardware,
– low-latency and optical networking,
– OS or runtime support for heterogeneous processing cores,
– non-cache-coherent shared memory,
– scheduling on many-core and rack-scale architectures,
– programmable hardware,
– energy efficiency, fault tolerance and resource management on
future multi-core and rack-scale architectures,
– rack-scale storage,
– performance evaluation of emerging hardware,
– architectural support for systems-level software,
– case studies of system-level software design for current or future
multi-core and rack-scale hardware, and
– applications for and experiences with multi-core and rack-scale
systems.

PAPER SUBMISSION:
Authors are invited to submit original and unpublished work that exposes a
new problem, advocates a specific solution, or reports on actual experience.
Papers should be submitted using the standard two-column ACM SIG proceedings
or SIG alternate template, and are limited to 5 pages (including everything
except references). Additional pages can be used for references if required.
Papers that violate the submission guidelines may be rejected without
consideration of their merit.

Final papers will be made available to participants electronically at the
meeting, but to facilitate resubmission to more formal venues, no archival
proceedings will be published, and papers will not be sent to the ACM Digital
Library. Authors will be given the option of having their final paper
accessible from the workshop website. Authors of accepted papers will be
invited to give a talk at the workshop.

TALK SUBMISSION:
If you are interested in giving a talk at MaRS 2016, please submit a one-page
abstract instead of a full paper. Authors of accepted papers/talks will also
be invited to present a poster and/or demo in the EuroSys ’16 joint poster
session. Student speakers will be eligible to apply for EuroSys travel grants
to attend.

ORGANIZERS:
Boris Grot (University of Edinburgh)
Simon Peter (UT Austin)
Chris Rossbach (VMware and UT Austin)

Program Committee:
Mahesh Balakrishnan (Yale)
Antonio Barbalace (Virginia Tech)
Taesoo Kim (Georgia Tech)
Mark Oskin (University of Washington)
Mark Silberstein (Technion)
Cheng-Chun Tu (VMware)
John Wilkes (Google)
Bernard Wong (University of Waterloo)

Call For Papers: ISLPED 2016

Submitted by Vijay Raghunathan
http://www.islped.org
February 21, 2016 at 24:00

Submitted by Vijay Raghunathan
http://www.islped.org

ACM/IEEE International Symposium on Low Power Electronics and
Design (ISLPED)

San Francisco, CA, USA
August 8-10, 2016
 

IMPORTANT DATES:
Abstract registration: Feb 21, 2016
Full paper due: Feb 28, 2016
Panel and Embedded Tutorial Proposals Deadline: Apr 16, 2016
Notification of Paper Acceptance: Apr 30, 2016
Camera-ready due: Jun 15, 2016
 

The International Symposium on Low Power Electronics and Design (ISLPED)
is the premier forum for presentation of innovative research in all aspects of
low power electronics and design, ranging from process technologies and
analog/digital circuits, simulation and synthesis tools, system-level design
and optimization, to system software and applications. Specific topics
include, but are not limited to, the following tracks:

1.1. Technologies
Low-power technologies for Device, Interconnect, Logic, Memory, 2.5/3D,
Cooling, Harvesting, Sensors, Optical, Printable, Biomedical, Battery, and
Alternative energy storage devices.

1.2. Circuits
Low-power digital circuits for Logic, Memory, Reliability, Clocking, Power
gating, Resiliency, Near-threshold and Sub-threshold, Variability, and
Digital assist schemes; Low-power analog/mixed-signal circuits and
Analog assist schemes.

1.3. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, Processor cores
(compute, graphics and other special purpose cores), Cache, Memory, Arithmetic
/Signal processing, Cryptography, Variability, Asynchronous design, and Non-
conventional computing.

2.1. CAD Tools and Methodologies
CAD tools and methodologies for low-power and thermal-aware design
addressing power estimation, optimization, reliability and variation impact
on power, and power-down approaches at all levels of design abstraction:
physical, circuit, gate, register transfer, behavior, and algorithm.

2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design and platforms for
microprocessors, DSPs, embedded systems, FPGAs, ASICs, SoCs, heterogeneous
computing, data-center power delivery and cooling, and system-level power
implications due to reliability and variability.

2.3. Software and Applications
Energy-efficient, energy-aware, and thermal-aware system software and
application design including scheduling and management, power optimizations
through HW/SW interactions, and emerging low power applications such as
approximate and brain-inspired computing, the Internet-of-Things (IoT),
wearable computing, body-area/in-body networks, and wireless sensor networks.

3.1. Industry Perspectives
ISLPED’16 solicits papers for an “Industrial Design” track to reinforce
interaction between the academic research community and industry. Industrial
Design track papers have the same submission deadline as regular papers and
should focus on similar topics, but are expected to provide a complementary
perspective to academic research by focusing on challenges, solutions, and
lessons learnt while implementing industrial-scale designs. Industrial
design papers that focus on any of the topics mentioned in the tracks above
are welcome.

Submissions on new topics: emerging technologies, architectures/platforms,
and applications are particularly encouraged.

SUBMISSION GUIDELINES:
Submissions should be full-length papers of up to 6 pages (PDF format, double
-column, US letter size, using the ACM Conference format) including all illustrations,
tables, references, and an abstract of no more than 250 words. Submissions must
be anonymous. Submissions exceeding 6 pages or identifying the authors, either
directly or through explicit references to their prior work, will be automatically
rejected. More information about paper submission can be found at
http://www.islped.org.

Submitted papers must describe original work that has not been published/
accepted or currently under review by another journal, conference,
symposium, or workshop at the same time. Accepted papers will be submitted
to the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’16
will present two Best Paper Awards based on the ratings of reviewers and a
panel of judges.

There will be several invited talks by industry and academic thought leaders
on key issues in low power electronics and design. The Symposium may also
include embedded tutorials to provide attendees with the necessary background
to follow recent research results, as well as panel discussions on future
directions in low power electronics and design. Proposals for invited talks,
embedded tutorials, and panels should be sent by email to the ISLPED’16
Technical Program Co-Chairs, David Garrett (garrett@broadcom.com) and Chia-
Lin Yang (yangc@csie.ntu.edu.tw) by the deadline listed above.

Call for Papers: GreenMetrics 2016

Submitted by Niklas Carlsson
http://www.sigmetrics.org/greenmetrics/
June 14, 2016

Submitted by Niklas Carlsson
http://www.sigmetrics.org/greenmetrics/

GreenMetrics 2016 Workshop
in conjunction with ACM SIGMETRICS 2016
Sponsored by ACM SIGMETRICS
Antibes Juan-les-Pins, France
June 14 (or June 18), 2016
 

IMPORTANT DATES:
– Monday, April 11, 2016: Paper Submission
– Wednesday, April 27, 2016: Author Notification
– Wednesday, June 1, 2016: Final Versions Due
– Tuesday (June 14) or Saturday (June 18), 2016: Workshop
– Date TBD (likely mid-July): Final Versions for PER Due
 

Sustainability is a topic of increasing importance in modern society. The
primary objective of this workshop is to explore how improvements to or new
uses of Information and Communication Technology (ICT) can improve the
environmental, economic and/or social sustainability of ICT systems, networks,
and applications and of non-ICT processes (e.g., quantify the reduction in
cost or carbon emissions from using tele-presence services instead of travel).

Topics of interest fall broadly into three main areas:
– Designing sustainable ICT: Such work includes research measuring, evaluating,
or designing energy efficient systems in data centers, networking and
communication protocols, etc.

– ICT for sustainability: new uses of ICT to improve the environmental,
economic, and/or social sustainability of non-ICT processes.

– Building a smarter, more sustainable electricity grid: addressing the
challenges (both engineering and economic) that come from incorporating
increasing penetration of renewable energy into the grid, demand-response
techniques, and smart-metering.

This workshop is intended to bring together researchers from the
(traditional) SIGMETRICS and Performance communities with researchers and
practitioners in the three areas above, to exchange technical ideas and
experiences on issues related to sustainability and ICT. The workshop will
include a mixture of invited talks and presentations of accepted papers,
and will serve as a forum for the SIGMETRICS and Performance communities to
apply their techniques to this emerging and important area.

An award will be presented for the best student paper, and we will have an
exciting series of keynote talks, including talks by Florian Dörfler (ETH
Zürich), Xue (Steve) Liu (McGill University), and Kameshwar Poolla (UC
Berkeley).
 

SUBMISSION GUIDELINES:
In order to be inclusive of authors from different communities Greenmetrics
will have two options for paper submissions. Authors may either submit
full papers or extended abstracts. Full papers are allowed to be six
double-column pages, while extended abstracts are allowed to be up to three
double-column pages. Both types of submissions should be in the standard
ACM format, and both types of submissions will be reviewed. While full
papers must be either new material or a survey article, extended abstracts
may summarize recent submissions to other venues (either conferences or
journals). Thus, we hope that authors will submit extended abstracts in
order to present recent work from other communities to the Sigmetrics
community.

Submissions must be submitted electronically in printable PDF form, via the
GreenMetrics 2016 submission site:
http://www.sigmetrics.org/greenmetrics/submission.shtml

Submissions will be reviewed by the GreenMetrics program committee, from
which a number of papers will be selected for presentation at the workshop.
The accepted papers will be published in ACM SIGMETRICS Performance
Evaluation Review (PER). Authors of accepted papers grant permission to ACM
to publish the paper in PER and the ACM digital library. Authors do retain
the copyright of their paper.
 

ORGANIZERS:
– Niklas Carlsson, Linkoping University (niklas.carlsson@liu.se)
– Zhenhua Liu, Stony Brook University (zhenhua.liu@stonybrook.edu)
– Thu Nguyen, Rutgers University (tdnguyen@cs.rutgers.edu)
– Catherine Rosenberg, University of Waterloo ‎(cath@uwaterloo.ca)
– Adam Wierman, Caltech (adamw@caltech.edu)

Program Committee:
– Tarek Abdelzaher, UIUC
– Danilo Ardagna, Politecnico di Milano
– Martin Arlitt, Hewlett Packard Labs
– Subhonmesh Bose, Cornell Univerity
– Tim Brecht, University of Waterloo
– Giuliano Casale, Imperial College
– Abhishek Chandra, University of Minnesota
– Lydia Y. Chen, IBM Zurich Research Laboratory
– Minghua Chen, The Chinese University of Hong Kong
– Yuan Chen, Hewlett Packard Labs
– Gyorgy Dan, KTH Royal Institute of Technology
– Derek Eager, University of Saskatchewan
– Yashar Ghiassi-Farrokhfal, Erasmus University Rotterdam
– Emir Halepovic, AT&T
– Longbo Huang, Tsinghua University
– David Irwin, UMASS Amherst
– Canturk Isci, IBM
– Guillaume Jourjon, NICTA
– Srinivasan Keshav, University of Waterloo
– Diwakar Krishnamurthy, University of Calgary
– Deepa Kundur, University of Toronto
– Na Li, Harvard
– Manish Marwah, Hewlett Packard Labs
– Arif Merchant, Google
– Lei Rao, Huawei US R&D
– Cristina Rottondi, IDSIA
– Anand Sivasubramaniam, Pennsylvania State University
– Christopher Stewart, Ohio State University
– Jia Wang, AT&T Research

Call for Proposals: 2016 Fellowships in ACM History

Submitted by Sarita Adve
http://history.acm.org/public/public_documents/acm_history_fellowship_announce_2016.php
February 1, 2016

Submitted by Sarita Adve
http://history.acm.org/public/public_documents/acm_history_fellowship_announce_2016.php

2016 Fellowships in ACM History

Proposals due: February 1, 2016
 

ACM will support up to four research projects with awards of up to $4,000
each. Successful candidates may be of any rank, from graduate students
through senior researchers. See the list of past supported projects at
http://history.acm.org/public/public_documents/acm_history_fellows.php

APPLICATION GUIDELINES:
Applicants should send a 2-page CV as well as a 750-word project description
that
– describes the proposed research;
– identifies specific ACM historical materials, whether traditional archival
collections or online historical materials (oral histories, digitized
conference papers, ACM organizational records, etc.);
– discusses project outcomes (e.g. journal article, book or dissertation
chapter, teaching resource, museum exhibit, website); and
– outlines a timeline for completing the project—generally within 12 months.

In preparing a proposal, applicants should examine the document “ACM Research
Materials” posted at http://history.acm.org/content.php?do=links as well as
“Sources for ACM History,” CACM 50 #5 (May 2007): 36-41
http://doi.acm.org/10.1145/1230819.1230836. Other research materials relating
to ACM may also be used. Applicants should include a letter of endorsement
from their home institution or an external scholarly reference.

Proposals are due by 1 February 2016. Proposals should be submitted as a
single pdf-format document to history-webmaster@acm.org. Notification of
awards will be made within 8 weeks.

The current and past winners of the fellowship can be found at
http://history.acm.org/public/public_documents/acm_history_fellows.php.

Call for Participation: ACM Workshop on Oral History

Submitted by Sarita Adve
http://history.acm.org/public/public_documents/acm_oralhistory_workshop_announce_2016.php
January 15, 2016

Submitted by Sarita Adve
http://history.acm.org/public/public_documents/acm_oralhistory_workshop_announce_2016.php

ACM Workshop on Oral History
University of North Carolina at Chapel Hill, USA
Friday, May 12-13, 2016
 

Project proposal deadline: Friday, January 15, 2016
 

Applications are invited to a 1.5 day oral history workshop, to be held
Thursday and Friday, May 12-13, 2016 at the University of North Carolina at
Chapel Hill, North Carolina. For each successful application, one person’s
expenses for workshop travel, lodging, and meals will be paid by the ACM
History Committee. The workshop will be led by Mary Marshall Clark, director
of the Columbia Center for Oral History (CCOH); see
http://library.columbia.edu/locations/ccoh.html.

Who should attend?
ACM members and others who are planning or actually doing oral history
projects. The audience is people who are performing interviews for oral
histories, or thinking about doing so. The workshop should be of special
interest to ACM officers and staff, SIG leaders, historically minded ACM
members, and others working on oral history projects. Priority will be given
to ACM members and members of other national computer societies affiliated
with the ACM, but some places have been reserved for non-affiliated
individuals who are actively engaged in oral history projects.

Workshop topics and activities include:
– developing an oral history program;
– presentation and training on oral history processes and principles;
– hands-on exercises interviewing each other;
– analysis and discussion of the exercises;
– how to analyze results, findings and evaluate an oral history project;
– practical considerations: lessons learned and best practices; and
– ample networking time, including lunches and the workshop dinner.
Participants will leave with a “tool kit” of practical, useful procedures as
well as insight into professional oral history practices.

Small workshop format will permit maximum hands-on experience and personal
interaction. We are planning for 16 participants.

The ACM History Committee will fund travel, hotel and meals for accepted
invitees. Applicants should send a 2-page CV as well as a 250-word proposed
project and/or oral history interest description that
(1) explains the significance of a proposed oral history project (if
applicable), potential uses of the techniques learned, and its importance;
(2) affirms your willingness to participate fully in the 1.5 day agenda.

Project proposals are due by Friday, January 15, 2016. Proposals should be
submitted as a single PDF document to history-webmaster@acm.org. Notification
of project acceptance will be made within eight weeks.

Questions about the workshop or requests for clarification may be directed, at
any time, to history-webmaster@acm.org.