Dark Silicon Workshop (DaSi 2012) Call for Presentations

Submitted by Jack Sampson
http://darksilicon.ucsd.edu
April 2, 2012 at 23:45

Submitted by Jack Sampson
http://darksilicon.ucsd.edu
The 1st Dark Silicon Workshop
Portland, Oregon USA
June 10th, 2012. Held in conjunction with ISCA

The first Dark Silicon Workshop provides a unique forum for discussing
the challenges and opportunities that Dark Silicon presents. There are
many research questions left to answer before new architectures built
specifically to mitigate or exploit dark silicon become the default
platforms for general purpose computing. To scale alongside dark
silicon, architects will need to design and verify specialized
processors in increasing numbers. Making heterogeneous platforms easy
to program will require us to reconsider traditional language and OS
abstractions. Traditionally, many of the performance gains from
specialized hardware stem from customized memory designs, and it is
not yet clear how best to integrate multiple such memory designs
together into a single architecture. These and other challenges will
face researchers as they shed light on silicon’s dark future.

The organizing committee is soliciting presentations on any topic
related to Dark Silicon, including (but not limited to):

• Architectural approaches to managing and exploiting dark silicon
• Power management techniques
• Energy/power-efficient circuit designs
• Energy/power-efficient memory systems
• Scalable design and synthesis techniques for customizable and
specialized cores
• Novel applications for idle chip area

The goal is to facilitate the exchange of the latest ideas, insights,
and knowledge that can propel future progress. In lieu of printed
proceedings, we will post the slides and extended abstracts of the
presentations online. Presentation of new work at the workshop does
not preclude future publication.

Workshop submissions should be in the form of a 2-page presentation
abstract. Submissions will be evaluated on the basis of impact,
novelty, and general interest. The submission deadline is April 2,
2012, with notification of acceptance by May 3, 2012.

Further details on abstract submission, technical program, tutorials,
travel, social program, and travel grants will be provided at the
workshop website:

http://DarkSilicon.ucsd.edu

Organizing Committee:
Babak Falsafi, EPFL
Jack Sampson, UCSD
Steven Swanson, UCSD
Michael B. Taylor, UCSD

Program Committee:
Krste Asanovic, Berkeley
David Brooks, Harvard
Calin Cascaval, Qualcomm
Babak Falsafi, EPFL
Nikos Hardavellas, Northwestern University
James Hoe, Carnegie Mellon
Norm Jouppi, HP Labs
Brucek Khailany, Nvidia
Martha Kim, Columbia
Scott Mahlke, University of Michigan
Milo Martin, University of Pennsylvania
Jack Sampson, UCSD
Karthikeyan Sankaralingam, University of Wisconsin
Kevin Skadron, University of Virginia
Guri Sohi, University of Wisconsin
Steven Swanson, UCSD
Michael B. Taylor, UCSD

IEEE TCCA Young Computer Architect Award

Submitted by Timothy Pinkston
http://www.computer.org/portal/web/awards

Submitted by Timothy Pinkston
http://www.computer.org/portal/web/awards
Call for Nominations: The IEEE TCCA Young Computer Architect Award

This annual award recognizes outstanding contributions in the field
of computer architecture by an individual who has made contributions
in research and/or education and received his/her PhD degree within
6 years from the date of the nomination. The award will be presented
at the International Symposium on Computer Architecture (ISCA) Awards
Banquet.

Nominations should consist of the following:

1. Name/email of person making the nomination (self-nominations are
not eligible)

2. Name/email of candidate for whom the award is recommended

3. A statement by the nominator (maximum of 500 words) as to why the
nominee is highly deserving of the award. Note that since the award
is for outstanding contributions in both research and education,
the statement and supporting letters should address what the
contributions are and why they are both outstanding and significant.
The nomination should also list the names and email of two (at most three)
persons who will provide letters supporting the nomination.

4. CV of the nominee

5. Two (at most three) support letters from persons other than
the nominator, to be sent directly to the Chair of the Awards
Selection Committee

Deadline for nominations: April 1, 2012.

Nominations are to be sent to the TCCA Awards Selection Committee Chair:
Timothy Pinkston

FastPath 2012 Workshop call for papers

Submitted by Peter Sweeney
http://www.fastpath2012.net.tc/
April 1, 2012

Submitted by Peter Sweeney
http://www.fastpath2012.net.tc/

CALL FOR PAPERS
(Extended submission date and invited speakers)
FastPath 2012 Workshop on Performance Modeling and Analysis of
Workload Optimized Systems
April 1, 2012
New Brunswick, NJ
http://www.fastpath2012.net.tc
To be held with the ISPASS Conference: http://ispass.org/ispass2012

GOAL
FastPath brings together researchers and practitioners involved in
cross-stack hardware/software performance analysis, evaluation, and
modeling of workload optimized systems.

OVERVIEW
With microprocessor clock speeds being held constant, optimizing systems
around specific workloads is an increasingly attractive means to improve
performance. The importance of workload optimized systems is seen in their
ubiquitous deployment in diverse systems from cellphones to tablets to routers
to game machines to Top500 supercomputers, and IT appliances such as IBMs
DataPower and Netezza, and Oracle’s Exadata.

More precisely, workload optimized systems have hardware and/or software
specifically designed to run well for a particular application or application
class. The types and components of workload optimized systems vary, but a
partial list includes traditional CPUs assisted with accelerators (ASICs,
FPGAs, GPUs), memory accelerators, I/O accelerators, hybrid systems, and
IT appliances.

TOPICS
FastPath seeks to facilitate the exchange of ideas on performance
analysis, evaluation and modeling of workload optimized systems.
Please submit a 6-page research papers (2-column, 10 to 12-point type,
single spaced, 1-inch margins) from one or more of the topics that
include, but not limited to:

o Workloads o GPUs
o Simulators o FPGAs
o Measured results on accelerated systems o ASIC Accelerators
o Industrial Experiences o Programming Models
o Analytical Techniques o Runtime Management Systems

INVITED SPEAKERS
Simha Sethumadhavan (Columbia University)
Mark Hempstead (Drexel University)

SUBMISSIONS
Please make submissions here:
https://www.easychair.org/account/signin.cgi?conf=fastpath2012
Fastpath papers will be made available through the workshop website and
hard copies will be provided at the workshop to the attendees. There are
no copyright issues with Fastpath papers, and thus authors retain the
copyright of their work with complete freedom to submit their work elsewhere.
Additional details are on our website: http://www.fastpath2012.net.tc

KEY DATES:
Submission: February 27, 2012 (extended date)
Notification: March 12, 2012
Final Materials Due: March 23, 2012
Workshop April 1, 2012

ORGANIZERS
General Co-Chairs: David Brooks (Harvard), Parijat Dube (IBM)
Program Committee Co-Chairs: Erik Altman (IBM), Lieven Eeckhout (Ghent)
Publicity Chair: Peter F. Sweeney (IBM)
Web Chair: Augusto Vega (IBM)

PROGRAM COMMITTEE
Tor Aamodt British Columbia
Stijn Eyerman Ghent
R. Govindarajan IISc
Hans Jacobson IBM
Russ Joseph Northwestern
Mikko Lipasti Wisconsin
Toshio Nakatani IBM
Alex Ramirez BSC
Alma Riska EMC
Arrvindh Shriraman Simon Fraser
James E Smith Intel
Li Zhang IBM

Third International Green Computing Conference (IGCC'12) – Extended deadlines

Submitted by John Owens
http://www.green-conf.org
January 20, 2012

Submitted by John Owens
http://www.green-conf.org
June 5-8, 2012 in San Jose, California, USA

Scope
IGCC’12 will provide a forum for presenting and discussing innovative
research on a broad range of topics in the fields of sustainable and
energy-efficient computing, and computing for a more sustainable
planet. The conference will hold a technical program, panels,
workshops, and tutorials on these topics. IGCC’12 will be technically
co-sponsored by the IEEE. Topics of interest include, but are not
limited to:

Sustainable Computing
* Power-aware algorithms and protocols
* Power-aware software and hardware
* Low-power electronics and systems
* Application-specific ASICs and FPGAs
* Sensing and monitoring
* Characterization, metrics, and modeling
* Reliability, thermal behavior and control
* Power-efficient delivery and cooling
* Life-cycle analysis of IT equipment

Computing for Sustainability
* Renewable energy models and prediction
* Matching energy supply and demand
* Smart grid and microgrids
* Smart transportation and manufacturing
* Smart buildings and urban development
* Energy harvesting, storage, and recycling
* Climate and ecosystem monitoring
* Using IT to reduce carbon emissions
* Carbon metering and user feedback

IGCC’12 welcomes submissions that have not been published and that are
not under review by another conference or journal. All submissions
will be evaluated on their originality, technical soundness,
significance, presentation, and interest to the conference attendees.
Submissions must not exceed 10 letter-size pages using the IEEE format
for conference proceedings. Papers must be received by the submission
deadline to be considered for presentation.

Best paper award and journal publication
The Technical Committee will select the best paper as well as several
papers to be extended and considered by the Journal on Sustainable
Computing.

Workshops and tutorials
Proposals are solicited for workshops and tutorials to be held in
conjunction with the conference. Proposals should be submitted to the
Workshops and Tutorials Chairs. Additional details are available at
http://www.green-conf.org.

Important dates
Abstract submission: Extended to January 20, 2012 at 11:59pm US Pacific time
Paper submission: Extended to January 27, 2012 at 11:59pm US Pacific time
Notifications sent to authors: April 4, 2012
Camera-ready papers due: May 1, 2012

Organization
General chairs:
David Culler (UC Berkeley), Behrooz Shirazi (Wash. State Univ.)

Program chairs:
Ricardo Bianchini (Rutgers Univ.), Fred Chong (UC Santa Barbara)

Program committee:
Tarek F. Abdelzaher UI Urbana-Champaign
Hakan Aydin George Mason Univ.
Cullen Bash HP Labs
Kirk W. Cameron Virginia Tech
John Carter IBM Research
Prabal Dutta Univ. of Michigan
Klaus Fichter Borderstep Institute
Rodrigo Fonseca Brown Univ.
Eugene Gorbatov Intel Research
Rajesh Gupta UC San Diego
Sandeep Gupta Arizona State Univ.
Sudhanva Gurumurthi Univ. of Virginia
Mor Harchol-Balter Carnegie Mellon Univ.
Canturk Isci IBM Research
Mahmut Kandemir Penn State Univ.
Aman Kansal Microsoft Research
Krishna Kant National Science Foundation
Randy H. Katz UC Berkeley
Dejan Kostic EPFL
Christos Kozyrakis Stanford Univ.
Ulrich Kremer Rutgers Univ.
Benjamin C. Lee Duke Univ.
Tao Li Univ. of Florida
Srilatha Manne AMD
Ethan L. Miller UC Santa Cruz
Onur Mutlu Carnegie Mellon Univ.
Manish Parashar Rutgers Univ.
Massoud Pedram Univ. of Southern California
Kirk Pruhs Univ. of Pittsburgh
Partha Ranganathan HP Labs
Tajana S. Rosing UC San Diego
Martin Schulz Lawrence Livermore National Lab.
Ankur Srivastava Univ. of Maryland
Mani Srivastava UC Los Angeles
Michael Taylor UC San Diego
Bhuvan Urgaonkar Penn State Univ.
Xiaorui Wang Ohio State Univ.
Thomas F. Wenisch Univ. of Michigan

Workshops chair:
Sanjay Ranka (Univ. of Florida)

Publications chair:
Saeed Rajput (Nova Southeastern Univ.)

Publicity chairs:
Giuseppe Anastasi (Universita di Pisa, Italy), John Owens (UC Davis)

Submissions chair:
Guoping Long (Institute of Software, Chinese Academy of Sciences)

Steering committee:
Ishfaq Ahmad Co-Chair, UT Arlington
Rajesh Gupta UC San Diego
Sandeep Gupta Arizona State Univ.
Ali Hurson Missouri Univ. of Science and Technology
Ashfaq Khokhar UI Chicago
Francis Lau Univ. of Hong Kong
Sanjay Ranka Univ. of Florida
Behrooz Shirazi Co-Chair, Wash. State Univ.

FastPath 2012

Submitted by Erik Altman
https://sites.google.com/site/fastpath2012
February 9, 2012

Submitted by Erik Altman
https://sites.google.com/site/fastpath2012

Workshop on Performance Modeling and Analysis of Workload Optimized Systems
To be held with the ISPASS Conference: http://ispass.org/ispass2012

GOAL
The goal of FastPath is to bring together researchers and practitioners
involved in cross-stack hardware/software performance analysis, modeling,
and evaluation of workload optimized systems.

The goal is increasingly important as the slowdown in Moore’s Law makes
it more compelling to optimize systems around specific workloads. Such
workload optimized systems have hardware and/or software specifically
designed to run well for a particular application or application class.
Such systems include, but are not limited to traditional CPUs assisted
with accelerators (ASICs, FPGAs, GPUs), memory accelerators, I/O
accelerators, hybrid systems, and IT appliances. This workload optimized
system approach contrasts to the broad general purpose direction of
computing over many decades. However, the workload optimized systems
approach is growing in importance, as we see in systems from cellphones
to tablets to routers to game machines to Top500 supercomputers, and IT
appliances such as IBM’s DataPower and Netezza, and Oracle’s Exadata.

TOPICS

FastPath seeks to facilitate the exchange of ideas on performance modeling,
analysis and evaluation of workload optimized systems and seeks 6-page
research papers on a wide range of topics including, but not limited to:

o Workloads o GPUs
o Simulators o FPGAs
o Measured results on accelerated systems o ASIC Accelerators
o Industrial Experiences o Programming Models
o Analytical Techniques o Runtime Management Systems

SUBMISSIONS
Please make submissions here:
https://www.easychair.org/account/signin.cgi?conf=fastpath2012

Additional details are on our website:
https://sites.google.com/site/fastpath2012

KEY DATES:
Submission: February 9, 2012
Notification: March 12, 2012
Final Materials Due: March 23, 2012
Workshop April 1, 2012

ORGANIZERS
General Co-Chairs: David Brooks, Parijat Dube
Program Committee Co-Chairs: Erik Altman, Lieven Eeckhout

Publicity Chair: Peter Sweeney
Web Chair: Augusto Vega

PROGRAM COMMITTEE

Power Management of Multicore Systems Tutorial

Submitted by Robert Mullins
http://www.ece.cmu.edu/~sld/wiki/doku.php?id=shared:asplos
March 4, 2012

Submitted by Robert Mullins
http://www.ece.cmu.edu/~sld/wiki/doku.php?id=shared:asplos

Power Management of Multicore Systems:
Challenges, Approaches, and Recent Developments

ASPLOS 2012 Tutorial

Presenters
Radu Marculescu, Carnegie Mellon Univ.
Umit Y. Ogras, Intel Corp.
Siddharth Garg, Univ. of Waterloo

When/Where
This full-day tutorial will be held on Sunday, March 4, 2012.

Summary
Continuous technology scaling allows hundreds of processing cores to
run multiple heterogeneous applications concurrently on a single
chip. However, on-chip power consumption represents one of the main
bottlenecks in providing increased performance and enhanced
capabilities for such platforms. Indeed, increased power consumption
results not only in higher on-die temperature and reduced lifetime
reliability, but also leads to faster discharge of battery-powered
mobile devices. On-chip power management is therefore a critical
component of run time multicore optimization in presence of workload
and process-driven variations.

Power management techniques for single core processor are well
established. For example, current commercial products support numerous
sleep and performance states. However, orchestrating power management
policies for processors consisting of many cores interconnected by an
on-chip network is much less addressed. The multiple voltage and
frequency island (VFI) design style with support for dynamic voltage
and frequency scaling (DVFS) was recently proposed as an effective
paradigm to deal with application heterogeneity in highly parallel
multi-core platforms. Such systems are divided into multiple VFIs
where the voltage and frequency of each island in the system can be
set independently of all other islands and can be adapted at run-time
in response to temporal variations in application characteristics.

Starting from these overarching ideas, this tutorial addresses some
fundamental issues of designing effective and highly scalable DVFS
control algorithms able to regulate the voltage and frequency of the
VFIs in large multi-core platforms in response to application
heterogeneity and process-driven variations. In order to understand
the challenges and opportunities in this problem space, this tutorial
presents a comprehensive review of advanced design techniques for
multi-domain power and thermal management for high-performance
processors and low power systems-on-chip (SoCs). Finally, we discuss
fundamental limits on the performance of such control algorithms for
power management due to the challenges introduced by technology
scaling and process variations, particularly with respect to emerging
thousand core platforms.

Intended Audience
This tutorial is intended for an audience relatively new to the design
and optimization techniques for power- and variability-aware design
and management of multicore systems, with a minimal background in
micro-architecture, VLSI, and design automation techniques. The
presentation will introduce the relevant background material, give an
overview of the current state-of-the-art results in VFI and Globally
Asynchronous Locally Synchronous alternatives for designing the
communication infrastructure, and finally, talk about run-time
resource optimization and dynamic power management in the presence of
workload and parameter variations. The material discussed in this
tutorial is highly relevant to system designers and software
developers interested in the future of multi- and many-core systems.

Topics to be covered
Multicore Platforms Overview
Multi-voltage/clock domain server, cell phone, and media processors
Network-based communication and multiple voltage-frequency island (VFI) design
Industrial examples: Intel 80-core design, Intel SCC 48-core, Tilera, etc.
Control and Power Management: Algorithms and Implementation
Dynamic control of multi-VFI designs at micro-architecture/OS/application-level
Centralized, distributed, and hierarchical approaches for power and
thermal management
Implementation complexity and practical evaluations using Intel SCC platform
DVFS Control in Presence of Process Variations
Variation-aware dynamic power and thermal management
Power and thermal management for 3-D architectures
Scalability and workload challenges for thousand core platforms

HOT CHIPS 24

Submitted by Don Draper
http://www.hotchips.org
March 30, 2012

Submitted by Don Draper
http://www.hotchips.org

HOT CHIPS 24: A Symposium on High-Performance Chips

Stanford University, Palo Alto, California

August 2012

AUTHOR’S SCHEDULE
Deadline for submissions: March 30, 2012
Notification of acceptance: May 1, 2012
Deadline for final version: July 1, 2012

AREAS OF INTEREST:
* General Purpose Processor Chips
– High-Performance and Low-Power
– Multi-Core and Highly-Reliable Systems

* Mobile and Embedded Devices
– Graphics/Multimedia/Game
– SoC, Security, and DSP chips

* Communications and Networking
– Wireless LAN/WAN/PAN
– Network and IO Processors

* Other Chips
– FPGAs and FPGA-Based Systems
– Memory Technologies and Chipsets

* Software for multi-Core and Heterogeneous Systems
– Programming models, Runtime Systems
– Compilers and Operating Systems
– Performance and Power Debug and Evaluations

* Other Technologies
– Power and Thermal Management
– Packaging and Testing
– Display Technologies
– On-Chip Optics & Sensors
– Novel Computing Technologies

AUTHOR INFORMATION AND FORMAT
Presentations at HOT CHIPS are in the form of
30-minute talks in PowerPoint or .PDF. Presentation
slides will be published in the HOT CHIPS Proceedings.
Participants are not required to submit written
papers, but a select group will be invited to submit
a paper for inclusion in a special issue of IEEE Micro.

A limited number of Student Posters describing applied
research performed at a university will be accepted for
presentation at the conference. Student poster submissions
consist of 4 slides and a one-page summary. The most
outstanding poster will receive a Best Poster Award.

Submissions must specify “Presentation” or “Student
Poster” and consist of a title, extended abstract
(two pages maximum.), and the presenter’s contact
information (name, affiliation, job title, address,
phone(s), fax, and email). Please indicate whether
you have submitted, intend to submit, or have already
presented or published a similar or overlapping
submission to another conference or journal. Also
indicate if you would like the submission to be held
confidential. If so indicated, these submissions
remain confidential until the first day of the conference.

Submissions are evaluated by the Program Committee on
the basis of performance of the device(s), degree of
innovation, use of advanced technology, potential market
significance, and anticipated interest to the audience.
Research and software contributions will be evaluated
with similar criteria. To the extent that you are
describing a product, you must indicate its status
– design, development, tape out, silicon, shipping, etc.

Submit extended abstracts in plain text or .PDF, which
may contain figures, with a minimum 10-point font by
following instructions on the Hot Chips 24 website:
http://www.hotchips.org

Authors will be notified of acceptance decisions by May 1,
2012. Send questions relating to the program to the
program chairs at: program2012@hotchips.org
and questions relating to conference operation or
organization to the general chair, Larry Lewis, at:
info2012@hotchips.org

Sponsored by the Technical Committee on Microprocessors
and Microcomputers of the IEEE Computer Society and the
Solid State Circuits Society.

To view Hot Chips 2011 presentations and videos, which are
now open to the public, go to:
http://www.hotchips.org/archives/hc23

Program Committee Co-Chairs:
Christos Kozyrakis Stanford University
Rumi Zahir Intel

SYSTOR 2012

Submitted by Dan Tsafrir
http://systor.org/2012
February 13, 2012

Submitted by Dan Tsafrir
http://systor.org/2012

In cooperation with ACM (pending), IEEE, and USENIX

On behalf of the 2012 Annual International Systems and Storage
Conference (SYSTOR 2012), we invite you to submit original and
innovative papers. The conference will take place in June 4-6, 2012
Haifa, Israel; it is held in cooperation with ACM (pending), IEEE, and
USENIX.

SYSTOR has a broad scope, promoting experimental and practical
computer systems research encompassing the following topics:

* operating systems, computer architecture, and their interaction
* distributed, parallel, and cloud systems
* networking, mobile, wireless, peer-to-peer, and sensor systems
* runtime systems, compilers, and programming languages
* energy/power management
* file and storage systems
* security, privacy, and trust
* virtualization
* embedded and realtime systems
* fault tolerance, reliability, and availability
* deployment, usage, and experience
* performance evaluation and workload characterization

SYSTOR attempts to combine high-quality international systems research
of practical nature with interactions between the relevant industry
and academia communities. We therefore solicit paper submissions in
four separate tracks:

* full research papers
* short research papers
* highlight papers (a small number of exciting research results
accepted to a recent top-tier systems conference or journal;
accepted submissions will not be published in the proceedings)
* industry papers (describing the technologies behind real systems or
products and the; authors of accepted paper decide if they
would be included in the conference proceedings)

Proceedings including all (non-highlight) accepted papers will be
published by ACM. See more details at the conference web site
[http://systor.org/2012]. SYSTOR 2012 will host distinguished keynote
speakers, a posters session, and several social events at the
conference.

IMPORTANT DATES:

Paper submission: Feb 13, 2012 (11:59pm GMT)
Paper notification: Mar 26, 2012 (11:59pm GMT)
Camera-ready: Apr 14, 2012 (11:59pm GMT)

Highlights submission: Mar 12, 2012 (11:59pm GMT)
Highlights notification: Mar 26, 2012 (11:59pm GMT)

Poster submission: Apr 30, 2012 (11:59pm GMT)
Poster notification: May 07, 2012 (11:59pm GMT)

PROGRAM COMMITTEE CHAIRS

Dan Tsafrir, Technion
Erez Zadok, Stony Brook U.

PROGRAM COMMITTEE

Irfan Ahmad, VMware
Jonathan Appavoo, Boston U.
Yariv Aridor, Intel
Eitan Bachmat, Ben-Gurion U.
Mary Baker, HP Labs
Emery Berger, UMass Amherst
Tsahi Birk, Technion
Bill Bolosky, Microsoft Research
Andre Brinkmann, JGU Mainz
Randal Burns, Johns Hopkins U.
Dilma Da Silva, IBM Watson
Eyal DeLara, U. of Toronto
Peter Desnoyers, Northeastern U.
Shlomi Dolev, Ben-Gurion U.
Matan Erez, UT Austin
Yoav Etsion, BSC
Christof Fetzer, TU Dresden
Roy Fridman, Technion
Tal Garfinkel, VMware
Sharon Goldberg, Boston U.
Thomas Gross, ETH Zurich
Maurice Herlihy, Brown U.
Shivkumar Kalyanaraman, IBM India
Gokul Kandiraju, IBM Watson
Alexander Kipp, U. of Stuttgart
Avi Mendelson, Microsoft
Ethan Miller, UC Santa Cruz
Alan Mislove, Northeastern U.
Gilles Muller, Inria
Toshio Nakatani, IBM Tokyo
Yale Patt, UT Austin
Barbara Pernici, Politecnico di Milano
Donald Porter, Stony Brook U.
Raju Rangaswami, Florida Int’l U.
Luis Rodrigues, IST/INESC-ID
Neeraj Suri, TU Darmstadt
Sivan Toledo, Tel-Aviv U.
Eran Tromer, Tel-Aviv U.
Martin Vechev, ETH Zurich
Andy Wang, Florida State U.
Ric Wheeler, Redhat
Eran Yahav, Technion
Yuanyuan Zhou, UC San Diego

7th International Conference on High-Performance and Embedded Architectures and Compilers

Submitted by Philip Brisk
http://www.hipeac.net/conference
January 23 to January 25, 2012

Submitted by Philip Brisk
http://www.hipeac.net/conference

23-25 January 2012, Paris, France

Registration for HiPEAC 2012 is now open at:
http://www.hipeac.net/conference/paris/registration

———-

The HiPEAC conference aims to become the premier forum for experts in
computer architecture, programming models, compilers and operating
systems for embedded and general-purpose systems. Emphasis is given
on either cross-cutting research (embedded/high performance,
architecture/software stack, etc.) or innovative ideas (new
programming models, novel architecture approaches to cope with
technology constraints or new technologies, etc.).

The conference will be held in Paris, France, at Eurosites George V,
ideally located in the “Triangle d’Or” (Golden Triangle),
famous business district just South of the Champs Elyses:
http://www.eurosites.fr/en/Eurosites_George_V.php

The 7th HiPEAC conference will be a first in several innovative ways.

* HiPEAC’12 partners with ACM TACO to promote a “journal first” model:
http://www.hipeac.net/conference/paris/publicationmodel
http://www.hipeac.net/conference/paris/reviewers

* HiPEAC’12 is a unique research, innovation, training and networking
event:
http://www.hipeac.net/conference/paris/program

– 25-30 outstanding journal papers (ACM TACO)
The program of selected papers will be announced on November 23

– 17 workshops and 9 tutorials
http://www.hipeac.net/conference/paris/workshops%2526tutorials

– 1 industrial exhibit and 1 European research projects exhibit
http://www.hipeac.net/conference/paris/exhibits

– 1 large poster session
Invitation for every student and junior researcher to present a
poster

– 3 keynote speakers
from academia, industry, and the European funding agency

– 1 social event
Dinner cruise on the Seine river

Accomodation: there are several hotels close to the conference venue,
and hundreds of hotels within a few metro stops; since there is no
real low season in Paris, early registration is highly encouraged.
Recommendations will be updated regularly:

http://www.hipeac.net/conference/paris/accomodation

The HiPEAC 2012 conference is organized by Universiteit Ghent,
Belgium, and INRIA, France, with the support from the Seventh
Framework Programme (European Commission) and generous donations from
industry sponsors (list and acknowledgment in upcoming communications).

ACM SIGMETRICS/Performance 2012

Submitted by Y. Charlie Hu
http://www.sigmetrics.org/sigmetrics2012/
February 24, 2012

Submitted by Y. Charlie Hu
http://www.sigmetrics.org/sigmetrics2012/

Joint International Conference on Measurement
and Modeling of Computer Systems

Imperial College London
11 and 15 June 2012, London, United Kingdom

IMPORTANT DATES

* Tutorial and Workshop Submission Deadline: 24 February 2012 –
11:59pm GMT
* Notification of Decision: 9 March 2012

SCOPE AND AIMS

The 12th joint ACM SIGMETRICS / Performance conference solicits
proposals for Tutorials on Monday, 11 June 2012 and for Workshops on
Friday, 15 June 2012. If there is an excellent response, it is
possible for us to utilize Saturday, 16 June also, for example for any
planned full day events. The main conference will take place over
three days, 12-14 June 2012.

We welcome proposals related to the development and application of
state-of-the-art, broadly applicable, analytic, simulation and
measurement-based performance evaluation techniques – including
considerations of speed and scalability as well as reliability,
availability, sustainability and manageability of systems. We
encourage both theoretical contributions and submissions relating to
real world empirical studies or focusing on implementation and
experimental issues. Proposals relating to emerging, influential,
tangential areas are appropriate for both Tutorials and Workshops.

WORKSHOPS: Send proposals of 1-2 pages to the General Chair
(sigmeperf12-general-chair@imperial.ac.uk ). Please include the
proposed title, outline timetable including a brief description of the
topics in each session, potential invited speaker(s), the intended
audience, membership of the workshop organizing committee, and
intended arrangements for publication of the proceedings. Technical
management of the workshops will be autonomous but the fees and
registration will be handled by the main conference organizers.
Workshops are encouraged to seek sponsors from industrial contacts,
but this will in no way influence the selection of a proposal.

TUTORIALS: Send proposals of 1-2 pages for 90-minute or 3-hour
tutorials to the Tutorial Chair (sigmeperf12-tutorial-chair@imperial.ac.uk).
Include the proposed title, brief description of material, intended
audience, assumed background of attendees, and the name, affiliation,
contact information (email and phone) and brief biography of the
speaker(s). Tutorial overviews will be published in the main
conference proceedings.

ORGANIZERS:

GENERAL CHAIR:
Peter G. Harrison, Imperial College London, United Kingdom

TUTORIAL CHAIR:
Catalina Llado, Universitat de les Illes Balears, Spain

MAIN CONFERENCE PROGRAM CHAIRS:
Martin Arlitt, HP Labs, USA and University of Calgary, Canada
Giuliano Casale, Imperial College London, United Kingdom

FINANCE CHAIR:
Tony Field, Imperial College London, United Kingdom

PUBLICITY CHAIRS:
Y. Charlie Hu, Purdue University, USA
Samuel Kounev, KIT, Germany
Anirban Mahanti, NICTA, Australia

PROCEEDINGS CHAIR:
Urtzi Ayesta, BCAM and Ikerbasque, Spain

STUDENT ACTIVITIES CHAIR:
Jia Wang, AT&T Research, USA

LOCAL ARRANGEMENTS CHAIR / WEBMASTER:
Uli Harder, Imperial College London, United Kingdom