Call for Submissions: Intel Hardware Accelerator Research Program v2

Submission Deadline: Oct 21, 2016

Intel Corporation is pleased to announce the second round of the Hardware Accelerator Research Program, which will provide faculty with access to computer systems containing Intel microprocessors and an Altera Arria-10 FPGA in a multi-chip package (MCP) that incorporates Intel’s Accelerator Abstraction Layer Software in order to spur research in programming tools, operating systems, and innovative applications for accelerator-based computing systems.

In recent years, accelerators and coprocessors have attracted a great deal of interest, but the effort required to program heterogeneous systems has limited their impact. Current programming tools for these technologies require a great deal of domain-specific knowledge to reformulate algorithms for FPGA, partition a design between FPGA and CPU, and orchestrate data transfers between FPGA and CPU. In addition, portability still remains a challenge between different CPU+FPGA systems.

In order to improve the usability of these systems, Intel Corporation is interested in research into tools, applications, and methodologies that:
– Reduce the amount of effort required to map an application onto a coprocessor or accelerator
– Operating systems and schedulers that can automatically assign tasks to the most efficient hardware in a heterogeneous system
– Techniques to make applications portable across different hardware technologies
– Innovative applications that demonstrate the potential of heterogeneous systems.

To support and encourage this research, the Hardware Accelerator Research Program is making systems available to researchers that pair a 12-core Intel microprocessor with an Altera Arria10 FPGA.
Intel plans to build approximately 30 next-generation Hardware Accelerator Research Program systems (Broadwell + Arria10). These systems will be provided through two allocations:
1. To enable distributed-systems and data-center research, systems will be placed in centralized cluster installations in the U.S. and Europe (20 nodes total, 10 nodes per installation). The clusters will be made available via remote access to eligible program participants.
2. Several systems will be provided to researchers who need physical access to the platform based on their research agenda.

Researchers awarded access to Hardware Accelerator Research Program systems may also qualify for a license to use the Altera Quartus Design Software and other software tools free of charge.

Additionally, researchers awarded access to Hardware Accelerator Research Program systems will be invited to a series of workshops to be held at Intel campuses. The first workshop, to be held in late 2016 and will include tutorials on Intel’s Accelerator Abstraction Layer Software and provide basic training on how to develop hardware/software for the system. It will also give researchers an opportunity to discuss ideas for research using the Hardware Accelerator Research Program systems. Later workshops will provide a forum for researchers to present the results of their work and discuss opportunities for technology transfer with Intel researchers and product designers.

Topics of interest to this CFP include, but are not limited to:
1) Applications and algorithms, e.g.
– Studies of algorithm/application/library design, remapping, and tuning to exploit different aspects of the Hardware Accelerator Research Program MCP system, with a special focus on leveraging close accelerator coupling, cache coherency, and partial reconfiguration and the Accelerator Abstraction Layer
– Techniques to evaluate the applicability and efficiency of algorithms on different components of a reconfigurable heterogeneous architecture and to select the most effective hardware for different phases of an application
– Approaches to simplify and partially automate design, development, deployment, and/or performance characterization of applications to closely-coupled heterogeneous systems

2) Operating system integration and data center scaling, e.g.
– Operating system integration and scheduling techniques for dynamically reconfigurable accelerator-based systems, including shared access, virtualization, and migration of workloads
– Scaling approaches for cluster-level deployments of heterogeneous systems, including orchestration frameworks leveraging the platform’s re-configurability and the Accelerator Abstraction Layer’s service-oriented architecture

3) Domain-specific languages and high-level design, e.g.
– Languages and libraries for coprocessor and accelerator design and development, including domain-specific languages and other high-level design methods
– Analysis of domain- or language-specific characteristics that map to the Hardware Accelerator Research Program platform’s characteristics (i.e. partial re-configurability, close accelerator coupling, cache-coherent memory model).
– Automated HW/SW partitioning approaches that exploit the benefits of low-latency cache-coherent communication between CPU and accelerators

We welcome research proposals from academic institutions new to the program. At the same time, we specifically encourage participants in the first round of Hardware Accelerator Research Program to submit research proposals that build upon and extend the research performed within that program.

We also welcome and encourage applicants to include ideas on how to integrate reconfigurable heterogeneous platforms into their coursework/curriculum alongside their scientific research proposals.

ELIGIBILITY:
To be eligible for this program, proposers must be associated with a non-profit college, university, or research institution. U.S. export regulations prohibit the export of goods and services to Cuba, Iran, North Korea, Sudan and Syria. Therefore, residents or nationals of these countries are not eligible to participate. Proposer and their institution must not be listed on a denial order published by the U.S. Government or any other applicable Government. We welcome proposals from individual researchers, groups, and centers. As part of our evaluation of submitted proposals, we will decide whether successful proposals will be awarded access to the cluster installations closest to their location, or whether successful proposals will receive a single Hardware Accelerator Research Program system.

Proposals will be evaluated on technical merit, potential impact of the proposed research, the proposer’s ability to carry out the proposed research, and potential for collaboration with Intel researchers. Submitters of successful proposals will be expected to sign an agreement not to resell the donated equipment for a period of three years, to make results of their work available to Intel, and to participate on the program’s web forum by giving feedback about their experiences with the Hardware Accelerator Research Program platforms.

Each Recipient must acknowledge that donated equipment is subject to export controls under U.S. and other applicable Government laws and regulations. Recipient will comply with these laws and regulations governing export, re-export, import, transfer, distribution, use, and servicing of donated equipment, and agree to obtain all required Government authorizations. Recipient will not sell or transfer donated equipment to any entity listed on a denial order published by Government, or a country subject to sanctions, without first obtaining a license or authorization. Recipient will not use, sell, or transfer donated equipment for purposes prohibited by Government, including, without limitation, the development, design, manufacture, or production of nuclear, missile, chemical or biological weapons, unless authorized by a specific license. For more details on your export obligations, please visit http://www.intel.com/content/www/us/en/legal/export-compliance.html.

SUBMISSION INSTRUCTIONS:
Interested parties should submit a proposal of at most two 8.5″x11″ pages, in at least 10pt font, to hw_accelerator_research_program@intel.com by midnight Pacific Standard Time (UTC-8) on October 21, 2016. Proposals should be in PDF format, and should include the name and institution of the individual(s) requesting the platform, a description of the research that will be performed using the platform, and a brief summary of the requestor’s relevant previous work, if any.