Call for Papers: IEEE Micro Special Issue on Secure Architectures

Submitted by Lizy K John

Hardware is the bedrock on which all computing systems are built. Recently developed hardware ideas for enhancing software security from both academia and industry hold significant promise to improve software security. At the same time, recent hardware attacks on current commodity hardware has shown hardware to be a weak foundation for building secure systems. As we enter Post-Moore’s-Law era, there are significant questions surrounding what would make security techniques more practical.

IEEE Micro seeks articles on hardware enhanced security and privacy seeks papers on a range of topics, including but not limited to:
– Microarchitectural side-channel attacks and defenses; fault attacks and defenses
– Architectures for key management, attestation, patching and updating firmware and software
– Architectures for isolation and compartmentalization/tamper-proof execution
– Architectures for metadata based approaches to security and privacy
– Architectures for introspection, debugging, and root cause analysis
– Microarchitectural techniques for malware detection and adversarial resistance
– Secure storage, e.g. using emerging non-volatile memories
– Metrics and evaluation methodologies for secure architectures including languages/frameworks for early design stage security exploration
– Approaches to Post-Moore’s-Law security (secure-accelerator designs will ideally be in the context of an end-to-end application)
– Microarchitectural design patterns for security
– Social processes for creating security in large scale designs
– Secure architectures for domains such as voting machines, implantable medical devices, automotives, Internet-of-Things, and data centers.

IMPORTANT DATES:
Submissions due: March 4, 2019
Initial notifications: Apr 4, 2019
Revised papers due: May 4, 2019
Final notifications: May 10, 2019
Final versions due: May 24, 2019
Publication date: July/Aug 2019

SUBMISSION GUIDELINES:
Please see the Write for Us page and the general author guidelines for more information. Please submit electronically through ScholarOne Manuscripts, selecting this special-issue option.

Questions?
Contact the guest editors at Simha Sethumadhavan (simha@columbia.edu) and Mohit Tiwari (tiwari@austin.utexas.edu) or the editor-in-chief at Lizy John (ljohn@ece.utexas.edu).

Call for Papers: IEEE Micro Special Issue on Machine Learning Acceleration

Submitted by Lizy K John

In recent years, machine learning (ML) has become one of the most important pillars of computing industry, driven by the remarkable advances in the theory and their extensive use in real-world applications. To accomplish the phenomenal success, research and industry communities have exploited acceleration solutions, which deliver orders-of-magnitude greater performance and efficiency by specializing hardware and software for ML. As the importance of ML in the emerging applications increases, the ML accelerators have become the critical component of every modern computing system–from data centers to mobile/IoT devices. The community has not only extensively explored new architectures to improve the performance and efficiency of these accelerators, but also put significant effort on raising usability and programmability by offering programming models, high-level language, compiler, runtime software, and tools.

This special issue of IEEE Micro will explore academic and industrial research on all topics, which relate to hardware and software acceleration solutions, specialized for ML. Such topics include, but are not limited to:
– New design methodologies for ML-centric or ML-aware hardware accelerators
– New microarchitecture designs of hardware accelerators for ML
– ML workload acceleration on existing accelerators such as GPU, FPGA, CGRA, or ASIC
– New compiler and optimization techniques for ML acceleration
– New tools to design/build/optimize/debug the accelerated systems
– New ML modeling, optimization, quantization, and compression for acceleration
– Acceleration for new ML algorithms
– ML acceleration for edge computing and IoT
– ML acceleration for cloud computing
– Comparison studies of different acceleration techniques
– Survey and tutorial studies of ML acceleration

IMPORTANT DATES:
Submissions due: April 12, 2019
Initial notifications: May 22, 2019
Revised papers due: June 21, 2019
Final notifications: June 28, 2019
Final versions due: July 12, 2019
Publication date: Sept/Oct 2019

SUBMISSION GUIDELINES:
Please see the Write for Us page and the general author guidelines for more information. Please submit electronically through ScholarOne Manuscripts, selecting this special-issue option.

Questions?
Contact the guest editors at Hadi Esmaeilzadeh (hadi@eng.ucsd.edu) and Jongse Park (jspark@gatech.edu) or the editor-in-chief at Lizy John (ljohn@ece.utexas.edu).