Call for Papers: Serverless Systems, Applications and Methodologies (SESAME) Workshop
https://sesame23.github.io
Submitted by Boris Grot

Serverless Systems, Applications and Methodologies (SESAME) Workshop
co-located with EuroSys 2023
Rome, ItalyMay 8, 2023
https://sesame23.github.io

The 1st Workshop on SErverless Systems, Applications and MEthodologies (SESAME) aims to bring together industry and academia to discuss serverless computing and emerging cloud computing models. The goal of the workshop is to foster the discussion on the design and implementation of serverless platforms (i.e., how to deploy, optimize, and manage serverless infrastructure), and leverage their full potential (i.e., what types of applications and eco-systems of services need to exist to support serverless computing). The workshop is designed to ensure that industry and academia come together to discuss early ideas and promote cutting-edge research.

The workshop welcomes short papers (up to 6 pages) and work-in-progress submissions (2 pages).

Submissions due: February 27, 2023
Author notification: March 27, 2023

ORGANIZERS: Dmitrii Ustiugov (NTU Singapore), Rodrigo Bruno (University of Lisbon), Antonio Barbalace (University of Edinburgh) Pedro Fonseca (Purdue University), Boris Grot (University of Edinburgh)

For further details, including topics of interest and submission guidelines, visit https://sesame23.github.io.

Call for Papers: RAGE 2023 @ CPS-IoT Week
https://rage2023.github.io/
Submitted by Miguel Gutiérrez Gaitán | CISTER Research Centre

RAGE 2023
2nd Workshop on Real-time And intelliGent Edge computing
https://rage-workshop.github.io/2023/
May 9, 2023, San Antonio, Texas, USA
co-located with the CPS-IoT Week 2023
Technically co-sponsored by EMSIG and IEEE Future Networks

Important Dates

Submission deadline: February 1st, 2023 (Anywhere on Earth)
Notification to authors: March 1st, 2023
Workshop date: May 9th, 2023

Workshop Proceedings

Accepted papers will be published by the ACM Digital Library.

About

The edge computing paradigm is becoming increasingly popular as it facilitates real-time computation, reduces energy consumption and carbon footprint, and fosters security and privacy preservation by processing the data closer to its origin, thereby drastically reducing the amount of data sent to the cloud. On the application side, there is a growing interest in using edge computing as a key pillar to support decentralized artificial intelligence by implementing federated learning and adaptive deep learning inference at the edge. However, many edge applications tightly interact with the surrounding environment and are required to deliver a result (e.g., perform actuation or send a message through a 5G network) within a predefined deadline. Therefore, a key requirement in edge computing is the need to be predictable across the edge-to-cloud continuum while also efficiently utilizing the system resources.

However, meeting the above requirements is non-trivial. Modern edge devices can be very diverse, ranging from hand-held devices to large in-premise servers, and can include complex embedded platforms with multiple heterogeneous cores and hardware accelerators such as GPUs, TPUs, and FPGAs. This complexity introduces considerable challenges when trying to guarantee timing requirements of real-time applications: for example, due to scheduling policies implemented by the hardware accelerators (often not publicly disclosed by vendors) or due to the memory contention experienced by applications when accessing main memory concurrently in a multi-core setup. Secondly, network transmission time (TSN over Ethernet to 5G links) can lead to variability in the end-to-end latencies incurred by edge applications. Thirdly, a distributed infrastructure is naturally exposed to security attacks potentially able to compromise the execution of one or multiple devices or threaten their corresponding communications.

Furthermore, the operating system (OS) also plays a crucial role in enabling the edge computing paradigm, but quite often at the price of increasing the difficulty in deriving timing guarantees: for example, think of a complex deep neural network that needs to leverage a Linux-based OS (which is far more complicated than a real-time operating system), since it provides all the software stacks (e.g., TensorRT) and device drivers to interact with NVIDIA GPUs.

The complexity of the problem is further increased by the usage of middleware frameworks, which simplify the development of applications, but at the cost of introducing scheduling policies in addition to the one offered by the underlying operating system, hindering predictability. Some relevant examples are ROS, in the context of robotics, TensorFlow for artificial intelligence, TensorRT for efficient deep neural network inference on GPUs, and others. Virtualization technologies are also becoming crucial in implementing the edge paradigm, but again, at the expense of creating a more complex operating environment, where guaranteeing temporal properties is a challenging endeavor. These problems are common to many application domains, including cyber-physical systems, future-generation autonomous driving applications, robotics, Industry 4.0, smart buildings, and more.

Workshop topics include, but are not limited to:

• Real-time edge computing
• QoS mechanisms for temporal isolation in light-weight virtualization mechanisms (Docker, WebAssembly)
• Mechanisms for end-to-end latency guarantees in the edge-to-cloud continuum
• Methods for functional decomposition between the edge and cloud
• Predictability in middleware frameworks (ROS, TensorFlow, TensorRT, and more)
• Real-time edge computing use cases
• Real-time network protocols for edge computing
• Real-time distributed artificial intelligence
• Resource scheduling and allocation in embedded real-time systems
• Predictable and efficient parallel applications
• Energy- and power-aware allocation in the edge-to-cloud Continuum
• Timing predictability for artificial intelligence
• Security and safety verification techniques for edge computing and infrastructures
• Software/hardware/communication mechanisms, analysis, and/or tools supporting security in edge computing or in critical infrastructures.

Workshop Format

The workshop will include the following three types of contributions:

• Submissions of workshop papers, which will be peer-reviewed by the workshop’s technical program committee. Accepted papers will be presented with an envisioned time slot of 15 minutes (including the Q&A).
• Invited talks from expert speakers from both academia and industry, with slots of 30-45 minutes, depending on the number of talks.
• An open discussion that will include experts both from academia and industry as well as the workshop’s audience to further support the discussion and community building in the workshop.

We plan for an 8 hours workshop.

Organizers

Technical Program Co-Chairs

Dr. Francesco Restuccia,
University of California San Diego, CA, USA

Dr. Inés Álvarez,
Mälardalen University, Västerås, Sweden

Prof. Matthias Becker,
KTH Royal Institute of Technology, Sweden

Steering Committee

Prof. Daniel Casini,
Scuola Superiore Sant’Anna, Italy

Dr. Dakshina Dasari,
Robert Bosch GmbH, Germany

Prof. Matthias Becker,
KTH Royal Institute of Technology, Sweden

Web Chair
Gabriel Serra,
Scuola Superiore Sant’Anna, Pisa, Italy

Publicity Chair
Miguel Gutiérrez Gaitán,
Andrés Bello University (UNAB), Chile
CISTER Research Centre, Porto, Portugal

Call for Papers: ASPLOS’23 Young Architect Workshop
https://web.mit.edu/yarch2023/
Submitted by Suvinay Subramanian

YArch 2023: The Fifth Young Architect Workshop
March 26, 2023 (Co-located with ASPLOS)
Website: https://web.mit.edu/yarch2023/

Submissions Due: January 27, 2023

YArch is a workshop for junior researchers with an interest in computer architecture (broadly defined) who may have early research ideas they’d like to get feedback on. The goal of YArch is to facilitate contacts between junior computer architecture researchers and more senior researchers in the field. It is also an opportunity to get feedback on early research ideas. 

Two-page double-blind submissions should describe the scope of the problem, the proposed idea/solution, the intended evaluation methodology, and related work.

Topics of interest include, but are not limited to:

• Datacenter systems
• Hardware acceleration
• Memory hierarchy
• Virtualization
• Security
• Microarchitecture
• GPUs
• Parallel architectures
• Emerging technologies

To qualify, a researcher must have completed fewer than 3 years of graduate studies. YArch is primarily targeting early graduate students in computer science/engineering, but exceptional undergrads with research experience are also welcome to submit ideas. We intend to cover the travel and registration costs for presenters of accepted submissions.

The workshop is not a venue for publication; there will be no published proceedings. Simultaneous submissions are allowed from the perspective of YArch.

More information can be found on the workshop’s website: https://web.mit.edu/yarch2023/
For any questions, please contact us at youngarchitectw@gmail.com

Organizers

Dimitrios Skarlatos, CMU
Suvinay Subramanian, Google
Mengjia Yan, MIT

Important dates

Paper registration deadline: January 20th, 2023
Paper submission deadline: January 27th, 2023
Notification of acceptance: February 22nd, 2023
Workshop date: March 26th, 2023 (Co-located with ASPLOS)

Call for Papers: HCM 2023 (HPCA Workshop)
https://hcm-workshop.github.io
Submitted by Hyeran Jeon

The memory systems are becoming heterogeneous and composable. Increasing memory heterogeneity and composability is beneficial to increase memory capacity and improve memory utilization in a cost-effective way, and reduce total cost of ownership. The heterogenous and composable memory (HCM) provides a feasible solution to support terabyte- or petabye-scale big memory systems, meeting the performance and efficiency requirements of emerging big-data applications.

However, building and using HCM is challenging. We must answer a series of questions, such as how to interconnect memory components based on different memory technologies (e.g., using compute express link or CXL), how to organize those memory components in HCM for high performance, how to evolve (or even revolutionize) existing system software that traditionally handles homogeneous memory systems with small capacity, and how to build memory abstract and program constructs for HCM management. In general, HCM brings many unique opportunities and challenges, and we lack knowledge on how to build and use HCM.

The workshop on HCM aims to deepen our knowledge on HCM and bring together researchers in academia and industry to share early discoveries, successful examples, and opinions on opportunities and challenges regarding HCM.

Submission Guidelines

All submissions should be made electronically through the Easychair website. Submissions must be double blind, i.e., authors should remove their names, institutions or hints found in references to earlier work. When discussing past work, they need to refer to themselves in the third person, as if they were discussing another researcher’s work. Furthermore, authors must identify any conflict of interest with the PC chair or PC members. Each paper is a 2-page abstract, using IEEE conference format. The page limit includes figures, tables, and your appendices, but does not include references, for which there is no page limit. Papers should be submitted in PDF format. We kindly refer authors to the necessary template.

We encourage researchers from all institutions to submit their work for review. Preliminary results of interesting ideas and work-in-progress are welcome. A paper accepted to HCM’23 would not preclude its future publication in a major conference. Submissions that are likely to generate vigorous discussion will be favored!

Submission Timeline

Submission link : https://easychair.org/conferences/?conf=hcm23
Submission deadline : December 12, 2022
Notification : January 25, 2023

List of Topics

• HCM architectures, such as interconnect technologies (such as CXL), memory pooling, and memory disaggregation;
• Operating system designs to support HCM, such as memory profiling methods, page migration and allocation, and huge pages;
• Characterization of HCM from the perspectives of performance, energy consumption, and reliability;
• Use cases for HCM, such as deep-learning training and scientific applications;
• Tools (such as simulators or platforms) for HCM research and engineering;
• New programming models and program constructs to enable easy programming of HCMs;
• HCM in virtualization environments;
• New algorithms and performance models to manage and use HCM;
• Runtime systems to manage HCM

Committees

Program Committee

• Cyril Guyot, HGST
• Youngjae Kim, Sogang University
• Michael Lang, Los Alamos National Laboratory
• Jason Lowe-Power, University of California Davis
• Antonio J. Peña, Barcelona Supercomputing Center (BSC)
• Frank Mueller,  North Carolina State University
• Kwangsik Shin, SK Hynix
• Jishen Zhao, University of California San Diego

Organizing committee

• Dong Li, University of California Merced
• Hyeran Jeon, University of California Merced
• Jie Ren, College of William and Mary

Contact

All questions about submissions should be emailed to Jie Ren (jren03@wm.edu)

Call for Papers: 8th Workshop on Energy Efficient Machine Learning and Cognitive Computing
https://www.emc2-ai.org/aaai-23
Submitted by Sushant Kondguli

Transformers are the foundational principles of large deep learning language models. Recent successes of Transformer-based models in image classification and action prediction use cases indicate their wide applicability. In this workshop, we want to focus on the leading ideas using Transformer models such as PALM from Google. We will learn what have been their key observations on performance of the model, optimizations for inference and power consumption of both mixed-precision inference and training.

The goal of this Workshop is to provide a forum for researchers and industry experts who are exploring novel ideas, tools, and techniques to improve the energy efficiency of machine learning and deep learning as it is practiced today and would evolve in the next decade. We envision that only through close collaboration between industry and the academia we will be able to address the difficult challenges and opportunities of reducing the carbon footprint of AI and its uses. We have tailored our program to best serve the participants in a fully digital setting.  Our forum facilitates active exchange of ideas through

• Keynotes, invited talks and discussion panels by leading researchers from industry and academia
• Peer-reviewed papers on latest solutions including works-in-progress to seek directed feedback from experts
• Independent publication of proceedings through IEEE CPS

We invite full-length papers describing original, cutting-edge, and even work-in-progress research projects about efficient machine learning. Suggested topics for papers include, but are not limited to:

• Neural network architectures for resource constrained applications
• Efficient hardware designs to implement neural networks including sparsity, locality, and systolic designs
• Power and performance efficient memory architectures suited for neural networks
• Network reduction techniques – approximation, quantization, reduced precision, pruning, distillation, and reconfiguration
• Exploring interplay of precision, performance, power, and energy through benchmarks, workloads, and characterization
• Simulation and emulation techniques, frameworks, tools, and platforms for machine learning
• Optimizations to improve performance of training techniques including on-device and large-scale learning
• Load balancing and efficient task distribution, communication and computation overlapping for optimal performance
• Verification, validation, determinism, robustness, bias, safety, and privacy challenges in AI systems

The proceedings from previous instances have been published through the prestigious IEEE Conference Publishing Services (CPS) and are available to the community via IEEE Xplore. In each instance, IEEE conducted independent assessment of the papers for quality.

Call for Papers: 5th Workshop on Accelerated Machine Learning (AccML) at HiPEAC 2023
https://accml.dcs.gla.ac.uk/
Submitted by José Cano

5th Workshop on Accelerated Machine Learning (AccML)
Co-located with the HiPEAC 2023 Conference
(https://www.hipeac.net/2023/toulouse/)
January 18, 2023
Toulouse, France

The remarkable performance achieved in a variety of application areas (natural language processing, computer vision, games, etc.) has led to the emergence of heterogeneous architectures to accelerate machine learning workloads. In parallel, production deployment, model complexity and diversity pushed for higher productivity systems, more powerful programming abstractions, software and system architectures, dedicated runtime systems and numerical libraries, deployment and analysis tools. Deep learning models are generally memory and computationally intensive, for both training and inference. Accelerating these operations has obvious advantages, first by reducing the energy consumption (e.g. in data centers), and secondly, making these models usable on smaller devices at the edge of the Internet. In addition, while convolutional neural networks have motivated much of this effort, numerous applications and models involve a wider variety of operations, network architectures, and data processing. These applications and models permanently challenge computer architecture, the system stack, and programming abstractions. The high level of interest in these areas calls for a dedicated forum to discuss emerging acceleration techniques and computation paradigms for machine learning algorithms, as well as the applications of machine learning to the construction of such systems.

Links to the Workshop pages

Organizers: https://accml.dcs.gla.ac.uk/
HiPEAC: https://www.hipeac.net/2023/toulouse/#/program/sessions/8030/

Topics of interest include (but are not limited to):

– Novel ML systems: heterogeneous multi/many-core systems, GPUs, FPGAs;
– Software ML acceleration: languages, primitives, libraries, compilers and frameworks;
– Novel ML hardware accelerators and associated software;
– Emerging semiconductor technologies with applications to ML hardware acceleration;
– ML for the construction and tuning of systems;
– Cloud and edge ML computing: hardware and software to accelerate training and inference;
– Computing systems research addressing the privacy and security of ML-dominated systems.

Submission
Papers will be reviewed by the workshop’s technical program committee according to criteria regarding the submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions in the context of accelerating machine learning. Research papers, case studies, and position papers are all welcome.

In particular, we encourage authors to submit work-in-progress papers: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and spark productive discussions.

The workshop does not have formal proceedings.

Important Dates
Submission deadline: November 30, 2022
Notification of decision: December 15, 2022

Organizers
José Cano (University of Glasgow)
Valentin Radu (University of Sheffield)
José L. Abellán (Catholic University of Murcia)
Marco Cornero (DeepMind)
Dominik Grewe (DeepMind)
Ulysse Beaugnon (Google)

Call for Papers: FastPath: Workshop on Performance Analysis of Machine Learning Systems
https://fastpathconference.github.io/FastPath2022/
Submitted by Erik Altman

Call for Papers
FastPath: Workshop on Performance Analysis of Machine Learning Systems
In conjunction with MICRO 2022

FastPath 2022 brings together researchers and practitioners involved in cross-stack hardware/software performance analysis, modeling, and evaluation for efficient machine learning systems. Machine learning demands tremendous amount of computing. Current machine learning systems are diverse, including cellphones, high performance computing systems, database systems, self-driving cars, robotics, and in-home appliances. Many machine-learning systems have customized hardware and/or software. The types and components of such systems vary, but a partial list includes traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators, hybrid systems, converged infrastructure, and IT appliances. Designing efficient machine learning systems poses several challenges.

These include distributed training on big data, hyper-parameter tuning for models, emerging accelerators, fast I/O for random inputs, approximate computing for training and inference, programming models for a diverse machine-learning workloads, high-bandwidth interconnect, efficient mapping of processing logic on hardware, and cross system stack performance optimization. Emerging infrastructure supporting big data analytics, cognitive computing, large-scale machine learning, mobile computing, and internet-of-things, exemplify system designs optimized for machine learning at large.

Topics

FastPath seeks to facilitate the exchange of ideas on performance analysis and evaluation of machine learning/AI systems and seeks papers on a wide range of topics including, but not limited to:

• Workload characterization, performance modeling and profiling of machine learning applications
• GPUs, FPGAs, ASIC accelerators
• Memory, I/O, storage, network accelerators
• Hardware/software co-design
• Efficient machine learning algorithms
• Approximate computing in machine learning
• Power/Energy and learning acceleration
• Software, library, and runtime for machine learning systems
• Workload scheduling and orchestration
• Machine learning in cloud systems
• Large-scale machine learning systems
• Emerging intelligent/cognitive systems
• Converged/integrated infrastructure
• Machine learning systems for specific domains, e.g., financial, biological, education, commerce, healthcare

Submission

Prospective authors must submit a 2-4 page extended abstract electronically on EasyChair

Authors of selected abstracts will be invited to give a 30-min presentation at the workshop.

Key Dates

• Submission: September 9, 2022
• Notification: September 19, 2022

Organizers

• General Chair: Erik Altman (IBM)
• Program Chairs: Parijat Dube (IBM), Nandita Vijaykumar (University of Toronto)
• Web Chair: Gavin Guan (University of Toronto)

Call for Papers: RoboARCH (co-located with MICRO 2022)
https://sites.google.com/g.harvard.edu/roboarch2022
Submitted by Sabrina Neuman

Call for Abstracts and Participation: RoboARCH at MICRO 2022
Workshop on Robotics Acceleration with Computing Hardware (RoboARCH)
October 2, 2022 in Chicago, IL
Co-located with the IEEE/ACM International Symposium on Microarchitecture (MICRO)

Robotics is pushing the limits of conventional computing. Autonomous robots must operate untethered in dynamic and unpredictable environments, requiring many robotics software applications to run online in real-time. Conventional CPU systems are proving unable to deliver the high performance needed by essential latency-critical robotics applications. This is a call to action for researchers across academia and industry: we must leverage nontraditional computing hardware (e.g., custom accelerator ASICs, FPGAs, and GPUs) and navigate enormous design spaces spanning across algorithms, hardware, and physical robot parameters in order to design new high performance systems enabling critical tasks in robotics. This workshop aims to gather pioneers and innovators working at the intersection of robotics and computer architecture, and to provide an introduction to this exciting emerging field to the computer architecture community.

We welcome submission of 1-page abstracts on any topic related to accelerating robotics applications (e.g., computer vision, mapping, localization, motion planning, control, and end-to-end learning, for all robotics systems) using nontraditional computing hardware (e.g., ASICs, FPGAs, GPUs), as well as real-time, distributed, cloud, and edge computing systems that might be leveraged by robotics platforms. We especially encourage early work, and work-in-progress.

Accepted authors will be invited to present a 2-minute single-slide lightning talk during the main program and a poster at the poster sessions. Submissions are anonymous, so please remove author names and all identifying information from the submission. See submission instructions on the workshop website: https://sites.google.com/g.harvard.edu/roboarch2022/call-for-abstracts

Abstract Submission Deadline: September 19, 2022 (extended)
Author Notification: September 23, 2022
Workshop Date: October 2, 2022

Call for Papers: DISCC 2022 (Co-located with MICRO)
https://disccworkshop.org/
Submitted by David Trilla

Recent papers from Meta (Facebook) and Google have created a major concern about data integrity in large-scale computing in cloud data centers. The term “mercurial cores” has been coined to refer to errant processor cores that have been clearly diagnosed as being the source of generating silent data errors – and recent panels (as referred to above) have brought together experts from cloud service providers and processor chip designers with the objective of raising awareness of this acute problem, and also encouraging leading-edge research to devise affordable chip and system-level mitigation solutions. In addition to such data integrity concerns, the rise of data security and privacy breaches in cloud computing environments has accelerated research and development of practical solutions that enable computing with encrypted data (e.g., advanced cryptographic methods like Fully Homomorphic Computing or FHE); e.g., recent papers.

This workshop (DISCC-2022) proposes to bring together aspects of data integrity and security in a single, unified forum. The workshop will comprise a keynote speech, several contributed papers and, time permitting, a closing panel session involving leading edge experts in data integrity and security in a hyper-scale cloud computing setting. Potential speakers are encouraged to submit an extended abstract (1-2 pages) highlighting the key contributions in the light of the above-stated technical scope of the problem. Solution approaches at the algorithm, software/firmware and/or hardware level are encouraged for early dissemination and discussion in a workshop setting.

Topics of interest include but are not limited to:

• Testing (including detection and/or diagnosis) of silent data errors (SDEs) for plaintext and/or HE-mode ciphertext computation.
• Detection and mitigation of malicious attacks that can lead to SDEs.
• Privacy-preserving data-secure computation: novel software and/or hardware solutions.
• Characterization of HE workloads for “discovery” of hardware acceleration primitives.
• Simulation and/or emulation based modeling methods to evaluate DISCC domain software-hardware solutions.
• Modeling of cloud-edge solutions for specific safety-, security- and/or privacy-critical applications: e.g., autonomous vehicles, internet banking, credit card fraud detection, etc.

Call for Papers: WDDSA at MICRO 2022
https://www.escalab.org/wddsa2022
Submitted by Christopher Torng