Call for Papers: ISCA 2024
https://www.iscaconf.org/isca2024/submit/papers.php
Submitted by Xiaochen Guo

The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. In 2024, the 51^st edition of ISCA will be held in Buenos Aires during June 29 – July 3, 2024

Call for Papers: FPGA 2024
https://www.isfpga.org/
Submitted by Aman Arora

Call for Papers – FPGA 2024
32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
March 3 – 5, 2024
Website: https://isfpga.org
Submission site: https://fpga24.hotcrp.com (now live)
Abstracts Due:   October 6, 2023
Submissions Due:  October 13, 2023

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2024, the 32nd edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.

Paper Submissions (with and without Artifacts)

We solicit research papers related to the following areas:

• FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.

• FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory or nano-scale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability.

• CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.

• High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.

• FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.

• Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.

Research submissions can be in either of two categories:

• Regular —  at most 10 pages (excluding references), for a regular presentation at the conference.

• Short — at most 6 pages (excluding references), for a brief presentation.

A paper submitted as either regular or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).

Submission Process

Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/. LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LaTeX link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract and paper submissions in PDF must be received by 11:59 PM AoE (Anywhere-on-Earth time zone).

Submissions will be considered for acceptance as regular or short papers. A paper submitted to the regular or short category will only be considered in that category. Regular or short submissions will also be considered for acceptance as a poster. Once a paper has been submitted, its authorship list is considered to be fixed and final.

By submitting articles to an ACM Publication, authors are hereby acknowledging that they and their co-authors are subject to all ACM Publications Policies (https://www.acm.org/publications/policies), including ACM’s new Publications Policy on Research Involving Human Participants and Subjects (https://www.acm.org/publications/policies/research-involving-human-participants-and-subjects). Alleged violations of this policy or any ACM Publications Policy will be investigated by ACM and may result in a full retraction of their paper, in addition to other potential penalties, as per ACM Publications Policy.

Authors should ensure that they and their co-authors obtain an ORCID ID (https://orcid.org/register), so that they can complete the publishing process for accepted papers. ACM has been involved in ORCID from the start and ACM has recently made a commitment to collect ORCID IDs from all of their published authors (https://authors.acm.org/author-resources/orcid-faqs). The collection process has started and will roll out as a requirement throughout 2023. ACM is committed to improve author discoverability, ensure proper attribution, and contribute to ongoing community efforts around name normalization; authors’ ORCID ID will help in these efforts.

Double Blind Policy

The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. References to the authors’ prior work should be made in the third person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as “Removed for blind review,” but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission. When necessary, authors should cite widely-available Open Source software website(s) without claiming ownership. Grant numbers and other government markings should also be blinded during the review process. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged. Similarly, if a paper can be unblinded by active search, this is not considered to undermine the spirit of the double-blind review. However, there are resources to blind open-source repositories for review, including: https://github.com/tdurieux/anonymous_github.

If you have questions about how to meet these guidelines, please contact the program chair before the submission deadline.

Reviewer Conflict Policy

During paper submission, all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is left undeclared or a nonexistent conflict is declared in an attempt to manipulate the review process, the submission may be rejected.

For more information about the ACM Conflict of Interest Policy, see: https://www.acm.org/publications/policies/conflict-of-interest

Originality of Submissions

Papers submitted are guaranteed by the authors to be unique manuscripts and not previously published, currently accepted or under consideration for acceptance at another venue. They cannot be substantially similar to any other current/future conference, journal, or workshop submission(s) unless the content appeared at a venue that does not have archived proceedings.

Rebuttal Process

The conference review process includes a rebuttal phase for authors to provide an optional response to reviewers’ questions and comments. This information is considered during the final deliberation process.

Author participation

For inclusion in the ACM digital library, at least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel (more instruction will be available after the camera-ready submission).

Best Paper Award

Authors of this year’s best manuscripts will be eligible for the conference’s best paper awards. They will also be invited to extend their work for consideration in a special issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS).

Artifact Evaluation

The conference will allow authors to submit accompanying artifacts for their paper submissions for evaluation. This process will allow ACM recognized badges to be associated with the final publication. The inclusion of artifacts with a submission is not required for a paper submission nor will any preference be given to submissions with artifacts over those without. Papers and artifacts will be subjected to separate and independent review processes. Artifact evaluation must NOT interfere with the double blind reviewing process of their accompanying papers, so all accompanying links in the paper to the artifacts should be blinded. All authors will be required at the time of paper submission to indicate if there will also be associated artifacts for evaluation. If artifacts will be included, a descriptor of their nature will be required. 

For more information, see: https://isfpga.org/artifact-evaluation/

Diversity and Inclusion

The open exchange of ideas and the freedom of thought and expression are central to the aims and goals of the conference. The organizers aim and commit to providing a harassment-free accessible and pleasant conference experience with equity in rights for all. We want every participant to feel welcome, included and safe at the conference.

For more information, see: https://isfpga.org/statement-on-diversity-and-inclusion/

Important Dates

All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12)

Visa Application

Prospective authors and participants requiring a B-2 visa to enter the US should check the visa appointment wait time using this link: https://travel.state.gov/content/travel/en/us-visas.html, and consider applying IMMEDIATELY for a visa, scheduling an appointment in December 2023. By then, notification of acceptance will have been sent out (if applicable), registrations will have been opened, and ACM will be able to deliver letters of support. To the best of our knowledge, the letter of support will never be required before the interview.

Organizing Committee

Call for Papers: Bench 2023
https://www.benchcouncil.org/bench2023/index.html
Submitted by Chen Liu

CALL FOR PAPERS
The 15th BenchCouncil International Symposium on Benchmarking, Measuring and Optimizing (Bench 2023)
In conjunction with Federated Intelligent Computing and Chip Conference (FICC 2023)
https://www.benchcouncil.org/bench2023/index.html

Paper Submission Due (full and short papers): Aug 21, 2023, 11:59 PM AoE
Notification: September 30, 2023, 11:59 PM AoE
Final Papers Due: October 31, 2023, 11:59 PM AoE
Conference Date: December 3-5, 2023
Venue: Sanya, China.

Please note that citizens from up to 59 nations can visit Sanya without a Visa from the Chinese Government. Sanya is a beautiful seaside city, well known as Hawaii in China.

Submission website: https://bench2023.hotcrp.com/

Organization

General Co-Chairs
* Rakesh Agrawal, Data Insights Laboratories, San Jose, CA, USA
* Aoying Zhou, East China Normal University

Program Co-Chairs
* Weining Qian, East China Normal University
* Sascha Hunold, TU Wien, Austria

Program Vice-Chairs
* Biwei Xie, Institute of Computing Technology, CAS
* Kai Shu, Illinois Institute of Technology

Web Chair
* Jiahui Dai, BenchCouncil

Publicity Chairs
* Weicong Chen, University of California, Merced
* Dipti Shankar, SAP Labs, Munich

Technical Program Committee
* Ahmad Ghazal, PingCAP
* Bartlomiej Przybylski, Adam Mickiewicz University, Poznań
* Ben Blamey, Uppsala University
* Benson Muite, University of Tartu
* Bin Ren, College of William & Mary
* Bo Wu, Colorado School of Mines
* Chen Zheng, Institute of Software, Chinese Academy of Sciences
* Cheol-Ho Hong, Chung-Ang University
* Chunjie Luo, Institute of Computing Technology, Chinese Academy of Sciences
* David Boehme, Lawrence Livermore National Laboratory
* Florina Ciorba, University of Basel
* Francieli Boito, University of Bordeaux
* Guangli Li, Institute of Computing Technology, Chinese Academy of Sciences
* Gwangsun Kim, POSTECH
* Joseph Schuchart, University of Tennessee, Knoxville
* K. Selçuk Candan, Arizona State University
* Khaled Ibrahim, Lawrence Berkeley National Laboratory
* Lucas Mello Schnorr, UFRGS
* Mario Marino, Leeds Beckett University
* Miaoqing Huan, University of Arkansas
* Murali Emani, Argonne National Laboratory
* Philippe Swartvagher, TU Wien
* Piotr Luszczek, University of Tennessee, Knoxville
* Ryan Grant, Sandia National Laboratories
* Salman Zubair Toor, Uppsala University
* Shu Yin, ShanghaiTech University
* Sophie Cerf, INRIA
* Steven Farrell, Lawrence Berkeley National Laboratory
* Todor Ivanov, Lead Consult
* Woongki Baek, UNIST
* Xiaoyi Lu, University of California, Merced
* Zhen Jia, Amazon
* Zhihui Du, New Jersey Institute of Technology

Award Committees

2023 BenchCouncil Achievement Award Committee
* D. K. Panda, The Ohio State University
* Lizy Kurian John, the University of Texas at Austin
* Geoffrey Fox, Indiana University
* Jianfeng Zhan, University of Chinese Academy of Sciences
* Tony Hey, Rutherford Appleton Laboratory STFC
* David J. Lilja, University of Minnesota, Minneapolis
* Jack J. Dongarra, University of Tennessee
* John L. Henning, Oracle

2023 BenchCouncil Rising Star Award Committees
* D. K. Panda, The Ohio State University
* Lizy Kurian John, the University of Texas at Austin
* Geoffrey Fox, Indiana University
* Jianfeng Zhan, University of Chinese Academy of Sciences
* Torsten Hoefler, ETH Zürich
* Vijay Janapa Reddi, Harvard University
* Peter Mattson, Google, USA
* Douwe Kiela, Stanford University

BenchCouncil Distinguished Doctoral Dissertation Award Committee in Other Areas
* Jack J. Dongarra, University of Tennessee
* Xiaoyi Lu, The University of California, Merced
* Jeyan Thiyagalingam, STFC-RAL
* Lei Wang, ICT, Chinese Academy of Sciences
* Spyros Blanas, The Ohio State University

BenchCouncil Distinguished Doctoral Dissertation Award Committee in Computer Architecture
* Resit Sendag, University of Rhode Island, USA
* Peter Mattson, Google
* Vijay Janapa Reddi, Harvard University
* Wanling Gao, Chinese Academy of Sciences

Bench Steering Committee
* Jack J. Dongarra, University of Tennessee
* Geoffrey Fox, Indiana University
* D. K. Panda, The Ohio State University
* Felix Wolf, TU Darmstadt
* Xiaoyi Lu, University of California, Merced
* Resit Sendag, University of Rhode Island, USA
* Wanling Gao, ICT, Chinese Academy of Sciences & UCAS
* Jianfeng Zhan, BenchCouncil

Topics

The Bench conference encompasses a wide range of topics in benchmarks, datasets, metrics, indexes, measurement, evaluation, optimization, supporting methods and tools, and other best practices in computer science, medicine, finance, education, management, etc. Bench’s multidisciplinary and interdisciplinary emphasis provides an ideal environment for developers and researchers from different areas and communities to discuss practical and theoretical work. The topics of interest include, but are not limited to the following:

Benchmark science and engineering across multi-disciplines:
* The formulation of problems or challenges in emerging and future computing
* The benchmarks, datasets, and indexes in multidisciplinary applications,
e.g., medical, finance, education, management, psychology, etc.
* Benchmark-based quantitative approaches to tackle multidisciplinary and
interdisciplinary challenges, industry best practices

Benchmark and standard specifications, implementations, and validations
* Big Data, Artificial Intelligence (AI), High-Performance Computing (HPC)
* Machine learning, Big scientific data, Datacenter, Cloud, Warehouse-scale computing
* Mobile robotics, Edge and fog computing, Internet of Things (IoT), Blockchain
* Data management and storage, Financial, Education, Medical or other application domains

Datasets
* Detailed descriptions of research or industry datasets,
including the methods used to collect the data and technical analyses
supporting the quality of the measurements
* Analyses or meta-analyses of existing data and original articles on systems,
technologies, and techniques that advance data sharing and reuse
to support reproducible research
* Evaluating the rigor and quality of the experiments used to generate
the data and the completeness of the data description
* Tools that can generate large-scale data while preserving their
original characteristics

Workload characterization, quantitative measurement, design, and evaluation studies
* Computer and communication networks, protocols and algorithms
* Wireless, mobile, ad-hoc and sensor networks, IoT applications
* Computer architectures, hardware accelerators, multi-core processors, memory systems
and storage networks
* HPC systems; Operating systems, file systems and databases; Virtualization, data centers,
distributed and cloud computing, fog and edge computing
* Mobile and personal computing systems, energy-efficient computing systems; real-time and
fault-tolerant systems, security and privacy of computing and networked systems,
software systems and services, and enterprise applications, social networks,
multimedia systems, web services, cyber-physical systems, including the smart grid

Methodologies, metrics, abstractions, algorithms, and tools
* Analytical modeling techniques and model validation
* Workload characterization and benchmarking
* Performance, scalability, power and reliability analysis
* Sustainability analysis and power management
* System measurement, performance monitoring and forecasting
* Anomaly detection, problem diagnosis and troubleshooting
* Capacity planning, resource allocation, run-time management and scheduling
* Experimental design, statistical analysis, and simulation

Measurement and evaluation
* Measurement standards, evaluation methodologies and metrics,
testbed methodologies and systems
* Instrumentation, sampling, tracing and profiling of large-scale,
real-world applications and systems;
* Measurement-based modeling (e.g., workloads, scaling behavior, assessment of
performance bottlenecks)
* Methods and tools to monitor and visualize measurement and evaluation data
* Systems and algorithms that build on measurement-based findings
* Advances in data collection, analysis and storage
(e.g., anonymization, querying, sharing)
* Reappraisal of previous empirical measurements and measurement-based conclusions
* Descriptions of challenges and future directions that the measurement and
evaluation community should pursue

Paper Submission

Papers must be submitted in PDF. For a full paper, the page limit is 15 pages in the LNCS format, not including references. For a short paper, the page limit is 8 pages in the LNCS format, not including references. The review process follows a strict double-blind policy per the established Bench conference norms. The submissions will be judged based on the merit of the ideas rather than the length. After the conference, the proceedings will be published by Springer LNCS (Indexed by EI). Please note that the LNCS format is the final one for publishing.

At least one author must pre-register for the symposium, and at least one author must attend the symposium to present the paper. Papers for which no author is pre-registered will be removed from the proceedings.

Formatting Instructions

Please make sure your submission satisfies ALL of the following requirements: All authors and affiliation information must be anonymized. The paper must be submitted in printable PDF format (LNCS format). Please number the pages of your submission. The submission must be formatted for black-and-white printers. Please make sure your figures are readable when printed in black and white. The submission must describe novel, unpublished work that is not currently under review of any other conference venue or journal.

Submission site: https://bench2023.hotcrp.com/
LNCS latex template: https://www.benchcouncil.org/file/llncs2e.zip

Awards

BenchCouncil Achievement Award ($3,000)
– This award recognizes a senior member who has made long-term contributions to benchmarking, measuring, and optimizing. The winner is eligible for the status of a BenchCouncil Fellow.

BenchCouncil Rising Star Award ($1,000)
– This award recognizes a junior member who demonstrates outstanding potential for research and practice in benchmarking, measuring, and optimizing.

BenchCouncil Best Paper Award ($1,000)
– This award recognizes a paper presented at the Bench conferences, which demonstrates potential impact on research and practice in benchmarking, measuring, and optimizing.

BenchCouncil Distinguished Doctoral Dissertation Award ($2000)
– This award recognizes and encourages superior research and writing by doctoral candidates in the broad field of benchmarks, data, standards, evaluations, and optimizations community. This year, the award includes two tracks, including the BenchCouncil Distinguished Doctoral Dissertation Award in Computer Architecture ($1000) and BenchCouncil Distinguished Doctoral Dissertation Award in other areas ($1000).

Call for Papers: ISFPGA
https://www.isfpga.org/call-for-papers/
Submitted by Aman Arora

Call for Papers – FPGA 2024
32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
March 3 – 5, 2024
Website: https://isfpga.org
Submission site: https://fpga24.hotcrp.com
Abstracts Due:   October 6, 2023

Submissions Due:  October 13, 2023

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2024, the 32nd edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.

Paper Submissions (with and without Artifacts)

We solicit research papers related to the following areas:

• FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.

• FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory or nano-scale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability.

• CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.

• High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.

• FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.

• Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.

Research submissions can be in either of two categories:

• Regular —  at most 10 pages (excluding references), for a regular presentation at the conference.

• Short — at most 6 pages (excluding references), for a brief presentation.

A paper submitted as either regular or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).

Submission Process

Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/. LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LaTeX link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract and paper submissions in PDF must be received by 11:59 PM AoE (Anywhere-on-Earth time zone).

Submissions will be considered for acceptance as regular or short papers. A paper submitted to the regular or short category will only be considered in that category. Regular or short submissions will also be considered for acceptance as a poster. Once a paper has been submitted, its authorship list is considered to be fixed and final.

By submitting articles to an ACM Publication, authors are hereby acknowledging that they and their co-authors are subject to all ACM Publications Policies (https://www.acm.org/publications/policies), including ACM’s new Publications Policy on Research Involving Human Participants and Subjects (https://www.acm.org/publications/policies/research-involving-human-participants-and-subjects). Alleged violations of this policy or any ACM Publications Policy will be investigated by ACM and may result in a full retraction of their paper, in addition to other potential penalties, as per ACM Publications Policy.

Authors should ensure that they and their co-authors obtain an ORCID ID (https://orcid.org/register), so that they can complete the publishing process for accepted papers. ACM has been involved in ORCID from the start and ACM has recently made a commitment to collect ORCID IDs from all of their published authors (https://authors.acm.org/author-resources/orcid-faqs). The collection process has started and will roll out as a requirement throughout 2023. ACM is committed to improve author discoverability, ensure proper attribution, and contribute to ongoing community efforts around name normalization; authors’ ORCID ID will help in these efforts.

Double Blind Policy

The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. References to the authors’ prior work should be made in the third person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as “Removed for blind review,” but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission. When necessary, authors should cite widely-available Open Source software website(s) without claiming ownership. Grant numbers and other government markings should also be blinded during the review process. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged. Similarly, if a paper can be unblinded by active search, this is not considered to undermine the spirit of the double-blind review. However, there are resources to blind open-source repositories for review, including: https://github.com/tdurieux/anonymous_github.

If you have questions about how to meet these guidelines, please contact the program chair before the submission deadline.

Reviewer Conflict Policy

During paper submission, all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is left undeclared or a nonexistent conflict is declared in an attempt to manipulate the review process, the submission may be rejected.

For more information about the ACM Conflict of Interest Policy, see: https://www.acm.org/publications/policies/conflict-of-interest

Originality of Submissions

Papers submitted are guaranteed by the authors to be unique manuscripts and not previously published, currently accepted or under consideration for acceptance at another venue. They cannot be substantially similar to any other current/future conference, journal, or workshop submission(s) unless the content appeared at a venue that does not have archived proceedings.

Rebuttal Process

The conference review process includes a rebuttal phase for authors to provide an optional response to reviewers’ questions and comments. This information is considered during the final deliberation process.

Author participation

For inclusion in the ACM digital library, at least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel (more instruction will be available after the camera-ready submission).

Best Paper Award

Authors of this year’s best manuscripts will be eligible for the conference’s best paper awards. They will also be invited to extend their work for consideration in a special issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS).

Artifact Evaluation

The conference will allow authors to submit accompanying artifacts for their paper submissions for evaluation. This process will allow ACM recognized badges to be associated with the final publication. The inclusion of artifacts with a submission is not required for a paper submission nor will any preference be given to submissions with artifacts over those without. Papers and artifacts will be subjected to separate and independent review processes. Artifact evaluation must NOT interfere with the double blind reviewing process of their accompanying papers, so all accompanying links in the paper to the artifacts should be blinded. All authors will be required at the time of paper submission to indicate if there will also be associated artifacts for evaluation. If artifacts will be included, a descriptor of their nature will be required. 

For more information, see: https://isfpga.org/artifact-evaluation/

Diversity and Inclusion

The open exchange of ideas and the freedom of thought and expression are central to the aims and goals of the conference. The organizers aim and commit to providing a harassment-free accessible and pleasant conference experience with equity in rights for all. We want every participant to feel welcome, included and safe at the conference.

For more information, see: https://isfpga.org/statement-on-diversity-and-inclusion/

Important Dates

All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12)

Visa Application

Prospective authors and participants requiring a B-2 visa to enter the US should check the visa appointment wait time using this link: https://travel.state.gov/content/travel/en/us-visas.html and consider applying IMMEDIATELY for a visa, scheduling an appointment in December 2023. By then, notification of acceptance will have been sent out (if applicable), registrations will have been opened, and ACM will be able to deliver letters of support. To the best of our knowledge, the letter of support will never be required before the interview.

Organizing Committee

Call for Papers: HOST 2024
http://www.hostsymposium.org/
Submitted by Kimia Z Azar

The IEEE International Symposium on Hardware Oriented Security and Trust (HOST) – the premier event aiming to facilitate the rapid growth of hardware security research and development – is set to take place in May 2024 in Washington D.C. Attendees can look forward to a diverse range of technical sessions from original and novel contributions, informative tutorials, captivating exhibitions and hardware demonstrations, and exciting competitions, including the microelectronic security competition and PhD dissertation competition. HOST 2024 invites original contributions in all areas of overlap between hardware and security, including but not limited to the following:

• Computer-aided Design (CAD) for Hardware Security Verification
  • e.g., automatic techniques and metrics for life cycle security management and detecting security vulnerabilities.
• Hardware Security Primitives
  • e.g., PUFs, TRNGs, cryptography, post-quantum cryptography, odometers.
• Hardware Attack and Defense
  • e.g., hardware Trojans, fault injection, side-channels, hardware reverse engineering, hardware obfuscation.
• Architecture Security
  • e.g., architectural side-channels, trusted execution environment, FPGA and reconfigurable fabric security.
• System security
  • e.g., machine learning security, SoC/IP security, CPS/IoT security, sensor network security, smart grid security, cloud security.
• Emerging or Other Topics
  • e.g., privacy-enhancing architecture, cryptocurrency security, and other hardware/system security topics.

Fall Submission

August 21, 2023: Abstract Submission*
August 28, 2023: Full Paper Submission
October 15, 2023: Notification of Acceptance
November 15, 2023: Camera-ready Version

Winter Submission

December 11, 2023: Abstract Submission*
December 18, 2023: Submission of Paper
February 15, 2024: Notification of Acceptance
March 15, 2024: Camera-ready Version

Abstract registration is required – Only the papers registered by the abstract submission deadline can update the submission file by the paper submission deadline. HOST 2024 also accepts proposals for tutorials and demos. More information will be disseminated in future calls.

Contact Inforamtion

Program Chairs

• Farimah Farahmandi (Email: ffarahmandi at ufl.edu)
• Ioannis Savidis (Email: isavids at coe.drexel.edu)

General Chairs

• Ankur Srivastava (Email: ankurs at umd.edu)
• Mark Tehranipoor (Email: tehranipoor at ece.ufl.edu)

Vice Program Chairs

• Ujjwal Guin (Email: ujjwal.guin at auburn.edu)
• Naghmeh Karimi (Email: naghmeh.karimi at umbc.edu)

Call for Papers: HPCA 2024
https://www.hpca-conf.org/2024/
Submitted by Christina Giannoula

REGULAR TRACK CALL FOR PAPERS
30th IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Edinburgh, UK
March 2 – March 6, 2024
https://www.hpca-conf.org/2024/

The International Symposium on High-Performance Computer Architecture (HPCA) is the premier forum for new ideas and research results in computer architecture. In 2024, the 30th edition of HPCA will be held in Edinburgh, Scotland, UK.

Important Dates
Abstract: July 28, 2023 at 11:59 PM PDT
Full Paper: August 4, 2023 at 11:59 PM PDT
Rebuttal/Revision:October 2 – 13, 2023
Author Notification:October 24, 2023

Regular Track Call For Papers
Some topics of interest are listed below, but we encourage authors to contact the PC chair, if they have a question regarding the topic fit.

• Processor, memory, and storage systems architecture
• Instruction-, thread-, and data-level parallelism
• Interconnection network, router, and network interface architecture
• Domain-Specific architectures, including FPGA, CGRA, and reconfigurable systems
• Near/In-Memory computing
• Cloud, datacenter, cluster/distributed systems and applications
• Approximate computing
• Compilers/PL for novel architectures
• IoT, mobile, Edge, and embedded architecture
• Effects of circuits or technology on architecture (3D/chiplets/interposer/wafer-scale)
• Architecture modeling and simulation methodologies
• Neuromorphic computing
• Quantum/ Superconducting computing
• Reliability/Fault Tolerance
• Security/Privacy
• Evaluation and measurement of real computing systems