This is the 1st July 2025 digest of SIGARCH Messages.

In This Issue

Call for Papers: HASP @ MICRO 2025 - (Note: The Call for Paper type has not been set for this item!)


Call for Participation: ASAP 2025

Submitted by Hanrui Wang

The 36th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2025)
July 28-30, 2025
Vancouver, BC, Canada
https://www.asap-2025.org 

Registration link: https://www.asap-2025.org/registration/ 

Early registration deadline: June 28, 2025

The history of the event traces back to the International Workshop on Systolic Arrays, organized in 1986 in Oxford, UK. It later developed into the International Conference on Application Specific Array Processors. With its current title, it was organized for the first time in Chicago, USA in 1996. Since then it has alternated between Europe and North-America. The conference will cover the theory and practice of application-specific systems, architectures, and processors. 

For a quick preview of ASAP 2025, we will have a variety of talks across 1) LLMs, Transformers, and Accelerators, 2) Scalable Systems and Secure Acceleration, 3) RISC-V and Custom Architectures, and 4) Design Exploration and Emerging Hardware. Besides regular paper talks, we will have two exciting keynotes, and a few invited sessions on special topics such as 1) Reconfigurable Edge Computing, 2) Architectures for Sustainable Security, and 3) Custom Computing in Canada. One special event this year is a retrospective review of most impactful ASAP papers in the past decades. In addition, we are also planning for a couple of sponsor workshops and/or tutorials, as well as lots of interesting poster presentations. 

Keynotes
Keynote 1: Towards 40 Years of ASAP: From Systolic Array to Application-Specific Processing
Prof. Wayne Luk, Imperial College London

Keynote 2: For ML and With ML: The New Normal in Hardware Design
Prof. Lizy John, University of Texas at Austin

Organizing Committee:
* General Chair: Zhenman Fang, Simon Fraser University, Canada
* Program Chairs: Philip Brisk, University of California, Riverside, USA
      Cong Callie Hao, Georgia Institute of Technology, USA

We look forward to your participation and welcome you to Vancouver for an engaging and inspiring ASAP 2025!

 


Call for Papers: IEEE Cross-Disciplinary Conference on Memory-Centric Computing
https://ccmcc.eclectx.org/cfp.html
Submitted by Saugata Ghose

IEEE Cross-disciplinary Conference on Memory-Centric Computing (CCMCC)
Dresden, Germany
October 8–10, 2025
https://ccmcc.eclectx.org/cfp.html

The IEEE Cross-disciplinary Conference on Memory-Centric Computing (CCMCC) is a new conference that aims to bring experts from diverse fields together, all working on advancing memory-centric computing, including processing in memory and processing near memory. It is a platform for sharing new ideas, exchanging insights, and fostering collaboration. CCMCC’s mission is to accelerate innovation in memory-centric computing and its the integration into real-world applications.

We are soliciting papers across the entire memory-centric computing stack, from software to architecture to circuits and devices. You can see a broader list of topics on the CFP.

Abstracts are due June 2, with full drafts due on June 9.
Papers are due June 15th. We are accepting both long (10-12 page) and short (4-6) page papers. Please consider submitting!


Call for Papers: CAMS25 – The 3rd Workshop on Computer Architecture Modeling and Simulation
https://sarchlab.org/cams25
Submitted by Enze Xu

3rd Workshop on Computer Architecture Modeling and Simulation (CAMS 2025)
held in conjunction with IEEE/ACM MICRO25.
Seoul, Korea.
October 18/19, 2025

Summary
The goal of the workshop is to provide a forum for researchers and practitioners to exchange ideas and discuss the latest advances in the field of computer architecture modeling and simulation. The focus on modeling and simulation techniques is of vital importance to the ongoing advancements in microarchitecture, as these methods are essential tools for improving system performance, efficiency, and reliability.

Topics of interest
The workshop will cover various aspects of computer architecture modeling and simulation, including but not limited to:
 * Simulator Development: Advances in design, theory, implementation, and integration of simulators.
 * Performance Modeling: Strategies for prediction, validation, and the impact of architectural features.
 * Power Modeling and Simulation: Methods for power-efficient design and power-performance trade-offs.
 * Tools and Studies Survey: Review and compare existing simulation tools and applications.
 * Scalable Simulation Techniques: Approaches for improving simulation scalability and efficiency.
 * Modeling and Simulation for Unconventional Architectures: Exploration of unique challenges and approaches for emerging and unconventional architectures.
 * Hardware-in-the-loop Simulation: Performance modeling and simulator validation with hardware.
 * Modeling for Machine Learning (Sim4AI): Architectural considerations and models for hardware accelerators.
 * Validation Techniques: Approaches for validating the accuracy of simulation models.
 * Human-centered simulation methods: Analysis, visualization, and monitoring methods.
Submissions
Call for full papers
The workshop invites submissions of original work in the form of full papers (up to 6 pages, reference not included) covering all aspects of computer architecture modeling and simulation. Submissions will be peer-reviewed, and accepted papers will be included in the workshop proceedings.
Call for Abstracts for Tool Release Talks
The talks will announce new simulators or new releases of existing simulators, highlighting their new features and improvements. We solicit talks from a broader community. Please submit a one-page abstract that includes the simulator, the new version, the new features you wish to present, and the website for your tool (if it exists). The selection will be made based on the relevance to the workshop topics, decided by the workshop chairs.
Important Dates
* August 11th, 2025 (23:59 AoE) – Full Paper Submissions
* September 8th, 2025 – Full Paper Author Notifications
* September 15th, 2025 (23:59 AoE) – Tool Release Talk Submissions
* September 22nd, 2025 – Tool Release Talk Author Notifications
Workshop Chairs
 * Yifan Sun, College of William & Mary (W&M), USA, ysun25@wm.edu
 * Trevor E. Carlson, National University of Singapore (NUS), Singapore,  tcarlson@comp.nus.edu.sg

Call for Papers: PDSW 2025
https://www.pdsw.org/index.shtml
Submitted by Izzet Yildirim

The 10th International Parallel Data Systems Workshop (PDSW 2025)
Co-located with Supercomputing 2025

Summary
The increasing importance of efficient data storage and management continues to drive scientific productivity across traditional simulation-based HPC environments and emerging Cloud, AI/ML, and Big Data analysis frameworks. Challenges are compounded by the rapidly expanding volumes of experimental and observational data, the growing disparity between computational and storage hardware performance, and the rise of novel data-driven algorithms in machine learning. This workshop aims to advance research and development by addressing the most pressing challenges in large-scale data storage and processing.

We invite the community to contribute original research manuscripts that introduce and evaluate novel algorithms or architectures, share significant scientific case studies or workloads, or assess the reproducibility of previously published work. We emphasize the importance of community collaboration for problem identification, workload capture, solution interoperability, standardization, and shared tools. Authors are encouraged to provide comprehensive experimental environment details (software versions, benchmark configurations, etc.) to promote transparency and facilitate collaborative progress.

Important Dates
Paper Submissions due: Aug 1st, 2025, 11:59 PM AoE
AD due: Aug 8th, 2025, 11:59 PM AoE
Paper Notification: Sep 5th, 2025, 11:59 PM AoE
Camera ready due: Sep 27th, 2025, 11:59 PM AoE
Final AD/AE due: Oct 15, 2025, 11:59 PM AoE

Submissions website: https://submissions.supercomputing.org/

Topics of Interest
– Scalable Architectures: Distributed data storage, archival, and virtualization.
– New Data Processing Models and Algorithms: Application of innovative data processing models and algorithms for parallel computing and analysis.
– Performance Analysis: Benchmarking, resource management, and workload studies.
– Cloud and Container-Based Models: Enabling cloud and container-based frameworks for large-scale data analysis.
– Storage Technologies: Adaptation to emerging hardware and computing models.
– Data Integrity: Techniques to ensure data integrity, availability, reliability, and fault tolerance.
– Programming Models and Frameworks: Big data solutions for data-intensive computing.
– Hybrid Cloud Data Processing: Integration of hybrid cloud and on-premise data processing.
– Cloud-Specific Opportunities: Data storage and transit opportunities specific to cloud computing.
– Storage System Programmability: Enhancing programmability in storage systems.
– Data Reduction Techniques: Filtering, compression, and reduction techniques for large-scale data.
– File and Metadata Management: Parallel file systems, metadata management at scale.
– In-Situ and In-Transit Processing: Integrating computation into the memory and storage hierarchy for in-situ and in-transit data processing.
– Alternative Storage Models: Object stores, key-value stores, and other data storage models.
– Productivity Tools: Tools for data-intensive computing, data mining, and knowledge discovery.
– Data Movement: Managing data movement between compute and data-intensive components.
– Cross-Cloud Data Management: Efficient data management across different cloud environments.
– AI-enhanced Systems: Storage system optimization and data analytics using machine learning.
– New Memory and Storage Systems: Innovative techniques and performance evaluation for new memory and storage systems.

More details are available at: https://www.pdsw.org/index.shtml

Organizers
General Chair: Suren Byna (The Ohio State University, USA)
Program Co-Chairs:
Anthony Kougkas (Illinois Institute of Technology, USA)
Sarah Neuwirth (Johannes Gutenberg University Mainz, Germany)


Note: The Call for Paper type has not been set for this item!

Call for Papers: HASP @ MICRO 2025
https://www.haspworkshop.org/2025/
Submitted by Shuwen Deng

The 14th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP)
October 18 or 19, 2025
HASP is intended to bring together researchers, developers, and practitioners from academia and industry, to share practical implementations and experiences related to all aspects of hardware and architectural support for security and privacy, and to discuss future trends in research and applications.
Topics of interest
• Secure hardware processor architectures and implementations
• Side-channel attacks, evaluations, and defenses
• Secure cache designs and evaluation, focusing on side-channels
• Commercial TEE systems and security solutions
• Hardware-enhanced cloud security
• Security of emerging architectures, such as Quantum Computers
• Hardware support for secure Internet-of-Things
• Smartphone hardware security
• Hardware fingerprinting and PUFs
• Hardware and architectural support for trust management
• Hardware trojan threat evaluation, detection, and prevention
• Attack resilient hardware and architectural design
• Cryptographic hardware design, implementation, and evaluation
• Security simulation, testing, validation and verification
Authors can submit the following types of papers:
I. Regular Paper (8 Pages, including the bibliography and appendices)
• Research Paper
• SoK: Systemization-of-Knowledge papers should concisely, but exhaustively, systematize and conceptualize existing knowledge (similar to SoK papers in S&P conferences, but focusing on hardware and architecture). Papers should use “SoK Paper:” as their title prefix.
• Position Paper: Position papers should define new problems in hardware or architecture security and privacy topics. Papers should use “Position Paper:” as their title prefix.
II. Short Paper (4 Pages, including the bibliography and appendices)
• Research Paper: Papers should use “Short Paper:” as their title prefix.
• WiP: Papers should use “WiP:” as their title prefix. Work-in-Progress papers will not appear in the proceedings, but the title and authors will be listed on the HASP web page as a public record of the presentation.
Important Dates
Submission Deadline: Jul 27, 2025, by end of day Anywhere on Earth (AoE)
Notification of Acceptance: September 2, 2025
Camera-ready Version: September 15, 2025
Workshop Date: October 18 or 19, 2025 (tentative)
Submission Information
Papers can be submitted on the EasyChair web page: https://easychair.org/conferences/?conf=hasp2025 . All submissions must be using the double-column ACM ICPS template. Please use the ACM Standard template in the usual two-column format. The submissions should be anonymized for double-blind review. Regular paper and short paper submissions must be at most 8 or 4 pages respectively (including the bibliography and appendices). Short research papers, position papers, SoK papers and Work-in-Progress papers should have “Short Paper”, “Position Paper”, “SoK”, and “WiP” as the title prefix.
All accepted research papers, short papers, position papers, and SoK papers will be included in the ACM Digital Library; Work-in-Progress papers are not included. The proceedings will be published through ACM ICPS and available through the ACM Digital Library
HASP 2025 Co-Chairs:
Prof. Wenjie Xiong, Virginia Tech, USA – wenjiex@vt.edu
Prof. Tianwei Zhang, Nanyang Technological University, Singapore
Prof. Shuwen Deng, Tsinghua University, China

Episode 20 of the Computer Architecture Podcast Released! Featuring Guest Dr. Ricardo Bianchini, Microsoft
https://comparchpodcast.podbean.com/
Submitted by Suvinay Subramanian

Computer Architecture Podcast: A series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.

Announcing the release of our 5-year anniversary episode — Episode 20: The Tech Transfer Playbook: Bridging Research to Production with Dr. Ricardo Bianchini, who is a Technical Fellow and Corporate Vice President at Microsoft Azure, where he leads the team responsible for managing Azure’s compute workload, server capacity, and datacenter infrastructure with a strong focus on efficiency and sustainability. Before joining Azure, Ricardo led the Systems Research Group and the Cloud Efficiency team at Microsoft Research (MSR).  He created research projects in power efficiency and intelligent resource management that resulted in large-scale production systems across Microsoft. Prior to Microsoft, he was a Professor at Rutgers University, where he conducted research in datacenter power and energy management, cluster-based systems, and other cloud-related topics. Ricardo is a Fellow of both the ACM and IEEE.

Listen to the episode at https://comparchpodcast.podbean.com. Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Akanksha Jain
SIGARCH Content Editor

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