Call for Papers: Embedded Systems Week 2019
https://www.esweek.org
Submitted by Lars Bauer

Embedded Systems Week (ESWEEK)
New York City, USA,
October 13 – 18, 2019

Embedded Systems Week (ESWEEK) is the premier event covering all aspects of embedded systems and software. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), a special IoMT Day, a symposium (NOCS), and hot-topic workshops and tutorials, ESWEEK presents attendees a wide range of topics unveiling the state of the art in embedded systems design and HW/SW architectures.

Registered attendees are entitled to attend sessions of all conferences CASES, CODES+ISSS, EMSOFT, and the IoMT Day. Symposia, workshops, and tutorials require separate registration.

IMPORTANT DATES:
Journal Track:
– Abstract Submission: April 5, 2019
– Full Paper Submission: April 12, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Work-in-Progress Track:
– Paper Submission: June 7, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Workshop Proposals: April 18, 2019
Tutorial Proposals: April 30, 2019
Special Session Proposals: April 30, 2019

SUBMISSION GUIDELINES:
ESWEEK 2019 continues a dual publication model comprising the Journal track and the Work-in-Progress (WiP) track. Journal track papers, which are full-length (10-page) papers describing mature work, will be published in the ACM Transactions on Embedded Computing Systems (TECS). The WiP track papers, which are short (2-page) papers representing not-yet-mature but promising research, will be published in the ESWEEK proceedings and will be listed as regular publications within the IEEE and/or ACM digital libraries. Authors of WiP papers have the opportunity to publish the extended form of their work in any conference or journal they prefer. Journal and WiP papers are mutually exclusive, i.e., a work can only be in submission in one of the two tracks.
For more information, please refer to: https://www.esweek.org/author-information

* CASES: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
CASES is a premier forum where researchers, developers and practitioners exchange information on the latest advances in compilers and architectures for high-performance, low-power embedded systems. The conference has a long tradition of showcasing leading edge research in embedded processor, memory, interconnect, storage architectures and related compiler techniques targeting performance, power, predictability, security, reliability issues for traditional and emerging applications. In addition, we invite innovative papers that address design, synthesis, and optimization in heterogeneous and accelerator-rich architectures.
https://esweek.org/sites/default/files/2019-CASES-cfp_0.pdf

CASES Program Chairs:
Akash Kumar, Technical University of Dresden, DE
Partha Pande, Washington State University, US

* CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis
The International Conference on Hardware/Software Codesign and System Synthesis is the premier event in system-level design, modeling, analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hardware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design. High-quality original papers will be accepted for oral presentation followed by interactive poster sessions.
https://esweek.org/sites/default/files/CODES%2BISSS-2019-CFP.pdf

CODES+ISSS Program Chairs:
Sudeep Pasricha, Colorado State University, US
Roman Lysecky, Arizona State University, US

* EMSOFT: International Conference on Embedded Software
The ACM SIGBED International Conference on Embedded Software (EMSOFT) brings together researchers and developers from academia, industry, and government to advance the science, engineering, and technology of embedded software development. Since 2001, EMSOFT has been the premier venue for cutting-edge research in the design and analysis of software that interacts with physical processes, with a long-standing tradition for results on cyber-physical systems, which compose computation, networking, and physical dynamics.
https://esweek.org/sites/default/files/EMSOFT2019_CfP_0.pdf

EMSOFT Program Chairs:
Sriram Sankaranarayanan, University of Colorado Boulder, US
Timothy Bourke, Inria Paris, FR

* IoMT: Internet of Medical Things
The Internet of Medical Things (IoMT) paves the foundations for intelligent and reliable personalized precision medicine. Grounded in the mathematical and physical modeling of human anatomy and physiology, it offers accurate multiscale medical monitoring through smart sensing, enabling continuous diagnosis via on-fly communication with medical experts. It provides hyperspectral and hyperdimensional processing and restores health through patient-specific actuation. The IoMT special day provides a forum for academic and industry representatives from areas such as medical and bio-engineering and embedded systems to discuss innovative ideas and solutions for precise personalized medicine. Sub-missions to the IoMT day are via the three conferences.
https://esweek.org/iomt/about

IoMT Chairs:
Insup Lee, University of Pennsylvania, US
Paul Bogdan, University of Southern California, US

* Call for Workshop Proposals
ESWEEK 2019 will host several workshops on Oct. 17/18th. ESWEEK workshops are excellent opportunities to bring together researchers and practitioners from different communities to share their experiences in an interactive atmosphere.
We invite you to submit workshop proposals on any topic related to the broad set of research, education, and application areas in embedded systems before the deadline of April 18, 2019.
https://esweek.org/sites/default/files/ESWEEK2019_CfP_1.pdf

Workshop Chair:
Laura Pozzi, USI Lugano, CH

* Call for Tutorial Proposals
ESWEEK 2019 is looking for high-quality tutorials that will take place on Oct. 13th. Tutorials offer a unique opportunity where presenters can interact with attendees and attendees can gain in-depth knowledge on specific topics. Tutorials on all topics related to embedded system design, analysis and development are welcome and can be either half or full day, lecture style or hands on.
We invite you to submit tutorial proposals before the deadline of April 30, 2019.

* Call for Special Session Proposals
ESWEEK 2019 will host several special sessions. They should cover hot, contemporary topics that are complementary to regular sessions and can constitute individual presentations, panels or other formats. Participants of each accepted special session will have the opportunity to co-author an overview paper (maximum 10 pages) of the session, published in the ESWEEK proceedings. We invite you to submit special session proposals on any topic related to the broad areas of interest of the conference or beyond before the deadline of April 30, 2019.
https://esweek.org/sites/default/files/ESWEEK2019_CfP_1.pdf

Tutorials and Special Sessions Chair:
Andreas Gerstlauer, University of Texas Austin, US

ESWEEK ORGANIZERS:
Petru Eles, Linköping University, SE
Tulika Mitra, National University of Singapore, SG (Vice General Chair)
Soonhoi Ha, Seoul National University, KR (Past Chair)

ESWEEK Local Arrangement Chairs:
Ramesh Karri, New York University, US
Siddarth Garg, New York University, US

www.esweek.org

Call for Papers: GPGPU 2019
https://insight-archlab.github.io/gpgpu.html
Submitted by Ashutosh Pattnaik

12th Workshop on General Purpose Processing Using GPU (GPGPU 2019)
in conjunction with ASPLOS 2019
Providence, RI, USA
April 13, 2019

IMPORTANT DATES:
Papers due: January 21, 2019
Notification: February 18, 2019
Final paper due: March 1, 2019

The goal of this workshop is to provide a forum to discuss new and emerging general-purpose programming architectures, environments, and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. This year’s workshop is particularly interested in security, new heterogeneous architecture or platforms, new forms of concurrency, and novel or irregular applications that can leverage these platforms.

Papers are being sought on many aspects of GPUs or accelerators, including (but not limited to):
– GPU applications
– GPU programming environments
– GPU runtime systems
– GPU compilation
– GPU architectures
– Multi-GPU systems
– GPU power/efficiency
– GPU reliability
– GPU benchmarking/measurements
– Heterogeneous architectures/platforms
– GPU security (NEW)
– Non-von Neumann architectures (NEW)
– Domain-specific architectures (NEW)

SUBMISSION GUIDELINES:
Full paper submissions must be in PDF format for US letter-size paper. They must not exceed 10 pages (all inclusive) in standard ACM two-column conference format (preprint mode, with page number). Templates for ACM format are available for Microsoft Word, and LaTeX can be found here. The submission site will be up soon.

ORGANIZERS:
Adwait Jog (co-chair), College of William & Mary
Onur Kayiran (co-chair), AMD Research
Ashutosh Pattnaik (submission/web chair), Penn State

Please contact the organizers if you have any questions.

HISTORY AND IMPACT
David Kaeli (Northeastern) and John Cavazos (Delaware) very successfully organized the previous versions of the GPGPU workshop. GPGPU workshop was first held in 2007 at Northeastern University. In 2008, the meeting was held with ASPLOS 2008. This trend continued and the GPGPU workshop was held with ASPLOS for the next 6 years. From 2015 and 2018, GPGPU workshop was co-located with PPoPP. GPGPU 2019 workshop returns to ASPLOS. The average citation count (as per Google Scholar), for a GPGPU workshop paper, is currently 37.5, where there have been 8 influential papers with 100+ citations.

Call for Papers: SELSE 2019
https://www.selse.org/
Submitted by Michael Sullivan

The 15th IEEE Workshop on Silicon Errors in Logic – System Effects
Stanford, Palo Alto, CA, USA
March 27 – March 28, 2019

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high-performance applications.

The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.

We are happy to announce that selected SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Portland, Oregon on June 24 – 27, 2019.

Key areas of interest include (but are not limited to):
– Error rates and trends in current and emerging technologies, including experimental failure data and the reliability characterization of deployed systems.
– New error mitigation techniques, robust software frameworks, and error handling protocols for resilient system design.
– Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.
– Resilience characterization and strategies for machine learning applications, including autonomous vehicles.
– Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.
– The design of resilient systems for space exploration.
– The interplay between system security issues and reliability.

SUBMISSION GUIDELINES:
Additional information and guidelines for submission are available at http://www.selse.org. Submissions and final papers should be PDF files following the IEEE two-column transactions format with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries—however, they are distributed to attendees of the workshop.

Call for Papers: Workshop on Accelerator Architecture in Computational Biology and Bioinformatics
https://aacbb-workshop.github.io/
Submitted by Dr. Leonid Yavits

2nd Accelerator Architecture in Computational Biology and Bioinformatics workshop (AACBB)
in conjunction with HPCA 2019
Washington DC, USA
February 16-20, 2019

IMPORTANT DATES:
Submission: December 25, 2018, AoE (postponed)
Notification: December 28, 2018

Over the last decade, the advent of high-throughput sequencing techniques brought an exponential growth in biosequence database sizes. With increased throughput demand and popularity of computational biology tools, reducing time-to-solution during computational analysis has become a significant challenge in the path to scientific discovery.
Conventional computer architecture is proven to be inefficient for computational biology and bioinformatics tasks. For example, aligning even several hundred DNA or protein sequences using progressive multiple alignment tools consumes several CPU hours on high performance computer. Hence, computational biology and bioinformatics rely on hardware accelerators to allow processing to keep up with the increasing amount of data generated from biology applications.

In a typical application, dominant portion of the runtime is spent in a small number of computational kernels, making it an excellent target for hardware acceleration. The combination of increasingly large datasets and high performance computing requirements make computational biology prime candidate to benefit from accelerator architecture research. Potential directions include 3D integration, near-data processing, automata processing, associative processing and reconfigurable architectures.

Topics of interest:
– Impact of bioinformatics and biology applications on computer architecture research
– Bioinformatics and computational biology accelerator architecture and design
– 3D memory-logic stack based accelerators
– Automata processing in bioinformatics and computational biology applications
– Associative processing in bioinformatics and computational biology applications
– Near-data (in-memory) acceleration bioinformatics and computational biology applications
– Emerging memory technologies and their impact on bioinformatics and computational biology
– Embedded and reconfigurable architectures
– Field programmable logic based accelerators
– Bioinformatics and computational biology-inspired hardware/software trade-offs
– Software acceleration of computational biology and bioinformatics

SUBMISSION GUIDELINES:
Interested authors are encouraged to submit papers (2-5 pages) through EasyChair: https://easychair.org/conferences/?conf=aacbb2019.
The full version should be a PDF file in HPCA25 submission format. For formatting instructions please refer to: http://hpca2019.seas.gwu.edu/guidelines_for_submission.html

ORGANIZERS:
Roman Kaplan, Technion
Leonid Yavits, Technion

CONTACT:
All questions about submissions should be emailed to Leonid Yavits (yavits@technion.ac.il) or Roman Kaplan (romankap@gmail.com)

Call for Papers: Workshop on Parallel AI and Systems for the Edge
http://bit.ly/PAISE2019
Submitted by Rajesh Sankaran

1st Workshop on Parallel AI and Systems for the Edge (PAISE)
in conjunction with IPDPS 2019
Rio de Janeiro, Brazil
May 24, 2019

IMPORTANT DATES:
Submission deadline: February 1, 2019
Notification of acceptance: March 1, 2019:
Workshop camera-ready papers due: March 11, 2019

For this workshop we welcome original work covering different aspects of:
1.Edge Inference
2.Hardware for Edge-computing and Machine Learning
3.Energy Efficient Processors for Training and Inference
4.Computer Vision at the Edge
5.Cyber Security for Edge Computing
6.Software and Hardware Multitenancy at the Edge
7.Machine Learning Hardware
8.Blockchains for Edge Computing
9.Programming Models for Edge Computing
10.Coupling HPC to Edge Applications
11.Communication and Control Strategies for Deploying and Managing Applications at the Edge

SUBMISSION GUIDELINES:
All papers must be original and not simultaneously submitted to another journal or conference. The papers submitted to the workshop will be peer reviewed by a minimum of 3 reviewers.

The following paper categories are welcome:
– Full Papers: Research papers should describe original work and be 8 or 10 pages in length.
– Short Papers: Short research papers, 4 pages in length, should contain enough information for the program committee to understand the scope of the project and evaluate the novelty of the problem or approach.
– Emerging Platforms and Practitioner Reports: Short reports, 3-6 pages in length, describing novel hardware and Software platforms, including initial proof-of-concept design and implementation are welcome. Reports may also focus on a particular aspect of technology usage in practice, or describe broad project experiences. They may describe a particular design idea, or experience with a particular piece of technology.

Templates for MS Word and LaTeX provided by IEEE eXpress Conference Publishing are available for download. See the latest versions here: https://www.ieee.org/conferences_events/conferences/publishing/templates.html

Upload your submission to EasyChair submission server in PDF format. EasyChair URL: https://easychair.org/cfp/PAISE2019.
Accepted manuscripts will be included in the IPDPS workshop proceedings.

ORGANIZERS:
Pete Beckman, Argonne National Laboratory, USA
Rajesh Sankaran, Argonne National Laboratory, USA

Call for Papers: Workshop On Energy Efficient Machine Learning And Cognitive Computing For Embedded Applications
https://www.emc2-workshop.com
Submitted by Michael Goldfarb

Workshop On Energy Efficient Machine Learning And Cognitive Computing For Embedded Applications (EMC^2)
in conjunction with HPCA 2019
Washington DC, USA
February 17, 2019

IMPORTANT DATES:
Paper Submission: Jan 18, 2019 (11:59 pm PST)
Notification and Rebuttals: Feb 5, 2019
Final Version Due: Feb 8, 2019

A new wave of intelligent computing, driven by recent advances in machine learning and cognitive algorithms coupled with process technology and new design methodologies, has the potential to usher unprecedented disruption in the way conventional computing solutions are designed and deployed. These new and innovative approaches often provide an attractive and efficient alternative not only in terms of performance but also power, energy, and area. This disruption is easily visible across the whole spectrum of computing systems ranging from low end mobile devices to large scale data centers and servers.

A key class of these intelligent solutions is providing real-time, on-device cognition at the edge to enable many novel applications including vision and image processing, language translation, autonomous driving, malware detection, and gesture recognition. Naturally, these applications have diverse requirements for performance, energy, reliability, accuracy, and security that demand a holistic approach to designing the hardware, software, and intelligence algorithms to achieve the best power, performance, and area (PPA).

The goal of this workshop is to provide a forum for researchers who are exploring novel ideas in the field of energy efficient machine learning and artificial intelligence for embedded applications. We also hope to provide a solid platform for forging relationships and exchange of ideas between the industry and the academic world through discussions and active collaborations.

Below is a set of suggested but not limited topics:
– Computing techniques for IoT, Automotive, and mobile intelligence
– Exploration new and efficient applications of machine learning
– Machine learning benchmarks, workloads and their characterization
– Energy efficient techniques and solutions for neural networks
– Efficient hardware proposals to implement neural networks
– Power and performance efficient memory architectures
– Exploring the interplay between precision, performance, power and energy
– Approximation, quantization and reduced precision computing techniques
– Improvements over conventional training techniques
– Hardware/software techniques to exploit sparsity and locality
– Security and privacy challenges and building secure systems

ORGANIZERS:
Raj Parihar, Tensilica/Cadence
Michael Goldfarb, Nvidia
Satyam Srivastava, Intel
Mahdi N. Bojnordi, University of Utah
Krishna Nagar, Intel
Tao Sheng, Amazon
Debu Pal, Cadence

Program Committee:
Raj Parihar, Tensilica/Cadence
Michael Goldfarb, Nvidia
Chen Ding, University of Rochester
Mahdi N. Bojnordi, University of Utah
Andy Glew, Nvidia
Sreepathi Pai, University of Rochester
Raj Jain, Washington University in St. Louis
Smruti R Sarangi, IIT Delhi
Shaoshan Liu, PerceptIn
Ali Shafiee, Samsung
Satyam Srivastava, Intel
Danian Gong, Cadence
Krishna Nagar, Intel
Tao Sheng, Amazon

Call for Papers: ALCHEMY 2019
https://sites.google.com/site/alchemyworkshop/
Submitted by Loïc CUDENNEC

Architecture, Languages, Compilation and Hardware support for EMerging and Heterogeneous sYstems (ALCHEMY)
in conjunction with ICCS 2019
Faro, Algarve, Portugal
June 12-14, 2019

Submission deadline: 31 January, 2019

The International Conference on Computational Science is an annual conference that brings together researchers and scientists from mathematics and computer science as basic computing disciplines, researchers from various application areas who are pioneering computational methods in sciences such as physics, chemistry, life sciences, and engineering, as well as in arts and humanitarian fields, to discuss problems and solutions in the area, to identify new issues, and to shape future directions for research.

ICCS is an A-rank conference in the CORE classification.
All accepted papers will be included in the Springer Lecture Notes in Computer Science (LNCS) series.

The future aims toward increasing parallelism and heterogeneity of systems to tackle the so-called power-wall while permitting a roadmap of increased performance. Several challenges rise for programming such systems. The ALCHEMY workshop goal is to show some of these relevant challenges and finding ways to tackle them, while permitting programmers to focus on important part of application designs and letting compilers or runtime optimization do most of the work toward good performance.

ALCHEMY is the track of ICCS addressing new distributed and parallel systems for compute-intensive applications, including heterogeneous aspects. It is also a good place of exchange between the traditional HPC domain of research and all the emerging HPES (High-Performance Embedded Systems) domain, since the programming issues are mostly the same, with a relatively high cost of communication and the difficulty to program hundreds of cores often under performance and power usage constraints.

Original high quality submission are encouraged on all topics related to parallel and distributed programming issues including (but not limited to):
– High-level Programming
– Programming models and languages
– Compilers for programming languages
– Runtime generation for parallel programming
– Handling heterogeneity in parallel and distributed systems

– Operational research and optimizations
– Application, runtime, system and hardware sizing
– Task scheduling
– Task placement, application mapping

– System and runtime
– New operating systems, dedicated OS
– Dedicated runtimes
– Shared memory, data consistency models and protocols

– Hardware architecture
– Architecture support for massive parallelism management
– Specific or reconfigurable accelerators (use of FPGA), many-cores
– Enhanced communications
– New memory technologies (NVRAM)

– Security
– Accelerators for security
– Crypto systems

– In-situ systems and user experiments
– User feedback on existing architectures
– Heterogeneous integration within HPC systems (micro-servers)
– Coping with heterogeneity at the user level

SUBMISSION GUIDELINES:
The manuscripts of 10-14 pages, written in English and formatted according to the Springer LNCS templates, should be submitted electronically via EasyChair. Templates are available for download in EasyChair horizontal menu “Templates”. Papers must be based on unpublished original work and must be submitted to ICCS only. Submission implies the willingness of at least one of the authors to register and present the paper. All accepted papers will be included in the Springer Lecture Notes in Computer Science (LNCS) series and indexed by Scopus, EI Engineering Index, Thomson Reuters Conference Proceedings Citation Index (included in ISI Web of Science), and several other indexing services.

Please use the ICCS submission system hosted by EasyChair and select the Architecture, Languages, Compilation and Hardware support for Emerging and Heterogeneous sYstems track.

ORGANIZERS:
General Co-Chairs:
Loïc CUDENNEC, CEA, LIST, France
Stéphane LOUISE, CEA, LIST, France

Program Committee:
Giovanni AGOSTA, Politecnico di Milano, Italy
Paul M. CARPENTER, BSC, Spain
Jeronimo CASTRILLON, CFAED, TU Dresden, Germany
Camille COTI, Université de Paris-Nord, France
Loïc CUDENNEC, CEA, LIST, France
Vianney LAPOTRE, Université de Bretagne-Sud, France
Stéphane LOUISE, CEA, LIST, France
Marco MATTAVELLI, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Raymond NAMYST, INRIA, Université de Bordeaux, France
Eric PETIT, Intel, France
Erwan PIRIOU, CEA, LIST, France
Antoniu POP, University of Manchester, UK
Mario PORRMANN, CITEC, Universität Bielefeld, Germany
Jason RIEDY, Georgia Institute of Technology, USA
Johanna SEPULVEDA, Institute for Security in Information Technology, TU Munich, Germany
(to be extended)