This is the 1st September 2023 digest of SIGARCH Messages.

In This Issue


Call for Nominations: Call for Nominations: Inaugural SIGMICRO Early Career and Dissertation Awards

Submitted by Reetuparna Das

We are excited to announce two new SIGMICRO awards!
Please consider nominating outstanding candidates for the inaugural year of these two new awards – the Early Career Award and the Dissertation Award.
The nomination deadline is August 18th. Please help us publicize this widely!
More information can be found here:
Early Career Award
Dissertation Award
Best Regards,
Reetu Das & Onur Mutlu
On behalf of the SIGMICRO Executive Committee

Call for Nominations: MICRO Test of Time Award 2023
https://www.microarch.org/tot/cfn.html
Submitted by Saugata Ghose

The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the tenth MICRO ToT Award. This award recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field.

The award will recognize an influential MICRO paper whose influence is still felt 18-22 years after its initial publication. In other words, the award will be given to one or more papers published at MICRO conferences in any of the years N-22, N-21, N-20, N-19, or N-18. This year, N = 2023, so only papers published at MICRO conferences held in 2001, 2002, 2003, 2004, or 2005 are eligible. An eligible paper that has received at least 100 citations (according to Google Scholar) is automatically nominated, but explicit nominations of such papers are still encouraged.

Nominating a Paper

To nominate a paper, send an email to micro-tot-award-nominations@googlegroups.com by August 31, 2023, with the following:

  1. The title, the author list, and publication year of the nominated paper
  2. A 100-word (maximum) nomination statement, describing why the paper deserves the Test of Time Award
  3. The name, title, affiliation of the nominator, and if appropriate, the relationship of the nominator to the authors

Only one paper can be nominated in a single email. There is a maximum of five nominations per person. You cannot nominate a paper that you are a co-author on. One paper will be selected as the award winner from the pool of nominees by the award committee.

For more information on the nomination and selection process, a list of all eligible papers, this year’s committee members, prior award winners, and other information, please visit https://www.microarch.org/tot/cfn.html


Call for Participation: MAAD: ML-Assisted Architecture Design Tutorial @ MICRO 2023
https://sites.google.com/g.harvard.edu/micro23-maad-tutorial/home
Submitted by Shvetank Prakash

Call for Participation

We invite folks to attend our upcoming full-day MAAD tutorial at MICRO 2023 on “ML-Assisted Architecture Design: A Hands-On Experience.”

Time & Date: Sunday, October 29, 2023  in Toronto, Canada from 8AM to 5PM.

Tutorial Overview

We have multiple invited talks from academia and industry discussing challenges and opportunities of ML-Assisted architecture design spanning a variety of topics including ML algorithms, datasets, tools & infrastructure, best practices, industry relations, and workforce training. 

In this tutorial, we also introduce ArchGym, an open-source gymnasium and easily extensible framework that connects various machine learning algorithms to architecture simulators. We will provide a hands-on experience of adding a hardware simulator to ArchGym and leveraging various machine learning algorithms (e.g. Reinforcement learning, Bayesian optimization, Genetic algorithm, etc.) for design space exploration. We will also showcase examples of integrating CFU-Playground and Astra-Sim, illustrating the practical implementation of ArchGym. 

Website & preliminary program: https://sites.google.com/g.harvard.edu/micro23-maad-tutorial/home 

Organizers

Tushar Krishna, Srivatsan Krishnan, Changhai Man, Shvetank Prakash, Vijay Janapa Reddi, Amir Yazdanbakhsh, Jason Yik


Call for Participation: Real-World PIM Tutorial @ MICRO 2023
https://events.safari.ethz.ch/micro-pim-tutorial/
Submitted by Organizers: Juan Gómez Luna, Onur Mutlu, Ataberk Olgun

We would like to announce our upcoming online tutorial at MICRO 2023 on “Real-world Processing-in-Memory Systems for Modern Workloads”.

Date: Sunday, October 29, 2023 (held during MICRO 2023,  October 28 – November 1, 2023 in Toronto, Canada).

Tutorial Overview:

We’ll have several invited talks from industry speakers, with additional talks and hands-on PIM sessions by Juan Gómez Luna, Onur Mutlu and Ataberk Olgun (ETH Zürich). We’ll cover the latest advances in PIM technology, introducing PIM concepts “processing near memory” and “processing using memory”, and give real world examples of both types of systems. We’ll also discuss workload characterization for PIM, and programming and optimizing PIM kernels, with a hands-on lab in the afternoon.

MICRO 2023 Real-World PIM tutorial website & preliminary program: https://events.safari.ethz.ch/micro-pim-tutorial/

Livestream Sunday, October 29 (full day, virtual): https://youtu.be/ohU00NSIxOI

MICRO 2023 Workshops and Tutorials: https://microarch.org/micro56/program/workshops.php

Organizers: Juan Gómez Luna, Onur Mutlu, Ataberk Olgun


Call for Participation: IISWC 2023
https://iiswc.org/iiswc2023
Submitted by Resit Sendag

CALL FOR PARTICIPATION
IEEE International Symposium on Workload Characterization (IISWC) — https://iiswc.org/iiswc2023/
Oct 1-3, 2023 — Ghent, Belgium

IISWC is dedicated to the understanding and characterization of workloads that run on all types of computing systems.

Conference program
A preliminary version of the conference program is now available (https://iiswc.org/iiswc2023/#/program/), featuring a mix of excellent keynotes, a great set of papers and posters on Monday Oct 2 and Tuesday Oct 3, and an inspiring tutorial and workshop on Sunday Oct 1. We also have prepared a nice social program (boat trip and reception on Sunday evening; and Augmented Reality tour of the fabulous Lam Gods followed by the conference dinner on Monday evening).

Registration
Registration is now open. Early registration ends on **Sept 15** after which registration will be 25% more expensive. If you need a visa to travel to Belgium/Europe, please register as soon as possible, so we can prepare the invitation letter in time for the conference.

Conference venue and room block
The conference will be held at the beautiful Monasterium PoortAckere, a former monastery (https://iiswc.org/iiswc2023/#/travel/venue/). The conference itself will be held in the monastery church — this should be a unique conference experience! We have a room block reserved for conference attendees — available until **Sept 4** after which rooms can only be booked based on availability (https://iiswc.org/iiswc2023/#/travel/accommodation/). If you prefer staying somewhere else, there are plenty of hotel options within walking distance.

Student travel grants
Thanks to the generous support from NSF and IEEE TCCA, we can offer student travel assistance grants (https://iiswc.org/iiswc2023/#/travel/student-grants/) even if you are not presenting at the conference and even if you are an undergraduate student! Deadline is **August 28**.

Feel free to reach out to the Organizing Committee and General Chair, Lieven Eeckhout (lieven.eeckhout@ugent.be), if you have questions or concerns.


Call for Participation: ESWEEK 2023
https://esweek.org/
Submitted by Lars Bauer

EMBEDDED SYSTEMS WEEK
Call for Participation
Hamburg, Germany, September 17-22, 2023

Home

About Embedded Systems Week (ESWEEK)
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent and connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), two symposia (MEMOCODE, NOCS), and several workshops and tutorials, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development.

The 2023 edition of the Embedded Systems Week will take place on the campus of Hamburg University of Technology (TUHH), Germany. Prior to the main event, there are 13 education classes to choose from on Thursday and Friday. Sunday starts with Tutorials, the Diversity Event, and a Welcome Reception. The three main conferences, Keynotes, Competition Sessions, Ph.D Forum and Recruitment Event take place on Monday to Wednesday, followed by Symposia and Workshops on Thursday/Friday.

News
* Student Travel Grants (deadline: July 10th): https://esweek.org/student-travel-grants/
* Undergraduate Scholar Program (deadline: July 10th): https://esweek.org/undergraduate-scholar/
* Ph.D. Forum (deadline: July 14th) and ESWEEK Recruitment Events: https://esweek.org/esweek-ph-d-forum-and-recruitment-events/
* The ESWEEK registration is open. Advanced registration deadline is August 25. There are student travel supports. Check the ESWEEK webpage for more details.
* The program is online: https://esweek.org/schedule/

Keynote Talks: https://esweek.org/keynotes/
* Keynote 1: “Enabling the Era of Immersive Computing: A Rich Agenda for Embedded Systems Research”, by Dr. Sarita Adve (UIUC)
* Keynote 2: “Advanced silicon technologies enabling next generation of embedded and AI architectures”, by Dr. Raja Swaminathan (AMD)
* Keynote 3: “The quest for resilient embedded systems in the era of machine learning”, by Dr. Lothar Thiele (ETH)

Conferences
* CASES: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Cases


Program Chairs: Swarup Bhunia, University of Florida, US
Jana Doppa, Washington State University, US
* CODES+ISSS: International Conference on Hardware/Software Codesign
and System Synthesis

Codes+ISSS


Program Chairs: Mohammad Abdullah Al Faruque, UC Irvine, US
Muhammad Shafique, New York University, US
* EMSOFT: International Conference on Embedded Software

EMSOFT


Program Chairs: Clarie Pagetti, Onera/ENSEEIHT, FR
Alessandro Biondi, Scuola Superiore Sant’Anna, IT

Symposia
* MEMOCODE: International Symposium on Formal Methods and Models for System Design

MEMOCODE


* NOCS: International Symposium on Networks-on-Chip

NOCS

Workshops
* CODAI: Workshop on Compilers, Deployment, and Tooling for Edge AI

CODAI’ 2023


* DOT-PIM: Workshop on Agile Design and Optimization Tools for Processing-
In-Memory

DOT-PIM: Agile Design and Optimization Tools for Processing-In-Memory


* RSP: International Workshop on Rapid System Prototyping

RSP 2023

Tutorials
* T1: Introduction to the AMD Versal ACAP Adaptable Intelligent Engine and to its Programming Model
* T2: Designing an Edge Inferencing Accelerator using HLS
* T3: How to Use Model Checking to Analyze Circuits at the Transistor Level
* T4: Neural Network and Autonomous Cyber-Physical Systems Formal Verification for Trustworthy AI and Safe Autonomy
* T5: MARS: A framework for runtime monitoring, modeling, and management of realtime systems
* T6: HW/SW Codesign for Brain-Inspired Hyperdimensional In-Memory Computing\

Education Classes: https://esweek.org/education-classes/
* EC1: TBA
* EC2: TBA
* EC3: 3D Memory – Thermal Challenges and System Management
* EC4: Deterministic Concurrency and the Lingua Franca Coordination Language
* EC5: Efficient and Robust Edge AI: Software, Hardware, and the Co-design
* EC6: CEDR: A Novel Runtime Environment for Accelerator-Rich Heterogeneous Architectures
* EC7: Basics of Machine Learning Accelerator Design
* EC8: Coarse-Grained Reconfigurable Array (CGRA): Architectures and Compilers
* EC9: Design Methodology for Low Power Computer Vision Systems
* EC10: High-Level Synthesis of Complex Parallel Specifications
* EC11: Bringing ML to the Extreme Edge
* EC12: Optical Computing for AI Acceleration
* EC13: The Five Must-to-Have Features of Modern Automotive System-on- Chip Architectures

Competitions
* ACM SIGBED Student Research Competition (SRC)

SRC


* Embedded System Software Competition (ESSC)
https://embedded-research-competition.github.io/cop/
* Tiny and Fair ML Design Contest

Tiny and Fair ML Design

Ph.D. Forum and Recruitment Events: https://esweek.org/esweek-ph-d-forum-and-recruitment-events/

The Ph.D. Forum at ESWEEK 2023 is a poster session with lightning talks for Ph.D. students. The forum is open to all members of the embedded systems community and is free-of-charge. For Ph.D. students presenting posters in this Forum, limited funds will be available for travel assistance, based on financial needs.

The Recruitment Event at ESWEEK 2023 is a place for students and professionals looking for internships or jobs to meet with representatives from companies and academia. In the beginning of the event, one representative from each organization has the opportunity
to introduce the organization and its job opening(s). Afterward, all attendees have a chance to mingle.

Organization: https://esweek.org/organizing-committee/

ESWEEK 2023 General Chairs:
Xiaobo Sharon Hu, University of Notre Dame, US (General Chair)
Alain Girault, INRIA, FR (Vice General Chair)

Conference and Local Arrangement Chair:
Heiko Falk, Hamburg University of Technology, DE


Call for Papers: ISCA 2024
https://www.iscaconf.org/isca2024/submit/papers.php
Submitted by Xiaochen Guo

The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. In 2024, the 51st edition of ISCA will be held in Buenos Aires during June 29 – July 3, 2024

Important Dates

  • Abstracts: November 14, 2023 at 11:59 PM AoE
  • Full Paper Deadline: November 21, 2023 at 11:59 PM AoE
  • Rebuttal/Revision Period: February 9 – 23, 2024
  • Author Notification: March 19, 2024

Topics

Papers are solicited on a broad range of topics, including (but not limited to):

  • Processor, memory, and storage systems architecture
  • Parallelism: instruction, thread, data, multiprocessor
  • Datacenter-scale computing
  • IoT, mobile, and embedded architecture
  • Interconnection network, router, and network interface architectures
  • Architectures for emerging applications including machine learning and bioinformatics
  • Architectural support for programming languages or software development
  • Architectural support for interfacing with accelerators
  • Architectural support for security, virtual memory, and virtualization
  • Dependable processor and system architecture
  • Architectures for emerging technologies including novel circuits, memory technologies, quantum computing, etc.
  • Architecture modeling, simulation methodologies, and tools
  • Evaluation and measurement of real computing system

 Organizers

  • General Chairs: Augusto Vega (IBM Research) and Esteban Mocskos (University of Buenos Aires)
  • Program Chairs: Sandhya Dwarkadas (University of Virginia) and Rajeev Balasubramonian (University of Utah)
  • Industry Track Chair: John Carter (IBM Research)

Call for Papers: FPGA 2024
https://www.isfpga.org/
Submitted by Aman Arora

Call for Papers – FPGA 2024
32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
March 3 – 5, 2024
Website: https://isfpga.org
Submission site: https://fpga24.hotcrp.com (now live)
Abstracts Due:   October 6, 2023
Submissions Due:  October 13, 2023

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2024, the 32nd edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.

Paper Submissions (with and without Artifacts)

We solicit research papers related to the following areas:

  • FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
  • FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory or nano-scale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability.
  • CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
  • High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
  • FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
  • Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.

Research submissions can be in either of two categories:

  • Regular —  at most 10 pages (excluding references), for a regular presentation at the conference.
  • Short — at most 6 pages (excluding references), for a brief presentation.

A paper submitted as either regular or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).

Submission Process

Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/. LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LaTeX link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract and paper submissions in PDF must be received by 11:59 PM AoE (Anywhere-on-Earth time zone).

Submissions will be considered for acceptance as regular or short papers. A paper submitted to the regular or short category will only be considered in that category. Regular or short submissions will also be considered for acceptance as a poster. Once a paper has been submitted, its authorship list is considered to be fixed and final.

By submitting articles to an ACM Publication, authors are hereby acknowledging that they and their co-authors are subject to all ACM Publications Policies (https://www.acm.org/publications/policies), including ACM’s new Publications Policy on Research Involving Human Participants and Subjects (https://www.acm.org/publications/policies/research-involving-human-participants-and-subjects). Alleged violations of this policy or any ACM Publications Policy will be investigated by ACM and may result in a full retraction of their paper, in addition to other potential penalties, as per ACM Publications Policy.

Authors should ensure that they and their co-authors obtain an ORCID ID (https://orcid.org/register), so that they can complete the publishing process for accepted papers. ACM has been involved in ORCID from the start and ACM has recently made a commitment to collect ORCID IDs from all of their published authors (https://authors.acm.org/author-resources/orcid-faqs). The collection process has started and will roll out as a requirement throughout 2023. ACM is committed to improve author discoverability, ensure proper attribution, and contribute to ongoing community efforts around name normalization; authors’ ORCID ID will help in these efforts.

Double Blind Policy

The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. References to the authors’ prior work should be made in the third person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as “Removed for blind review,” but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission. When necessary, authors should cite widely-available Open Source software website(s) without claiming ownership. Grant numbers and other government markings should also be blinded during the review process. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged. Similarly, if a paper can be unblinded by active search, this is not considered to undermine the spirit of the double-blind review. However, there are resources to blind open-source repositories for review, including: https://github.com/tdurieux/anonymous_github.

If you have questions about how to meet these guidelines, please contact the program chair before the submission deadline.

Reviewer Conflict Policy

During paper submission, all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is left undeclared or a nonexistent conflict is declared in an attempt to manipulate the review process, the submission may be rejected.

For more information about the ACM Conflict of Interest Policy, see: https://www.acm.org/publications/policies/conflict-of-interest

Originality of Submissions

Papers submitted are guaranteed by the authors to be unique manuscripts and not previously published, currently accepted or under consideration for acceptance at another venue. They cannot be substantially similar to any other current/future conference, journal, or workshop submission(s) unless the content appeared at a venue that does not have archived proceedings.

Rebuttal Process

The conference review process includes a rebuttal phase for authors to provide an optional response to reviewers’ questions and comments. This information is considered during the final deliberation process.

Author participation

For inclusion in the ACM digital library, at least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel (more instruction will be available after the camera-ready submission).

Best Paper Award

Authors of this year’s best manuscripts will be eligible for the conference’s best paper awards. They will also be invited to extend their work for consideration in a special issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS).

Artifact Evaluation

The conference will allow authors to submit accompanying artifacts for their paper submissions for evaluation. This process will allow ACM recognized badges to be associated with the final publication. The inclusion of artifacts with a submission is not required for a paper submission nor will any preference be given to submissions with artifacts over those without. Papers and artifacts will be subjected to separate and independent review processes. Artifact evaluation must NOT interfere with the double blind reviewing process of their accompanying papers, so all accompanying links in the paper to the artifacts should be blinded. All authors will be required at the time of paper submission to indicate if there will also be associated artifacts for evaluation. If artifacts will be included, a descriptor of their nature will be required. 

For more information, see: https://isfpga.org/artifact-evaluation/

Diversity and Inclusion

The open exchange of ideas and the freedom of thought and expression are central to the aims and goals of the conference. The organizers aim and commit to providing a harassment-free accessible and pleasant conference experience with equity in rights for all. We want every participant to feel welcome, included and safe at the conference.

For more information, see: https://isfpga.org/statement-on-diversity-and-inclusion/

Important Dates

All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12)

Abstracts Due (All Papers) October 6, 2023

(No Extensions)

Submissions Due (All Papers) October 13, 2023

(No Extensions)

Rebuttals Period November 18 – November 26, 2023
Notification of Acceptance (All Papers) December 13, 2023
Camera-Ready Submission Due Mid-January, 2024
Conference March 4 – 5, 2024

Visa Application

Prospective authors and participants requiring a B-2 visa to enter the US should check the visa appointment wait time using this link: https://travel.state.gov/content/travel/en/us-visas.html, and consider applying IMMEDIATELY for a visa, scheduling an appointment in December 2023. By then, notification of acceptance will have been sent out (if applicable), registrations will have been opened, and ACM will be able to deliver letters of support. To the best of our knowledge, the letter of support will never be required before the interview.

Organizing Committee

General Chair Zhiru Zhang Cornell University
Program Chair Andrew Putnam Microsoft
Publications Chair Grace Zgheib Intel
Finance Chair Paolo Ienne EPFL
Workshop Chair Dustin Richmond UC Santa Cruz
Workshop Co-Chair Tyler Sheaves UC Davis
Publicity and Website Chair Aman Arora Arizona State University
Artifact Evaluation Co-Chair Miriam Leeser Northeastern University
Artifact Evaluation Co-Chair Suhaib Fahmy KAUST
Artifact Evaluation Co-Chair Sitao Huang UC Irvine

 


Call for Papers: Bench 2023
https://www.benchcouncil.org/bench2023/index.html
Submitted by Chen Liu

CALL FOR PAPERS
The 15th BenchCouncil International Symposium on Benchmarking, Measuring and Optimizing (Bench 2023)
In conjunction with Federated Intelligent Computing and Chip Conference (FICC 2023)
https://www.benchcouncil.org/bench2023/index.html

Paper Submission Due (full and short papers): Aug 21, 2023, 11:59 PM AoE
Notification: September 30, 2023, 11:59 PM AoE
Final Papers Due: October 31, 2023, 11:59 PM AoE
Conference Date: December 3-5, 2023
Venue: Sanya, China.

Please note that citizens from up to 59 nations can visit Sanya without a Visa from the Chinese Government. Sanya is a beautiful seaside city, well known as Hawaii in China.

Submission website: https://bench2023.hotcrp.com/

Organization

General Co-Chairs
* Rakesh Agrawal, Data Insights Laboratories, San Jose, CA, USA
* Aoying Zhou, East China Normal University

Program Co-Chairs
* Weining Qian, East China Normal University
* Sascha Hunold, TU Wien, Austria

Program Vice-Chairs
* Biwei Xie, Institute of Computing Technology, CAS
* Kai Shu, Illinois Institute of Technology

Web Chair
* Jiahui Dai, BenchCouncil

Publicity Chairs
* Weicong Chen, University of California, Merced
* Dipti Shankar, SAP Labs, Munich

Technical Program Committee
* Ahmad Ghazal, PingCAP
* Bartlomiej Przybylski, Adam Mickiewicz University, Poznań
* Ben Blamey, Uppsala University
* Benson Muite, University of Tartu
* Bin Ren, College of William & Mary
* Bo Wu, Colorado School of Mines
* Chen Zheng, Institute of Software, Chinese Academy of Sciences
* Cheol-Ho Hong, Chung-Ang University
* Chunjie Luo, Institute of Computing Technology, Chinese Academy of Sciences
* David Boehme, Lawrence Livermore National Laboratory
* Florina Ciorba, University of Basel
* Francieli Boito, University of Bordeaux
* Guangli Li, Institute of Computing Technology, Chinese Academy of Sciences
* Gwangsun Kim, POSTECH
* Joseph Schuchart, University of Tennessee, Knoxville
* K. Selçuk Candan, Arizona State University
* Khaled Ibrahim, Lawrence Berkeley National Laboratory
* Lucas Mello Schnorr, UFRGS
* Mario Marino, Leeds Beckett University
* Miaoqing Huan, University of Arkansas
* Murali Emani, Argonne National Laboratory
* Philippe Swartvagher, TU Wien
* Piotr Luszczek, University of Tennessee, Knoxville
* Ryan Grant, Sandia National Laboratories
* Salman Zubair Toor, Uppsala University
* Shu Yin, ShanghaiTech University
* Sophie Cerf, INRIA
* Steven Farrell, Lawrence Berkeley National Laboratory
* Todor Ivanov, Lead Consult
* Woongki Baek, UNIST
* Xiaoyi Lu, University of California, Merced
* Zhen Jia, Amazon
* Zhihui Du, New Jersey Institute of Technology

Award Committees

2023 BenchCouncil Achievement Award Committee
* D. K. Panda, The Ohio State University
* Lizy Kurian John, the University of Texas at Austin
* Geoffrey Fox, Indiana University
* Jianfeng Zhan, University of Chinese Academy of Sciences
* Tony Hey, Rutherford Appleton Laboratory STFC
* David J. Lilja, University of Minnesota, Minneapolis
* Jack J. Dongarra, University of Tennessee
* John L. Henning, Oracle

2023 BenchCouncil Rising Star Award Committees
* D. K. Panda, The Ohio State University
* Lizy Kurian John, the University of Texas at Austin
* Geoffrey Fox, Indiana University
* Jianfeng Zhan, University of Chinese Academy of Sciences
* Torsten Hoefler, ETH Zürich
* Vijay Janapa Reddi, Harvard University
* Peter Mattson, Google, USA
* Douwe Kiela, Stanford University

BenchCouncil Distinguished Doctoral Dissertation Award Committee in Other Areas
* Jack J. Dongarra, University of Tennessee
* Xiaoyi Lu, The University of California, Merced
* Jeyan Thiyagalingam, STFC-RAL
* Lei Wang, ICT, Chinese Academy of Sciences
* Spyros Blanas, The Ohio State University

BenchCouncil Distinguished Doctoral Dissertation Award Committee in Computer Architecture
* Resit Sendag, University of Rhode Island, USA
* Peter Mattson, Google
* Vijay Janapa Reddi, Harvard University
* Wanling Gao, Chinese Academy of Sciences

Bench Steering Committee
* Jack J. Dongarra, University of Tennessee
* Geoffrey Fox, Indiana University
* D. K. Panda, The Ohio State University
* Felix Wolf, TU Darmstadt
* Xiaoyi Lu, University of California, Merced
* Resit Sendag, University of Rhode Island, USA
* Wanling Gao, ICT, Chinese Academy of Sciences & UCAS
* Jianfeng Zhan, BenchCouncil

Topics

The Bench conference encompasses a wide range of topics in benchmarks, datasets, metrics, indexes, measurement, evaluation, optimization, supporting methods and tools, and other best practices in computer science, medicine, finance, education, management, etc. Bench’s multidisciplinary and interdisciplinary emphasis provides an ideal environment for developers and researchers from different areas and communities to discuss practical and theoretical work. The topics of interest include, but are not limited to the following:

Benchmark science and engineering across multi-disciplines:
* The formulation of problems or challenges in emerging and future computing
* The benchmarks, datasets, and indexes in multidisciplinary applications,
e.g., medical, finance, education, management, psychology, etc.
* Benchmark-based quantitative approaches to tackle multidisciplinary and
interdisciplinary challenges, industry best practices

Benchmark and standard specifications, implementations, and validations
* Big Data, Artificial Intelligence (AI), High-Performance Computing (HPC)
* Machine learning, Big scientific data, Datacenter, Cloud, Warehouse-scale computing
* Mobile robotics, Edge and fog computing, Internet of Things (IoT), Blockchain
* Data management and storage, Financial, Education, Medical or other application domains

Datasets
* Detailed descriptions of research or industry datasets,
including the methods used to collect the data and technical analyses
supporting the quality of the measurements
* Analyses or meta-analyses of existing data and original articles on systems,
technologies, and techniques that advance data sharing and reuse
to support reproducible research
* Evaluating the rigor and quality of the experiments used to generate
the data and the completeness of the data description
* Tools that can generate large-scale data while preserving their
original characteristics

Workload characterization, quantitative measurement, design, and evaluation studies
* Computer and communication networks, protocols and algorithms
* Wireless, mobile, ad-hoc and sensor networks, IoT applications
* Computer architectures, hardware accelerators, multi-core processors, memory systems
and storage networks
* HPC systems; Operating systems, file systems and databases; Virtualization, data centers,
distributed and cloud computing, fog and edge computing
* Mobile and personal computing systems, energy-efficient computing systems; real-time and
fault-tolerant systems, security and privacy of computing and networked systems,
software systems and services, and enterprise applications, social networks,
multimedia systems, web services, cyber-physical systems, including the smart grid

Methodologies, metrics, abstractions, algorithms, and tools
* Analytical modeling techniques and model validation
* Workload characterization and benchmarking
* Performance, scalability, power and reliability analysis
* Sustainability analysis and power management
* System measurement, performance monitoring and forecasting
* Anomaly detection, problem diagnosis and troubleshooting
* Capacity planning, resource allocation, run-time management and scheduling
* Experimental design, statistical analysis, and simulation

Measurement and evaluation
* Measurement standards, evaluation methodologies and metrics,
testbed methodologies and systems
* Instrumentation, sampling, tracing and profiling of large-scale,
real-world applications and systems;
* Measurement-based modeling (e.g., workloads, scaling behavior, assessment of
performance bottlenecks)
* Methods and tools to monitor and visualize measurement and evaluation data
* Systems and algorithms that build on measurement-based findings
* Advances in data collection, analysis and storage
(e.g., anonymization, querying, sharing)
* Reappraisal of previous empirical measurements and measurement-based conclusions
* Descriptions of challenges and future directions that the measurement and
evaluation community should pursue

Paper Submission

Papers must be submitted in PDF. For a full paper, the page limit is 15 pages in the LNCS format, not including references. For a short paper, the page limit is 8 pages in the LNCS format, not including references. The review process follows a strict double-blind policy per the established Bench conference norms. The submissions will be judged based on the merit of the ideas rather than the length. After the conference, the proceedings will be published by Springer LNCS (Indexed by EI). Please note that the LNCS format is the final one for publishing.

At least one author must pre-register for the symposium, and at least one author must attend the symposium to present the paper. Papers for which no author is pre-registered will be removed from the proceedings.

Formatting Instructions

Please make sure your submission satisfies ALL of the following requirements: All authors and affiliation information must be anonymized. The paper must be submitted in printable PDF format (LNCS format). Please number the pages of your submission. The submission must be formatted for black-and-white printers. Please make sure your figures are readable when printed in black and white. The submission must describe novel, unpublished work that is not currently under review of any other conference venue or journal.

Submission site: https://bench2023.hotcrp.com/
LNCS latex template: https://www.benchcouncil.org/file/llncs2e.zip

Awards

BenchCouncil Achievement Award ($3,000)
– This award recognizes a senior member who has made long-term contributions to benchmarking, measuring, and optimizing. The winner is eligible for the status of a BenchCouncil Fellow.

BenchCouncil Rising Star Award ($1,000)
– This award recognizes a junior member who demonstrates outstanding potential for research and practice in benchmarking, measuring, and optimizing.

BenchCouncil Best Paper Award ($1,000)
– This award recognizes a paper presented at the Bench conferences, which demonstrates potential impact on research and practice in benchmarking, measuring, and optimizing.

BenchCouncil Distinguished Doctoral Dissertation Award ($2000)
– This award recognizes and encourages superior research and writing by doctoral candidates in the broad field of benchmarks, data, standards, evaluations, and optimizations community. This year, the award includes two tracks, including the BenchCouncil Distinguished Doctoral Dissertation Award in Computer Architecture ($1000) and BenchCouncil Distinguished Doctoral Dissertation Award in other areas ($1000).


Call for Papers: ISFPGA
https://www.isfpga.org/call-for-papers/
Submitted by Aman Arora

Call for Papers – FPGA 2024
32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
March 3 – 5, 2024
Website: https://isfpga.org
Submission site: https://fpga24.hotcrp.com
Abstracts Due:   October 6, 2023

Submissions Due:  October 13, 2023

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2024, the 32nd edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.

Paper Submissions (with and without Artifacts)

We solicit research papers related to the following areas:

  • FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
  • FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory or nano-scale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability.
  • CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
  • High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
  • FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
  • Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.

Research submissions can be in either of two categories:

  • Regular —  at most 10 pages (excluding references), for a regular presentation at the conference.
  • Short — at most 6 pages (excluding references), for a brief presentation.

A paper submitted as either regular or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).

Submission Process

Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/. LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LaTeX link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract and paper submissions in PDF must be received by 11:59 PM AoE (Anywhere-on-Earth time zone).

Submissions will be considered for acceptance as regular or short papers. A paper submitted to the regular or short category will only be considered in that category. Regular or short submissions will also be considered for acceptance as a poster. Once a paper has been submitted, its authorship list is considered to be fixed and final.

By submitting articles to an ACM Publication, authors are hereby acknowledging that they and their co-authors are subject to all ACM Publications Policies (https://www.acm.org/publications/policies), including ACM’s new Publications Policy on Research Involving Human Participants and Subjects (https://www.acm.org/publications/policies/research-involving-human-participants-and-subjects). Alleged violations of this policy or any ACM Publications Policy will be investigated by ACM and may result in a full retraction of their paper, in addition to other potential penalties, as per ACM Publications Policy.

Authors should ensure that they and their co-authors obtain an ORCID ID (https://orcid.org/register), so that they can complete the publishing process for accepted papers. ACM has been involved in ORCID from the start and ACM has recently made a commitment to collect ORCID IDs from all of their published authors (https://authors.acm.org/author-resources/orcid-faqs). The collection process has started and will roll out as a requirement throughout 2023. ACM is committed to improve author discoverability, ensure proper attribution, and contribute to ongoing community efforts around name normalization; authors’ ORCID ID will help in these efforts.

Double Blind Policy

The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. References to the authors’ prior work should be made in the third person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as “Removed for blind review,” but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission. When necessary, authors should cite widely-available Open Source software website(s) without claiming ownership. Grant numbers and other government markings should also be blinded during the review process. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged. Similarly, if a paper can be unblinded by active search, this is not considered to undermine the spirit of the double-blind review. However, there are resources to blind open-source repositories for review, including: https://github.com/tdurieux/anonymous_github.

If you have questions about how to meet these guidelines, please contact the program chair before the submission deadline.

Reviewer Conflict Policy

During paper submission, all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is left undeclared or a nonexistent conflict is declared in an attempt to manipulate the review process, the submission may be rejected.

For more information about the ACM Conflict of Interest Policy, see: https://www.acm.org/publications/policies/conflict-of-interest

Originality of Submissions

Papers submitted are guaranteed by the authors to be unique manuscripts and not previously published, currently accepted or under consideration for acceptance at another venue. They cannot be substantially similar to any other current/future conference, journal, or workshop submission(s) unless the content appeared at a venue that does not have archived proceedings.

Rebuttal Process

The conference review process includes a rebuttal phase for authors to provide an optional response to reviewers’ questions and comments. This information is considered during the final deliberation process.

Author participation

For inclusion in the ACM digital library, at least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel (more instruction will be available after the camera-ready submission).

Best Paper Award

Authors of this year’s best manuscripts will be eligible for the conference’s best paper awards. They will also be invited to extend their work for consideration in a special issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS).

Artifact Evaluation

The conference will allow authors to submit accompanying artifacts for their paper submissions for evaluation. This process will allow ACM recognized badges to be associated with the final publication. The inclusion of artifacts with a submission is not required for a paper submission nor will any preference be given to submissions with artifacts over those without. Papers and artifacts will be subjected to separate and independent review processes. Artifact evaluation must NOT interfere with the double blind reviewing process of their accompanying papers, so all accompanying links in the paper to the artifacts should be blinded. All authors will be required at the time of paper submission to indicate if there will also be associated artifacts for evaluation. If artifacts will be included, a descriptor of their nature will be required. 

For more information, see: https://isfpga.org/artifact-evaluation/

Diversity and Inclusion

The open exchange of ideas and the freedom of thought and expression are central to the aims and goals of the conference. The organizers aim and commit to providing a harassment-free accessible and pleasant conference experience with equity in rights for all. We want every participant to feel welcome, included and safe at the conference.

For more information, see: https://isfpga.org/statement-on-diversity-and-inclusion/

Important Dates

All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12)

Abstracts Due (All Papers) October 6, 2023

(No Extensions)

Submissions Due (All Papers) October 13, 2023

(No Extensions)

Rebuttals Period November 18 – November 26, 2023
Notification of Acceptance (All Papers) December 13, 2023
Camera-Ready Submission Due Mid-January, 2024
Conference March 4 – 5, 2024

Visa Application

Prospective authors and participants requiring a B-2 visa to enter the US should check the visa appointment wait time using this link: https://travel.state.gov/content/travel/en/us-visas.html and consider applying IMMEDIATELY for a visa, scheduling an appointment in December 2023. By then, notification of acceptance will have been sent out (if applicable), registrations will have been opened, and ACM will be able to deliver letters of support. To the best of our knowledge, the letter of support will never be required before the interview.

Organizing Committee

General Chair Zhiru Zhang Cornell University
Program Chair Andrew Putnam Microsoft
Publications Chair Grace Zgheib Intel
Finance Chair Paolo Ienne EPFL
Workshop Chair Dustin Richmond UC Santa Cruz
Workshop Co-Chair Tyler Sheaves UC Davis
Publicity and Website Chair Aman Arora Arizona State University
Artifact Evaluation Co-Chair Miriam Leeser Northeastern University
Artifact Evaluation Co-Chair Suhaib Fahmy KAUST
Artifact Evaluation Co-Chair Sitao Huang UC Irvine

 


Call for Papers: HOST 2024
http://www.hostsymposium.org/
Submitted by Kimia Z Azar

The IEEE International Symposium on Hardware Oriented Security and Trust (HOST) – the premier event aiming to facilitate the rapid growth of hardware security research and development – is set to take place in May 2024 in Washington D.C. Attendees can look forward to a diverse range of technical sessions from original and novel contributions, informative tutorials, captivating exhibitions and hardware demonstrations, and exciting competitions, including the microelectronic security competition and PhD dissertation competition. HOST 2024 invites original contributions in all areas of overlap between hardware and security, including but not limited to the following:

  • Computer-aided Design (CAD) for Hardware Security Verification
    • e.g., automatic techniques and metrics for life cycle security management and detecting security vulnerabilities.
  • Hardware Security Primitives
    • e.g., PUFs, TRNGs, cryptography, post-quantum cryptography, odometers.
  • Hardware Attack and Defense
    • e.g., hardware Trojans, fault injection, side-channels, hardware reverse engineering, hardware obfuscation.
  • Architecture Security
    • e.g., architectural side-channels, trusted execution environment, FPGA and reconfigurable fabric security.
  • System security
    • e.g., machine learning security, SoC/IP security, CPS/IoT security, sensor network security, smart grid security, cloud security.
  • Emerging or Other Topics
    • e.g., privacy-enhancing architecture, cryptocurrency security, and other hardware/system security topics.

Fall Submission

August 21, 2023: Abstract Submission*
August 28, 2023: Full Paper Submission
October 15, 2023: Notification of Acceptance
November 15, 2023: Camera-ready Version

Winter Submission

December 11, 2023: Abstract Submission*
December 18, 2023: Submission of Paper
February 15, 2024: Notification of Acceptance
March 15, 2024: Camera-ready Version

Abstract registration is required – Only the papers registered by the abstract submission deadline can update the submission file by the paper submission deadline. HOST 2024 also accepts proposals for tutorials and demos. More information will be disseminated in future calls.

Contact Inforamtion

Program Chairs

General Chairs

Vice Program Chairs


Call for Papers: HPCA 2024
https://www.hpca-conf.org/2024/
Submitted by Christina Giannoula

REGULAR TRACK CALL FOR PAPERS
30th IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Edinburgh, UK
March 2 – March 6, 2024
https://www.hpca-conf.org/2024/

The International Symposium on High-Performance Computer Architecture (HPCA) is the premier forum for new ideas and research results in computer architecture. In 2024, the 30th edition of HPCA will be held in Edinburgh, Scotland, UK.

Important Dates
Abstract: July 28, 2023 at 11:59 PM PDT
Full Paper: August 4, 2023 at 11:59 PM PDT
Rebuttal/Revision:October 2 – 13, 2023
Author Notification:October 24, 2023

Regular Track Call For Papers
Some topics of interest are listed below, but we encourage authors to contact the PC chair, if they have a question regarding the topic fit.

  • Processor, memory, and storage systems architecture
  • Instruction-, thread-, and data-level parallelism
  • Interconnection network, router, and network interface architecture
  • Domain-Specific architectures, including FPGA, CGRA, and reconfigurable systems
  • Near/In-Memory computing
  • Cloud, datacenter, cluster/distributed systems and applications
  • Approximate computing
  • Compilers/PL for novel architectures
  • IoT, mobile, Edge, and embedded architecture
  • Effects of circuits or technology on architecture (3D/chiplets/interposer/wafer-scale)
  • Architecture modeling and simulation methodologies
  • Neuromorphic computing
  • Quantum/ Superconducting computing
  • Reliability/Fault Tolerance
  • Security/Privacy
  • Evaluation and measurement of real computing systems
Submissions should follow the guidelines and formatting rules specified on the conference website
(
https://www.hpca-conf.org/2024/submit/guidelines.php). 

Call for Papers: Workshop on Accelerated Machine Learning @ HiPEAC 2024
https://accml.dcs.gla.ac.uk/
Submitted by José Cano

6th Workshop on Accelerated Machine Learning (AccML)
Co-located with the HiPEAC 2024 Conference
(https://www.hipeac.net/2024/munich/)
January 17, 2024
Munich, Germany

Call For Contributions
The remarkable performance achieved in a variety of application areas (natural language processing, computer vision, games, etc.) has led to the emergence of heterogeneous architectures to accelerate machine learning workloads. In parallel, production deployment, model complexity and diversity pushed for higher productivity systems, more powerful programming abstractions, software and system architectures, dedicated runtime systems and numerical libraries, deployment and analysis tools. Deep learning models are generally memory and computationally intensive, for both training and inference. Accelerating these operations has obvious advantages, first by reducing the energy consumption (e.g. in data centers), and secondly, making these models usable on smaller devices at the edge of the Internet. In addition, while convolutional neural networks have motivated much of this effort, numerous applications and models involve a wider variety of operations, network architectures, and data processing. These applications and models permanently challenge computer architecture, the system stack, and programming abstractions. The high level of interest in these areas calls for a dedicated forum to discuss emerging acceleration techniques and computation paradigms for machine learning algorithms, as well as the applications of machine learning to the construction of such systems.

Organizers: https://accml.dcs.gla.ac.uk/

Topics
Topics of interest include (but are not limited to):

  • Novel ML systems: heterogeneous multi/many-core systems, GPUs and FPGAs;
  • Software ML acceleration: languages, primitives, libraries, compilers and frameworks;
  • Novel ML hardware accelerators and associated software;
  • Emerging semiconductor technologies with applications to ML hardware acceleration;
  • ML for the construction and tuning of systems;
  • Cloud and edge ML computing: hardware and software to accelerate training and inference;
  • Computing systems research addressing the privacy and security of ML-dominated systems;
  • ML techniques for more efficient model training and inference (e.g. sparsity, pruning, etc);
  • Generative AI and their impact on computational resources

Invited Speakers
Keynote: Giuseppe Desoli (STMicroelectronics)
Other invited speakers will be announced before the paper submission deadline.

Submission
Papers will be reviewed by the workshop’s technical program committee according to criteria regarding the submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions in the context of accelerating machine learning. Research papers, case studies, and position papers are all welcome.

In particular, we encourage authors to submit work-in-progress papers: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and spark productive discussions.

The workshop does not have formal proceedings.

Important Dates
Submission deadline: November 3, 2023
Notification of decision: December 1, 2023

Organizers
José Cano (University of Glasgow)
Valentin Radu (University of Sheffield)
José L. Abellán (University of Murcia)
Marco Cornero (DeepMind)
Ulysse Beaugnon (Google)
Juliana Franco (DeepMind)


Call for Papers: Workshop on Democratizing Domain-Specific Accelerators @ MICRO56
https://www.escalab.org/wddsa2023/
Submitted by Hung-Wei Tseng

WDDSA is a venue that explores the potential of the renaissance of general-purpose computing using emerging domain-specific accelerators (DSAs).  

While we are interested in work that supports general-purpose computing on recent DSAs, we also encourage submissions in general on DSAs and their infrastructure. This workshop is interested in but is not limited to the following topics.

  1. Novel use cases of an accelerator where applications are outside accelerators’ original application domains
  2. Systems, programming, and software for democratizing domain-specific accelerators.
  3. Architectural support for democratizing domain-specific accelerators.
  4. Performance/power/energy evaluation/analysis of democratizing domain-specific accelerators
  5. Implications to future “democratized” accelerator design.

  We have three tracks of submissions.

  1. Original research papers. WDDSA welcomes papers on projects working on innovative ideas with preliminary results. WDDSA works together with IEEE Computer Architecture Letters (IEEE CAL) to invite top papers in this track to publish in IEEE CAL.
  2. Published research papers with artifacts available. The submission can be based on an already published work (published within 12 months upon the submission deadline). WDDSA provides a platform for these papers to promote their artifacts, allowing the community to use and extend existing projects. The presentation may consider including a live demo.
  3. Industry insights. WDDSA also welcomes papers on industry projects, encouraging the industry to have conversations with the academia.

The submission deadline is 9/15/2023. Please check https://www.escalab.org/wddsa2023/ for more details.


Call for Papers: RoboARCH @ MICRO 2023
https://sites.google.com/g.harvard.edu/roboarch2023
Submitted by Sabrina M. Neuman

Call for Abstracts and Participation: RoboARCH at MICRO 2023
Workshop on Robotics Acceleration with Computing Hardware (RoboARCH)
October 28, 2023 in Toronto, Canada
Co-located with the IEEE/ACM International Symposium on Microarchitecture (MICRO)

Robotics is pushing the limits of conventional computing. Autonomous robots must operate untethered in dynamic and unpredictable environments, requiring many robotics software applications to run online in real-time. Conventional CPU systems are proving unable to deliver the high performance needed by essential latency-critical robotics applications. This is a call to action for researchers across academia and industry: we must leverage nontraditional computing hardware (e.g., custom accelerator ASICs, FPGAs, and GPUs) and navigate enormous design spaces spanning across algorithms, hardware, and physical robot parameters in order to design new high performance systems enabling critical tasks in robotics. This workshop aims to gather pioneers and innovators working at the intersection of robotics and computer architecture, and to provide an introduction to this exciting emerging field to the computer architecture community.

We welcome submission of 2-page abstracts on any topic related to accelerating robotics applications (e.g., computer vision, mapping, localization, motion planning, control, and end-to-end learning, for all robotics systems) using nontraditional computing hardware (e.g., ASICs, FPGAs, GPUs), as well as real-time, distributed, cloud, and edge computing systems that might be leveraged by robotics platforms. We especially encourage early work, and work-in-progress. Position papers and “wild and crazy ideas” papers are also welcome.

Accepted authors will be invited to present a 2-minute single-slide lightning talk during the main program and a poster. Submissions are anonymous, so please remove author names and all identifying information from the submission. See submission instructions on the workshop website: https://sites.google.com/g.harvard.edu/roboarch2023/call-for-abstracts

Important Dates:

Abstract Submission Deadline: September 22, 2023
Author Notification: September 27, 2023
Workshop Date: October 28, 2023


Call for Papers: CAMS 2023 : The 1st Workshop on Computer Architecture Modeling and Simulation
https://sarchlab.github.io/cams2023/
Submitted by Ying Li

Call for papers
The 1st Workshop on Computer Architecture Modeling and Simulation (CAMS 2023)
https://sarchlab.github.io/cams2023/
October 28 or 29, 2023
Toronto, Canada

Summary

Simulator and performance modeling tools are the lifeblood of advancements in computer architecture research and design. They allow researchers to predict, analyze, and understand complex systems, ultimately driving forward technological innovation. Our “Computer Architecture Modeling and Simulation” workshop is dedicated to this critical field. It offers a platform for enthusiasts, researchers, and industry professionals to discuss simulator development, performance and power modeling, AI-based modeling techniques, and more. Beyond exploring technical aspects, this workshop emphasizes the necessity of creating and appreciating effective tools and standardizing methods to evaluate them. We aim to generate meaningful discussions and collaboration, fostering the development of impactful solutions and methodologies that will shape the future of computer architecture modeling and simulation.

Authors are invited to submit original research papers in the general area of computer architecture modeling and simulation. Topics include, but are not limited to:

  • Simulator Development: Design, theory, implementation, and integration of simulators.
  • Performance Modeling: Strategies for prediction, validation, and architectural feature impact assessment.
  • Power Modeling and Simulation: Methods for power-efficient design and power-performance trade-off analysis.
  • Tools and Studies Survey: Review and comparison of existing simulation tools and applications.
  • Scalable Simulation Techniques: Approaches for improving simulation scalability and efficiency.
  • Modeling and Simulation for Unconventional Architectures: Challenges and approaches for emerging and unconventional architectures.
  • Hardware-in-the-loop Simulation: Advancements and case studies in hardware-in-the-loop validation.
  • Modeling for Machine Learning (Sim4AI): Architectural considerations and models for hardware accelerators.
  • AI-Based Performance Modeling Techniques (AI4Sim): Exploration of AI application in performance modeling.
  • Validation Techniques: Approaches for validating simulation model accuracy.
  • Human-centered Simulation Methods: User-friendly visualization, real-time monitoring, and user-centric analysis techniques.

Important Dates

Papers due: September 1, 2023
Author Notification: October 6, 2023

Submission Guideline

Full paper submissions must be in PDF format for US letter-size or A4 paper. They must not exceed 6 pages (excluding unlimited references) in standard ACM two-column conference format (review mode, with page numbers and both 9 or 10pt can be used). More concise papers with ideas clearly expressed are also welcomed. Authors can select if they want to reveal their identity in the submission. Templates for ACM format are available for Microsoft Word and LaTeX at this link. https://www.acm.org/publications/proceedings-template

We do not put the paper in the ACM or IEEE digital libraries. Therefore, the papers submitted to the event can be submitted to other venues without restrictions.

At least one author of accepted papers is expected to present in person during the event. We understand the travel difficulty of the post-pandemia era. In extreme cases, we will allow remote or pre-recorded presentations.

Organization

Chairs

  • Yifan Sun (William & Mary)
  • Trevor E. Carlson (National University of Singapore)

Web Chair

  • Ying Li (William & Mary)

Program Committee

  • José L. Abellán (University of Murcia)
  • Bobby Bruce (University of California, Davis)
  • Shi Dong (Cerebras)
  • Hyeran Jeon (University of California, Merced)
  • Adwait Jog (University of Virginia)
  • Youngsok Kim (Yonsei University)
  • Daniel Wong (University of California, Riverside)
  • Jieming Yin (Nanjing University of Post and Telecommunications)
  • Zi Yan (NVIDIA)
  • Le Xu (University of Texas Austin)
  • Amir Kavyan Ziabari (AMD)

Call for Papers: Hardware and Architectural Support for Security and Privacy (HASP)
https://www.haspworkshop.org/2023/index.html
Submitted by Tianwei Zhang

Although much attention has been directed to the study of security at the system and application levels, security and privacy research focusing on hardware and architecture aspects is still a new frontier. In the era of cloud computing, smart devices, and novel nano-scale devices, practitioners and researchers have to address new challenges and requirements in order to meet the ever-changing landscape of security research and new demands from consumers, enterprises, governments, defense and other industries.

HASP is intended to bring together researchers, developers, and practitioners from academia and industry, to share practical implementations and experiences related to all aspects of hardware and architectural support for security and privacy, and to discuss future trends in research and applications. To that end, papers are solicited from the areas, including, but not limited to:

  • Secure hardware processor architectures and implementations
  • Side-channel attacks, evaluations, and defenses
  • Secure cache designs and evaluation, focusing on side-channels
  • SGX, SEV and Trustzone based systems and security solutions
  • Hardware-enhanced cloud security
  • Security of emerging architectures, such as Quantum Computers
  • Hardware support for secure Internet-of-Things
  • Smartphone hardware security
  • Hardware fingerprinting and PUFs
  • Hardware and architectural support for trust management
  • Hardware trojan threat evaluation, detection, and prevention
  • Attack resilient hardware and architectural design
  • Cryptographic hardware design, implementation, and evaluation
  • Security simulation, testing, validation and verification
  • Analysis of real attacks and threat evaluation

In addition to regular papers, authors can also submit the following types of papers: (1) Short papers. The program committee may recommend that certain regular papers be accepted and presented at short papers, instead of the regular papers. If authors agree, they will have to shorten their paper prior to publication. (2) Position papers. These papers should define new problems in hardware or architecture security and privacy topics. (3) Systemization-of-Knowledge papers. These papers should concisely, but exhaustively, systematize and conceptualize existing knowledge (similar to SoK papers in S&P conferences, but focusing on hardware and architecture). (4) Work-in-progress papers. researchers wishing to share their ongoing work without publishing a paper should submit application for a Work-in-Progress presentation. These papers will not be published in the proceedings, but the title and authors will be listed on the HASP web page as a public record of the presentation.

HASP 2023 will feature keynote and invited talks by Edward Suh, Cornell University/Meta, Jakub Szefer from Yale University, Gururaj Saileshwar, University of Toronto/Nvidia Research, and another speaker from industry.

HASP 2023 will also organize a mentoring program, which provides student attendees opportunities to (1) know senior researchers at MICRO, (2) receive feedback and advice on their research and career. They will be paired up with faculty/postdoc mentors for meetings during the workshop/conference, and any following ups afterwards.

Submission Information

Papers can be submitted on the EasyChair web page: https://easychair.org/conferences/?conf=hasp2023. All submissions must be using the double-column ACM ICPS template. Please use the ACM Standard template in the usual two-column format. The submissions should be anonymized for double-blind review. Regular submissions and position papers must be at most 8 pages including the bibliography and appendices (these papers may be recommended for acceptance as short 5-page papers during the review process, but full-length papers should be initially submitted if authors want to be considered for a full-length paper publication). Authors can also directly submit a short paper of at most 5 pages including the bibliography and appendices. Work-in-Progress submissions must be at most 3 pages total (the submission is only for review, Work-in-Progress papers are not published). SoK papers should also be 8 pages, but exceptions can be made, please contact the organizers with any questions. Short papers, position papers, SoK papers and Work-in-Progress papers should have “Short Paper”, “Position Paper”, “SoK”, and “WiP” as the prefix to the title.

All accepted regular papers, short papers, position papers, and SoK papers will be included in the ACM Digital Library; Work-in-Progress papers are not included. The proceedings will be published through ACM ICPS and available through the ACM Digital Library.

Important Dates

  • Submission Deadline:                      August 10, 2023, AoE
  • Notification of Acceptance:              August 31, 2023
  • Camera-ready Version:                    September 30, 2023

Organization and Contact Information
Program Chairs

  • Wenjie Xiong, Virginia Tech, wenjiex@vt.edu
  • Tianwei Zhang, Nanyang Technological University, tianwei.zhang@ntu.edu.sg

Steering Committee

  • Ruby B. Lee, Princeton University
  • Weidong Shi, University of Houston
  • Jakub Szefer, Yale University

Call for Papers: IEEE Micro Special Issue on Top Picks from the 2023 Computer Architecture Conferences
https://www.linkedin.com/company/98719560
Submitted by Yan Solihin

Call for Papers: IEEE Micro Special Issue on Top Picks from the 2023 Computer Architecture Conferences

IEEE Micro will publish its annual “Top Picks from the Computer Architecture Conferences” issue in July/August 2024. This issue collects some of the most significant research papers in computer architecture based on novelty and potential for long-term impact. Any computer architecture paper published in the top conferences of 2023 (including MICRO-56) is eligible. Each Top Picks submission must be based on a single paper, not a combination of multiple papers. The Top Picks Selection Committee will recognize those significant and insightful papers that have the potential to influence the work of computer architects for years to come.

Important Dates

  • Submission website opens: October 6, 2023
  • Submission deadline: November 3, 2023
  • Author notification: January 19, 2024
  • Revised papers due: February 16, 2024
  • Publication: July/August 2024

Submission Guidelines

To simplify reviewing, there is a mandatory format for submissions. Authors will need to upload the following two documents:

1. A three-page (including all references), two-column document using 10-point type. The first two pages should summarize the paper. The third page should argue for the potential of the work to have long-term impact, clearly articulating why and how it will influence other researchers and/or industry.

2. The final version of the original conference paper.

Submissions that do not follow this format will not be reviewed. The first document should contain the names of the authors with a footnote that includes the title of the original conference paper, the full name of the conference, and date of publication.

Please submit here: https://toppicks2024.hotcrp.com

Accepted Paper Guidelines

Authors of accepted papers will receive further instructions on how to prepare the final papers to conform to IEEE Micro‘s guidelines. Final papers should not exceed 6,000 words including no more than 15 references and short bios of authors, with each average-size figure counting as 250 words toward this limit. Papers must have at least 30 percent new content. Final papers will be reviewed again before publication and edited for structure, style, clarity, and readability.

Guest Editor (and Selection Committee Chair)

Yan Solihin, University of Central Florida
Contact the guest editors at toppicks2024@gmail.com


Call for Presentations: MICRO 2023 PhD Forum
https://microarch.org/micro56/submit/PhDForum.php
Submitted by Benjamin Lee

We are inviting submissions to the MICRO 2023 PhD Forum, a conference session for Ph.D students to present their dissertation research and gain visibility within the computer architecture community as they prepare for the academic job market. The presentation format will be a poster session. The Forum welcomes presentations on any topic in computer architecture (e.g., see MICRO call for papers). 

Eligibility. Students should have published in the community’s rigorously peer-reviewed conferences or journals. Students should be within 1-2 years, before or after, of dissertation completion. Students closer to graduation will be given priority as other students can attend a future forum with more mature results. Interested participants will submit (a) two-page research statement; (b) published or accepted first-author paper from ASPLOS, HPCA, ISCA, or MICRO; and (c) curriculum vitae. 

Important Dates
Submissions Due: 23 August 2023
Author Notification : 1 September 2023

Details and Submission Webpage.
https://microarch.org/micro56/submit/PhDForum.php

Contact
Benjamin C. Lee, Ph.D.
Professor, University of Pennsylvania
Department of Electrical and Systems Engineering
Department of Computer and Information Science
https://www.seas.upenn.edu/~leebcc/


Call for Workshops/Tutorials: SAGE @ MICRO 2023
https://sites.google.com/corp/view/sage2023/
Submitted by Amir Yazdanbakhsh

System and Architecture for Generative AI on the Edge/Mobile Platforms is an interdisciplinary workshop that brings together researchers in computer architecture and systems and machine learning. This workshop is meant to serve as a platform to promote discussions between researchers in the workshop’s target areas. Subject areas of the workshop included (but not limited to):

  • Mobile-specific architectural designs for generative AI models
  • System-level optimizations for efficient execution of generative AI on mobile devices
  • Energy-efficient techniques for training and inference of generative AI models
  • Model compression methods, such as sparsification and quantization, for reducing the memory footprint of generative AI on mobile platforms
  • Federated learning and collaborative techniques for training generative AI models on distributed mobile devices
  • Privacy-preserving and secure frameworks for generative AI on mobile platforms
  • Integration of generative AI into mobile applications and services
  • Case studies and real-world deployments of generative AI on mobile platforms
  • Wild and crazy ideas (WACI) of generative AI use cases

We welcome paper submissions of up to 4 pages. Deadline: September 4th, 2023, 11:59 AoE.


Call for Workshops/Tutorials: Machine Learning for Systems at NeurIPS 2023
http://mlforsystems.org/
Submitted by Divya Mahajan

Machine Learning for Systems at NeurIPS 2023
 http://mlforsystems.org/

Important Dates

  • Competition Start Date: Late August, 2023 (to be announced)
  • Paper Submission Deadline: September 29, 2023 by midnight (Anywhere in the World)
  • Paper Acceptance Notifications: October 27, 2023
  • Competition Submission Deadline: November 17, 2023
  • Workshop: December 16, 2023 (tentatively scheduled)

NeurIPS 2023 Machine Learning for Systems Call for Papers

Machine Learning for Systems is an interdisciplinary workshop that brings together researchers in computer systems and machine learning. This workshop is meant to serve as a platform to promote discussions between researchers in these target areas.

We invite submission of up to 4-page extended abstracts in the broad area of using machine learning in the design of computer systems. We are especially interested in submissions that move beyond using machine learning to replace numerical heuristics. This year, we additionally look for:

1.   Using LLMs for systems challenges, such as program synthesis for hardware and other specialized domains.

2.   Applying ML to systems issues that emerge from large-scale training and serving, such as compiler partitioning schemes for training LLMs across thousands of GPU or TPU devices.

Accepted papers will be made available on the workshop website, but there will be no formal proceedings. Authors may therefore publish their work in other journals or conferences. The workshop will include invited talks from industry and academia as well as oral and poster presentations by workshop participants.

You can find accepted papers to the previous iteration of ML for Systems from NeurIPS 2018, 2019, 2020, 20212022, and ISCA 2019.

Areas of interest:

  • Supervised, unsupervised, and reinforcement learning research with applications to:
    • Systems software
    • Runtime systems
    • Distributed systems
    • Security
    • Compilers, data structures, and code optimization
    • Databases
    • Computer architecture, microarchitecture, and accelerators
    • Circuit design and layout
    • Interconnects and Networking
    • Storage
    • Datacenters
    • Programming Languages
  • Representation learning for hardware and software
  • Optimization of computer systems and software
  • Systems modeling and simulation
  • Implementations of ML for systems and challenges
  • High quality datasets for ML for systems problems
  • Emerging applications
    • Using LLMs for systems
    • Using ML for challenges in large-scale machine learning systems for ML training and serving

Submission Instructions

We welcome submissions of up to 4 pages (not including references). This is not a strict limit, but authors are encouraged to adhere to it if possible. All submissions must be in PDF format and should follow the NeurIPS 2023 format. Submissions do not have to be anonymized.

Please submit your paper no later than September 29th, 2023 midnight anywhere in the world to the OpenReview submission site.

Competition Track

This year, our workshop introduces a competition track to showcase and explore state-of-the-art techniques in ML for systems. We hope that the first iteration of the competition track will serve as an initiative to encourage industry to share ML for systems data and research based on real-world production data. The top winners have the opportunities to share their technical reports to receive sponsor prizes.

The instructions for the competition track will be posted soon. If you would like to be notified when the competition is up, please join:

https://groups.google.com/g/tpu_graphs_competition

Organizing Committee

  • Beidi Chen, CMU
  • Dan Zhang, Google DeepMind
  • Divya Mahajan, Microsoft and Georgia Tech
  • Mangpo Phothilimthana, Google DeepMind
  • Mimee Xu, NYU
  • Yawen Wang, Google

Competition Committee

  • Bryan Perozzi, Google Research
  • Mangpo Phothilimthana, Google DeepMind
  • Sami Abu-el-haija, Google Research

Contact Us

Contact us at mlforsystems@googlegroups.com


Call for Workshops/Tutorials: HPCA 2024: Call for Workshops & Tutorials
https://www.hpca-conf.org/2024/
Submitted by Christina Giannoula

CALL FOR WORKSHOPS & TUTORIALS
30th IEEE International Symposium on High-Performance Computer Architecture (HPCA)
HPCA 2024   
Edinburgh, UK
March 2 – March 3, 2024
https://www.hpca-conf.org/2024/

The International Symposium on High-Performance Computer Architecture (HPCA) is the premier forum for new ideas and research results in computer architecture. In 2024, the 30th edition of HPCA will be held in Edinburgh, Scotland, UK.

Important Dates
Proposal Submission Deadline: September 15, 2023 at 23:59 AoE
Notification: September 29, 2023
Proposals should be sent via email to: wt.hpca2024@gmail.com


Proposal Format
Workshop and tutorial proposals should be one to two pages, and must include the following information:
* the title of the workshop/tutorial
* the organizers, their affiliations, and short bios
* the expected duration of the workshop/tutorial (i.e., half day or full day),
* If the workshop/tutorial was held previously, the location (which conference), date, number of talks, and number of attendees
* for workshop proposals: a sample call for papers, including the main workshop topics
* for tutorial proposals: an abstract and a tentative outline of the tutorial program / topics covered


Call for Posters: ACM Student Research Competition at PACT 2023
https://pact2023.github.io/src/
Submitted by Saugata Ghose

PACT 2023 invites students to participate in the ACM Student Research Competition (SRC). The SRC is a forum for graduate and undergraduate students to share their research results, exchange ideas, and improve their communication skills while competing for prizes. The SRC consists of three rounds: (1) an online abstract submission, (2) a poster session at PACT 2023 for accepted abstracts, and (3) a presentation at PACT 2023 by poster session finalists.

All authors of accepted abstracts will receive discounted conference registration to PACT (October 23-25, 2023, in Vienna), to help offset costs of attendance. Students must attend PACT 2023 in person to take part in the poster session and finalist presentation.

Student winners receive prizes of $500, $300, and $200 for first/second/third place, respectively, in each of the undergraduate and graduate divisions, along with a framed certificate.

800-word poster abstracts are due August 17, 2023 (AoE), and authors are expected to be notified on September 1.

For more details, please see the ACM SRC @ PACT 2023 website at https://pact2023.github.io/src/


Call for Posters: Call for Posters: IISWC 2023
https://iiswc.org/iiswc2023/#/call-for-posters/
Submitted by Resit Sendag

Call for posters
Submissions: iiswc2023posters.hotcrp.com

IEEE International Symposium on Workload Characterization (IISWC) is dedicated to the understanding and characterization of workloads that run on all types of computing systems. This symposium will focus on characterizing and understanding emerging applications in consumer, commercial and scientific computing. IISWC 2023 will be held on October 1-3, 2023 in Ghent, Belgium.

Authors are invited to submit extended poster abstracts encompassing ongoing or late breaking research, tools or benchmarks in any of the following fields.

Characterization of applications in domains including:

  • Life sciences, bioinformatics, scientific computing, finance, forecasting
  • Machine learning, data analytics, data mining
  • Cyber-physical systems, pervasive computation and Internet of Things (IoT)
  • Security and privacy-preserving computing
  • High performance computing
  • Cloud and edge computing
  • Mobile computing
  • User behavior and system-user interaction
  • Search engines, e-commerce, web services, and databases
  • Embedded, multimedia, real-time, 3D-graphics, gaming
  • Blockchain services
  • Augmented reality and virtual reality

Characterization of workloads for emerging workloads and architectures, such as

  • Quantum computations and communication
  • Serverless computing
  • Near-threshold computing
  • Non-volatile memory
  • Near data processing architectures
  • Neuromorphic and brain-inspired computing
  • Transactional memory systems
  • Biology (e.g., DNA sequencing) and chemistry workloads

Characterization of OS, Virtual Machine, middleware and library behavior, including

  • Virtual machines, .NET, Java VM, databases
  • Graphics libraries, scientific libraries
  • Operating system and hypervisor effects and overheads

Implications of workloads in system design, such as

  • Power management, reliability, security, privacy, performance
  • Processors, memory hierarchy, I/O, and networks
  • Design of accelerators, FPGAs, GPUs, CGRAs, etc.
  • Large-scale computing infrastructures and facilities

Benchmark methodologies and suites, including

  • Representative benchmarks for emerging workloads
  • Benchmark cloning methods
  • Profiling, trace collection, synthetic traces
  • Validation of benchmarks

Measurement tools and techniques, including

  • Instrumentation methodologies for workload verification and characterization
  • Techniques for accurate analysis/measurement of production systems
  • Analytical and abstract modeling of program behavior and systems

Important dates

  • Poster abstract submission deadline: Aug 2, 2023
  • Poster notification: Aug 9, 2023
  • Conference dates: October 1-3, 2023

Submission guidelines

Poster abstract submission website: iiswc2023posters.hotcrp.com
Submission template: iiswc2023poster.zip

The content of the poster must be original work that has neither been published before in another conference or journal, nor is currently under review. However, you can submit work that has been presented earlier in a workshop without copyrighted proceedings. The poster abstract – including references – must be submitted in two single-spaced double-column pages using a 10-point size font on 8.5×11 inch using the submission template. References must list all the authors of the paper. Reviewing will be double blind. Therefore, please do not include any author names on any submitted documents except in the space provided on the submission form. If you refer to your own prior work, please do it in third person, as if you were referencing someone else’s work. Submissions that exceed the page limit or do not follow the formatting guidelines will be rejected without review. The extended abstract must be submitted in PDF format, and must be understandable with a black-and-white printout.


Episode 12 of Computer Architecture Podcast: 50th Anniversary of SIGARCH, Special Episode with Dr. David Patterson, Dr. Norm Jouppi and Dr. Natalie Enright-Jerger

Submitted by Suvinay Subramanian

Computer Architecture Podcast: a series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.

This is a special episode to commemorate the 50th anniversary of the SIGARCH in June 2023. We have three leaders from our community who have served as SIGARCH chairs — Dr. David Patterson, Dr. Norm Jouppi and Dr. Natalie Entright-Jerger — reflect on the evolution of the computer architecture field as well as our community over half a century, and share their perspectives on opportunities and exciting times ahead.

David Patterson is a professor emeritus at ​​UC Berkeley, a distinguished engineer at Google, and recipient of the Turing Award. Norm Jouppi, a VP and Engineering Fellow at Google, where he is the chief architect for Google’s Tensor Processing Units (TPUs), and a recipient of the Eckert-Mauchly award. Natalie Enright-Jerger is a professor at the University of Toronto, where she is the Canada Research Chair in Computer Architecture, and is a recipient of the Alfred P. Sloan Research Fellowship, and distinguished member of ACM and IEEE.

Listen to the episode at https://comparchpodcast.podbean.com/. Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Akanksha Jain
SIGARCH Content Editor

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