This is the 1st December 2019 digest of SIGARCH Messages.

In This Issue


Call for Participation: Chisel Community Conference 2020
https://events.linuxfoundation.org/chisel-community-conference/program/cfp/
Submitted by Adam Izraelevitz

Chisel Community Conference 2020
Milpitas, CA, USA
January 29-30, 2020

Update: Proposal/talk submission deadline extended until December 12th, 2019. Proposals will be accepted on a rolling basis to provide time for international travel considerations.

We’re happy to announce that we’ll be having a 3rd Chisel Community Conference (hosted by CHIPS Alliance) on January 29–30, 2020 at the Western Digital campus in Milpitas, CA.

There’s a website up with both a call for proposals and a registration link:

Main site: https://events.linuxfoundation.org/chiselcommunity-conference/
Call For Proposals: https://events.linuxfoundation.org/chiselcommunity-conference/program/cfp/
Registration: https://events.linuxfoundation.org/chiselcommunity-conference/register/

We’re accepting proposals for talks through November 26, so get those talks in on topics related to:

– Extensions to the Chisel frontend or FIRRTL compiler
– Chisel libraries
– Chisel-based projects (such as Rocketchip-based designs)
– Chisel-related infrastructure (testers, transforms, backends, simulators)
– Chisel in teaching, and other tools/contributions that promote reusability in hardware
– Anything else you think the community would be interested in!

Sincerely,

The Chisel Devs


Call for Participation: CLOSER 2020
http://closer.scitevents.org
Submitted by closer.secretariat@insticc.org

The 10th International Conference on Cloud Computing and Services Science, CLOSER 2020, focuses on the highly important area of Cloud Computing, inspired by some latest advances that concern the infrastructure, operations, and available services through the global network. Further, the conference considers as essential the link to Services Science, acknowledging the service-orientation in most current IT-driven collaborations. The conference is nevertheless not about the union of these two (already broad) fields, but about Cloud Computing where we are also interested in how Services Science can provide theory, methods and techniques to design, analyze, manage, market and study various aspects of Cloud Computing.

Emerging Enterprise Technologies are profoundly changing the way we think of IT – from economics and efficiency to process and usage models. Many organizations look to the “externalized” IT systems and services as a potential cost-savings advantage by moving internally hosted IT services to external providers. Other organizations view the “external” IT as potential disaster recovery systems or as on-demand capacity to boost business continuity and customer service levels. We need to take a closer look, discerning what emerging enterprise technologies are and how they can catalyze creativity and produce a competitive advantage. There is hence a new wave of interest in ‘Externalization of IT’ – anything as a service (including Software as a Service, Infrastructure as a Service, Platform as a Service), On Demand delivery, outsourcing, edge cloud and so on. This emerging facilitation and way of utilizing services through IT is what we are referring to as Cloud Computing.

Conference Topics:
Area 1: Services Science
– Business Process Management and Web Services
– Service Innovation
– Service Lifecycle Management
– Service-Oriented Architecture
– Service Society
– Service Management
– Service Platforms
– Business Services Realized by IT Services
– Enterprise Architectures and Services
– Industrial Applications of Services Science
– Information and Service Economy
– Internet of Services
– Model-Driven Web Service Engineering
– Semantic and Service Web
– Microservices: Atomation Deployment and Management, Resource Allocation Elasticity, Service State and Resilience

Area 2: Data as a Service
– On-Line Transaction Processing (OLTP) Services
– NOSQL Services: Store, Visualization, Processing
– Time Series Services: Databases, Dashboards

Area 3: Cloud Operations
– Cloud Management Platforms
– Cloud Reliability and Resilience
– Cloud Automation
– Hybrid Clouds and Their Integration

Area 4: Edge Cloud and Fog Computing
– Edge Cloud Orchestration
– Cluster Management
– Edge Cloud Network Management
– Edge Cloud Data Management
– IoT-Cloud Integration

Area 5: Service Modelling and Analytics
– Cloud Cost Analysis
– Service Discovery
– Service Modeling and Specification
– Service Monitoring and Control
– Services Security and Reliability
– Service Ecosystems
– Service Simulation
– Service Performance Analytics
– Analytics and Services

Area 6: Mobile Cloud Computing
– Mobile and Energy-Efficient Use of Clouds
– Mobile and Wearable Computing Systems and Services
– Mobile Cloud Architectures and Models
– Mobile Cloud Networking
– Mobile Commerce, Handheld Commerce and emarkets on Cloud

Area 7: Cloud Computing Fundamentals
– Cloud Application Portability
– Privacy, Security and Trust
– Federated Cloud
– Web Services
– Consistency and Consensus
– Cloud Computing Architecture
– Cloud Delivery Models
– Cloud Deployment Models: Public/Private/Hybrid Cloud
– Cloud Interoperability
– Cloud Risk, Challenges and Governance
– Cloud Standards
– QoS for Applications on Clouds
– Resource Management

Area 8: Cloud Computing Platforms and Applications
– Access Control
– Development Methods for Cloud Applications
– XaaS
– Cloud Services
– Mobile Cloud Computing Models, Infrastructures and Approaches
– Cloud Data Centers, Storage and Networking Technologies
– Mobile-Aware Cloud Data Management and Data Retrieval
– High Performance Computing Cloud Applications; Use Cases, Experiences with HPC Clouds
– Hybrid Cloud Integration
– Cloud Brokering
– Cloud Workflow Management Systems
– Cloud Solution Design Patterns
– Native Cloud Applications
– Cloud for Enterprise Business Transformation
– Cloud Application Architectures
– Cloud Application Scalability and Availability
– Cloud Applications Performance and Monitoring
– Cloud Economics
– Cloud Middleware Frameworks
– Engineering Mobile Clouds and Mobile-Based Systems
– Social and Green Cloud Computing

Area 9: Cloud Computing Enabling Technology
– API Management
– Security, Privacy and Compliance Management
– Virtualization Technologies
– Application Containers
– Microservices and Lambda Functions
– Multi-Cloud Solutions Enablement
– Cloud Quality and Performance
– Cloud Optimization and Automation
– Cloud Resource Virtualization and Composition
– Cloud Management and Operations
– High Performance Cloud Computing
– Cloud Migration
– Monitoring of Services, Quality of Service, Service Level Agreements
– Function-as-a-Service and Serverless Computing


Call for Participation: DATE 2020
https://www.date-conference.com/
Submitted by Fabien Clerm

Design, Automation and Test in Europe Conference (DATE 2020)
Highlighting Embedded AI and Silicon Photonics
Grenoble, France
9-13 March 2020

For the 23rd year in a row, DATE has prepared an exciting technical program. With the help of the 328 members of the Technical Programme Committee, who carried out 3014 reviews (mostly four reviews per submission), 196 papers (26%) were finally selected for regular presentation and 82 additional ones (cumulatively 37%, including all papers) for interactive presentation.

DATE 2020 program will include five keynote talks. Two visionary talks will be given during the opening ceremony: one from Philippe Magarshack, Corporate Vice President at ST Microelectronics, and one from Luca Benini, chair of digital Circuits and Systems at ETH Zurich and Professor at University of Bologna. Moreover, three luncheon keynotes will inspire the attendees: on Tuesday, Catherine Schumann from Oak Ridge National Laboratory will talk about neuromorphic computing; on Wednesday, Jim Tung will present Mathworks’ vision on how to leverage Embedded Intelligence in Industry; on Thursday, Joachim Schultze from DZNE will talk about bottlenecks and challenges for HPC in medicinal and genomics research.

The conference program includes several executive and hot-topic sessions, addressing Memories for Emerging Applications, Architectures for Emerging Technologies (Quantum Computing, Edge Computing, Neural Algorithms, In-Memory Computing, Bio-Inspired Adaptive Hardware), Hardware Security, 3D Integration and Logic Reasoning for Functional ECO.

On the first day of the DATE week, seven in-depth technical tutorials on the main topics of DATE as well as one industry hands-on tutorial will be given by leading experts in their respective fields. The topics cover Early Reliability Analysis in Microprocessor Systems, AI Chip Technologies and DFT Methodologies, Data Analytics for Scalable Computing Systems Design, Security in the Post-Quantum Era, Industrial Control Systems Security, HW/SW codesign of Heterogeneous Parallel dedicated Systems, Evolutionary computing for EDA, and the Deployment of deep learning networks on FPGA (Mathworks).

On Friday, 8 full-day workshops cover several hot topics from areas like Autonomous Systems Design, Optical/Photonic Interconnects, Computation-In-Memory, Design Automation for Understanding Hardware Designs, Open-Source Design Automation, Stochastic Computing for Neuromorphic Architectures, Hardware Security and Quantum Computing.

Two Special Days in the program will focus on areas bringing new challenges to the system design community: Embedded AI and Silicon Photonics. Each of the Special Days will have a full program of keynotes, panels, tutorials and technical presentations.

More in detail, the Special Day on Embedded Artificial Intelligence will cover new trends in cognitive algorithms, hardware architectures, software designs, emerging device technologies as well as the application space for deploying AI into edge devices. The topics will include technical areas to enable the realization of embedded artificial intelligence on specialized chips, such as bio-inspired chips, with and without self-learning capabilities, special low-power accelerator chips for aiding in vector/matrix-based computations, convolution and deep-net chips for possible machine learning, cognitive, and perception applications in health, automotive, robotics, or smart cities applications.

The Special Day on Silicon Photonics will focus on data communication via photonics for both data centre/high-performance computing and optical networks on chip applications. Industrial and academic experts will highlight recent advances on devices and integrated circuits. The sessions will also feature talks on design automation and link-level simulations. Other applications of silicon photonics such as sensing and optical compute will also be discussed.

A timely Special Initiative “Autonomous Systems Design – Automated Vehicles and beyond” on Thursday and Friday will include reviewed and invited papers as well as working sessions.

To inform attendees on commercial and design-related topics, there will be a full program in the Exhibition Theatre which will combine presentations by exhibiting companies, best-practice reports by industry leaders on their latest design projects and selected conference special sessions. 

The conference is complemented by an exhibition, running for three days (Tuesday – Thursday), including exhibition booths from companies, and collaborative research initiatives including EU project presentations. The exhibition provides a unique networking opportunity and is the perfect venue for industries to meet University Professors to foster University Programmes and especially for PhD Students to meet future employers.

The conference online registration is now open, and the complete advance programme will be available on the DATE website starting from December 2019.

Updated information is always available online: www.date-conference.com

DATE 2020 Press Contacts

General Chair
Giorgio Di Natale, CNRS/TIMA, FR
giorgio.di-natale@univ-grenoble-alpes.fr

Programme Chair
Cristiana Bolchini, Politecnico di Milano, IT
cristiana.bolchini@polimi.it


Call for Participation: Chisel Community Conference 2020
https://events.linuxfoundation.org/chisel-community-conference/program/cfp/
Submitted by Adam Izraelevitz

Chisel Community Conference 2020
Milpitas, CA, USA
January 29-30, 2020

We’re happy to announce that we’ll be having a 3rd Chisel Community Conference (hosted by CHIPS Alliance) on January 29–30, 2020 at the Western Digital campus in Milpitas, CA.

There’s a website up with both a call for proposals and a registration link:

Main site: https://events.linuxfoundation.org/chiselcommunity-conference/
Call For Proposals: https://events.linuxfoundation.org/chiselcommunity-conference/program/cfp/
Registration: https://events.linuxfoundation.org/chiselcommunity-conference/register/

We’re accepting proposals for talks through November 26, so get those talks in on topics related to:

– Extensions to the Chisel frontend or FIRRTL compiler
– Chisel libraries
– Chisel-based projects (such as Rocketchip-based designs)
– Chisel-related infrastructure (testers, transforms, backends, simulators)
– Chisel in teaching, and other tools/contributions that promote reusability in hardware
– Anything else you think the community would be interested in!

Sincerely,

The Chisel Devs


Call for Participation: WACCPD 2019: Sixth Workshop on Accelerator Programming using Directives
https://www.waccpd.org
Submitted by Dr. B. Neelima

========================================================================
Sixth Workshop on Accelerator Programming using Directives (WACCPD 2019)
(in conjunction with SC19)
November 18, 2019 – https://www.waccpd.org
========================================================================

Call for Participation
———————–

The ever-increasing heterogeneity in supercomputing applications has given rise to complex compute node architectures offering multiple, heterogeneous levels of massive parallelism. Exploiting the maximum available parallelism out of such systems necessitates sophisticated programming approaches that can provide scalable as well as portable solutions without compromising on performance. Software abstraction-based programming models, such as OpenMP and OpenACC, have been raising the abstraction of code to reduce the burden on the programmer while improving productivity.

Recent architectural trends indicate a heavy reliance of future exascale machines on accelerators for performance. Toward this end, the workshop will highlight the improvements over state-of-art through the accepted papers and prompt discussion through keynotes and panel. The workshop aims to showcase all aspects of heterogeneous systems discussing innovative high-level language features, lessons learned while using directives to migrate scientific legacy code to parallel processors, compilation and runtime scheduling techniques among others.

We cordially invite you to attend and look forward to seeing you there!

Location: Room 702, Colorado Convention Center, Denver, CO
Time: 9:00 a.m.- 5:30 p.m.

Program
——–

09:00-09:10     Opening Remarks –  Sandra Wienke & Sridutt Bhalachandra

09:10-10:00     Keynote: Nicholas James Wright (Lawrence Berkeley National Laboratory, USA) –  Perlmutter –  A 2020 Pre-Exascale GPU-accelerated System for NERSC: Architecture and Application Performance Optimization

10:00-10:30     WACCPD Morning Break

Topic: Porting Scientific Applications to Heterogeneous Architectures Using Directives

10:30-11:00     Takuma Yamaguchi (University of Tokyo, Japan) – GPU Implementation of a Sophisticated Implicit Low-Order Finite Element Solver with FP21-32-64 Computation Using OpenACC

11:00-11:30     Noriyuki Kushida (Comprehensive Nuclear-Test-Ban Treaty Organization) – Acceleration in Acoustic Wave Propagation Modelling using OpenACC/OpenMP and its hybrid for the Global Monitoring System

11:30-12:00     Zhengji Zhao (NERSC, Lawrence Berkeley National Laboratory, USA) – Accelerating the Performance of Modal Aerosol Module of E3SM Using OpenACC

12:00-12:30     Fazlay Rabbi (Michigan State University, USA) – Evaluation of Directive-based GPU Programming Models on a Block Eigensolver with Consideration of Large Sparse Matrices

12:30-14:00     WACCPD Lunch Break

14:00-14:30     Invited Talk: Robert Henschel (Indiana University, USA) – The SPEC ACCEL Benchmark Results and Lessons Learned

Topic: Directive-Based Programming for Math Libraries

14:30-15:00     JaeHyuk Kwack (Argonne National Laboratory, USA) – Performance of the RI-MP2 Fortran Kernel of GAMESS on GPUs via Directive-Based Offloading with Math Libraries

15:00-15:30     WACCPD Afternoon Break

Topic: Performance Portability for Heterogeneous Architectures

15:30-16:00     Yuuichi Asahi (National Institute for Quantum and Radiological Science and Technology, Japan) – Performance portable implementation of a kinetic plasma simulation mini-app

16:00-16:30     Damodar Sahasrabudhe (University of Utah, USA) – A Portable SIMD Primitive using Kokkos for Heterogeneous Architectures

16:30-16:35     WACCPD Best Paper Award

16:35-17:25     Panel: Fernanda Foertter (NVIDIA, USA) – Convergence, Divergence, or New Approaches? The Future of Software-Based Abstractions for Heterogeneous Supercomputing
Panelists: Jeff R. Hammond, Jack Deslippe, Christian Robert Trott, Michael Wolfe, Johannes Doerfert

17:25-17:30     WACCPD Closing Remarks

Further information can be found on the WACCPD web page: https://www.waccpd.org

Contact
——–
Sandra Wienke (RWTH Aachen University, Germany) and Sridutt
Bhalachandra (Lawrence Berkeley National Laboratory, USA), WACCPD
Program Chairs
Email: organizers@waccpd.org

Steering Committee
——————-
* Barbara Chapman (Stony Brook, USA)
* Duncan Poole (OpenACC, USA)
* Jeffrey Vetter (ORNL, USA)
* Kuan-Ching Li (Providence University, Taiwan)
* Oscar Hernandez (ORNL, USA)

Publicity Chair: Neelima Bayyapu (NMAM Institute of Technology,
Karnataka, India)
Web Chair: Shu-Mei Tseng (University of California, Irvine, USA)


Call for Papers: HPDC 2020
http://hpdc.org/2020/
Submitted by David Irwin

The 29th International Symposium on High-Performance Parallel and Distributed Computing
Stockholm, Sweden
June 22-26, 2020

Submissions Due: January 23, 2020

OVERVIEW
The ACM International Symposium on High-Performance Parallel and Distributed Computing (HPDC) is the premier annual conference for presenting the latest research on the design, implementation, evaluation, and the use of parallel and distributed systems for high-end computing.

SCOPE AND TOPICS
Submissions are welcomed on high-performance parallel and distributed computing (HPDC) topics including but not limited to: clouds, clusters, grids, big data, massively multicore, and extreme-scale computing systems. Experience reports of operational deployments that provide significantly novel insights for future research on HPDC applications and systems will
also receive special consideration.

In the context of high-performance parallel and distributed computing, the topics of interest include, but are not limited to:

* Operating systems, networks, and architectures
* High performance runtime environments
* Massively multicore systems, including heterogeneous systems
* Datacenter technology, resource virtualization
* Programming languages, APIs, and system inter-operation approaches
* File and storage systems, I/O, and data management
* Big data stacks and big data ecosystems
* Resource management and scheduling, including energy-aware techniques
* Performance modeling, analysis, and engineering
* Fault tolerance, reliability, and availability
* Operational guarantees, risk assessment and management
* Emerging application areas that include cloud/edge computing and IoT

SUBMISSION GUIDELINES
Authors are invited to submit technical papers of at most 12 pages in PDF format, including figures and references. Papers should be formatted in the ACM Proceedings Style and submitted via the conference web site. Submitted papers must be original work that has not appeared in and is not under consideration for another conference or a journal. Submissions should be double-blind. Refer to the HPDC website below for more information.

http://hpdc.org/2020/papers/call-for-papers/

GENERAL CHAIRs
Manish Parashar, Rutgers University
Vladimir Vlassov, KTH Stockholm

PROGRAM CO-CHAIRS
Kathryn Mohror, Lawrence Livermore National Lab
David Irwin, UMass Amherst

DEADLINES
* Abstracts due: January 16, 2020
* Papers due: January 23, 2020
* Author notifications: March 27, 2020
* Conference dates: June 22 – 26, 2020

MORE INFO http://www.hpdc.org/2020


Call for Papers: LCTES 2020
https://conf.researchr.org/home/LCTES-2020
Submitted by Dongyoon Lee


The 21st ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2020) 
London, United Kingdom (co-located with PLDI 2020)
https://conf.researchr.org/home/LCTES-2020
June 16, 2020


Submissions Due: Feb 28, 2020

Embedded system design faces many challenges both with respect to functional requirements and nonfunctional requirements, many of which are conflicting. They are found in areas such as design and developer productivity, verification, validation, maintainability, and meeting performance goals and resource constraints. Novel design-time and run-time approaches are needed to meet the demands of emerging applications and to exploit new hardware paradigms, and in particular to scale up to multicores (including GPUs and FPGAs) and distributed systems built from multicores.

LCTES 2020 solicits papers presenting original work on programming languages, compilers, tools, theory, and architectures that help in overcoming these challenges. Research papers on innovative techniques are welcome, as well as experience papers on insights obtained by experimenting with real-world systems and applications.

LCTES 2020 accepts two types of submissions:

1. Full paper: 10 pages papers presenting original work.
2. Work-in-progress paper: 4 pages papers triggering interesting discussions.

Accepted papers in both categories will appear in the proceedings published by ACM.

This year LCTES is introducing a journal mode in addition to the usual conference mode. ***All accepted full papers will be invited to be published in a special issue of ACM Transactions on Embedded Computing Systems (TECS)***

Important dates:
-  Paper submission: Feb 28
-  Author notification: Mar 30
-  Camera-ready submission: April 26

Original contributions are solicited on the topics of interest including, but not
limited to:

1. Compiler challenges, including:
- Interaction between embedded architectures, operating systems, and compilers
- Interpreters, binary translation, just-in-time compilation, and split compilation
- Support for enhanced programmer productivity
- Support for enhanced debugging, profiling, and exception/interrupt handling
- Optimization for low power/energy/code size, and best-effort/real-time performance
- Parameterized and structural compiler design space exploration and auto-tuning

2. Tools for analysis, specification, design, and implementation, including:
- Hardware, system software, application software, and their interfaces
- Distributed real-time control, media players, and reconfigurable architectures
- System integration and testing
- Performance estimation, monitoring, and tuning
- Run-time system support for embedded systems
- Design space exploration tools
- Support for system security and system-level reliability
- Approaches for cross-layer system optimization

3. Theory and foundations of embedded systems, including:
- Predictability of resource behavior: energy, space, time
- Validation and verification, in particular of concurrent and distributed systems
- Formal foundations of model-based design for code generation/analysis/verification
- Mathematical foundations for embedded systems
- Models of computations for embedded applications

4. Novel embedded architectures, including:
- Design and implementation of novel architectures
- Workload analysis and performance evaluation
- Architecture for new language features/virtualization/compilation/debugging tools
- Architectural features to improve power/energy, code/data size, and predictability

5. Mobile systems and IoT, including:
- Operating systems for mobile and IoT devices
- Compiler and software tools for mobile and IoT systems
- Energy management for mobile and IoT devices
- Memory and IO techniques for mobile and IoT devices

6. Empirical studies and their reproduction, and confirmation

Organizers:
- General Chair: Jingling Xue, University of New South Wales, Sydney
- Program Chair: Changhee Jung, Purdue University
- Publicity Chair: Dongyoon Lee, Stony Brook University

More information can be found at https://conf.researchr.org/home/LCTES-2020

Call for Papers: SDS 2020 PhD Forum and Posters
http://emergingtechnet.org/SDS2020/PhD-Posters.php
Submitted by Marco Guazzone

###############################################################################
7th International Conference on Software Defined Systems (SDS 2020)
Paris, France.
April 20-23, 2020

Submissions Due: December 1, 2019
################################################################################

*** PHD FORUM AND POSTERS Track ***

URL: http://emergingtechnet.org/SDS2020/PhD-Posters.php

IMPORTANT DATES

* Submission Date: 1 December 2019
* Notification to Authors: 21 February 2020
* Camera Ready Submission: 10 March 2020

CALL FOR PHD FORUM

The PhD Forum provides a unique opportunity for PhD students to present their research work and to receive constructive feedback from their peers as well as experts in the field (including academics and practitioners) at the conference. The forum will also be an excellent occasion for stimulating fruitful interactions and developing person-to-person networks to the benefit of the PhD students in their future careers. The goal of this forum is to create opportunities for students to meet with peers outside of their home institution, to get technical feedback as well as career advice from established researchers in their field, to find out about internship and job opportunities, and to articulate their own work in a public, friendly forum. The presenters at the forum are expected to be PhD students in any phase of their doctoral studies. Topics of interest are the same as those listed in the main conference call for papers. We will try to offer remote video presentation options for authors who are unable to attend due to visa issues. A Best Student Paper Award will be assigned by an independent review committee according to the quality of research work and the quality of presentation.

CALL FOR POSTERS

The poster session provides an excellent opportunity to present early-stage or ongoing research, and to receive interesting and valuable feedback from conference attendees. We also strongly encourage student and industry submissions. Topics of interest are the same as those listed in the main conference call for papers. A Best Poster Award will be assigned by an independent review committee according to the quality of research work and the quality of poster presentation.

TOPICS OF INTERESTS

* Software Defined Systems support for Cloud Computing .
* Software Defined Networking (SDN).
* SDN concepts, architecture, and APIs.
* Network Virtualization
* SDN and OpenFlow protocol
* Software Defined Radio
* Cognitive Radio Networks .
* Access Control models in SDN.
* Software Defined Storage.
* Storage Automation and Abstraction.
* Policy-driven storage provisioning.
* Software Defined Servers and Virtualization.
* Software Defined Datacenters.
* Software Defined Security o Security policies automation.
* Autonomic Security in SDS.
* Autonomic Computing techniques.
* Real-time load prediction model to optimize the user satisfaction.
* Software Defined Systems Scalability.
* Software Defined Systems optimization.
* Software tools and frameworks to support SDS .
* Software Defined Systems challenges and opportunities
* Software Defined Systems surveys .
* Social engineering, insider threats system for SDS.
* Incident Handling and Penetration Testing with SDS.
* Software Defined Systems support if IoT.
* Security protocols and mechanisms in SDS.
* Security and privacy of mobile SDS based cloud computing
* Service-oriented architectures, service portability andP2P
* Network virtualization and cloud-based radio access networks

PUBLICATION

All accepted papers will appear in the conference proceedings and will be published by IEEE and included in the IEEE Xplore digital library.

PROGRAM CHAIRS

* Attila Kertesz
* Marco Guazzone

 


Call for Papers: FMEC 2020 PhD Forum and Posters
http://emergingtechnet.org/FMEC2020/PhD-Posters.php
Submitted by Marco Guazzone

################################################################################
5th International Conference on Fog and Mobile Edge Computing (FMEC 2020)
Paris, France.
April 20-23, 2020

Submission Due: December 1, 2019
################################################################################

*** PHD FORUM AND POSTERS Track ***

URL: http://emergingtechnet.org/FMEC2020/PhD-Posters.php

IMPORTANT DATES

* Submission Date: 1 December 2019
* Notification to Authors: 21 February 2020
* Camera Ready Submission: 10 March 2020

CALL FOR PHD FORUM

The PhD Forum provides a unique opportunity for PhD students to present their research work and to receive constructive feedback from their peers as well as experts in the field (including academics and practitioners) at the conference. The forum will also be an excellent occasion for stimulating fruitful interactions and developing person-to-person networks to the benefit of the PhD students in their future careers. The goal of this forum is to create opportunities for students to meet with peers outside of their home institution, to get technical feedback as well as career advice from established researchers in their field, to find out about internship and job opportunities, and to articulate their own work in a public, friendly forum. The presenters at the forum are expected to be PhD students in any phase of their doctoral studies. Topics of interest are the same as those listed in the main conference call for papers. We will try to offer remote video presentation options for authors who are unable to attend due to visa issues. A Best Student Paper Award will be assigned by an independent review committee according to the quality of research work and the quality of presentation.

CALL FOR POSTERS

The poster session provides an excellent opportunity to present early-stage or ongoing research, and to receive interesting and valuable feedback from conference attendees. We also strongly encourage student and industry submissions. Topics of interest are the same as those listed in the main conference call for papers. A Best Poster Award will be assigned by an independent review committee according to the quality of research work and the quality of poster presentation.

TOPICS OF INTERESTS

* Mobile Cloud Computing Systems.
* FMEC Security and Privacy Issues.
* FMEC Pricing and billing models.
* FMEC support for VANETS and MANETS
* Cloudlet based computing
* Lightweight authentication mechanisms in FMEC architecture.
* Access Control models in FMEC.
* Identification of incentives for FMEC service providers.
* The future perspective for FMEC: Challenges and Open Issues.
* FMEC Quality of Service (QoS) improvements techniques.
* FMEC architecture features and evolution.
* FMEC Real-time communication interfaces and protocols.
* FMEC virtualization.
* Data storage, processing, and management at FMEC platform.
* Cyber hacking, next generation fire wall of FMEC.
* Deployment strategies of FMEC Servers
* Admission control for FMEC.
* Social engineering, insider threats, advance spear phishing.
* Incident Handling and Penetration Testing.
* Forensics of Virtual and FMEC Environments.
* Security protocols in FMEC.
* Security and privacy of mobile cloud computing
* Security, privacy and reliability issues of MCC and IoT
* Security and privacy of IoT
* Security and privacy management in MCC
* MCC intrusion detection systems
* Security of pricing and billing for mobile cloud computing services
* Security of mobile, peer-to-peer and pervasive services in clouds
* Security of mobile commerce and mobile Internet of Things
* Security of mobile social networks
* Security and privacy in smartphone devices
* Security and privacy in social applications and networks
* Security of Mobile, peer-to-peer and pervasive services in clouds
* Security of Mobile commerce and mobile internet of things
* Security of Operating system and middleware support for mobile computing
* Security and privacy in sensor networks
* Security and privacy in social applications and networks
* Web service security
* Security of 3G/4G systems, Wi-MAX, Ad-hoc
* Security of Mobile social networks
* Near field communication services
* Service-oriented architectures, service portability, P2P
* Network virtualization and cloud-based radio access networks

PUBLICATION

All accepted papers will appear in the conference proceedings and will be published by IEEE and included in the IEEE Xplore digital library.

PROGRAM CHAIRS

* Attila Kertesz
* Marco Guazzone


Call for Papers: FPGA 2020
http://www.isfpga.org
Submitted by Jing (Jane) Li

Twenty-Eighth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)
February 23-25, 2020
Seaside, California, USA

Submissions due: September 9, 2019

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020) is the premier conference for presentation of advances in FPGA technology. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library.

Types of Submissions Sought:

1. Research Papers (with and without Artifacts)

As usual, we solicit research papers related to the following areas:
– FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
– FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory memory or nano-scale devices. Methods for analyzing and improving static and dynamic power, power and clock distribution, yield, manufacturability, security, reliability, and testability.
– CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
– High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
– FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
– Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.

Research submissions may be either:
– Full: at most 10 pages (excluding references), for a full presentation at the conference; or
– Short: at most 6 pages (excluding references), for a brief presentation.

A paper submitted as either full or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).

2. Tutorial Papers on Emerging Applications / Methodologies

The conference will include a Sunday workshop oriented toward users of FPGAs: be it deep learning implementations, computer security or other emerging topics of interest. For this category, we solicit tutorial papers describing effective design techniques and design flows. The ideal submission will enable beginning researchers to enter the area, current researchers to broaden their scope, and practitioners to gain new insights and applicable skills. Tutorial submissions need not present novel research results, but should integrate expert practical and/or research knowledge related to FPGAs for a broader audience. This may include:
– Technical descriptions of new commercial or academic design tools of general interest;
– Insightful summaries of the state-of-the-art that suggest open research problems; and
– In-depth design tutorials and design experiences.

Tutorial submissions are at least 4 and at most 10 pages. Accepted submissions are published in the proceedings and allocated a presentation time of up to one hour, appropriate to the content.

3. Panel Discussion Proposals

We also solicit proposals for the panel discussion at the conference banquet. The submission should outline the topic, questions to be addressed, and suggested speakers.

SUBMISSION GUIDELINES:
Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/. Submissions will be considered for acceptance as full or short regular papers, workshop papers, or posters. Regular submissions related to the workshop topic may be scheduled for presentation during the workshop. Regular or workshop submissions will also be considered for acceptance as a poster. A paper submitted to the short or full paper category will only be considered in that category. Once a paper has been submitted, its authorship list is considered to be fixed and finalized. As the inclusion and evaluation of artifacts is new for FPGA 2020, additional information will be provided at http://www.isfpga.org/artifactEvaluation.html by August 2019.

IMPORTANT DATES:
Abstract Submissions due: September 9, 2019
Full Paper Submissions due: September 9, 2019
Final Artifacts for Evaluation due: September 9, 2019
Author Paper Rebuttals due: October 18, 2019
Notification of acceptance: Mid-November, 2019
Camera-ready copy of accepted papers due: Early December, 2019

ORGANIZERS:
General Chair: Stephen Neuendorffer, Xilinx
Program Chair: Lesley Shannon, Simon Fraser University
Finance Chair: Kia Bazargan, University of Minnesota, financechair@isfpga.org.
Artifact Evaluation Co-Chairs: Miriam Leeser, Northeastern University, and Suhaib Fahmy, University of Warwick
Publicity Chair: Jing Li, University of Wisconsin-Madison


Call for Papers: CF 2020: ACM International Conference on Computing Frontiers
http://computingfrontiers.org/
Submitted by Salvatore Monteleone

==================================================================
ACM International Conference on Computing Frontiers 2020 (CF’20)
May 11 – 13, 2020
Catania, Sicily, Italy

Submissions Due: January 28, 2020

www.computingfrontiers.org
==================================================================

The next ACM International Conference on Computing Frontiers will be held May 11th – 13th in Sicily, Italy in the town of Catania. Computing Frontiers is an eclectic, interdisciplinary, collaborative community of researchers who investigate emerging technologies in the broad field of computing: our common goal is to drive the scientific breakthroughs that transform society.

CF’s broad scope is driven by recent technological advances in wide-ranging fields impacting computing, such as memory hardware and systems, network and systems architecture, cloud computing, novel device physics and materials, power efficiency, new application domains of machine and deep learning and big data analytics, and systems portability and wearability. The boundaries between the state-of-the-art and revolutionary innovation constitute the advancing frontiers of science, engineering, and information technology — and are the CF community focus. CF provides a venue to share, discuss and advance broad, forward-thinking, early research on the future of computing and welcomes work on a wide spectrum of computer systems, from embedded and hand-held/wearable to supercomputers and datacenters.

IMPORTANT DATES
===============

Submissions deadline: January 28th, 2020
Notification: March 15th, 2020
Camera-Ready Papers Due: April 5th, 2020
Conference Dates: May 11-13th, 2020

TOPICS OF INTEREST
==================

We seek original research contributions at the frontiers of a wide range of topics, including novel computational models and algorithms, new application paradigms, computer architecture (from embedded to HPC systems), computing hardware, memory technologies, networks, storage solutions, compilers, and environments.

* Innovative Computing Approaches, Architectures, Accelerators, Algorithms and Models
– Approximate, analog, inexact, probabilistic computing
– Quantum computing
– Neuromorphic, biologically-inspired computing and optical computing
– Dataflow architectures, near-data and in-memory processing

* Technological Scaling Limits and Beyond
– Limits: Defect- and variability-tolerant designs, graphene and other novel materials, nanoscale design, dark silicon
– Extending past Moore’s law: 3D-stacking, many-core architectures and accelerators, distributed computing on mobile devices and their challenges

* Machine Learning, Deep Learning and Big Data Analytics
– Novel architecture and systems across computing systems (IoT to datacenter)
– High performance data analytics
– Exascale data management

* Embedded, IoT and Cyber-Physical Systems
– Ultra-low power designs, energy scavenging
– Physical security, attack detection and prevention
– Reactive, real-time, scalable, reconfigurable and self-aware systems
– Sensor networks, IoT, and architectural innovation for wearable computing

* Large-Scale System Design and Networking
– Large-scale homogeneous/heterogeneous architectures and networking
– System-balance and CPU-offloading
– Power- and energy-management for clouds, datacenters and exascale systems

* System Software, Compiler Technologies and Programming Languages
– Technologies that push the limits of operating systems, virtualization, and container technologies
– Large scale frameworks for distributed computing and communication
– Resource and job management, scheduling, workflow systems for managing large-scale heterogeneous systems
– Compiler technologies: hardware/software integrated solutions, high-level synthesis
– Tools for analyzing and managing performance at large scale
– Novel programming approaches

* Fault Tolerance and Resilience
– Solutions for ultra-large and safety-critical systems (e.g. infrastructure, airlines)
– Hardware and software approaches in adverse environments such as space

* Security
– Methods, system support, and hardware for protecting against malicious code
– Real-time implementations of security algorithms and protocols
– Quantum and post-quantum cryptography

* Computers and Society
– Artificial Intelligence (AI) Ethics and AI environmental impact
– Education, health, cost/energy-efficient design, smart cities, and emerging markets, interdisciplinary applications

We strongly encourage submissions in emerging fields that may not fit into traditional categories — if in doubt, contact the PC co-chairs by email.

CONFERENCE WEBSITE
==================

http://www.computingfrontiers.org/

SUBMISSION
==========

We encourage the submission of both full and short papers containing high-quality research describing original and unpublished work.

Papers must be submitted through

https://easychair.org/conferences/?conf=cf2020

Short papers describe preliminary or highly speculative work as well as position papers. Full papers are a maximum of eight (8) (excluding references) and short papers a maximum of four (4) double-column pages (including references) in ACM conference format. Authors may buy up to two (2) extra pages for accepted full papers. Page limits include figures, tables and appendices. The review process is double-blind and removal of all identifying information from paper submissions (i.e. cite own work in third person) is required. Papers not conforming to the above submission policies on formatting, page limits and the removal of identifying information will be automatically rejected.

No-show policy: Any accepted papers are expected to be presented at the conference and at least one full registration is required from a submission author for each accepted paper. A no-show of papers will result in exclusion from the ACM digital library proceedings. If circumstances arise such that authors are unable to present their papers at the conference, they must contact the PC co-chairs.

ORGANIZATION
============

Computing Frontiers 2020 Chairs

General Co-Chairs:
Maurizio Palesi, University of Catania, IT
Gianluca Palermo, Politechnico di Milano, IT

Program Co-Chairs:
Cat Graves, Hewlett Packard Labs, US
Eishi Arima, ITC University of Tokyo, JP

FURTHER INFORMATION
===================

For further information and updates, check the CF20 website at

www.computingfrontiers.org


Call for Papers: GPGPU 2020 @ PPoPP 2020
https://insight-archlab.github.io/gpgpu.html
Submitted by Adwait Jog

13th Workshop on General Purpose Processing Using GPU (GPGPU 2020) @ PPoPP 2020
San Diego, CA, USA
February 23, 2020

https://insight-archlab.github.io/gpgpu.html

Submissions Due: December 06, 2019

Organizers
========================================
Adwait Jog (co-chair), William & Mary (Email: ajog@wm.edu)
Onur Kayiran (co-chair), AMD Research (Email: onur.kayiran@amd.com )
Ashutosh Pattnaik (co-chair), Penn State/ARM (Email: ashutosh@psu.edu)
Mohamed Assem Ibrahim (submission/web chair), William & Mary (Email: maibrahim@email.wm.edu)

Overview
========================================
The goal of this workshop is to provide a forum to discuss new and emerging general-purpose graphics processing architectures, programming environments, and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. Papers are being sought on many aspects of GPUs or accelerators, including (but not limited to):

GPU Applications
GPU Programming Environments
GPU Runtime Systems
GPU Compilation
GPU Architectures
Multi-GPU Systems
GPU Power/Efficiency
GPU Reliability
GPU Benchmarking/Measurements
Heterogeneous Architectures/Platforms
Non-von Neumann Architectures
Domain-specific Architectures
GPU Security
Machine/Deep Learning
Graphics

Important Dates
========================================
Papers due: December 06, 2019
Notification: January 06, 2020
Final paper due: February 03, 2020
Workshop Date: February 23, 2020

Submission
========================================
Full paper submissions must be in PDF format for US letter-size paper. They must not exceed 10 pages (all-inclusive) in standard ACM two-column conference format (review mode, with page numbers and both 9 or 10pt can be used). The review process will be double-blind. Templates for ACM format are available for Microsoft Word, and LaTeX at: http://www.sigplan.org/authorInformation.htm

Submission site is hosted here: https://gpgpu2020.hotcrp.com/

Proceedings
========================================
All accepted papers will be published in the ACM Online Conference Proceedings Series.

Questions?
========================================
Please contact the organizers if you have any questions.

History and Impact
========================================
David Kaeli (Northeastern) and John Cavazos (Delaware) started this GPGPU workshop series, which was first held in 2007 at Northeastern University. In 2008, the workshop was held with ASPLOS 2008. This trend continued and this GPGPU workshop was held with ASPLOS for the next 6 years. From 2015 to 2018, the GPGPU workshop was co-located with PPoPP. GPGPU 2019 workshop was held with ASPLOS 2019. GPGPU 2020 workshop returns to PPoPP. The average citation count (as per Google Scholar), for a GPGPU workshop paper is currently 37.5, where there have been 8 influential papers with 100+ citations.


Call for Papers: CogArch 2020: The Fourth Workshop on Cognitive Architectures
http://cogarch-workshop.org/
Submitted by Karthik Swaminathan

CogArch 2020
Fourth Workshop on Cognitive Architectures
Towards Cloud-Backed Edge Cognition
February 23, 2020
San Diego, CA, USA (Colocated with HPCA 2020)

Submissions Due: December 6, 2019

Introduction

The emerging new interest in artificial intelligence (AI) has led to a paradigm shift in the field of computer architecture. Architectures that focus on machine learning and neuromorphic computing are increasingly being adopted into the mainstream. The design of future processors is increasingly being predicated on metrics based on cognitive applications. The interplay between the development of state-of-the-art algorithms in cognitive sciences, computer vision, speech recognition and the design of the underlying system architectures has resulted in several cross-disciplinary advances. After highly successful editions of the Workshop on Cognitive Architectures in the past, in this year’s edition we expect to consolidate the many recent works in this field and provide concrete roadmaps as to what subsequent directions the research in this field should take. This workshop at HPCA 2020 proposes to bring together researchers and practitioners within systems architecture, computer vision, artificial intelligence and robotics to discuss the latest ideas, applications and commercialization strategies around the cognitive computing theme. In addition, it also aims to foster an interest in such emerging fields among industry and academic researchers alike. The primary focus is expected to be on driving towards a better understanding of key cognitive algorithms of interest and the allied architectural support issues.

Of particular interest are application areas of mobile cognition, which may comprise of a distributed swarm of intelligent computing modules. This paradigm is relevant in the context of unmanned aerial vehicles and connected cars. Further, the rising investment by industry in designing IoT (Internet-of-Things) platforms, has resulted in several opportunities to build architectures that support capabilities such as intelligent data exchange and interaction with cloud, pattern matching, data analytics and other cognitive aspects to build truly transformative systems.

Call for Papers

Recent advances in architectures for AI have been instrumental in the development and deployment of autonomous systems, such as self-driving vehicles, and unmanned aerial vehicles. The Tesla FSD and Nvidia Xavier SoC are examples of commercial chips in the autonomous driving space with dedicated hardware units for processing AI algorithms. Next-generation processors in this domain are being envisioned as multi-agent systems that support swarm-based decision-making, as well as intelligent data exchange capabilities amongst each other or with a backing cloud server. The proliferation of mobile computing platforms, Internet-of-Things and cloud support features thereof have opened up exciting new opportunities for such real-time, mobile (distributed or swarm-driven) cognition. The CogArch workshop, solicits formative ideas and new product offerings in this general space.

Topics of interest include (but are not limited to):

  • Algorithms in support of cognitive reasoning: recognition, intelligent search, diagnosis, inference and informed decision-making.
  • Swarm intelligence and distributed architectural support; brain-inspired and neural computing architectures.
  • Prototype demonstrations of state-of-the-art AI computing systems.
  • Accelerators and micro-architectural support for artificial intelligence.
  • Approaches to reduce training time and enable faster model delivery.
  • Cloud-backed autonomics and mobile cognition: architectural and OS support thereof.
  • Resilient design of distributed (swarm) mobile AI architectures.
  • Reliability and safety considerations, and security against adversarial attacks in mobile AI architectures.
  • Energy efficiency, battery life extension and endurance in mobile AI architectures.
  • Case studies and real-life demonstrations/prototypes in specific application domains: e.g. smart homes, connected cars and UAV-driven commercial services, as well as applications of interest to defense and homeland security.

The workshop shall consist of regular presentations and/or prototype demonstrations by authors of selected submissions. In addition, it will include invited keynotes by eminent researchers from industry and academia as well as interactive panel discussions to kindle further interest in these research topics. Submissions will be reviewed by a workshop Program Committee, in addition to the organizers.

Submitted manuscripts must be in English of up to 2 pages (with same formatting guidelines as main conference) indicating the type of submission: regular presentation or prototype demonstration. Submissions should be sent to submissions@cogarch-workshop.org by December 6th, 2019. Further details can be found at http://cogarch-workshop.org. If you have questions regarding submission, please contact us: info@cogarch-workshop.org

Organizers

  • Vijay Janapa Reddi, Harvard University
  • Augusto Vega, IBM Research
  • Karthik Swaminathan, IBM Research
  • Nandhini Chandramoorthy, IBM Research
  • Alper Buyuktosunoglu, IBM Research
  • Pradip Bose, IBM Research

Important Dates

  • Submission deadline: December 6th, 2019
  • Notification: January 10th, 2020
  • Camera ready deadline: February 7th, 2020

Call for Papers: SELSE 2020: Workshop on Silicon Errors in Logic – System Effects
http://www.selse.org
Submitted by Michael Sullivan

The 16th IEEE Workshop on Silicon Errors in Logic – System Effects
SELSE 2020 (http://www.selse.org)
February 19 – February 20, 2020
Stanford University, CA, USA

Submissions Due: December 9, 2019

Important dates:

Paper Registration (mandatory): December 2, 2019
Paper Submission (for registered papers): December 9, 2019
Author Notification: January 10, 2020
Early Registration: January 17, 2020
Camera-Ready Submission: January 31, 2020

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high performance applications.

The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.

We are happy to announce that selected SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2020. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Valencia, Spain on June 29 – July 2, 2020.

Areas

Key areas of interest include (but are not limited to):

  • Error rates and trends in current and emerging technologies, including experimental failure data and the reliability characterization of deployed systems.
  • New error mitigation techniques, robust software frameworks, and error handling protocols for resilient system design.
  • Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.
  • Resilience characterization and strategies for machine learning applications, including autonomous vehicles.
  • Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.
  • The design of resilient systems for space exploration.
  • The interplay between system security issues and reliability.

Submission Guidelines

Additional information and guidelines for submission are available at http://www.selse.org.  Submissions and final papers should be PDF files following the IEEE two-column transactions format with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries—however, they are distributed to attendees of the workshop.

Organizing Committee

General Co-Chairs John Daly, LPS
Paolo Rech, UFRGS
Laura Monroe, LANL (Emerita)
Program Co-Chairs Stefano Di Carlo, Torino
Qiang Guan, Kent State
Michael Sullivan, NVIDIA (Emeritus)
Finance Co-Chairs Sarah Michalak, LANL

Sandhya Chandrashekhar, Cypress

Registration Chair Karthik Swaminathan, IBM
Local Arrangements Chair Saurabh Hukerikar, NVIDIA
Publicity Co-Chairs Michael Sullivan, NVIDIA (North America)
Tiago Balen, UFRGS (South America)
Stefano Di Carlo, PoliTo (Europe)
Yi-Pin Fang, TSMC (Asia)
Bay Area Industry Liaisons Shahrzad Mirkhani, Bigstream
Mark Gottscho, Google
Webmaster Vanessa Job, LANL/UNM
Advisors to the Committee Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD

 


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Samira Khan
SIGARCH Content Editor

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