This is the 1st September 2020 digest of SIGARCH Messages.

In This Issue

Call for Papers: 3rd Workshop on Accelerated Machine Learning (AccML) at HiPEAC 2021 - (Note: The Call for Paper type has not been set for this item!)

Call for Papers: FCCM 2021 - (Note: The Call for Paper type has not been set for this item!)

Call for Papers: IEEE Micro Top Picks - (Note: The Call for Paper type has not been set for this item!)

Call for Papers: International Conference on Fog and Edge Computing (ICFEC 2021) - (Note: The Call for Paper type has not been set for this item!)

Call for Papers: IoTSMS 2020 - (Note: The Call for Paper type has not been set for this item!)


Call for Participation: PACT 2020
https://pact20.cc.gatech.edu/
Submitted by Jiajia Li

The 29th International Conference on Parallel Architectures and Compilation Techniques (PACT 2020)
October 2, 5-7, 2020
Virtual

PACT 2020

Registration Link ($0-$45 for different registration types):
https://whova.com/portal/registration/icpaa_202010/

Please find the program here:

Program

The registration for the 29th International Conference on Parallel Architectures and Compilation Techniques (PACT) is now open. Registration includes the main conference, along with access to all recordings of talks, Q&A sessions, and keynotes through October 31 2020. Workshops and tutorials are free.

For more details, please visit https://pact20.cc.gatech.edu


Call for Participation: MICRO-53
https://www.microarch.org/micro53/
Submitted by Dimitrios Skarlatos

53rd IEEE/ACM International Symposium on Microarchitecture (MICRO-53)

17-21 October 2020, Global Online Event

https://www.microarch.org/micro53/

The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. The symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and this tradition continues at MICRO-53. Due to the COVID-19 pandemic, the MICRO 2020 edition will be a global online event. The Athens edition of MICRO has been rescheduled for 2021.

MICRO-53 Technical Program

o   Experiences with IoT and the New Internet as a Platform of Things, Rich Wolski (UC Santa Barbara)

o   Exscalate4CoV: Towards an Exascale-Ready Docking Platform Targeting Urgent Computing Against Pandemics, Cristina Silvano (Politecnico di Milano)

o   Architecting a Sustainable Planet, Srilatha (Bobbie) Manne (Microsoft)

o   More papers than any prior MICRO edition; result of an all-times record number of paper submissions in MICRO’s 53-year history.

o   Live presentations and Q&As will take place for each paper and recordings along with the papers in the IEEE proceedings will be available to all registered attendees before the symposium.

  • 8 weekend workshops/tutorials

o   https://www.microarch.org/micro53/program/workshops.php

 

MICRO-53 Registration

The MICRO global online edition this year offers very low registration fees to maximize global participation. Registration gives full access to all the symposium live events (all keynotes and all regular paper sessions), all live workshops/tutorials, and all recordings that are made as part of MICRO. Information about the full fee structure, along with details on when materials will be made available to registered attendees, can be found on the registration information page https://www.microarch.org/micro53/attend/register.php

Early registration ends on Saturday, October 10, at 11:59 PM PDT.


Call for Participation: NOCS 2020
http://nocs2020.engr.uky.edu/
Submitted by Lizhong Chen

14th IEEE/ACM International Symposium on Networks-on-Chip
September 24 – 25, 2020
9 AM to 1:30 PM (ET)
Virtual Event within ESWEEK
http://nocs2020.engr.uky.edu/

The full program is now available, featuring an outstanding combination of keynote speakers, regular and special sessions. Some highlights are:
The keynotes from José Duato (Universitat Politècnica de València) on network congestion in datacenters, and Dennis Abts (Groq) on domain-specific networks for machine learning;
A special session on scalable platforms for machine learning, including an industry perspective from Nvidia and Cerebras on this hot topic;
A special session on learnings from many-core NoC architecture chip tapeouts, with talks from researchers at Cornell and University of Washington;
See the full program at:
http://nocs2020.engr.uky.edu/program

Registration is only 10$ for IEEE/ACM members ($20 for non-members) and gives you access to the whole ESWEEK, including NOCS. Registration details can be found at:
http://nocs2020.engr.uky.edu/registration

======================
About NOCS
======================
The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation.

======================
Conference Leadership
======================
General Chairs:
– Sudeep Pasricha (Colorado State University)
– Ajay Joshi (Boston University)

Technical Program Chairs:
– Tushar Krishna (Georgia Tech)
– John Kim (KAIST)

Steering Committee Chair:
– Radu Marculescu (University of Texas, Austin)


Call for Participation: CONCUR 2020
https://concur2020.forsyte.at
Submitted by Mihaela Rozman, TU Wien

31th International Conference on Concurrency Theory (CONCUR)
part of QONFEST 2020
ONLINE (Vienna, Austria)
September 1-4, 2020

CONCUR 2020 – Call for Participation

====================================
https://concur2020.forsyte.at
====================================

The 31st International Conference on Concurrency Theory (CONCUR) will be held online on 1-4 September 2020. The purpose of the CONCUR conferences is to bring together researchers, developers, and students in order to advance the theory of concurrency, and promote its applications.

It is held as part of the QONFEST 2020, the umbrella conference comprising the joint international 2020 meetings alongside with several workshops and tutorials.

================
Keynote speakers
================

-Roderick Bloem – TU Graz (Austria)
-Thomas A. Henzinger – IST (Austria)
-Annabelle McIver – Macquarie University (Australia)
-Catuscia Palamidessi – INRIA Saclay and LIX (France)

================
High-quality papers
===================
CONCUR 2020 features 45 high-quality papers:
https://concur2020.forsyte.at/accepted.html

The program of CONCUR 2020 can be found at:
https://easychair.org/smart-program/CONCUR20

====================================
Co-located conferences and workshops
====================================
CONCUR 2020 is part of the umbrella conference QONFEST 2020 comprising the joint international 2020 meetings CONCUR, FMICS, FORMATS, QEST, alongside with tutorials and the workshops EXPRESS/SOS, FRIDA, SNR, TRENDS, and QAVS.

More details to be found at: https://qonfest2020.github.io and https://concur2020.forsyte.at/workshops.html

============
Registration
============
This year, the early registration fee (August 13, 2020) for the whole of QONFEST is only 10 EUR. The early workshop registration fee is 5 EUR.  Late registration is 50% more expensive (15 EUR and 8 EUR, respectively).
More information at: https://qonfest2020.github.io/registration.html

==================
Organizing Committee
==================
QONFEST General Chair: Ezio Bartocci  (TU Wien, Austria)
Workshop Chair: Florian Zuleger (TU Wien, Austria)
Program Co-chairs: Igor Konnov (Informal Systems, Austria), Laura Kovacs (TU Wien, Austria)


Call for Participation: ISPASS 2020
https://www.ispass.org/ispass2020/
Submitted by I-Ting Angelina Lee

International Symposium on Performance Analysis of Systems and Software (ISPASS)
August 23-26, 2020
Virtual Meeting

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software. Due to the global pandemic, ISPASS 2020 will be held as a virtual conference August 24 through 26, 2020.  The conference will include pre-recorded paper talks available online, as well as live portions during those mornings (EDT).

The following workshops and tutorials are being held in conjunction with ISPASS, which occur virtually on Sunday August 23:

  • SECRISC-V 2020 
  • FastPath 2020 International Workshop on Performance Analysis of Machine Learning Systems
  • MLBench2020 Workshop on Benchmarking Machine Learning Workloads
  • Timeloop/Accelergy Tutorial: Tools for Evaluating Deep Neural Network Accelerator Designs 
  • Deep Learning Benchmarking and Analysis

The preliminary virtual conference program is online and registration is open.  Visit the  conference website for the program and to register: https://www.ispass.org/ispass2020/

We invite all to attend the conference and look forward to interacting with you online!

Michael Ferdman
ISPASS 2020 Program Chair

Dave Kaeli and Kelly Shaw
ISPASS 2020 Co-General Chairs


Call for Papers: PDP 2021
http://www.pdp2021.org
Submitted by Dora B. Heras

29th Euromicro International Conference on Parallel, Distributed and Network-based Processing (Virtual)
March 10 – 12, 2021

Submissions Due: October 4, 2020

INTRODUCTION:

Parallel, Distributed, and Network-Based Processing has undergone impressive change over recent years. New architectures and applications have rapidly become the central focus of the discipline. These changes are often a result of cross-fertilisation of parallel and distributed technologies with other rapidly evolving technologies. It is of paramount importance to review and assess these new developments in comparison with recent research achievements in the well-established areas of parallel and distributed computing, from industry and the scientific community. PDP 2021 will provide a forum for the presentation of these and other issues through original research presentations and will facilitate the exchange of knowledge and new ideas at the highest technical level.

Topics of interest include, but are not restricted to:

  • Parallel Computing: massively parallel machines; embedded parallel and distributed systems; multi- and many-core systems; GPU and FPGA based parallel systems; parallel I/O; memory organisation.
  • Distributed and Network-based Computing: Cluster, Grid, Web and Cloud computing; mobile computing; interconnection networks.
  • Big Data: large scale data processing; distributed databases and archives; large scale data management; metadata; data intensive applications.
  • Programming models and Tools: programming languages and environments; runtime support systems; performance prediction and analysis; simulation of parallel and distributed systems.
  • Systems and Architectures: novel system architectures; high data throughput architectures; service-oriented architectures; heterogeneous systems; shared-memory and message-passing systems; middleware and distributed operating systems; dependability and survivability; resource management.
  • Advanced Algorithms and Applications: distributed algorithms; multi-disciplinary applications; computations over irregular domains; numerical applications with multi-level parallelism; real-time distributed applications.

IMPORTANT DATES (ALL 23:59 A.O.E)

Deadline for paper submission: October 4, 2020
Acceptance notification: December 18, 2020
Camera ready paper due: January 17, 2021
Registration: *** to be announced
On-line conference: March 10 – 12, 2021

SUBMISSION OF PAPERS:

Prospective authors should submit a full paper not exceeding 8 pages in the Conference proceedings format (double-column, 10pt) to the conference main track or to the Special Sessions through the EasyChair conference submission system indicating thr Main Track or the chosen Special Session.

Double-blind review: the paper should not contain authors names and affiliations; in the reference list, references to the authors’ own work entries should be substituted with the string “omitted for blind review”.

Publication: Proceedings will be published by Conference Publishing Services (CPS). All accepted papers will be included in the same volume, published by the Conference Publishing Services (CPS). The Final Paper Preparation and Submission Instructions will be published after the notification of acceptance. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be submitted to IEEE explore, CDSL, and for indexing among others, to DBLP, Scopus ScienceDirect, and ISI Web of Knowledge.

JOURNAL SPECIAL ISSUES

Selected papers will be invited to submit an extended version to a special issue in a JCR-indexed journal.

ABOUT EUROMICRO

Euromicro is an international scientific organization advancing sciences and applications of Information Technology and Microelectronics. A major focus is on organizing conferences and workshops in Computer Science and Computer Engineering. Euromicro is a non-profit association founded in 1974 and annual conferences have taken place in more than 20 countries all over Europe. Find out more

ORGANIZERS:

General Co-chairs:
Diego R. Llanos, Universidad de Valladolid, Spain
Arturo Gonzalez-Escribano, Universidad de Valladolid, Spain
Jose Daniel García, Universidad Carlos III de Madrid, Spain
Dora Blanco Heras, Universidad de Santiago de Compostela, Spain

Program Co-chairs:
Jose Daniel García, Universidad Carlos III de Madrid, Spain
Arturo Gonzalez-Escribano, Universidad de Valladolid, Spain
Massimo Torquati, University of Pisa, Italy


Call for Papers: DATE 2021: Dependability and System-level Test
http://www.date-conference.com/
Submitted by Karthik Pattabiraman

Topic T3: Dependability and System-level Test
Test and Dependability Track @ DATE 2021
Grenoble, France
February 1-5, 2021

Submissions Due: September 21, 2020

https://www.date-conference.com/tpc#T3

DEADLINES: The deadline to submit papers is 
************************************************
Abstract: Sunday, September 14, 2020 23:59:59 CET.
************************************************

For a paper to be considered a valid submission, at least a title, abstract, and the complete list of authors (cannot be modified after Monday, September 14, 2020 23:59:59 CET) should be submitted by this date. The full paper can be submitted at the same time or later, but must be uploaded at the latest by

************************************************
Full Paper: Monday, September 21, 2020 23:59:59 CET.
************************************************

Please note that there will not be any additional deadline extensions beyond Monday, September 21, 2020 23:59:59 CET.

DATE 2021
The 24th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems, and embedded software. The conference addresses all aspects of research into technologies for electronic and (embedded) systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecom, wireless communications, multimedia, healthcare and automotive systems.

Persons involved in innovative industrial designs are particularly encouraged to submit papers to foster the feedback from design to research. Panels, hot-topic sessions and embedded tutorials highlight and inform about emerging topics. The Test and Dependability track addresses various quality aspects of electronic and embedded systems. The emphasis is on test technology, design-for-testability, security, reliability and other dimensions of dependability. The track’s focus includes significant improvements on existing methods, algorithms and tools as well as forward-looking approaches related to these topics.

T3 – DEPENDABILITY AND SYSTEM-LEVEL TEST TOPIC
The Dependability and System-level Test topic is one of the six topics foreseen in the Test and Dependability track. It is devoted to the presentation and discussion of state-of-the-art advances in the theory and practice of hardware and software solutions for system’s dependability crossing all layers of the system’s stack. Topics of interest include, but are not limited to:

  • microarchitecture-level and system-level error/fault modeling; 
  • cross-layer dependability analysis and evaluation; 
  • reliable and fail-safe architectures and systems design; 
  • system-level on-line test and functional safety; 
  • runtime system management for dependability; 
  • cross-layer solutions for dependability (microarchitecture-level, software-level, system-level); 
  • application resilience; 
  • high-level synthesis (HLS) dependability;
  • approximate computing for resilient systems;
  • computational intelligence methods (AI/ML) for dependability; 
  • system-level and microarchitecture-level solutions for safety- and mission-critical systems, IoT and cloud infrastructure

TOPIC TECHNICAL COMMITTEE
Karthik Pattabiraman, University of British Columbia (chair)
Stefano Di Carlo, Politecnico di Torino (cp-chair),
Jyotika Athavale, Intel Corp
Görschwin Fey, Hamburg University of Technology
Dimitris Gizopoulos, University of Athens
Paolo Rech, UFRGS
Juan Carlos Ruiz Garcia, UPV Valencia
Rishad Shafik, Newcastle University

SUBMISSION INSTRUCTIONS
Submission instructions can be found on the conference web page: www.date-conference.com


Call for Papers: IoTSMS 2020
https://emergingtechnet.org/IOTSMS2020/
Submitted by Marco Guazzone

7th International Conference on Internet of Things: Systems, Management and Security (IoTSMS 2020)
Paris, France
December 14-16, 2020

Submissions Due: September 10, 2020

URL: https://emergingtechnet.org/IOTSMS2020/

IMPORTANT DATES
* Submission Date: September 10, 2020 (firm and final extension)
* Notification to Authors: October 10, 2020
* Camera Ready Submission: November 1, 2020

The Internet of Things (IoT) technology offers unprecedented opportunities to interconnect human beings as well as Machine-to-Machine (M2M), whereby sensors and networks allow all ‘things’ to communicate directly with each other to share vital information allowing us to have an instrumented universe where accurate data is readily available to inform optimal decision making. The IoT is about to enable a range of new capabilities and services far beyond today’s offerings. It will fundamentally change how people go about their lives. According to Gartner, the number of objects connected to the Internet is set to reach 20 billion by 2020. Cisco estimates the number will be close to 26 billion objects by 2020. Others believe the actual number will be even higher with the assumption that any object with a simple micro controller and on-off switch will be connected to the Internet in the near feature. The scale of the IoT is set to have a major economic, social and environmental impacts; the intersection of which forms the future sustainable growth.

The international conference on Internet of Things: Systems, Management and Security (IoTSMS) aims at soliciting original ideas on the broad area of IoT including challenges and opportunities, concepts and applications and future trends. The IoTSMS aims to facilitate discussions among academics and IoT practitioners and make positive contributions to the field.

TOPICS OF INTERESTS
* Emerging concepts of IoT Systems
* Architectures of IoT systems
* Machine-to-Machine Communication and IoT
* Modeling of IoT applications
* SDN and NFV support for IoT applications and Systems
* Fog and Edge support for IoT Applications
* 5G support for IoT Applications
* IoT for Smart Cities
* Energy management in IoT
* Design methodologies for IoT
* Novel services and applications of IoT to facilitate environmental responsibility
* Green by Internet of Things
* IoT and Social benefits/impact
* IoT Economics and Business Models
* Emerging Internet of Things business models and process changes
* Communication systems and network architectures for the IoT
* IoT and Data Management
* Security and privacy of IoT
* Reliability of IoT
* Disaster recovery in IoT
* Applications of Internet of things
* Emerging applications and interaction paradigms for everyday citizens
* Big data and IoT
* Self-organizing IoT
* Cloud Computing and IoT
* IoT and sustainable Growth

PUBLICATION
All accepted papers will appear in the conference proceedings and will be published by IEEE and included in the IEEE Xplore digital library.

GENERAL CHAIRS
* Abdelhakim Hafid Senhadji, University of Montreal, Canada.
* Francisco Falcone, Universidad Publica de Navarra, Spain.

PROGRAM CHAIRS
* Attila Kertesz <keratt@inf.u-szeged.hu>
* Marco Guazzone <marco.guazzone@uniupo.it>


Call for Papers: CGO 2021
http://cgo.org/
Submitted by Dongyoon Lee

IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
co-located with PPoPP, CC, and HPCA
February 27 – March 3, 2021, Virtual Conference
http://cgo.org/

UPDATES
With the continued impact of the COVID-19, the joint steering committee of CGO/PPoPP/HPCA/CC has decided to make the conference a virtual event this year. The next conference will be held in Seoul again in 2022. The details on the virtual conference format will be announced later.

Submissions Due: September 1, 2020

CALL FOR PAPERS

The International Symposium on Code Generation and Optimization (CGO) is a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

IMPORTANT DATES
Abstract Submission: August 25, 2020
Paper Submission: September 1, 2020
Author Rebuttal Period: October 11 – 17, 2020
Paper Notification: November 5, 2020

Original contributions are solicited on, but not limited to, the following topics:

– Code Generation, Translation, Transformation, and Optimization for performance, energy, virtualization, portability, security, or reliability concerns, and architectural support
– Efficient execution of dynamically typed and higher-level languages
– Optimization and code generation for emerging programming models, platforms, domain-specific languages
– Dynamic/static, profile-guided, feedback-directed, and machine learning based optimization
– Static, Dynamic, and Hybrid Analysis for performance, energy, memory locality, throughput or latency, security, reliability, or functional debugging
– Program characterization methods
– Efficient profiling and instrumentation techniques; architectural support
– Novel and efficient tools
– Compiler design, practice and experience
– Compiler abstraction and intermediate representations
– Vertical integration of language features, representations, optimizations, and runtime support for parallelism
– Solutions that involve cross-layer (HW/OS/VM/SW) design and integration
– Deployed dynamic/static compiler and runtime systems for general purpose, embedded system and Cloud/HPC platforms
– Parallelism, heterogeneity, and reconfigurable architectures
– Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA
– Compiler support for vectorization, thread extraction, task scheduling, speculation, transaction, memory management, data distribution and synchronization

ARTIFACT EVALUATION

The Artifact Evaluation process is run by a separate committee whose task is to assess how the artifacts support the work described in the papers. This process contributes to improve reproducibility in research that should be a great concern to all of us. There is also some evidence that papers with a supporting artifact receive higher citations than papers without (Artifact Evaluation: Is It a Real Incentive? by B. Childers and P. Chrysanthis).

Authors of accepted papers at CGO have the option of submitting their artifacts for evaluation within two weeks of paper acceptance. To ease the organization of the AE committee, we kindly ask authors to indicate at the time they submit the paper, whether they are interested in submitting an artifact. Papers that go through the Artifact Evaluation process successfully will receive a seal of approval printed on the papers themselves. Additional information is available on the CGO AE web page. Authors of accepted papers are encouraged, but not required, to make these materials publicly available upon publication of the proceedings, by including them as “source materials” in the ACM Digital Library.

CALL FOR TOOLS AND PRACTICAL EXPERIENCE PAPERS

Last year CGO had a special category of papers called “Tools and Practical Experience,” which was very successful. CGO this year will have the same category of papers. Such a paper is subject to the same page length guidelines, except that it must give a clear account of its functionality and a summary about the practice experience with realistic case studies, and describe all the supporting artifacts available.

For papers submitted in this category that present a tool it is mandatory to submit an artifact to the Artifact Evaluation process and to be successfully evaluated. These papers will initially be conditionally accepted based on the condition that an artifact is submitted to the Artifact Evaluation process and that this artifact is successfully evaluated. Authors are not required to make their tool publicly available, but we do require that an artifact is submitted and successfully evaluated.

Papers submitted in this category presenting practical experience are encouraged but not required to submit an artifact to the Artifact Evaluation process.

The selection criteria for papers in this category are:

– Originality: Papers should present CGO-related technologies applied to real-world problems with scope or characteristics that set them apart from previous solutions.
– Usability: The presented Tools or compilers should have broad usage or applicability. They are expected to assist in CGO-related research, or could be extended to investigate or demonstrate new technologies. If significant components are not yet implemented, the paper will not be considered.
– Documentation: The tool or compiler should be presented on a web-site giving documentation and further information about the tool.
– Benchmark Repository: A suite of benchmarks for testing should be provided.
– Availability: Preferences will be given to tools or compilers that are freely available (at either the source or binary level). Exceptions may be made for industry and commercial tools that cannot be made publicly available for business reasons.
– Foundations: Papers should incorporate the principles underpinning Code Generation and Optimization (CGO). However, a thorough discussion of theoretical foundations is not required; a summary of such should suffice.
– Artifact Evaluation: The submitted artifact must be functional and supports the claims made in the paper. Submission of an artifact is mandatory for papers presenting a tool.

Authors should carefully consider the difference in focus with the co-located conferences when deciding where to submit a paper. CGO will make the proceedings freely available via the ACM DL platform during the period from two weeks before to two weeks after the conference. This option will facilitate easy access to the proceedings by conference attendees, and it will also enable the community at large to experience the excitement of learning about the latest developments being presented in the period surrounding the event itself.

ORGANIZERS

General Chair
Jae W. Lee, Seoul National University

Program Chairs
Mary Lou Soffa, University of Virginia
Ayal Zaks, Intel


Call for Papers: tinyML 2021
https://docs.google.com/document/d/165lfe1dmgB4SYuuE4FkWUdyVDUAzsIUledMqJfu5tms/edit
Submitted by Vijay Janapa Reddi

tinyML Research Symposium 2021
New academic & commercial research symposium as part of the 3rd annual tinyML Summit
Monday, March 22, 2021

Submissions Due:  Nov 2, 2020

Tiny machine learning (tinyML) is a fast-growing field of machine learning technologies and applications including algorithms, hardware, and software capable of performing on-device sensor (vision, audio, IMU, biomedical, etc.) data analytics at extremely low power, typically in the mW range and below, and hence enabling a variety of always-on use-cases and targeting battery-operated devices. tinyML systems are becoming “good enough” for (i) many commercial applications and new systems on the horizon; (ii) significant progress is being made on algorithms, networks, and models down to 100 kB and below; and (iii) initial low power applications in vision and audio are becoming mainstream and commercially available. There is growing momentum demonstrated by technical progress and ecosystem development.

The first annual tinyML research symposium serves as a flagship venue for research at the intersection of machine learning applications, algorithms, software, and hardware in deeply embedded machine learning systems. We solicit papers from academia and industry combining cross-layer innovations across topics. Submissions must describe tinyML innovations that intersect and leverage synergy between at least two of the following subject areas:

tinyML Datasets

  • Public release of new datasets to tinyML
  • Frameworks that automate dataset development
  • Survey and analysis of existing tiny datasets that can be used for research

tinyML Applications

  • Novel applications across all fields and emerging use cases
  • Discussions about real-world use cases
  • User behavior and system-user interaction
  • Survey on practical experiences

tinyML Algorithms

  • Federated learning or stream-based active learning methods
  • Deep learning and traditional machine learning algorithms
  • Pruning, quantization, optimization methods
  • Security and privacy implications

tinyML Systems

  • Profiling tools for measuring and characterizing system performance and power
  • Solutions that involve hardware and software co-design
  • Characterization of tiny real-world embedded systems
  • In-sensor processing, design, and implementation

tinyML Software

  • Interpreters and code generator frameworks for tiny systems
  • Optimizations for efficient execution
  • Software memory optimizations
  • Neural architecture search methods

tinyML Hardware 

  • Power management, reliability, security, performance
  • Circuit and architecture design
  • Ultra-low-power memory system design
  • MCU and accelerator architecture design and evaluation

tinyML Evaluation

  • Measurement tools and techniques
  • Benchmark creation, assessment and validation
  • Evaluation and measurement of real production systems

Accepted papers will be published in the form of peer-reviewed online proceedings. An author of an accepted paper must attend the research symposium to give a presentation.

PROGRAM CHAIRS

Vijay Janapa-Reddi, Harvard Univ.

Boris Murmann, Stanford Univ.

 

PROGRAM & ORGANIZING COMMITTEE

Please see detailed CFP.

 

IMPORTANT DATES

  • Papers Due:  Nov 2nd, 2020
  • Author Notification: Jan 15th, 2021
  • Camera Ready: Feb 15th, 2021

SUBMISSION WEBSITE

Please visit OpenReview.


Call for Papers: ASPLOS 2021
https://asplos-conference.org/
Submitted by Emery Berger

The 26th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2021)
Detroit, USA
April, 2021

Submissions Due: August 21, 2020

https://asplos-conference.org/
https://asplos21.hotcrp.com/

ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, operating systems and networking. The 26th ASPLOS will be held in Detroit, Michigan (USA), a.k.a. Motor City, the historic heart of America’s automotive industry and the birthplace of Motown Records.

Like its predecessors, ASPLOS 2021 invites papers on ground-breaking research at the intersection of the ASPLOS disciplines: architecture, programming languages, operating systems, and related areas. Non-traditional topics are especially encouraged. The importance of cross-cutting research continues to grow as we grapple with the end of Dennard scaling, the explosion of big data, scales ranging from ultra-low power wearable devices to exascale parallel and cloud computers, the need for sustainability, and increasingly human-centered applications. ASPLOS embraces systems research that directly target new problems in innovative ways. The research may target diverse goals, such as performance, energy and thermal efficiency, resiliency, security, sustainability, applicability to future technologies, applications, and environments. The review process will be sensitive to the challenges of multidisciplinary work in emerging areas.

Areas of interest include, but are not limited to:

  • Existing and emerging platforms at all scales (embedded to cloud)
  • Internet services, cloud computing, and datacenters
  • Multicore architectures and systems
  • Heterogeneous architectures and accelerators
  • Systems for enabling parallelism at extreme scale
  • Programming models, languages, and compilation for all platforms
  • Managing, storing, and computing on big data
  • Virtualization and virtualized systems
  • Memory and storage technologies and architectures
  • Power, energy, and thermal management
  • Security, reliability, and availability
  • Verification and testing, and their impact on design
  • Support for approximations and approximate computing
  • Non-traditional computing systems, including emerging devices

Deadlines
Paper registration: August 14, 2020
Full paper submission: August 21, 2020
Author response: November 4-6, 2020
Notification: November 19, 2020
Final paper deadline: February 1, 2021

ASPLOS’21 Extended Abstracts

In the past decade, our community has grown considerably both in the number of researchers and the number of institutions involved. While this is a wonderful development for our field, the corresponding growth in conference submissions is stressing our paper review processes. The increasingly larger program committees (PC) and multi-day PC meetings have not been sufficient to address the problems. PC members complain about excessive reviewing workloads and long PC meetings where they rarely talk. Authors routinely complain about low quality of reviews and inconsistent review outcomes.

We believe the key to high quality review outcomes and an overall high quality program is to involve more PC members with the review and decision for each paper. To allow for that in the presence of record submission counts (almost 500 for ASPLOS’20), we will pilot the use of extended abstracts in ASPLOS’21.  Each paper submission must be accompanied by a 2-page extended abstract that summarizes the motivation, key insights, main artifacts, and important contributions (see this template for suggested structure). The extended abstracts are inspired by the familiar submission format for the yearly IEEE Micro Top Picks issue.

Here is how extended abstracts will help in the reviewing process:

  • We will use the extended abstracts in the first round of reviewing (R1). We expect each abstract to be reviewed by 4 or more PC members (plus additional external reviewers) and each PC member will review 4x to 5x more abstracts than papers in a traditional R1. We hope that more PC reviews per submission and better calibrated PC members will lead to better R1 decisions. Contrast this to recent ASPLOS conferences, where some papers were rejected in R1 with 1 or 2 PC reviews.
  • We will use the extended abstracts to increase the number of informed participants in the PC meeting. Ahead of the PC meeting, we will ask PC members to read a few additional extended abstracts and 1-page review summaries for submissions in their area. This will allow us to quickly bring further expertise into the discussion for challenging submissions. We will also allow any PC member to access extended abstract and review summaries. That way, we hope to avoid what is common in PC meetings, where a disagreement by the 3 PC reviewers is resolved with a vote by uninformed and uncalibrated PC members.

The PC members may suggest other uses for the extended abstracts throughout the review process.

We are excited to measure and understand how extended abstracts can improve our reviewing process. Along with other experiments, such as multiple submission deadlines throughout the year, they can help us achieve high quality paper review and selection as our community grows.

Christos Kozyrakis & Emery Berger
PC Co-chairs, ASPLOS’21


Call for Papers: PPoPP 2021
https://ppopp21.sigplan.org
Submitted by Boris Grot

26th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2021)
Co-located with CGO and HPCA
Seoul, South Korea
February 27 – March 3, 2021

Submissions Due: August 13, 2020

IMPORTANT DATES:
Paper registration and abstract submission: August 6, 2020
Full paper submission: August 13, 2020
Early notification for papers not passing first stage: October 10, 2020
Author response period: October 30–November 2, 2020
Author Notification: November 16, 2020
Artifact submission to AE committee (tentative): November 26, 2020
Artifact notification by AE committee (tentative): December 26, 2020
Final paper due: January 2, 2021
All deadlines are at midnight anywhere on earth (AoE), and are firm.

PPoPP is the premier forum for leading work on all aspects of parallel programming, including theoretical foundations, techniques, languages, compilers, runtime systems, tools, and practical experience. In the context of the symposium, “parallel programming” encompasses work on concurrent and parallel systems (multicore, multi-threaded, heterogeneous, clustered, and distributed systems; grids; data centers; clouds; and large scale machines). Given the rise of parallel architectures in the consumer market (desktops, laptops, and mobile devices) and data centers, PPoPP is particularly interested in work that addresses new parallel workloads and issues that arise out of extreme-scale applications or cloud platforms, as well as techniques and tools that improve the productivity of parallel programming or work towards improved synergy with such emerging architectures.

Conference submission site: https://ppopp21.hotcrp.com.

For further details, including topics of interest, submission guidelines and the artifact evaluation process, please refer to the conference web site.


Call for Papers: EuroSys 2021
https://2021.eurosys.org/cfp.html#cfp
Submitted by Boris Grot

European Conference on Computer Systems (EuroSys)
Edinburgh, Scotland, UK
April 26-29, 2021

Submissions Due: October 9, 2020

The European Conference on Computer Systems (EuroSys) is a premier international forum for presenting computer systems research. EuroSys 2021 seeks papers on all areas of computer systems research, including:

– Operating systems
– Distributed systems
– Cloud computing and datacenter systems
– File and storage systems
– Networked systems
– Language support and runtime systems
– Systems security and privacy
– Dependable systems
– Analysis, testing and verification of systems
– Database systems and data analytics frameworks
– Virtualization and virtualized systems
– Systems for machine learning/machine learning for systems
– Mobile and pervasive systems
– Parallelism, concurrency, and multicore systems
– Real-time, embedded, and cyber-physical systems

We encourage papers that span multiple topics and communities. Papers will be judged on novelty, significance, correctness, and clarity. The program committee seeks papers that address a significant problem with an interesting and compelling solution whose validity and practicality are clearly demonstrated. A good paper will draw appropriate conclusions, honestly present related prior work, acknowledge its own limitations, and clearly articulate the advances it offers over prior work.

There are three new features in this year’s Eurosys reviewing process:
1) Author response
2) Revision stage
3) Artifact Evaluation

Please visit the conference web site for a detailed description of each of these features.

Posters:
In addition to paper presentations, EuroSys 2021 will have a poster session. Submissions for posters will open closer to the conference deadline. Accepted papers will automatically qualify for the poster session, and authors will be strongly encouraged to participate.

Awards:
EuroSys grants awards for the best and best student papers. In addition, EuroSys will also present the best artifact award this year.

Submission guidelines:
Please see the conference web site for detailed submission guidelines.

Important dates
Abstract submission: 1 October 2020
Paper submission: 9 October 2020
Author response: 6-8 January 2021
Notification of conditional accept / revise / reject: 20 January 2021
Revision submission (selected papers): 17 February 2021
Notification of conditional accept/reject for revisions: 3 March 2021
Shepherding decisions: 23 March 2021
Camera-ready submission: 26 March 2021

Contact:
For any further information, please contact the PC chairs: pc-chairs-2021@eurosys.org
Lorenzo Alvisi (Cornell University)
Cristian Cadar (Imperial College London)


Call for Papers: Reconfigurable Systems at DATE 2021
https://www.date-conference.com
Submitted by Suhaib Fahmy

Topic D12 Reconfigurable Systems
Design Methods and Tools Track @ DATE 2021
Grenoble, France
February 1-5, 2021

Submissions Due: September 21, 2020

For a paper to be considered a valid submission, at least a title, abstract, and the complete list of authors (cannot be modified after Monday, September 14, 2020 23:59:59 CET) should be submitted by this date.

The full paper can be submitted at the same time or later, but must be uploaded at the latest by Monday, September 21, 2020 23:59:59 CET. Otherwise the initial submission will be automatically withdrawn. Please note that there will not be any additional deadline extensions beyond Monday, September 21, 2020 23:59:59 CET.

The 24th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems.

DATE puts strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems, and embedded software.

The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days and a track for executives. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software, and (industrial) design experiences from different application domains, e.g. automotive, wireless, telecom and multimedia applications. The organisation of user group meetings, fringe meetings, a university booth, a PhD forum, vendor presentations and social events offers a wide variety of extra opportunities to meet and exchange information on relevant issues for the design and test community. Special space will also be allocated for EU-funded projects to show their results.

The conference addresses all aspects of research into technologies for electronic and (embedded) systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecom, wireless communications, multimedia, healthcare and automotive systems.

Persons involved in innovative industrial designs are particularly encouraged to submit papers to foster the feedback from design to research. Panels, hot-topic sessions and embedded tutorials highlight and inform about emerging topics.

The Design Methods and Tools Track addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

The Reconfigurable Systems topic (D12) is one of fifteen topics in the Design Methods and Tools Track.

TOPIC DESCRIPTION

The Reconfigurable Systems topic (D12) is devoted to all aspects of reconfigurable computing systems. Topics of interest include, but are not limited to:

– Reconfigurable computing platforms and architectures
– Heterogeneous platforms (e.g., including FPGA/GPU/CPU)
– Reconfigurable processors
– Statically and dynamically reconfigurable systems and components
– Reconfigurable computing for machine learning, data center and high-performance computing
– FPGA architecture
– FPGA partial reconfiguration
– Design methods and tools for reconfigurable computing

TOPIC TECHNICAL COMMITTEE

– Christos Bouganis, Imperial College London, GB
– Miriam Leeser, Northeastern University, US
– Bogdan Pasca, Intel, FR
– Marco D. Santambrogio, Politecnico di Milano, IT
– David Sidler, Microsoft Corporation, CH
– Ioannis Sourdis, Chalmers University of Technology, SE
– Stephan Wong, Delft University of Technology, NL
– Daniel Ziener, Technische Universität Ilmenau, DE

SUBMISSION INSTRUCTIONS

Submission instructions can be found on the conference web page: www.date-conference.com

Papers can be submitted either as Scientific Papers for Oral Presentation or as Scientific Papers for Interactive Presentation.

Oral presentations require novel and complete research work supported by experimental results. They will be evaluated with regard to their suitability for the conference, originality, and technical soundness.
Accepted papers will be published in the conference proceedings (max six pages) and will be presented in either 30-minute (“long”) or 15-minute (“short”) slots in the conference program in front of an audience.
The Program Committee reserves the right to reorient Oral-Presentation papers to Interactive-Presentation, to obtain the most suitable presentation format.

Interactive presentations are expected to articulate emerging and future design, verification and test problems including work in progress and identify open problems that merit innovative future research.
Accepted papers will be published in the conference proceedings (max four pages) and will be presented in a face-to-face discussion area.
Presenters are required to prepare a poster (up to A0 format) to help the discussion.

The accepted file format is PDF.
Submissions should be formatted as close as possible to the final format: A4 or letter pages, double column, single spaced, Times or equivalent font of minimum 10pt (templates are available on the DATE Web site for your convenience).
To permit blind review, manuscripts should not include the author names nor affiliations. Manuscripts not in line with the above rules might be discarded.


Call for Papers: DASIP 2021

Submitted by Pillement Sebastien

The Workshop on Design and Architectures for Signal and Image Processing (DASIP)
in conjunction with HiPEAC 2021
Budapest, Hungary
January 18-20, 2021

Submissions Due: October 18, 2020

The Workshop on Design and Architectures for Signal and Image Processing (DASIP) provides an inspiring international forum for the latest innovations and developments in the field of leading signal, image and video processing and machine learning in custom embedded, edge and cloud computing architectures and systems. The workshop program will include keynote speeches and contributed paper sessions. The 14th edition will be held in conjunction with the 16th HiPEAC Conference in Budapest, Hungary, January 18-20, 2021.

SUBMISSION GUIDELINES

Authors should submit their full papers (up to 12 pages, single-column ACM format) in PDF through the EasyChair system <https://easychair.org/conferences/?conf=dasip2021>. Please use the ACM template <https://www.acm.org/publications/proceedings-template> (Latex only, Master Article Template – sample-manuscript.tex).

Submitted papers are required to describe original unpublished work and must not be under consideration for publication elsewhere. Submissions must be fully anonymous, but authors should not hide previous work, instead, they need to make self-references in the third person. More details on submission requirements, templates and submission instructions are provided on the DASIP website <http://www.dasip-conference.org/>.

Each submission will receive at least three independent double blind reviews from the members of our scientific committee. Authors will be encouraged to take the reviewers’ comments into account when they prepare the final versions of their papers and present the research during the workshop prior to its publication. The workshop proceedings will be published in the ACM International Conference Proceedings Series (ICPS). Paper and keynote presentation slides and tutorial documents will be made available to workshop attendees after the workshop (subject to confidentiality issues).

IMPORTANT DATES (ALL 23:59 A.O.E)

– Abstract submission deadline: October 11th, 2020
– Paper submission deadline: October 18th, 2020
– Notification of acceptance: November 22th, 2020
– Camera ready papers: December 6th, 2020
– Workshop : January 18-20, 2021

LIST OF TOPICS

Prospective authors are invited to submit manuscripts on topics including, but not limited to:

=> Custom embedded, edge and cloud architectures and systems:
– Machine learning and deep learning architectures for inference and training
– Systems for autonomous vehicles : cars, drones, ships and space applications
– Image processing and compression architectures
– Smart cameras, security systems, behaviour recognition
– Edge and cloud processing : special routing, configurable co-processors and low energy considerations
– Real-time cryptography, secure computing, financial and personal data processing
– Computer arithmetic, approximate computing, probabilistic computing, nanocomputing, bio-inspired computing
– Biological data collection and analysis, bioinformatics
– Personal digital assistants, natural language processing, wearable computing and implantable devices
– Global navigation satellite and inertial navigation systems

=> Design Methods and Tools:
– Design verification and fault tolerance
– Embedded system security and security validation
– System-level design and hardware/software co-design
– High-level synthesis, logic synthesis, communication synthesis
– Embedded real-time systems and real-time operating systems
– Rapid system prototyping, performance analysis and estimation
– Formal models, transformations, algorithm transformations and metrics

=> Development Platforms, Architectures and Technologies:
– Embedded platforms for multimedia and telecommunication
– Many-core and multi-processor systems, SoCs, and NoCs
– Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
– Memory system and cache management
– Asynchronous (self-timed) circuits and analog and mixed-signal circuits

=> Organizing committee

– Tomasz Kryjak, AGH University of Science and Technology
– Andrea Pinna, Sorbonne Universite

VENUE

The Workshop on Design and Architectures for Signal and Image Processing will be held in conjunction with the 16th HiPEAC Conference in Budapest <https://www.hipeac.net/2021/budapest/#/>, Hungary, January 18-20, 2021.

CONTACT

All questions about the workshop and submissions should be emailed to Tomasz Kryjak <tomasz.kryjak@agh.edu.pl> or Andrea Pinna <andrea.pinna@sorbonne-universite.fr>.


Call for Papers: Hardware and Architectural Support for Security and Privacy (HASP) 2020
https://haspworkshop.org
Submitted by Jakub Szefer

Hardware and Architectural Support for Security and Privacy (HASP) 2020
To be held October 17, 2020 — virtually in conjunction with MICRO 2020

https://haspworkshop.org

Submissions Due: (new extended deadline) Sep 19, 2020

=== Call for Papers ===

Although much attention has been directed to the study of security at the system and application levels, security and privacy research focusing on hardware and architecture aspects is still a new frontier. In the era of cloud computing, smart devices, and novel nano-scale devices, practitioners and researchers have to address new challenges and requirements in order to meet the ever-changing landscape of security research and new demands from consumers, enterprises, governments, defense and other industries.

HASP is intended to bring together researchers, developers, and practitioners from academia and industry, to share practical implementations and experiences related to all aspects of hardware and architectural support for security and privacy, and to discuss future trends in research and applications. To that end, papers are solicited from the areas, including, but not limited to:

Secure hardware processor architectures and implementations
Side-channel attacks, evaluations, and defenses
Secure cache designs and evaluation, focusing on side-channels
SGX, SEV and Trustzone based systems and security solutions
Hardware-enhanced cloud security
Hardware support for secure Internet-of-Things
Smartphone hardware security
Hardware fingerprinting and PUFs
Hardware and architectural support for trust management
Hardware trojan threat evaluation, detection, and prevention
Attack resilient hardware and architectural design
Cryptographic hardware design, implementation, and evaluation
Security simulation, testing, validation and verification
Analysis of real attacks and threat evaluation

In addition to regular research papers, authors are also invited to submit position papers or systematization-of-knowledge papers. Position papers should define new problems in hardware or architecture security and privacy topics. Titles of position papers should have Position Paper: as their prefix.

Systematization-of-Knowledge papers should concisely, but exhaustively, systematize and conceptualize existing knowledge (similar to SoK papers in S&P conferences, but focusing on hardware and architecture). Titles of Systematization-of-Knowledge papers should have SoK: as their prefix.

Finally, researchers wishing to share their ongoing work without publishing a paper should submit application for a Work-in-Progress presentation. To be considered, a short 4-page paper should be submitted, with WiP: as the prefix to the title. These papers will not be published in the proceedings, but the title and authors will be listed on the HASP web page as a public record of the presentation.

=== Important Dates ===

Submission Deadline: (new extended deadline) Sept. 19, 2020 by end of day Anywhere on Earth (AoE)
Notification of Acceptance: Oct. 3, 2020
Camera-Ready Version: Oct. 10, 2020
Virtual Workshop: October 17, 2020 (Saturday)

=== Submission Information ===

All submissions must be using the double-column ACM ICPS template. LaTeX template is preferred. Please use the ACM Standard template in the usual two-column format. The template can be found here.

The submissions should be anonymized for double-blind review.

Regular submissions and position papers must be at most 8 pages including the bibliography and appendices. Work-in-Progress submissions must be at most 4 pages total. SoK papers should also be 8 pages, but exceptions can be made, please contact the organizers with any questions.

All accepted regular papers, position papers, and SoK papers will be included in the ACM Digital Library; Work-in-Progress papers are not included. The proceedings will be published through ACM ICPS and available through the ACM Digital Library.

Papers can be submitted on the EasyChair web page: https://easychair.org/conferences/?conf=hasp2020.


Call for Papers: NoCArc 2020
http://www.nocarc.org/
Submitted by Naseef Mansoor

NoCArc 2020
13th International Workshop on Network on Chip Architectures
October 18, 2020 – Athens, Greece
To be held in conjunction with the 53rd Annual IEEE/ACM International Symposium on Microarchitecture
http://www.nocarc.org/

Submissions Due: Aug 14, 2020 (Extended)

*******************************************************************************

!!! Due to the evolution of the COVID-19 outbreak, it is not still clear if there will be a virtual event or the conference will be postponed. We are trying to figure this out as soon as possible. Regardless of the final choice, we will do our best to make it a safe and fruitful experience. Please visit NoCArc 2020 webpage (http://www.nocarc.org/) for updates. !!!

G E N E R A L  I N F O R M A T I O N

It is well recognized that on-chip communication plays a dominant role indetermining the overall performance, reliability, and energy figures in many-core architectures. Today, virtually all large-scale chips are designed on the basis of the Network-on-Chip (NoC). NoCs are now part of a large number of products that we use every day and this is a proof that NoC paradigm is scalable and can be adapted to support various computational paradigm, ranging from multiprocessing to reconfigurable computing and the emerging area of neuromorphic computing. The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to the design and implementation of many-core architectures based on the NoC paradigm.

A R E A S   O F   I N T E R E S T

The workshop will focus on issues related to design, analysis, and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation
  * Topologies, routing, and flow control
  * Managing QoS
  * Reliability issues
  * Security issues
  * Design methodologies and tools
NoC at System-level
  * Design of memory subsystem
  * NoC support for memory and cache access
  * OS support for NoCs
  * Programming models including shared memory, message passing, and novel
    programming models
  * Large-scale systems (datacenters and supercomputers) with NoC-based
    systems as building blocks
NoC Applications
  * Mapping of applications onto NoCs
  * Real and industrial NoC case studies
  * NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
  * NoC designs for heterogeneous systems
NoC Analysis, Optimization, and Verification
  * Power, energy and thermal issues
  * Benchmarking and experience with NoC-based systems
  * Modeling, simulation, and synthesis
  * Verification, debug and test of
  * Metrics and benchmarks
Emerging NoC Technologies
  * Wireless, Optical, and RF
  * NoCs for 3D and 2.5D packages
  * Approximate computing for NoC and NoC-based systems
  * Chip-to-Chip Interconnects
Machine Learning (ML) for NoC-based systems
  * Novel interconnection for machine learning systems
  * Memory access for the NoC-based machine learning system
  * NoC-based machine learning algorithm design
Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.
S U B M I S S I O N
Please, visit the workshop webpage (http://www.nocarc.org/) for information about the submission process.
The accepted conference papers will be invited for an extended journal version, to be published in a special issue in the MDPI Journal of Low Power Electronics and Applications (JLPEA, Impact Factor: 1.18)
I M P O R T A N T   D A T E S
* Abstract submission deadline: Aug 7, 2020 (Extended)
* Paper submission deadline: Aug 14, 2020 (Extended)
* Acceptance notification: September 1, 2020
* Camera-ready version due: September 8, 2020
* NoCArc workshop: October 18, 2020
O R G A N I Z E R S
GENERAL CHAIR
* Sergi Abadal, Universitat Politècnica de Catalunya, Spain
TPC CHAIRS
* Amlan Ganguly, Rochester Institute of Technology, NY, USA
* Salvatore Monteleone, CY Cergy Paris Université, ENSEA, France

Call for Papers: The 3rd P4 Workshop in Europe (EuroP4)
https://p4.org/events/2020-12-01-euro-p4-workshop
Submitted by Tamas Levai

The 3rd P4 Workshop in Europe (EuroP4)
A presentation by the P4 Language Consortium and ONF in conjunction with CoNEXT 2020
Barcelona, Spain
December 1, 2020

Submissions Due: September 8, 2020

EuroP4 will be held on December 1st, 2020 at Barcelona, Spain, in conjunction with CoNEXT 2020.

The 3rd P4 Workshop in Europe (EuroP4) will bring together networking researchers to discuss cutting-edge, P4-based, research. The workshop provides a venue for P4-based research and projects, a place to discuss P4-based tools, and the research community needs. The workshop aims to forge connections between researchers, introduce more networking researchers to the P4 community, and seed future top-tier publications and innovation.

TOPICS OF INTEREST

We solicit original, previously unpublished ideas on P4-based research and engineering work, and work-in-progress reports in the form of short papers. We further encourage papers that propose new research directions or that could stimulate lively debate at the workshop. We invite submissions on a wide range of topics of interest, including, but not limited to:

  • All aspects of P4-based network protocol research, including design, specification, verification, implementation, measurement, testing, and analysis.
  • Design, analysis, and evaluation of network architectures using P4 as a basis, e.g., specific algorithms and protocols for network virtualization or future Internet architectures.
  • New applications enabled by P4, including in-network computing and Big Data, Video and Virtual Reality, Mobile and Wireless Network Protocols and Applications, Ubiquitous computing, Internet-of-Things and Smart Cities.
  • Secure, reliable and dependable P4-based systems, including all aspects of monitoring, verification, debugging and troubleshooting networks enabled by P4.
  • P4-based and P4-NetFPGA based programmable data planes.
  • P4 end-host networking, offloading transport- and application-layer protocols to P4-enabled hardware.
  • Tools and frameworks for development using P4.
  • Contributions to the evolution of the P4 language.

IMPORTANT DATES

Abstract registration: Tuesday September 1st, 2020 (11:59PM AoE)
Submission deadline: Tuesday, September 8th, 2020 (11:59PM AoE) (hard deadline, no extensions will be given)
Acceptance notification: Monday, October 5th, 2020
Posters and demos deadline: Tuesday, September 8th, 2020 (11:59PM AoE)
Posters and demos notification: Monday, October 5th, 2020
Camera ready: Monday, October 26th, 2020 (11:59PM AoE)

PARTICIPATION

There are currently significant statutory lockdowns and travel restrictions in-place in many parts of the world. We are closely monitoring the situation, and working in collaboration with CoNext’20 to decide on the workshop’s mode. Please follow updates on CoNEXT 2020 and our website.

SUBMISSION INSTRUCTIONS

EuroP4 solicits full-length technical papers of 6 pages and short poster/demo papers as 2 page extended abstracts. Submissions should adhere to the ACM formatting requirements (2-column, 10pt ACM format). EuroP4 will use a double-blind review process.

Authors are required to present accepted papers at the workshop in order for the paper to appear in the proceedings and the ACM digital library. Exceptions from this policy for truly mitigating situations must be approved by the TPC Chairs before the beginning of the workshop.

SUBMISSION WEBSITE

https://europ4-20.hotcrp.com

WORKSHOP WEBSITE

https://p4.org/events/2020-12-01-euro-p4-workshop

WORKSHOP ORGANIZERS

General Chairs
Noa Zilberman, University of Oxford
Robert Soulé, Yale University

Program Chairs
Fernando Ramos, University of Lisbon
Gabor Retvari, Budapest University of Technology and Economics

Web and publications Chair
Salvatore Signorello, University of Lisbon

Publicity Chair
Tamas Levai, Budapest University of Technology and Economics

CONTACT

If you have any questions please email the TPC co-chairs: Fernando Ramos (fvramos@tecnico.ulisboa.pt) and Gabor Retvari (retvari@tmit.bme.hu).


Note: The Call for Paper type has not been set for this item!

Call for Papers: 3rd Workshop on Accelerated Machine Learning (AccML) at HiPEAC 2021
http://workshops.inf.ed.ac.uk/accml/
Submitted by José Cano

==================================================================
3rd Workshop on Accelerated Machine Learning (AccML)

Co-located with the HiPEAC 2021 Conference
(https://www.hipeac.net/2021/budapest/)

January 18, 2021
Budapest, Hungary

Submissions Due: November 8, 2020
==================================================================

IMPORTANT: Due to the current COVID-19 situation, HiPEAC 2021 may take place virtually

————————————————————————-
CALL FOR CONTRIBUTIONS
————————————————————————-
The remarkable performance achieved in a variety of application areas (natural language processing, computer vision, games, etc.) has led to the emergence of heterogeneous architectures to accelerate machine learning workloads. In parallel, production deployment, model complexity and diversity pushed for higher productivity systems, more powerful programming abstractions, software and system architectures, dedicated runtime systems and numerical libraries, deployment and analysis tools. Deep learning models are generally memory and computationally intensive, for both training and inference. Accelerating these operations has obvious advantages, first by reducing the energy consumption (e.g. in data centers), and secondly, making these models usable on smaller devices at the edge of the Internet. In addition, while convolutional neural networks have motivated much of this effort, numerous applications and models involve a wider variety of operations, network architectures, and data processing. These applications and models permanently challenge computer architecture, the system stack, and programming abstractions. The high level of interest in these areas calls for a dedicated forum to discuss emerging acceleration techniques and computation paradigms for machine learning algorithms, as well as the applications of machine learning to the construction of such systems.

————————————————————————-
Link to the Workshop page
————————————————————————-
http://workshops.inf.ed.ac.uk/accml/

————————————————————————-
Topics
————————————————————————-
Topics of interest include (but are not limited to):

– Novel ML systems: heterogeneous multi/many-core systems, GPUs, FPGAs;
– Software ML acceleration: languages, primitives, libraries, compilers and frameworks;
– Novel ML hardware accelerators and associated software;
– Emerging semiconductor technologies with applications to ML hardware acceleration;
– ML for the construction and tuning of systems;
– Cloud and edge ML computing: hardware and software to accelerate training and inference;
– Computing systems research addressing the privacy and security of ML-dominated systems.

————————————————————————-
Submission
————————————————————————-
Papers will be reviewed by the workshop’s technical program committee according to criteria regarding the submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions in the context of accelerating machine learning. Research papers, case studies, and position papers are all welcome.

In particular, we encourage authors to submit work-in-progress papers: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and spark productive discussions.

The workshop does not have formal proceedings.

————————————————————————-
Important Dates
————————————————————————-
Submission deadline: November 8, 2020
Notification of decision: December 4, 2020

————————————————————————-
Organizers
————————————————————————-
José Cano (University of Glasgow)
Valentin Radu (University of Sheffield)
José L. Abellán (Universidad Católica de Murcia)
Marco Cornero (DeepMind)
Albert Cohen (Google)
Dominik Grewe (DeepMind)
Alex Ramirez (Google)


Note: The Call for Paper type has not been set for this item!

Call for Papers: FCCM 2021
https://www.fccm.org/call-for-papers/
Submitted by Xinfei Guo

The 29th IEEE International Symposium On Field-Programmable Custom Computing Machines
Orlando, Florida, USA
May 9 – May 12, 2021

Submissions Due: January 11, 2021

The IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Submissions are solicited on the following topics related to Field Programmable Custom Computing Machines (FCCMs) including, but not limited to:

Architectures
– Novel reconfigurable architectures, including overlay architectures
– Architectures for high performance and/or low power computing
– Security assessment and enhancements for reconfigurable computing
– Specialized memory systems including volatile, non-volatile, and hybrid memory subsystems
– Emerging technologies with in-field reconfiguration abilities
– Clusters, data centers, or large systems of reconfigurable devices
– Heterogeneous programmable architectures
Abstractions, Programming Models, and Tools
– Abstractions, programming models, interfaces, and runtimes, including virtualization
– New languages and design frameworks for spatial or heterogeneous applications
– High-level synthesis and designer productivity in general
– Software-Defined-systems (e.g. radio, networks, frameworks for new domains)
– Customizable soft processors systems
Reconfiguration
– Run-time management of reconfigurable hardware
– System resilience/fault tolerance for reconfigurable hardware
– Evolvable, adaptable, or autonomous reconfigurable computing systems
– Security assessment and enhancement of run-time reconfiguration
Applications
– Data center or cluster with reconfigurable applications
– New uses of run-time reconfiguration in applications-specific systems
– Applications that utilize reconfigurable technology for performance and efficiency, and particularly submissions that make comparisons with other highly parallel architectures such as GPUs or DSPs
– Novel use of state-of-the-art commercial FPGAs

Submission Website:
https://easychair.org/conferences/?conf=fccm21

Important Dates:
All deadlines apply to the Anywhere on Earth (UTC – 12) timezone

Abstracts Due (All Papers)                                 January 4, 2021
Submissions Due (All Papers)                           January 11, 2021
Rebuttal Period                                                    February 8 – 12, 2021
Notification of Acceptance (All Papers)          March 8, 2021
Demo Night Submissions                                  March 22, 2021 (No Extensions)
Notification of Acceptance (Demo Night)      March 29, 2021
Camera-Ready Submission                               April 5, 2021
Early Registration Deadline                              TBD
Conference                                                            May 9 – May 12, 2021

Organizing Committee:
General Chair                                   Christophe Bobda (University of Florida)
Program Chair                                  Greg Stitt (University of Florida)
Publications Chair                           Jakub Szefer (Yale University)
Finance Chair                                   Andrew Schmidt (University of Southern California ISI)
Workshops Chair                             Laura Pozzi (USI Lugano)
Publicity and Website Chair          Xinfei Guo (NVIDIA)
Expo and Demo-Night Chair         Gabriel Weisz (Microsoft)
Panel Chair                                        Farinaz Koushanfar (UCSD)
Sponsorship Chair                            Grace Zgheib (Intel)
Local Arrangement Chair               TBD

Paper Types:
Submissions can be made for any of the three paper types:- Traditional technical papers that introduce and evaluate new technologies. These papers must have strong empirical results and must address major challenges of the corresponding problem.
– Practical papers that make significant practical contributions, including industry papers, as opposed to introducing and evaluating new technologies. For example, new tools built on existing technologies that help practitioners better use FPGAs. Practical papers will be reviewed based on significance and technical soundness of the practical contribution.
– Work-in-progress papers that present promising ideas that are too preliminary to solve all related technical challenges, but still provide some empirical data to make a convincing argument about the potential contribution after maturation.

Paper Formats:
– Long papers are limited to pages. Short papers are limited to 4 pages. The long/short formats apply to technical papers and practical papers. Work-in-progress papers are 4 pages for the initial submission, with an optional 2 additional pages after acceptance. Submissions accepted as posters will have a 1-page extended abstract.
– Page restrictions for all formats exclude references, which may use additional pages. Submissions violating the formatting requirements may be automatically rejected. Do not submit the same work as more than one of the formats.
– With the exception of work-in-progress papers, accepted papers will have the same page lengths as initial submissions. Short papers will have short oral presentations and long papers may have long or short presentations based on committee decisions on time required to present the material.
– All submissions should be written in English. An online submission link will be available on the FCCM website. Papers must conform to the US letter-sized IEEE conference proceedings format to be reviewed and published. A conformant LaTeX template is available here and a Microsoft Word template is available here. Overleaf users can find the LaTeX template here.


Note: The Call for Paper type has not been set for this item!

Call for Papers: IEEE Micro Top Picks
https://www.computer.org/digital-library/magazines/mi/call-for-papers-special-issue-on-top-picks-from-the-2020-computer-architecture-conferences
Submitted by Daniel A. Jiménez

IEEE Micro Top Picks from the 2020 Computer Architecture Conferences

Submissions Due: October 23, 2020

IEEE Micro will publish its annual “Top Picks from the Computer Architecture Conferences” issue in May/June 2021. This issue collects some of the most significant research papers in computer architecture based on novelty and potential for long-term impact. Any computer architecture paper (not a combination of papers) published in the top conferences of 2020 (including MICRO-53) is eligible. The Top Picks Selection Committee will recognize those significant and insightful papers that have the potential to influence the work of computer architects for years to come.

Submission Guidelines

To simplify reviewing, there is a mandatory format for submissions. Please upload the following two documents combined into a single PDF:

1. A three-page, two-column document using 10-point type. The first two pages should summarize the paper. The third page should argue for the potential of the work to have long-term impact, clearly articulating why and how it will influence other researchers and/or industry. On the third page, please also include what the citation of your paper would be if it won a Test of Time award in 10 years.

2. The final version of the original conference paper.

Submissions that do not follow this format will not be reviewed. The first document should contain the names of the authors with a footnote that contains the title of the original conference paper, with the full name of the conference, page numbers, and date of publication.

Paper submission site: https://toppicks2021.hotcrp.com

Important Dates

Submission website opens: September 21, 2020
Submission deadline: October 23, 2020
Author notification: January 9, 2021
Revised papers due: February 9, 2021
Publication: May/June 2021

Accepted Papers Guidelines

Authors of accepted papers will receive further instructions on how to prepare the final papers to conform to IEEE Micro‘s guidelines. Final papers should not exceed 5,000 words including references, with each average-size figure counting as 250 words toward this limit. Papers must have at least 30 percent new content compared to the original conference publication. Final papers will be edited for structure, style, clarity, and readability. Final papers will be reviewed for publication. February 9 is a hard deadline for final papers; papers received after that deadline will not be published.

Guest Editor and Selection Committee Chair

Daniel A. Jiménez, Texas A&M University (djimenez@tamu.edu)


Note: The Call for Paper type has not been set for this item!

Call for Papers: International Conference on Fog and Edge Computing (ICFEC 2021)
https://icfec2021.eeecs.qub.ac.uk/
Submitted by Antonino Galletta

5TH IEEE INTERNATIONAL CONFERENCE ON FOG AND EDGE COMPUTING (ICFEC 2021)
In conjunction with IEEE/ACM CCGrid 2021
May 10-13, 2021
Melbourne, Australia

Submissions Due: January 3, 2021

URL: https://icfec2021.eeecs.qub.ac.uk

We are delighted to invite you for the 5th IEEE International Conference on Fog and Edge Computing to be held in Melbourne, Australia. The conference will be held as part of and in conjunction with IEEE/ACM CCGrid 2021, which is sponsored by the IEEE Computer Society and ACM.

INTRODUCTION

Billions of devices and sensors ranging from user gadgets to more complex systems with sensing and actuating capabilities, such as power grids or vehicles, from the physical world are getting connected to the Internet. However, the need to operate the scale of heterogeneous devices and sensors while being performance-efficient in real-time is challenging. Typically, the data generated by the devices and sensors are transferred to and processed centrally by services hosted on geographically distant clouds. This is untenable given the communication latency incurred and the ingress bandwidth demand.

A new and disruptive paradigm spear-headed by academics and industry experts is taking shape so that applications can leverage resources located at the edge of the network and along the continuum between the cloud and the edge. These edge resources may be geographically or in the network topology be closer to devices and sensors, such as home router, gateways or more substantial micro data centers. Edge resources may be used to offload selected services from the cloud to accelerate an application or host edge-native applications. The paradigm within which the edge is harnessed is referred to as ‘Fog/Edge computing’.

The Fog/Edge computing paradigm is expected to improve the agility of service deployments, make use of opportunistic and cheap computing, and leverage the network latency and bandwidth diversities between these resources. Numerous challenges arise when using edge resources, which requires the re-examination of operating systems, virtualization and containers, and middleware techniques for fabric management. Extensions to current programming and storage models are required and new abstractions that will allow developers to design novel applications that can benefit from massively distributed and data-driven systems need to be developed. Addressing security, privacy and trust of the edge resources is of paramount importance while managing the resources and context for mobile, transient and hardware constrained resources. Lastly, emerging domains like autonomous vehicles and machine/deep learning need to be supported over such platforms.

CALL FOR PAPERS

The conference seeks to attract high-quality contributions covering both theory and practice over system software and domain-specific applications related to next-generation distributed systems that use the edge. Some representative topics of interest include, but are not limited to:

* Data centers and infrastructures for Fog/Edge computing
* Middleware and runtime systems for Fog/Edge infrastructures
* Programming models for Fog/Edge computing
* Storage and data management platforms for Fog/Edge computing
* Scheduling for Fog/Edge infrastructures
* Distributed and federated machine learning on Fog/Edge
* Performance monitoring and metering of Fog/Edge infrastructures
* Legal issues and business aspects of Fog/Edge computing
* Security, privacy, trust and provenance issues in Fog/Edge computing
* Modeling and simulation of Fog/Edge environments
* Novel, latency-sensitive and locality-critical applications of Fog/Edge computing

SUBMISSION INSTRUCTIONS

We invite original manuscripts that have neither been published elsewhere nor are under review at a different venue. The manuscripts should be structured as technical papers, written in English. Authors should submit papers electronically in PDF format and may not exceed 8 letter-size pages in length, including all figures, tables and references. Papers should follow the IEEE format template for conference proceedings available at http://www.ieee.org/conferences_events/conferences/publishing/templates.html. Submissions not conforming to these guidelines or received after the due date may not be reviewed. All manuscripts will be reviewed and judged on originality, technical strength, significance, quality of presentation, and relevance to the conference attendees.

Papers may be submitted online at https://www.easychair.org/conferences/?conf=icfec2021

IMPORTANT DATES

* Papers due: 03 January 2021 23:59 AoE
* Author notifications of Acceptance: 08 February 2021
* Camera Ready Paper: 03 March 2021

PUBLICATION

Papers that are accepted for publication may be accepted as REGULAR paper (8 pages) or SHORT papers (5 pages), depending on the reviewer recommendations. Accepted papers will be included in the conference proceedings that will be published through the IEEE Computer Society Conference Publishing Services.

ORGANIZATION

General Chairs
* Rajkumar Buyya, University of Melbourne, Australia
* Yogesh Simmhan, Indian Institute of Science, India

Program Chairs
* Blesson Varghese, Queen’s University Belfast, UK, b.varghese@qub.ac.uk
* Lena Mashayekhy, University of Delaware, USA, mlena@udel.edu


Note: The Call for Paper type has not been set for this item!

Call for Papers: IoTSMS 2020
https://emergingtechnet.org/IOTSMS2020/
Submitted by Marco Guazzone

7th International Conference on Internet of Things: Systems, Management and Security
Paris, France. December 14-16, 2020

URL: https://emergingtechnet.org/IOTSMS2020/

Submissions Due: 20 August 2020 (extended)

IMPORTANT DATES
* Submission Date: 20 August 2020 (extended)
* Notification to Authors: 10 October 2020
* Camera Ready Submission: 1 November 2020

The Internet of Things (IoT) technology offers unprecedented opportunities to interconnect human beings as well as Machine-to-Machine (M2M), whereby sensors and networks allow all ‘things’ to communicate directly with each other to share vital information allowing us to have an instrumented universe where accurate data is readily available to inform optimal decision making. The IoT is about to enable a range of new capabilities and services far beyond today’s offerings. It will fundamentally change how people go about their lives. According to Gartner, the number of objects connected to the Internet is set to reach 20 billion by 2020. Cisco estimates the number will be close to 26 billion objects by 2020. Others believe the actual number will be even higher with the assumption that any object with a simple micro controller and on-off switch will be connected to the Internet in the near feature. The scale of the IoT is set to have a major economic, social and environmental impacts; the intersection of which forms the future sustainable growth.

The international conference on Internet of Things: Systems, Management and Security (IoTSMS) aims at soliciting original ideas on the broad area of IoT including challenges and opportunities, concepts and applications and future trends. The IoTSMS aims to facilitate discussions among academics and IoT practitioners and make positive contributions to the field.

TOPICS OF INTERESTS
* Emerging concepts of IoT Systems
* Architectures of IoT systems
* Machine-to-Machine Communication and IoT
* Modeling of IoT applications
* SDN and NFV support for IoT applications and Systems
* Fog and Edge support for IoT Applications
* 5G support for IoT Applications
* IoT for Smart Cities
* Energy management in IoT
* Design methodologies for IoT
* Novel services and applications of IoT to facilitate environmental responsibility
* Green by Internet of Things
* IoT and Social benefits/impact
* IoT Economics and Business Models
* Emerging Internet of Things business models and process changes
* Communication systems and network architectures for the IoT
* IoT and Data Management
* Security and privacy of IoT
* Reliability of IoT
* Disaster recovery in IoT
* Applications of Internet of things
* Emerging applications and interaction paradigms for everyday citizens
* Big data and IoT
* Self-organizing IoT
* Cloud Computing and IoT
* IoT and sustainable Growth

PUBLICATION
All accepted papers will appear in the conference proceedings and will be published by IEEE and included in the IEEE Xplore digital library.

GENERAL CHAIRS
* Abdelhakim Hafid Senhadji, University of Montreal, Canada.
* Francisco Falcone, Universidad Publica de Navarra, Spain.

PROGRAM CHAIRS
* Attila Kertesz <keratt@inf.u-szeged.hu>
* Marco Guazzone <marco.guazzone@uniupo.it>


Call for Workshops/Tutorials: HPCA 2021 Workshop/Tutorial
https://hpca-conf.org/2021/workshop-tutorial-cfp
Submitted by Wenwen Wang

The 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA-27)
Online Event
February 27– March 3, 2021

Submissions Due: October 23, 2020

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field.

We are seeking proposals for workshops and tutorials on Saturday and Sunday before the main conference. Workshops and tutorials may be scheduled for a half day or a full day.

Workshops/tutorials are to be held virtually February 27–28, 2021.

PDF version

Proposals should be one to two pages and must include the following information:

  • Title of the workshop/tutorial
  • Organizers and their affiliations (including short bios)
  • Expected duration of the workshop/tutorial; i.e., half day or full day
  • If the workshop/tutorial was previously held, provide the location (i.e., which conference), date, number of published papers (if any), and number of attendees at the last event
  • If workshop proposal, provide sample call for papers, including the workshop main topics
  • If tutorial proposal, provide the abstract of the tutorial

Submit workshop and tutorial proposals (1 to 2 pages) to wt.hpca2021@gmail.com

** Important Dates **
Submission deadline: October 23, 2020
Notification date: November 25, 2020


Call for Posters: 6th Career Workshop for Women and Minorities in Computer Architecture
https://www.colorado.edu/conference/cwwmca/
Submitted by Dimitrios Skarlatos

6th Career Workshop for Women and Minorities in Computer Architecture
In conjunction with the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO-53)
October 17, 2020

Submissions Due: September 20, 2020

https://www.colorado.edu/conference/cwwmca/

Call for Posters:

The MICRO Career Workshop will bring together women and under-represented minorities at different levels in academia, industry, research, government and students to promote the recruitment, retention and progression of women and under-represented groups with research interests in computer architecture.

The workshop will highlight emerging and hot topics in computer architecture, but also provide opportunities for cross-disciplinary research, networking, and career advice and mentoring. The workshop will contain a mix of technical presentations and panel sessions given by academic and industry leaders as well as a special session to provide mentoring for students as they get started in their careers.

The workshop will include a student research poster session, career panels, advice on careers in academia, industry research, government, or deciding to start your own company, and a mentoring session. Keynotes and invited talks will cover the latest research trends in computer architecture.

To encourage participation, we will reimburse workshop registration for participants.

Important Dates:

* Abstract Submission Deadline: September 20, 2020
* Author Notification: September 25, 2020
* Workshop Date: October 17, 2020

Submission Guidelines:

Each submission should be formatted as an extended abstract, describing the research to be presented in the poster. The length of the extended abstract should be at most TWO single-column pages (formatted into the US letter size of 8.5 x 11 inches with fonts no smaller than 10 point size), including all figures and references. The extended abstract must include the names, affiliations and email addresses of all authors and should be submitted as a single PDF file to EasyChair:

https://easychair.org/conferences/?conf=cwwmca2020

Organizing Committee:

Valentina Salapura, AMD Research
Zehra Sura, Bloomberg L.P.
Tamara Lehman, University of Colorado Boulder
Hyeran Jeon, UC Merced
Alan Bivens, IBM Public Cloud


Call for Posters: 6th Career Workshop for Women and Minorities in Computer Architecture
https://www.colorado.edu/conference/cwwmca/
Submitted by Hyeran Jeon

6th Career Workshop for Women and Minorities in Computer Architecture
In conjunction with the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO-53)
Athens, Greece (or virtual)
October 17, 2020

Submissions Due: September 6, 2020

https://www.colorado.edu/conference/cwwmca/

Call for Posters:

The MICRO Career Workshop will bring together women and under-represented minorities at different levels in academia, industry, research, government, and students to promote the recruitment, retention and progression of women and under-represented groups with research interests in computer architecture.

The workshop will highlight emerging and hot topics in computer architecture, but also provide opportunities for cross-disciplinary research, networking, and career advice and mentoring. The workshop will contain a mix of technical presentations and panel sessions given by academic and industry leaders as well as informal activities to provide mentoring for students as they get started in their careers.

The workshop will include a student research poster session, career panels, advice on careers in academia, industry research, government, or deciding to start your own company, and a speed mentoring session. Keynotes and invited talks will cover the latest research trends in computer architecture.

Important Dates:

  • Abstract Submission Deadline: September 6, 2020
  • Author Notification: September 20, 2020
  • Workshop Date: October 17, 2020

Submission Guidelines:

Each submission should be formatted as an extended abstract, describing the research to be presented in the poster. The length of the extended abstract should be at most TWO single-column pages (formatted into the US letter size of 8.5 x 11 inches with fonts no smaller than 10 point size), including all figures and references. The extended abstract must include the names, affiliations and email addresses of all authors and should be submitted as a single PDF file to EasyChair:

https://easychair.org/conferences/?conf=cwwmca2020

Organizing Committee:

Valentina Salapura, AMD Research
Zehra Sura, Bloomberg L.P.
Tamara Lehman, University of Colorado Boulder
Hyeran Jeon, University of California, Merced
Alan Bivens, IBM Public Cloud


EuroSys Shadow PC: Call for Applications
https://2021.eurosys.org/shadow-pc.html#shadow-pc
Submitted by Boris Grot

Eurosys is organizing a shadow program committee for the EuroSys 2021 conference under the sponsorship of EuroSys. If you are interested in participating, please apply online at https://eurosys21shadowpc-apps.hotcrp.com/ before September 18, 2020. You will be requested to complete the application form, and attach your CV. Please also get in touch if you have any questions at shadow-2021@eurosys.org.

WHY JOIN A SHADOW PC?
Serving on a shadow PC is an excellent opportunity for young systems researchers (PhD students, postdocs, and new faculty members) to gain experience in community service, i.e., program committee practices.

Serving as a member of a shadow PC is a lot of work. But, besides the recognition of being selected, it is also worthwhile for a number of reasons, including:
– Getting to know how an academic PC is run and how it operates;
– Seeing how more experienced reviewers judge the same papers that you review;
– Getting to see both strong and weak papers at the submission stage;
– Discovering what it takes to publish a paper in a highly selective conference, such as EuroSys;
– Having a chance to read top-notch papers in your area of expertise before they are published;
– Getting to know other young researchers who are also selected to the shadow PC.

HOW DOES THE SHADOW PC WORK?
Shadow PC members must commit themselves to writing their own detailed and rigorous reviews for papers assigned to them by the allotted deadlines. This timely review commitment is essential to the good functioning of the Shadow PC. Candidates who might be unable to fulfill their reviewing duties should refrain from applying. We expect a review load of 10-15 papers per member in two review rounds. Members will not be expected to take part in the revision stage. Shadow PC members are also expected to attend a one-day online shadow PC meeting. The EuroSys shadow PC will follow roughly the same timeline as the main PC. We plan to have the shadow PC meeting close in time to the main PC meeting (foreseen in the week of January 13, 2021).

SUBMISSION WEBSITE:
Submit your application at: https://eurosys21shadowpc-apps.hotcrp.com/

ORGANIZERS:
Costin Raiciu (Universitatea Politehnica București)
Noa Zilberman (University of Oxford)

IMPORTANT DATES (All times are Anywhere on Earth):
Deadline to apply for shadow PC: 18 September 2020
Paper Submission: 9 October 2020
1st round of reviews due (tentative): 30 November 2020
Online discussions: 30 November – 4 December 2020
2nd round of reviews due (tentative): 5 January 2021
Online discussions: 6-12 January 2021
Online shadow PC meeting: Week of 13th January 2021
Main conference program: 27-29 April 2021

CONTACT:
For any further information, please contact the shadow PC chairs: shadow-2021@eurosys.org


New Book – Data Orchestration in Deep Learning Accelerators
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=1567
Submitted by Brent Beckley

Morgan & Claypool is proud to announce a recently published book in our Computer Architecture series.

Data Orchestration in Deep Learning Accelerators

Tushar Krishna, Georgia Institute of Technology
Hyoukjun Kwon, Georgia Institute of Technology
Angshuman Parashar, NVIDIA
Michael Pellauer, NVIDIA
Ananda Samajdar, Georgia Institute of Technology

ISBN: 9781681738697 | PDF ISBN: 9781681738703
Hardcover ISBN: 9781681738710
Copyright © 2020 | 164 Pages

This Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. The End of Moore’s Law, coupled with the increasing growth in deep learning and other AI applications has led to the emergence of custom Deep Neural Network (DNN) accelerators for energy-efficient inference on edge devices. Modern DNNs have millions of hyper parameters and involve billions of computations; this necessitates extensive data movement from memory to on-chip processing engines. It is well known that the cost of data movement today surpasses the cost of the actual computation; therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM. The book covers DNN dataflows, data reuse, buffer hierarchies, networks-on-chip, and automated design-space exploration. It concludes with data orchestration challenges with compressed and sparse DNNs and future trends. The target audience is students, engineers, and researchers interested in designing high-performance and low-energy accelerators for DNN inference.


2nd edition of “A Primer on Memory Consistency and Cache Coherence” now Open Access
https://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=1503
Submitted by Dan Sorin

A Primer on Memory Consistency and Cache Coherence, Second Edition

Vijay Nagarajan, University of Edinburgh,
Daniel J. Sorin, Duke University,
Mark D. Hill, University of Wisconsin, Madison,
David A. Wood, University of Wisconsin, Madison

This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.


MICRO-53: Global Online Event, October 17-21, 2020
https://www.microarch.org/micro53/
Submitted by Dimitrios Skarlatos

53rd IEEE/ACM International Symposium on Microarchitecture (MICRO-53)

17-21 October 2020, Global Online Event

https://www.microarch.org/micro53/

Until science and technology free humanity from the stress and the consequences of the pandemic, we will have to keep using science and technology to meet with our colleagues and share our research results only online. Our research community is looking forward to the time when we will be able again to meet in person, see each other’s eyes, chat over coffee, and debate over wine.

 

The MICRO 2020 symposium will be held as a global online event, to allow everyone from around the world to participate and enjoy the experience. Details about the technical program and the registration and participation procedures will be announced during the coming weeks. The committees of MICRO 2020 wish you are all staying well and safe.

 

On behalf of the steering and organizing committees of MICRO 2020,

—Dimitris Gizopoulos, General Chair

Jun Yang and Mattan Erez, Program Co-Chairs


New Book – Quantum Computer Systems
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=1550
Submitted by Brent Beckley

Morgan & Claypool is proud to announce a recently published book in our Computer Architecture series.

Quantum Computer Systems
Research for Noisy Intermediate-Scale Quantum Computers

Yongshan Ding, University of Chicago
Frederic T. Chong, University of Chicago

ISBN: 9781681738666 | PDF ISBN: 9781681738673
Hardcover ISBN: 9781681738680
Copyright © 2020 | 227 Pages

This book targets computer scientists and engineers who are familiar with concepts in classical computer systems but are curious to learn the general architecture of quantum computing systems. It gives a concise presentation of this new paradigm of computing from a computer systems’ point of view without assuming any background in quantum mechanics. As such, it is divided into two parts. The first part of the book provides a gentle overview on the fundamental principles of the quantum theory and their implications for computing. The second part is devoted to state-of-the-art research in designing practical quantum programs, building a scalable software systems stack, and controlling quantum hardware components. Most chapters end with a summary and an outlook for future directions. This book celebrates the remarkable progress that scientists across disciplines have made in the past decades and reveals what roles computer scientists and engineers can play to enable practical-scale quantum computing.

Find the book.


New Book – Efficient Processing of Deep Neural Networks
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=1530
Submitted by Brent Beckley

Morgan & Claypool is proud to announce a recently published book in our Computer Architecture series.

Efficient Processing of Deep Neural Networks

Vivienne Sze, Massachusetts Institute of Technology
Yu-Hsin Chen, Massachusetts Institute of Technology
Tien-Ju Yang, Massachusetts Institute of Technology
Joel S. Emer, Massachusetts Institute of Technology, Nvidia Research

ISBN: 9781681738314 | PDF ISBN: 9781681738321 | Hardcover ISBN: 9781681738352
Copyright © 2020 | 341 Pages

This book provides a structured treatment of the key principles and techniques for enabling efficient processing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Therefore, techniques that enable efficient processing of deep neural networks to improve metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems.

The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of the DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as a formalization and organization of key concepts from contemporary works that provides insights that may spark new ideas.

Find the book.


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Samira Khan
SIGARCH Content Editor

Top