This is the 1st December 2018 digest of SIGARCH Messages.

In This Issue


Call for Nominations: HPCA Test of Time Award
http://ieeetcca.org/awards/hpca-test-of-time-award/
Submitted by David Kaeli

HPCA Test of Time Award 2019

Deadline for nominations: December 1, 2018.

Please visit http://ieeetcca.org/awards/hpca-test-of-time-award for details.

For questions, contact David Kaeli (kaeli@ece.neu.edu).


Call for Papers: ARCS 2019
http://arcs2019.itec.kit.edu/
Submitted by Sascha Uhrig

32nd GI/ITG International Conference on Architecture of Computing Systems (ARCS)
Copenhagen, Denmark
May 20-23, 2019

IMPORTANT DATES:
Paper submission deadline: December 10, 2018
Notification: February 14, 2019
Final paper version: March 1, 2019
Conference: May 20-23, 2019

The ARCS conferences series has over 30 years of tradition reporting leading edge research in computer architecture and operating systems. The focus of the 2019 conference will be on architectures for complex real-time systems like autonomous control systems, as well as safety and security critical systems. This includes upcoming architectures and technologies, exploitable architectural features, languages, and tooling.

The proceedings of ARCS 2019 will be published in the Springer Lecture Notes on Computer Science (LNCS) series. A best paper and best presentation award will be presented at the conference.

Authors are invited to submit original, unpublished research papers on one or more of the following topics:

1) Hardware Architectures
– System-on-chip
– Distributed systems
– High performance systems
– Heterogeneous multi- and many-core architectures
– Architectures for real-time and mixed-criticality systems
– Coarse- and fine-grained reconfigurable architectures
– Flexible I/O support
– Advanced computing architectures

2) Programming models and runtime environments
– Programming models for many-core and/or heterogeneous computing platforms.
– Operating systems, hypervisors and middleware for homogeneous and heterogeneous multi-/many-core computing platforms.
– System management including but not limited to scheduling, memory management, power/thermal management, and RTOS.

3) Cross-sectional topics
– Adaptive systems (energy aware, self-x technologies)
– Pervasive systems
– Approximate Computing
– Autonomous systems
– Support for safety and security

SUBMISSION GUIDELINES:
All submitted manuscripts must conform to the Springer LNCS formatting requirements (https://www.springer.com/gp/computer-science/lncs/conference-proceedings-guidelines) and must not exceed 12 pages, including references and figures.
Manuscripts must be submitted online via EasyChair via the following link: https://easychair.org/conferences/?conf=arcs2019

ORGANIZERS:
General Chairs:
Martin Schoeberl, Technical University of Denmark, Lyngby, Denmark
Christian Hochberger, Technical University of Darmstadt, Germany

Program Chairs:
Sascha UHRIG, Airbus, Ottobrunn, Germany
Juergen Brehm, University of Hannover, Germany

Workshop and Tutorial Chair:
Carsten Trinitis, TU Munich, Germany

Publication Chair:
Thilo Pionteck, University of Magdeburg, Germany

Technical Program Committee:
Hamid Amiri, ENIT
Mladen Berekovic, C3E, Technical University of Braunschweig
Juergen Brehm, University of Hannover
Uwe Brinkschulte, University of Frankfurt
Rainer Buchty, Technical University of Braunschweig
Joao Cardoso, University of Porto
Laura Carrington, San Diego Supercomputer Center/University of California, San Diego
Martin Danek, daiteq s.r.o.
Nikitas Dimopoulos, University of Victoria
Ahmed El-Mahdy, Egypt-Japan University of Science and Technology (E-JUST)
Dietmar Fey, Friedrich-Alexander-University of Erlangen-Nuremberg
William Fornaciari, Politecnico di Milano
Roberto Giorgi, University of Siena
Daniel Gracia Pérez, Thales Research & Technology
Jan Haase, University of Luebeck
Joerg Haehner, University of Augsburg
Heiko Hamann, University of Luebeck
Andreas Herkersdorf, Technical University of Munich
Christian Hochberger, Technical University of Darmstadt
Gert Jervan, Tallinn University of Technology
Ben Juurlink, Technical University of Berlin
Wolfgang Karl, Karlsruhe Institute of Technology
Joerg Keller, FernUniversitaet in Hagen
Andreas Koch, Technical University of Darmstadt
Dirk Koch, University of Manchester
Hana Kubatova, FIT CTU in Prague
Erik Maehle, University of Luebeck
Alex Orailoglu, University of California San Diego
Luis Miguel Pinho, CISTER Research Centre/ISEP
Juergen Mottok, Ostbayerische Technische Hochschule Regensburg, Germany
Thilo Pionteck, Otto-von-Guericke Universitaet Magdeburg
Pascal Sainrat, IRIT – University of Toulouse
Luca Santinelli, ONERA
Toshinori Sato, Fukuoka University
Martin Schoeberl, Technical University of Denmark
Wolfgang Schroeder-Preikschat, Friedrich-Alexander-University of Erlangen-Nuremberg
Martin Schulz, Technical University of Munich
Muhammad Shafique, Technical University of Vienna
Leonel Sousa, University of Lisbon
Benno Stabernack, Fraunhofer Institut fuer Nachrichtentechnik Heinrich Hertz
Walter Stechele, Technical University of Munich
Juergen Teich, Friedrich-Alexander-University of Erlangen-Nuremberg
Sven Tomforde, University of Kassel
Eduardo Tovar, Polytechnic Institute of Porto
Carsten Trinitis, Technical University of Munich
Nicolas Tsiftes, RISE SICS
Sascha Uhrig, Airbus Central Research and Technology
Theo Ungerer, University of Augsburg
Hans Vandierendonck, Queen’s University Belfast
Stephane Vialle, CentraleSupelec, Univ. Paris-Saclay
Lucian Vintan, “Lucian Blaga” University of Sibiu
Klaus Waldschmidt, Goethe University Frankfurt/Main
Dominic Wist, Biotronik, Berlin, Germany
Stephan Wong, Technical University of Delft
Sungjoo Yoo, Seoul National University
(to be completed)


Call for Papers: ISVLSI 2019
http://www.eng.ucy.ac.cy/theocharides/isvlsi19/ISVLSI2019_CFP.pdf
Submitted by Domenic Forte

IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Miami, Florida, USA
July 15-17, 2019

The IEEE Symposium on VLSI (ISVLSI) 2019 explores emerging trends, novel ideas and basic concepts covering a broad range of VLSI-related topics: from VLSI systems, tools and design methods at different abstraction levels, to bringing VLSI design and methods into new technologies such as nano and molecular devices and burgeoning application areas, such as hardware security, and artificial intelligence. Future design methodologies are also one of the key topics at the symposium, as well as new EDA tools to support them. Over three decades ISVLSI has been a unique forum promoting multidisciplinary research and new visionary approaches in the area of VLSI, bringing together leading scientists and researchers from academia and industry. The ISVLSI proceedings will be published by IEEE Computer Society Press. Selected papers from past editions have been subsequently published in special issues of top archival journals. ISVLSI has a good reputation of bringing together well-known international scientists as invited speaks. ISVLSI 2019 will continue the momentum and carry forward these well-established trends for further growth of the symposium.

Contributions are sought in the following tracks:
1) Circuits, Reliability, and Fault-Tolerance (CRT): Analog/mixed-signal circuits design and testing, RF and communication circuits, design for testability and reliability, adaptive circuits, interconnects, static and dynamic defect-and fault-recoverability, and variation-aware design.
2) Computer-Aided Design and Verification (CAD): Hardware/software co-design, logic and behavioral synthesis, simulation and formal verification, physical design, signal integrity, power and thermal analysis, statistical approaches.
3) Digital Circuits and FPGA based Designs (DCF): Digital circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits, energy efficient circuits, near and sub-threshold circuits, memories, FPGA designs, FPGA based systems.
4) Emerging and Post-CMOS Technologies (EPT): Nanotechnology, molecular electronics, quantum devices, optical computing, spin-based computing, biologically-inspired computing, CNT, SET, RTD, QCA, reversible logic, and CAD tools for emerging technology devices and circuits.
5) System Design and Security (SDS): Structured and Custom Design methodologies, microprocessors/micro-architectures for performance and low power, embedded processors, analog/digital/mixed-signal systems, NoC, power and temperature aware designs, Hardware security, Cryptography, watermarking, and IP protection, TRNG and security oriented circuits, PUF circuits.
6) VLSI for Applied and Future Computing (AFC): Neuromorphic and brain-inspired computing, quantum computing, circuits and architectures for machine learning and artificial intelligence, methodologies for on-chip learning, deep learning acceleration techniques, applications for and use-cases of learning systems, sensor and sensor network, electronics for Internet of Things and smart medical devices.

The Symposium Program will include contributed papers and speakers invited by the Program Committee as well as a poster session. The keynotes, special sessions and Graduate Student Forum are planned as well. Authors are invited to submit full-length, original, unpublished papers. To enable blind review, the author list should be omitted from the main document.

SUBMISSION GUIDELINES:
Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. To enable blind review, the author list should be omitted from the main document. Papers violating length and blind-review criteria would be withdrawn from the review process. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered for publication.

Paper Submission Site: https://easychair.org/conferences/?conf=isvlsi2019


Call for Papers: Embedded Systems Week 2019
https://www.esweek.org
Submitted by Lars Bauer

Embedded Systems Week (ESWEEK)
New York City, USA,
October 13 – 18, 2019

Embedded Systems Week (ESWEEK) is the premier event covering all aspects of embedded systems and software. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), a special IoMT Day, a symposium (NOCS), and hot-topic workshops and tutorials, ESWEEK presents attendees a wide range of topics unveiling the state of the art in embedded systems design and HW/SW architectures.

Registered attendees are entitled to attend sessions of all conferences CASES, CODES+ISSS, EMSOFT, and the IoMT Day. Symposia, workshops, and tutorials require separate registration.

IMPORTANT DATES:
Journal Track:
– Abstract Submission: April 5, 2019
– Full Paper Submission: April 12, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Work-in-Progress Track:
– Paper Submission: June 7, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Workshop Proposals: April 18, 2019
Tutorial Proposals: April 30, 2019
Special Session Proposals: April 30, 2019

SUBMISSION GUIDELINES:
ESWEEK 2019 continues a dual publication model comprising the Journal track and the Work-in-Progress (WiP) track. Journal track papers, which are full-length (10-page) papers describing mature work, will be published in the ACM Transactions on Embedded Computing Systems (TECS). The WiP track papers, which are short (2-page) papers representing not-yet-mature but promising research, will be published in the ESWEEK proceedings and will be listed as regular publications within the IEEE and/or ACM digital libraries. Authors of WiP papers have the opportunity to publish the extended form of their work in any conference or journal they prefer. Journal and WiP papers are mutually exclusive, i.e., a work can only be in submission in one of the two tracks.
For more information, please refer to: https://www.esweek.org/author-information

* CASES: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
CASES is a premier forum where researchers, developers and practitioners exchange information on the latest advances in compilers and architectures for high-performance, low-power embedded systems. The conference has a long tradition of showcasing leading edge research in embedded processor, memory, interconnect, storage architectures and related compiler techniques targeting performance, power, predictability, security, reliability issues for traditional and emerging applications. In addition, we invite innovative papers that address design, synthesis, and optimization in heterogeneous and accelerator-rich architectures.
https://esweek.org/sites/default/files/2019-CASES-cfp_0.pdf

CASES Program Chairs:
Akash Kumar, Technical University of Dresden, DE
Partha Pande, Washington State University, US

* CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis
The International Conference on Hardware/Software Codesign and System Synthesis is the premier event in system-level design, modeling, analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hardware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design. High-quality original papers will be accepted for oral presentation followed by interactive poster sessions.
https://esweek.org/sites/default/files/CODES%2BISSS-2019-CFP.pdf

CODES+ISSS Program Chairs:
Sudeep Pasricha, Colorado State University, US
Roman Lysecky, Arizona State University, US

* EMSOFT: International Conference on Embedded Software
The ACM SIGBED International Conference on Embedded Software (EMSOFT) brings together researchers and developers from academia, industry, and government to advance the science, engineering, and technology of embedded software development. Since 2001, EMSOFT has been the premier venue for cutting-edge research in the design and analysis of software that interacts with physical processes, with a long-standing tradition for results on cyber-physical systems, which compose computation, networking, and physical dynamics.
https://esweek.org/sites/default/files/EMSOFT2019_CfP_0.pdf

EMSOFT Program Chairs:
Sriram Sankaranarayanan, University of Colorado Boulder, US
Timothy Bourke, Inria Paris, FR

* IoMT: Internet of Medical Things
The Internet of Medical Things (IoMT) paves the foundations for intelligent and reliable personalized precision medicine. Grounded in the mathematical and physical modeling of human anatomy and physiology, it offers accurate multiscale medical monitoring through smart sensing, enabling continuous diagnosis via on-fly communication with medical experts. It provides hyperspectral and hyperdimensional processing and restores health through patient-specific actuation. The IoMT special day provides a forum for academic and industry representatives from areas such as medical and bio-engineering and embedded systems to discuss innovative ideas and solutions for precise personalized medicine. Sub-missions to the IoMT day are via the three conferences.
https://esweek.org/iomt/about

IoMT Chairs:
Insup Lee, University of Pennsylvania, US
Paul Bogdan, University of Southern California, US

* Call for Workshop Proposals
ESWEEK 2019 will host several workshops on Oct. 17/18th. ESWEEK workshops are excellent opportunities to bring together researchers and practitioners from different communities to share their experiences in an interactive atmosphere.
We invite you to submit workshop proposals on any topic related to the broad set of research, education, and application areas in embedded systems before the deadline of April 18, 2019.
https://esweek.org/sites/default/files/ESWEEK2019_CfP_1.pdf

Workshop Chair:
Laura Pozzi, USI Lugano, CH

* Call for Tutorial Proposals
ESWEEK 2019 is looking for high-quality tutorials that will take place on Oct. 13th. Tutorials offer a unique opportunity where presenters can interact with attendees and attendees can gain in-depth knowledge on specific topics. Tutorials on all topics related to embedded system design, analysis and development are welcome and can be either half or full day, lecture style or hands on.
We invite you to submit tutorial proposals before the deadline of April 30, 2019.

* Call for Special Session Proposals
ESWEEK 2019 will host several special sessions. They should cover hot, contemporary topics that are complementary to regular sessions and can constitute individual presentations, panels or other formats. Participants of each accepted special session will have the opportunity to co-author an overview paper (maximum 10 pages) of the session, published in the ESWEEK proceedings. We invite you to submit special session proposals on any topic related to the broad areas of interest of the conference or beyond before the deadline of April 30, 2019.
https://esweek.org/sites/default/files/ESWEEK2019_CfP_1.pdf

Tutorials and Special Sessions Chair:
Andreas Gerstlauer, University of Texas Austin, US

ESWEEK ORGANIZERS:
Petru Eles, Linköping University, SE
Tulika Mitra, National University of Singapore, SG (Vice General Chair)
Soonhoi Ha, Seoul National University, KR (Past Chair)

ESWEEK Local Arrangement Chairs:
Ramesh Karri, New York University, US
Siddarth Garg, New York University, US

www.esweek.org


Call for Papers: GPGPU 2019
https://insight-archlab.github.io/gpgpu.html
Submitted by Ashutosh Pattnaik

12th Workshop on General Purpose Processing Using GPU (GPGPU 2019)
in conjunction with ASPLOS 2019
Providence, RI, USA
April 13, 2019

IMPORTANT DATES:
Papers due: January 21, 2019
Notification: February 18, 2019
Final paper due: March 1, 2019

The goal of this workshop is to provide a forum to discuss new and emerging general-purpose programming architectures, environments, and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. This year’s workshop is particularly interested in security, new heterogeneous architecture or platforms, new forms of concurrency, and novel or irregular applications that can leverage these platforms.

Papers are being sought on many aspects of GPUs or accelerators, including (but not limited to):
– GPU applications
– GPU programming environments
– GPU runtime systems
– GPU compilation
– GPU architectures
– Multi-GPU systems
– GPU power/efficiency
– GPU reliability
– GPU benchmarking/measurements
– Heterogeneous architectures/platforms
– GPU security (NEW)
– Non-von Neumann architectures (NEW)
– Domain-specific architectures (NEW)

SUBMISSION GUIDELINES:
Full paper submissions must be in PDF format for US letter-size paper. They must not exceed 10 pages (all inclusive) in standard ACM two-column conference format (preprint mode, with page number). Templates for ACM format are available for Microsoft Word, and LaTeX can be found here. The submission site will be up soon.

ORGANIZERS:
Adwait Jog (co-chair), College of William & Mary
Onur Kayiran (co-chair), AMD Research
Ashutosh Pattnaik (submission/web chair), Penn State

Please contact the organizers if you have any questions.

HISTORY AND IMPACT
David Kaeli (Northeastern) and John Cavazos (Delaware) very successfully organized the previous versions of the GPGPU workshop. GPGPU workshop was first held in 2007 at Northeastern University. In 2008, the meeting was held with ASPLOS 2008. This trend continued and the GPGPU workshop was held with ASPLOS for the next 6 years. From 2015 and 2018, GPGPU workshop was co-located with PPoPP. GPGPU 2019 workshop returns to ASPLOS. The average citation count (as per Google Scholar), for a GPGPU workshop paper, is currently 37.5, where there have been 8 influential papers with 100+ citations.


Call for Papers: SELSE 2019
https://www.selse.org/
Submitted by Michael Sullivan

The 15th IEEE Workshop on Silicon Errors in Logic – System Effects
Stanford, Palo Alto, CA, USA
March 27 – March 28, 2019

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high-performance applications.

The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.

We are happy to announce that selected SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Portland, Oregon on June 24 – 27, 2019.

Key areas of interest include (but are not limited to):
– Error rates and trends in current and emerging technologies, including experimental failure data and the reliability characterization of deployed systems.
– New error mitigation techniques, robust software frameworks, and error handling protocols for resilient system design.
– Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.
– Resilience characterization and strategies for machine learning applications, including autonomous vehicles.
– Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.
– The design of resilient systems for space exploration.
– The interplay between system security issues and reliability.

SUBMISSION GUIDELINES:
Additional information and guidelines for submission are available at http://www.selse.org. Submissions and final papers should be PDF files following the IEEE two-column transactions format with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries—however, they are distributed to attendees of the workshop.


Call for Papers: Workshop on Accelerator Architecture in Computational Biology and Bioinformatics
https://aacbb-workshop.github.io/
Submitted by Dr. Leonid Yavits

2nd Accelerator Architecture in Computational Biology and Bioinformatics workshop (AACBB)
in conjunction with HPCA 2019
Washington DC, USA
February 16-20, 2019

IMPORTANT DATES:
Submission: December 25, 2018, AoE (postponed)
Notification: December 28, 2018

Over the last decade, the advent of high-throughput sequencing techniques brought an exponential growth in biosequence database sizes. With increased throughput demand and popularity of computational biology tools, reducing time-to-solution during computational analysis has become a significant challenge in the path to scientific discovery.
Conventional computer architecture is proven to be inefficient for computational biology and bioinformatics tasks. For example, aligning even several hundred DNA or protein sequences using progressive multiple alignment tools consumes several CPU hours on high performance computer. Hence, computational biology and bioinformatics rely on hardware accelerators to allow processing to keep up with the increasing amount of data generated from biology applications.

In a typical application, dominant portion of the runtime is spent in a small number of computational kernels, making it an excellent target for hardware acceleration. The combination of increasingly large datasets and high performance computing requirements make computational biology prime candidate to benefit from accelerator architecture research. Potential directions include 3D integration, near-data processing, automata processing, associative processing and reconfigurable architectures.

Topics of interest:
– Impact of bioinformatics and biology applications on computer architecture research
– Bioinformatics and computational biology accelerator architecture and design
– 3D memory-logic stack based accelerators
– Automata processing in bioinformatics and computational biology applications
– Associative processing in bioinformatics and computational biology applications
– Near-data (in-memory) acceleration bioinformatics and computational biology applications
– Emerging memory technologies and their impact on bioinformatics and computational biology
– Embedded and reconfigurable architectures
– Field programmable logic based accelerators
– Bioinformatics and computational biology-inspired hardware/software trade-offs
– Software acceleration of computational biology and bioinformatics

SUBMISSION GUIDELINES:
Interested authors are encouraged to submit papers (2-5 pages) through EasyChair: https://easychair.org/conferences/?conf=aacbb2019.
The full version should be a PDF file in HPCA25 submission format. For formatting instructions please refer to: http://hpca2019.seas.gwu.edu/guidelines_for_submission.html

ORGANIZERS:
Roman Kaplan, Technion
Leonid Yavits, Technion

CONTACT:
All questions about submissions should be emailed to Leonid Yavits (yavits@technion.ac.il) or Roman Kaplan (romankap@gmail.com)


Call for Papers: Workshop on Parallel AI and Systems for the Edge
http://bit.ly/PAISE2019
Submitted by Rajesh Sankaran

1st Workshop on Parallel AI and Systems for the Edge (PAISE)
in conjunction with IPDPS 2019
Rio de Janeiro, Brazil
May 24, 2019

IMPORTANT DATES:
Submission deadline: February 1, 2019
Notification of acceptance: March 1, 2019:
Workshop camera-ready papers due: March 11, 2019

For this workshop we welcome original work covering different aspects of:
1.Edge Inference
2.Hardware for Edge-computing and Machine Learning
3.Energy Efficient Processors for Training and Inference
4.Computer Vision at the Edge
5.Cyber Security for Edge Computing
6.Software and Hardware Multitenancy at the Edge
7.Machine Learning Hardware
8.Blockchains for Edge Computing
9.Programming Models for Edge Computing
10.Coupling HPC to Edge Applications
11.Communication and Control Strategies for Deploying and Managing Applications at the Edge

SUBMISSION GUIDELINES:
All papers must be original and not simultaneously submitted to another journal or conference. The papers submitted to the workshop will be peer reviewed by a minimum of 3 reviewers.

The following paper categories are welcome:
– Full Papers: Research papers should describe original work and be 8 or 10 pages in length.
– Short Papers: Short research papers, 4 pages in length, should contain enough information for the program committee to understand the scope of the project and evaluate the novelty of the problem or approach.
– Emerging Platforms and Practitioner Reports: Short reports, 3-6 pages in length, describing novel hardware and Software platforms, including initial proof-of-concept design and implementation are welcome. Reports may also focus on a particular aspect of technology usage in practice, or describe broad project experiences. They may describe a particular design idea, or experience with a particular piece of technology.

Templates for MS Word and LaTeX provided by IEEE eXpress Conference Publishing are available for download. See the latest versions here: https://www.ieee.org/conferences_events/conferences/publishing/templates.html

Upload your submission to EasyChair submission server in PDF format. EasyChair URL: https://easychair.org/cfp/PAISE2019.
Accepted manuscripts will be included in the IPDPS workshop proceedings.

ORGANIZERS:
Pete Beckman, Argonne National Laboratory, USA
Rajesh Sankaran, Argonne National Laboratory, USA


Call for Papers: Workshop On Energy Efficient Machine Learning And Cognitive Computing For Embedded Applications
https://www.emc2-workshop.com
Submitted by Michael Goldfarb

Workshop On Energy Efficient Machine Learning And Cognitive Computing For Embedded Applications (EMC^2)
in conjunction with HPCA 2019
Washington DC, USA
February 17, 2019

IMPORTANT DATES:
Paper Submission: Jan 18, 2019 (11:59 pm PST)
Notification and Rebuttals: Feb 5, 2019
Final Version Due: Feb 8, 2019

A new wave of intelligent computing, driven by recent advances in machine learning and cognitive algorithms coupled with process technology and new design methodologies, has the potential to usher unprecedented disruption in the way conventional computing solutions are designed and deployed. These new and innovative approaches often provide an attractive and efficient alternative not only in terms of performance but also power, energy, and area. This disruption is easily visible across the whole spectrum of computing systems ranging from low end mobile devices to large scale data centers and servers.

A key class of these intelligent solutions is providing real-time, on-device cognition at the edge to enable many novel applications including vision and image processing, language translation, autonomous driving, malware detection, and gesture recognition. Naturally, these applications have diverse requirements for performance, energy, reliability, accuracy, and security that demand a holistic approach to designing the hardware, software, and intelligence algorithms to achieve the best power, performance, and area (PPA).

The goal of this workshop is to provide a forum for researchers who are exploring novel ideas in the field of energy efficient machine learning and artificial intelligence for embedded applications. We also hope to provide a solid platform for forging relationships and exchange of ideas between the industry and the academic world through discussions and active collaborations.

Below is a set of suggested but not limited topics:
– Computing techniques for IoT, Automotive, and mobile intelligence
– Exploration new and efficient applications of machine learning
– Machine learning benchmarks, workloads and their characterization
– Energy efficient techniques and solutions for neural networks
– Efficient hardware proposals to implement neural networks
– Power and performance efficient memory architectures
– Exploring the interplay between precision, performance, power and energy
– Approximation, quantization and reduced precision computing techniques
– Improvements over conventional training techniques
– Hardware/software techniques to exploit sparsity and locality
– Security and privacy challenges and building secure systems

ORGANIZERS:
Raj Parihar, Tensilica/Cadence
Michael Goldfarb, Nvidia
Satyam Srivastava, Intel
Mahdi N. Bojnordi, University of Utah
Krishna Nagar, Intel
Tao Sheng, Amazon
Debu Pal, Cadence

Program Committee:
Raj Parihar, Tensilica/Cadence
Michael Goldfarb, Nvidia
Chen Ding, University of Rochester
Mahdi N. Bojnordi, University of Utah
Andy Glew, Nvidia
Sreepathi Pai, University of Rochester
Raj Jain, Washington University in St. Louis
Smruti R Sarangi, IIT Delhi
Shaoshan Liu, PerceptIn
Ali Shafiee, Samsung
Satyam Srivastava, Intel
Danian Gong, Cadence
Krishna Nagar, Intel
Tao Sheng, Amazon


Call for Papers: ALCHEMY 2019
https://sites.google.com/site/alchemyworkshop/
Submitted by Loïc CUDENNEC

Architecture, Languages, Compilation and Hardware support for EMerging and Heterogeneous sYstems (ALCHEMY)
in conjunction with ICCS 2019
Faro, Algarve, Portugal
June 12-14, 2019

Submission deadline: 31 January, 2019

The International Conference on Computational Science is an annual conference that brings together researchers and scientists from mathematics and computer science as basic computing disciplines, researchers from various application areas who are pioneering computational methods in sciences such as physics, chemistry, life sciences, and engineering, as well as in arts and humanitarian fields, to discuss problems and solutions in the area, to identify new issues, and to shape future directions for research.

ICCS is an A-rank conference in the CORE classification.
All accepted papers will be included in the Springer Lecture Notes in Computer Science (LNCS) series.

The future aims toward increasing parallelism and heterogeneity of systems to tackle the so-called power-wall while permitting a roadmap of increased performance. Several challenges rise for programming such systems. The ALCHEMY workshop goal is to show some of these relevant challenges and finding ways to tackle them, while permitting programmers to focus on important part of application designs and letting compilers or runtime optimization do most of the work toward good performance.

ALCHEMY is the track of ICCS addressing new distributed and parallel systems for compute-intensive applications, including heterogeneous aspects. It is also a good place of exchange between the traditional HPC domain of research and all the emerging HPES (High-Performance Embedded Systems) domain, since the programming issues are mostly the same, with a relatively high cost of communication and the difficulty to program hundreds of cores often under performance and power usage constraints.

Original high quality submission are encouraged on all topics related to parallel and distributed programming issues including (but not limited to):
– High-level Programming
– Programming models and languages
– Compilers for programming languages
– Runtime generation for parallel programming
– Handling heterogeneity in parallel and distributed systems

– Operational research and optimizations
– Application, runtime, system and hardware sizing
– Task scheduling
– Task placement, application mapping

– System and runtime
– New operating systems, dedicated OS
– Dedicated runtimes
– Shared memory, data consistency models and protocols

– Hardware architecture
– Architecture support for massive parallelism management
– Specific or reconfigurable accelerators (use of FPGA), many-cores
– Enhanced communications
– New memory technologies (NVRAM)

– Security
– Accelerators for security
– Crypto systems

– In-situ systems and user experiments
– User feedback on existing architectures
– Heterogeneous integration within HPC systems (micro-servers)
– Coping with heterogeneity at the user level

SUBMISSION GUIDELINES:
The manuscripts of 10-14 pages, written in English and formatted according to the Springer LNCS templates, should be submitted electronically via EasyChair. Templates are available for download in EasyChair horizontal menu “Templates”. Papers must be based on unpublished original work and must be submitted to ICCS only. Submission implies the willingness of at least one of the authors to register and present the paper. All accepted papers will be included in the Springer Lecture Notes in Computer Science (LNCS) series and indexed by Scopus, EI Engineering Index, Thomson Reuters Conference Proceedings Citation Index (included in ISI Web of Science), and several other indexing services.

Please use the ICCS submission system hosted by EasyChair and select the Architecture, Languages, Compilation and Hardware support for Emerging and Heterogeneous sYstems track.

ORGANIZERS:
General Co-Chairs:
Loïc CUDENNEC, CEA, LIST, France
Stéphane LOUISE, CEA, LIST, France

Program Committee:
Giovanni AGOSTA, Politecnico di Milano, Italy
Paul M. CARPENTER, BSC, Spain
Jeronimo CASTRILLON, CFAED, TU Dresden, Germany
Camille COTI, Université de Paris-Nord, France
Loïc CUDENNEC, CEA, LIST, France
Vianney LAPOTRE, Université de Bretagne-Sud, France
Stéphane LOUISE, CEA, LIST, France
Marco MATTAVELLI, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Raymond NAMYST, INRIA, Université de Bordeaux, France
Eric PETIT, Intel, France
Erwan PIRIOU, CEA, LIST, France
Antoniu POP, University of Manchester, UK
Mario PORRMANN, CITEC, Universität Bielefeld, Germany
Jason RIEDY, Georgia Institute of Technology, USA
Johanna SEPULVEDA, Institute for Security in Information Technology, TU Munich, Germany
(to be extended)


Call for Papers: Special Issue on Intelligent Embedded Systems Architectures and Applications
https://www.journals.elsevier.com/microprocessors-and-microsystems/call-for-papers/special-issue-on-intelligent-embedded-systems-architectures
Submitted by Lars Bauer

Special Issue on Intelligent Embedded Systems Architectures and Applications
Elsevier Microprocessors and Microsystems

IMPORTANT DATES:
Paper submission deadline: Jan 15, 2019
Notification of the first review: Mar 15, 2019
Revisions due: Apr 15, 2019
Final notice of acceptance: May 15, 2019
Final version manuscripts due: Jun 15, 2019
Special issue to appear: Sep 2019

The purpose of this special issue is to provide an up-to-date picture of intelligent embedded systems architectures and applications with emphasis on Smart IoT and Cyber Physical Systems, including hot topics such as accelerating deep learning. The proposal covers several aspects, from the hardware related ones to embedded software and application issues.

Topics include, but not limited to, the following:
– Special purpose hardware to support deep learning in embedded architectures
– Edge computing for smart embedded systems: hardware and software aspects
– Run-time resource management for smart IoT/Edge Computing systems
– HW/SW codesign of Cyber Physical Systems
– Programming models for IoT/Edge computing applications
– Applications and case studies of intelligent embedded systems
– Design methodologies and platforms for wearable computing
– In-memory computing for unsupervised learning

SUBMISSION GUIDELINES:
Submissions will be evaluated on Novelty, Generality, Significance, Clarity and Support criteria. We invite the submission of full length papers to this special issue that will details the state-of-the-art technology and trends in Intelligent Embedded Systems Architectures and Applications.

GUEST EDITORS:
Maurizio Martina, Politecnico di Torino, Italy
William Fornaciari, Politecnico di Milano, Italy


Call for Workshops/Tutorials: NVM Workshop 2019
http://nvmw.ucsd.edu/
Submitted by Joseph Izraelevitz

Non-Volatile Memory Workshop (NVMW)
San Diego, CA, USA
March 10-12, 2019

Each year the Non-Volatile Memories Workshop includes a tutorial afternoon that covers a topic in more depth. Tutorials are typically 2-4 hours long and are a long-form presentation on the topic(s). Previous tutorial topics have included:
– Phase change memory
– Signal processing for NVMs
– Data integrity in storage stacks
– RamCloud
– Persistent memory programming

We invite proposals for the 2019 tutorial.

Tutorial proposals should be between 1 and 3 pages and include a brief outline of the material to be covered, discussion of its relevance to the NVMW community, and the qualifications of the presenters. The tutorial will be selected based on the timeliness and general interest of the topic to the NVMW community.

The submission deadline is January 15, 2019. Notifications will be out by Monday, January 22. The tutorial will be held the afternoon of Sunday, March 10, 2019.

More information on the workshop is available at the workshop website (http://nvmw.ucsd.edu).
For additional information, please contact the NVMW publicity chair, Joe Izraelevitz, at jizraelevitz@eng.ucsd.edu


Call for Posters: CGO Student Research Competition
http://cgo.org/cgo2019/src/
Submitted by Adwait Jog

CGO Student Research Competition (SRC) 2019
Washington DC, USA
February 16-20, 2019

IMPORTANT DATES:
Submission: December 1, 2018 (AoE)
Notification: December 10, 2018

The ACM Student Research Competition (SRC) offers a unique forum for undergraduate and graduate students to present their original research before a panel of judges and attendees at CGO. Participants must be undergraduates or graduate students pursuing an academic degree at the time of initial submission. Participants must be current student members of the ACM. The abstracts will be examined by a selection committee and selected abstracts will be invited to present as posters at the conference. SRC poster submissions are, in addition, evaluated by a jury during the poster session at the conference. The best three posters are then invited to give a short presentation (10 minutes + 5 minutes questions) on the next day. Based on the submitted abstract, the poster, and the presentation, the winner of CGO’s Student Research Competition will be selected, who will receive an award. In addition the winner will be invited to participate in the grand 2019 ACM SRC competition. Further information on the ACM SRC is available at: https://src.acm.org

CGO-2019 SRC submissions in the form of an extended abstract (details below) are solicited in any topics relevant to the main conference, including:
– Code Generation, Translation, Transformation, and Optimization for performance, energy, virtualization, portability, security, or reliability concerns, and architectural support
– Efficient execution of dynamically typed and higher-level languages Optimization and code generation for emerging programming models, platforms, domain-specific languages
– Dynamic/static, profile-guided, feedback-directed, and machine learning based optimization
– Static, Dynamic, and Hybrid Analysis for performance, energy, memory locality, throughput or latency, security, reliability, or functional debugging
– Program characterization methods
– Efficient profiling and instrumentation techniques; architectural support
– Novel and efficient tools
– Compiler design, practice and experience
– Compiler abstraction and intermediate representations
– Vertical integration of language features, representations, optimizations, and runtime support for parallelism
– Solutions that involve cross-layer (HW/OS/VM/SW) design and integration
– Deployed dynamic/static compiler and runtime systems for general purpose, embedded system and Cloud/HPC platforms
– Parallelism, heterogeneity, and reconfigurable architectures
– Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA
– Compiler-support for vectorization, thread extraction, task scheduling, speculation, transaction, memory management, data distribution and synchronization

SUBMISSION GUIDELINES:
Extended abstracts of up to 500 words should be submitted by email to Jagadish.Kotra@amd.com and in CC to zsura@us.ibm.com on or before December 1, 2018. All submissions will be reviewed by a selection committee. Notifications will be sent out by December 10, 2018. Selected submissions will have their abstract included in the CGO 2019 proceedings and will be invited to CGO to participate in the ACM SRC competition.

Please format your submission using the SIGPLAN format found here. Use one 8.5″x11″ single spaced, double-column page, with 10pt or larger font. Include your name and the name of your advisor(s). Optionally, send a pdf of the poster you plan to present (this does not have to be the final version of the poster).

SRC CHAIR:
Jagadish Kotra (AMD Research)

Please feel free to contact me at Jagadish.Kotra@amd.com for any further questions/concerns.


AutomataZoo: a Benchmark Suite for Automata Processing
https://github.com/hplp/AutomataZoo
Submitted by Tommy Tracy II

AutomataZoo

High performance automata processing engines are traditionally evaluated against a limited set of regular expression rulesets. These serve as valid, real-World example use cases, but they only represent a small proportion of all automata-based applications. With the recent availability of architectures and software frameworks for automata processing, many new applications have been discovered that benefit from automata processing. These demonstrate a broad variety of characteristics that differ from prior regular expression-based applications and warrant their own benchmarks.

We released an earlier benchmark suite, ANMLZoo, in 2016 to fulfill this need. We have improved upon ANMLZoo with AutomataZoo [Wadden et al., IISWC 2018] in the following ways:

– The suite of benchmarks is no longer standardized to a particular architecture, and does not inherit the same architectural biases as ANMLZoo.
– The benchmarks implement full kernels, which allows for comparisons between automata and non-automata approaches.
– The suite includes open-source tools for generating benchmark automata and inputs of various sizes, allowing for design space explorations.

BENCHMARKS:
– Snort: A widely used network intrusion detection system.
– ClamAV: A virus-detection tool that relies on a publicly-available database of malware patterns.
– Protomata: An automata-based application that searches for a set of 1309 protein motif patterns from the PROSITE database.
– Brill Tagging: A rule-based approach to part-of-speech tagging.
– Random Forest: A machine learning model based on ensembles of decision trees.
– Hamming Distance: A string-scoring kernel that accepts inputs that are within a set hamming distance of a configured pattern.
– Levenshtein Distance: A string-scoring kernel that accepts inputs that are within a set edit distance of a configured pattern.
– Sequence Matching: An automata application that counts sorted sequences of item sets to identify frequently-occurring sets.
– Entity Resolution: An automata application that attempts to find duplicate entries in a streaming database.
– CRISPR/Cas9: An automata application that enabled gene editing by identifying targeted locations.
– YARA: An automata application that discovers malware described in the YARA malware pattern description language.
– File Carving: An automata application that identifies files in a stream of input bytes.
– Pseudo Random Number Generation (PRNG): An automata application that models Markov Chains with finite automata to generate high-throughput PRNG streams.

The benchmark suite can be found here: https://github.com/hplp/AutomataZoo

[Wadden et al., IISWC 2018] Wadden, J., Tracy II, T., Sadredini, E., Wu, L., Bo, C., Du, J., Wei, Y., Wallace, M., Udall, J., Stan, M., and Skadron, K. “ANMLZoo: A Benchmark Suite for Exploring Bottlenecks in Automata Processing Engines and Architectures.” 2018 IEEE International Symposium on Workload Characterization (IISWC’18). IEEE, 2018.

We hope this new benchmark suite will fulfill your current and future research efforts related to automata computing.


Book Release: The Datacenter as a Computer, 3rd Edition
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=1320
Submitted by Bebe

The Datacenter as a Computer: Designing Warehouse-Scale Machines, Third Edition
Luiz André Barroso, Google LLC
Urs Hölzle, Google LLC
Parthasarathy Ranganathan, Google LLC

Paperback ISBN: 9781681734330
eBook ISBN: 9781681734347
Hardcover ISBN: 9781681734354

October 2018, 209 pages

This book describes warehouse-scale computers (WSCs), the computing platforms that power cloud computing and all the great web services we use every day. It discusses how these new systems treat the datacenter itself as one massive computer designed at warehouse scale, with hardware and software working in concert to deliver good levels of internet service performance. The book details the architecture of WSCs and covers the main factors influencing their design, operation, and cost structure, and the characteristics of their software base. Each chapter contains multiple real-world examples, including detailed case studies and previously unpublished details of the infrastructure used to power Google’s online services. Targeted at the architects and programmers of today’s WSCs, this book provides a great foundation for those looking to innovate in this fascinating and important area, but the material will also be broadly interesting to those who just want to understand the infrastructure powering the internet.

The third edition reflects four years of advancements since the previous edition and nearly doubles the number of pictures and figures. New topics range from additional workloads like video streaming, machine learning, and public cloud to specialized silicon accelerators, storage and network building blocks, and a revised discussion of data center power and cooling, and uptime. Further discussions of emerging trends and opportunities ensure that this revised edition will remain an essential resource for educators and professionals working on the next generation of WSCs.

Table of Contents:
Acknowlegements / Introduction / Workloads and Software Infrastructure / WSC Hardware Building Blocks / Data Center Basics: Building, Power, and Cooling / Energy and Power Efficiency / Modeling Costs / Dealing with Failures and Repairs / Closing Remarks / Bibliography / Author Biographies


Announcement: ACM Digital Library usage
http://www.acm.org/publications/acm-author-izer-service
Submitted by Natalie Enright Jerger

The SIGARCH EC would like to encourage further use of the ACM Digital library (dl.acm.org) by our members. Downloading papers published in SIGARCH-sponsored conferences from the ACM DL provides a revenue stream back to SIGARCH. This revenue stream supports existing programs such as student travel grants and allows SIGARCH to develop new programs to further support its members. Please use the ACM DL in your research and use the ACM Authorizer to post ACM DL links to your own papers on your website (http://www.acm.org/publications/acm-author-izer-service). To encourage use of the ACM DL, we will be highlighting the top 10 papers from SIGARCH (co-)sponsored conferences downloaded over the last 6 weeks in each monthly SIGARCH newsletter. Happy reading!

Top 10 Downloaded papers in SIGARCH-sponsored publications (as of Dec 3, 2018):

1. 3D Localization for Sub-Centimeter Sized Devices – 2018, SenSys
Rajalakshmi Nandakumar, Vikram Iyer, Shyamnath Gollakota
Downloaded 345 times

2. In-Datacenter Performance Analysis of a Tensor Processing Unit – 2017, ISCA
Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia,Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau,Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho,Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary,Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan,Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg,Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon
Downloaded 338 times

3. E-Eye: Hidden Electronics Recognition through mmWave Nonlinear Effects – 2018, SenSys
Zhengxiong Li, Zhuolin Yang, Chen Song, Changzhi Li, Zhengyu Peng, Wenyao Xu
Downloaded 196 times

4. EXIMIUS: A Measurement Framework for Explicit and Implicit Urban Traffic Sensing – 2018, SenSys
Zhou Qin, Zhihan Fang, Yunhuai Liu, Chang Tan, Wei Chang, Desheng Zhang
Downloaded 182 times

5. CapBand: Battery-free Successive Capacitance Sensing Wristband for Hand Gesture Recognition – 2018, SenSys
Hoang Truong, Shuo Zhang, Ufuk Muncuk, Phuc Nguyen, Nam Bui, Anh Nguyen, Qin Lv, Kaushik Chowdhury, Thang Dinh,Tam Vu
Downloaded 178 times

6. ProvChain: A Blockchain-based Data Provenance Architecture in Cloud Environment with Enhanced Privacy and Availability – 2017, CCGrid
Xueping Liang, Sachin Shetty, Deepak Tosh, Charles Kamhoua, Kevin Kwiat, Laurent Njilla
Downloaded 169 times

7. Passive-ZigBee: Enabling ZigBee Communication in IoT Networks with 1000X+ Less Power Consumption – 2018, SenSys
Yan Li, Zicheng Chi, Xin Liu, Ting Zhu
Downloaded 166 times

8. Fabric as a Sensor: Towards Unobtrusive Sensing of Human Behavior with Triboelectric Textiles – 2018, SenSys
Ali Kiaghadi, Morgan Baima, Jeremy Gummeson, Trisha Andrew, Deepak Ganesan
Downloaded 164 times

9. InK: Reactive Kernel for Tiny Batteryless Sensors – 2018, SenSys
Kasım Sinan Yıldırım, Amjad Yousef Majid, Dimitris Patoukas, Koen Schaper, Przemyslaw Pawelczak, Josiah Hester
Downloaded 160 times

10. Fall-curve: A novel primitive for IoT Fault Detection and Isolation – 2018, SenSys
Tusher Chakraborty, Akshay Uttama Nambi, Ranveer Chandra, Rahul Sharma, Manohar Swaminathan, Zerina Kapetanovic,Jonathan Appavoo
Downloaded 154 times


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Boris Grot
SIGARCH Content Editor

Top