This is the 1st August 2025 digest of SIGARCH Messages.

In This Issue

Call for Papers: HASP @ MICRO 2025 - (Note: The Call for Paper type has not been set for this item!)


Call for Participation: ASAP 2025

Submitted by Hanrui Wang

The 36th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2025)
July 28-30, 2025
Vancouver, BC, Canada
https://www.asap-2025.org 

Registration link: https://www.asap-2025.org/registration/ 

Early registration deadline: June 28, 2025

The history of the event traces back to the International Workshop on Systolic Arrays, organized in 1986 in Oxford, UK. It later developed into the International Conference on Application Specific Array Processors. With its current title, it was organized for the first time in Chicago, USA in 1996. Since then it has alternated between Europe and North-America. The conference will cover the theory and practice of application-specific systems, architectures, and processors. 

For a quick preview of ASAP 2025, we will have a variety of talks across 1) LLMs, Transformers, and Accelerators, 2) Scalable Systems and Secure Acceleration, 3) RISC-V and Custom Architectures, and 4) Design Exploration and Emerging Hardware. Besides regular paper talks, we will have two exciting keynotes, and a few invited sessions on special topics such as 1) Reconfigurable Edge Computing, 2) Architectures for Sustainable Security, and 3) Custom Computing in Canada. One special event this year is a retrospective review of most impactful ASAP papers in the past decades. In addition, we are also planning for a couple of sponsor workshops and/or tutorials, as well as lots of interesting poster presentations. 

Keynotes
Keynote 1: Towards 40 Years of ASAP: From Systolic Array to Application-Specific Processing
Prof. Wayne Luk, Imperial College London

Keynote 2: For ML and With ML: The New Normal in Hardware Design
Prof. Lizy John, University of Texas at Austin

Organizing Committee:
* General Chair: Zhenman Fang, Simon Fraser University, Canada
* Program Chairs: Philip Brisk, University of California, Riverside, USA
      Cong Callie Hao, Georgia Institute of Technology, USA

We look forward to your participation and welcome you to Vancouver for an engaging and inspiring ASAP 2025!

 


Call for Papers: ACM Sigmetrics 2026: Operational Systems Track
https://www.sigmetrics.org/sigmetrics2026/
Submitted by Stefan Schmid (TU Berlin)

ACM Sigmetrics would like to point the community to a new track which may be of interest to some of you.

Operational Systems Track at ACM Sigmetrics 2026: This is a new track that seeks papers describing deployed systems that are in significant use in a real-world setting.

Papers in this track should focus on principled measurement, modeling, and metrics pertaining to the system. Papers in this track need not necessarily present new ideas as judged by the “academic novelty” standard that we traditionally use for research paper submissions.
Good papers could present how known ideas work in practice, how design principles scale (or do not scale) to large production-scale systems, prove (or, disprove) existing assumptions with real-world data, bring out new performance modeling problems from real-world systems to the attention of the research community, etc.
The paper must describe “lessons learned” in the context of prior approaches known in the literature. Accepted papers in this track will be published as a regular paper along with papers in the research track.

More information at https://www.sigmetrics.org/sigmetrics2026/


Call for Papers: ASPLOS 2026
https://www.asplos-conference.org/asplos2026/cfp/
Submitted by Hyeran Jeon & Guangyu Sun

ASPLOS, the ACM International Conference on Architectural Support for Programming Languages and Operating Systems, is the premier academic forum for multidisciplinary applied computer systems research spanning hardware, software, and their interaction. It focuses on practical aspects of computer architecture, programming languages, operating systems, and associated areas such as networking and storage.

Please note the following main changes from previous years detailed in the rest of the CFP

  1. Two submission cycles
  2. Limit on the number of submissions by the same author
  3. Explicit assessment of Interdisciplinary research
  4. Unlimited appendix

https://www.asplos-conference.org/asplos2026/cfp/

Important Dates

ASPLOS 2026 has moved to two submission deadlines – spring and summer – which are meant to encourage authors to submit their papers when they are ready. As in recent years, ASPLOS 2026 will allow the authors of some submissions to choose to apply a major revision to their submission in order to fix a well-defined list of problems.

Spring Cycle

  • Abstract submission — March 05, 2025 (11:59pm Eastern)
  • Full paper submission — March 12, 2025
  • Author response — June 09 — 13, 2025
  • Notification — June 24, 2025

Summer Cycle

  • Abstract submission — Aug 13, 2025 (11:59pm Eastern)
  • Full paper submission — Aug 20, 2025
  • Author response — Nov 10 — 14, 2025
  • Notification — Nov 24, 2025

Scope and Expectations

The scope of ASPLOS 2026 covers all practical aspects related to the three main ASPLOS disciplines: computer architecture, programming languages, and operating systems, as well as closely-related associated areas. ASPLOS construes systems broadly, and areas of interest include, but are not limited to: operating systems, file and storage systems, distributed systems, cloud computing, mobile and edge systems, secure and reliable systems, systems aspects of big data and machine learning, embedded and real-time systems, and virtualization.

We seek original, high-quality research submissions that improve and further the knowledge of applied computer systems, with emphasis on the intersection between the main ASPLOS disciplines:  Operating Systems, Programming Languages, Computer Architecture and Emerging Hardware.

Research submission may be applicable to computer systems of any scale, ranging from small, ultra-low power wearable devices to large scale parallel computers and data centers. We embrace research that directly targets new problems in innovative ways. The research may target diverse goals, such as throughput, latency, energy, and security. Non-traditional topics are encouraged, and the review process will be sensitive to the challenges of multidisciplinary work in emerging areas. We welcome submission of “experience papers” that have a novel component and that clearly articulate the lessons learned. We likewise welcome submissions whereby novelty lies in furthering our understandings of existing systems, e.g., by uncovering previously unknown, valuable insights or by convincingly refuting prior published results and common wisdom. We value submissions more highly if they are accompanied by clearly defined artifacts not previously available, including traces, original data, source code, or tools developed as part of the submitted work. We particularly encourage new ideas and approaches.

Alphabetically sorted areas of interest related to practical aspects of computer architecture, programming languages, and operating systems include but are not limited to:

  • Existing, emerging, and nontraditional compute platforms at all scales
  • Heterogeneous architectures and accelerators
  • Internet services, cloud computing, and datacenters
  • Memory, storage, networking, and I/O
  • Power, energy, and thermal management
  • Profiling, debugging, and testing
  • Security, reliability, and availability
  • Systems for enabling parallelism and computation on big data
  • Virtualization and virtualized systems

A good submission will typically: motivate a significant problem; propose a practical solution or approach that makes sense; demonstrate not just the pros but also the cons of the proposal using sound experimental methods; explicitly disclose what has and has not been implemented; articulate the new contributions beyond previous work; and refrain from overclaiming, focusing the abstract and introduction sections primarily on the difference between the new proposal and what is already available. The latter statement should be interpreted broadly to also encompass studies that broaden our understanding of existing systems (rather than suggest new ones), which may constitute a significant problem in its own right. Submissions will be judged on relevance, novelty, technical merit, clarity. Submissions are expected to adhere to SIGPLAN’s Empirical Evaluation Guidelines and all the policies specified below.

Program Chairs

Benjamin C. Lee, University of Pennsylvania
Harry Xu, University of California Los Angeles
Mark Silberstein, Technion – Israel Institute of Technology

Please direct any questions to the program co-chairs at asplos2026pcchairs@gmail.com.


Call for Papers: PPoPP 2026
https://ppopp26.sigplan.org/
Submitted by Kenjiro Taura

31st ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2026)
Sydney, Australia
Co-located with CC, CGO and HPCA
January 31 – February 4, 2026.
https://ppopp26.sigplan.org/

Important dates:
* Full paper submission: Monday, September 1st, 2025
* Author response period: October 27 – 29, 2025 (Mon – Wed)
* Author notification: Monday, November 10th, 2025
* Artifact submission to AE committee: Monday, November 17th, 2025
* Artifact notification by AE committee: Monday, January 5th, 2026
* Final paper due: Friday, January 9, 2026 (TBC)

Scope:
PPoPP is the premier forum for leading work on all aspects of parallel and performance programming, including theoretical foundations, techniques, languages, compilers, runtime systems, tools, applications, and practical experience. This symposium focuses on improving the programming productivity and performance engineering of all concurrent and parallel systems – multicore, multi-threaded, heterogeneous, clustered, and distributed systems, grids, accelerators such as ASICs, GPUs, FPGAs, data centers, clouds, large scale machines, and quantum computers. PPoPP is also interested in new and emerging parallel workloads and applications, such as artificial intelligence and large-scale scientific/enterprise workloads.

Specific topics of interest include (but are not limited to):
* Languages, compilers, and runtime systems for parallel programs
* Parallel programming frameworks and domain-specific languages
* Parallel programming for emerging hardware, including AI accelerators, processor-in-memory, programmable logic, and non-volatile memory technologies
* High-performance libraries
* Parallel programming for deep memory hierarchies including nonvolatile memory
* Parallel algorithms
* Parallel applications including scientific computing and enterprise workloads
* Artificial intelligence and machine learning for parallel systems, including their use in system design, optimization, and runtime decisions
* Development, analysis, or management tools
* Performance analysis, debugging and optimization
* Productivity tools for parallel systems
* Software engineering for parallel programs
* Parallel programming theory and models
* Formal analysis and verification
* Concurrent data structures
* Synchronization and concurrency control
* Fault tolerance for parallel systems
* Middleware for parallel systems

Paper Submission:
Submission URL: https://ppopp26.hotcrp.com

All submissions must be made electronically through the conference website and include an abstract (100–400 words), author contact information, the full list of authors and their affiliations. Full paper submissions must be in PDF format printable on both A4 and US letter-size paper. All papers must be prepared in two-column ACM Conference Format

Further details available at https://ppopp26.sigplan.org/track/PPoPP-2026-papers#Call-for-Papers

PC co-chairs:
Madan Musuvathi (Microsoft Research)
Kenjiro Taura (The University of Tokyo)


Call for Papers: CAMS25 – The 3rd Workshop on Computer Architecture Modeling and Simulation
https://sarchlab.org/cams25
Submitted by Enze Xu

3rd Workshop on Computer Architecture Modeling and Simulation (CAMS 2025)
held in conjunction with IEEE/ACM MICRO25.
Seoul, Korea.
October 18/19, 2025

Summary

The goal of the workshop is to provide a forum for researchers and practitioners to exchange ideas and discuss the latest advances in the field of computer architecture modeling and simulation. The focus on modeling and simulation techniques is of vital importance to the ongoing advancements in microarchitecture, as these methods are essential tools for improving system performance, efficiency, and reliability.

Topics of interest
The workshop will cover various aspects of computer architecture modeling and simulation, including but not limited to:
 * Simulator Development: Advances in design, theory, implementation, and integration of simulators.
 * Performance Modeling: Strategies for prediction, validation, and the impact of architectural features.
 * Power Modeling and Simulation: Methods for power-efficient design and power-performance trade-offs.
 * Tools and Studies Survey: Review and compare existing simulation tools and applications.
 * Scalable Simulation Techniques: Approaches for improving simulation scalability and efficiency.
 * Modeling and Simulation for Unconventional Architectures: Exploration of unique challenges and approaches for emerging and unconventional architectures.
 * Hardware-in-the-loop Simulation: Performance modeling and simulator validation with hardware.
 * Modeling for Machine Learning (Sim4AI): Architectural considerations and models for hardware accelerators.
 * Validation Techniques: Approaches for validating the accuracy of simulation models.
 * Human-centered simulation methods: Analysis, visualization, and monitoring methods.
Submissions
Call for full papers
The workshop invites submissions of original work in the form of full papers (up to 6 pages, reference not included) covering all aspects of computer architecture modeling and simulation. Submissions will be peer-reviewed, and accepted papers will be included in the workshop proceedings.
Call for Abstracts for Tool Release Talks
The talks will announce new simulators or new releases of existing simulators, highlighting their new features and improvements. We solicit talks from a broader community. Please submit a one-page abstract that includes the simulator, the new version, the new features you wish to present, and the website for your tool (if it exists). The selection will be made based on the relevance to the workshop topics, decided by the workshop chairs.
Important Dates
* Full Paper Submissions: August 11th, 2025 August 25th, 2025 (23:59 AoE)  – Deadline extended
* Full Paper Author Notifications: September 8th, 2025
* Tool Release Talk Submissions: September 15th, 2025 (23:59 AoE)
* Tool Release Talk Author Notifications: September 22nd, 2025
Workshop Chairs
 * Yifan Sun, College of William & Mary (W&M), USA, ysun25@wm.edu
 * Trevor E. Carlson, National University of Singapore (NUS), Singapore,  tcarlson@comp.nus.edu.sg

Call for Papers: PDSW 2025
https://www.pdsw.org/index.shtml
Submitted by Izzet Yildirim

The 10th International Parallel Data Systems Workshop (PDSW 2025)
Co-located with Supercomputing 2025

Summary
The increasing importance of efficient data storage and management continues to drive scientific productivity across traditional simulation-based HPC environments and emerging Cloud, AI/ML, and Big Data analysis frameworks. Challenges are compounded by the rapidly expanding volumes of experimental and observational data, the growing disparity between computational and storage hardware performance, and the rise of novel data-driven algorithms in machine learning. This workshop aims to advance research and development by addressing the most pressing challenges in large-scale data storage and processing.

We invite the community to contribute original research manuscripts that introduce and evaluate novel algorithms or architectures, share significant scientific case studies or workloads, or assess the reproducibility of previously published work. We emphasize the importance of community collaboration for problem identification, workload capture, solution interoperability, standardization, and shared tools. Authors are encouraged to provide comprehensive experimental environment details (software versions, benchmark configurations, etc.) to promote transparency and facilitate collaborative progress.

Important Dates
Paper Submissions due: Aug 1st, 2025, 11:59 PM AoE  Aug 8th, 2025, 11:59 PM AoE (Extended)
AD due: Aug 8th, 2025, 11:59 PM AoE  Aug 15th, 2025, 11:59 PM AoE (Extended)
Paper Notification: Sep 5th, 2025, 11:59 PM AoE
Camera ready due: Sep 27th, 2025, 11:59 PM AoE
Final AD/AE due: Oct 15, 2025, 11:59 PM AoE

Submissions website: https://submissions.supercomputing.org/

Topics of Interest
– Scalable Architectures: Distributed data storage, archival, and virtualization.
– New Data Processing Models and Algorithms: Application of innovative data processing models and algorithms for parallel computing and analysis.
– Performance Analysis: Benchmarking, resource management, and workload studies.
– Cloud and Container-Based Models: Enabling cloud and container-based frameworks for large-scale data analysis.
– Storage Technologies: Adaptation to emerging hardware and computing models.
– Data Integrity: Techniques to ensure data integrity, availability, reliability, and fault tolerance.
– Programming Models and Frameworks: Big data solutions for data-intensive computing.
– Hybrid Cloud Data Processing: Integration of hybrid cloud and on-premise data processing.
– Cloud-Specific Opportunities: Data storage and transit opportunities specific to cloud computing.
– Storage System Programmability: Enhancing programmability in storage systems.
– Data Reduction Techniques: Filtering, compression, and reduction techniques for large-scale data.
– File and Metadata Management: Parallel file systems, metadata management at scale.
– In-Situ and In-Transit Processing: Integrating computation into the memory and storage hierarchy for in-situ and in-transit data processing.
– Alternative Storage Models: Object stores, key-value stores, and other data storage models.
– Productivity Tools: Tools for data-intensive computing, data mining, and knowledge discovery.
– Data Movement: Managing data movement between compute and data-intensive components.
– Cross-Cloud Data Management: Efficient data management across different cloud environments.
– AI-enhanced Systems: Storage system optimization and data analytics using machine learning.
– New Memory and Storage Systems: Innovative techniques and performance evaluation for new memory and storage systems.

More details are available at: https://www.pdsw.org/index.shtml

Organizers
General Chair: Suren Byna (The Ohio State University, USA)
Program Co-Chairs:
Anthony Kougkas (Illinois Institute of Technology, USA)
Sarah Neuwirth (Johannes Gutenberg University Mainz, Germany)


Call for Papers: DoSSA-7@ MICRO-58
http://prism.sejong.ac.kr/dossa-7/
Submitted by Hyesoon Kim

7th International Workshop on  Domain Specific System Architecture (DoSSA-7)
In conjunction with MICRO-58
October 19, 2025
Seoul, Korea

http://prism.sejong.ac.kr/dossa-7

Call for papers

Domain specific systems are an increasingly important computing environment for many people and businesses. As the information technologies emerge into various real-world applications such as autonomous driving, IoT (Internet of Things), CPS (Cyber physical systems) and health care applications in the 4th industrial revolution era, the interest in the specialized domain specific computing systems is increasing significantly. In addition to the conventional computing platforms, domain specific computing systems have a lot of design challenges including specialized hardware components like hardware accelerator, optimized library and domain specific languages. This workshop focuses on domain specific system design in both hardware and software aspects and their interaction to improve the availability and efficiency in the emerging real-world applications. The main theme of this workshop in this year is the HW/SW components for domain specific systems.

Topics of interest

  • Application analysis and workload characterization to design domain specific system for emerging applications, such as autonomous driving, IoT and health care applications.
  • Domain specific processor/system architectures and hardware features for domain specific systems;
  • Low-power, energy-efficient domain specific accelerator/system architectures for on-device AI systems
  • Hardware accelerators for domain specific systems;
  • Storage architectures for domain specific systems;
  • Experiences in domain specific system development;
  • Novel techniques to improve responsiveness by exploiting domain specific systems;
  • Novel techniques to improve performance/energy for domain specific systems;
  • Domain specific systems performance evaluation methodologies;
  • Application benchmarks for domain specific systems;
  • Enabling technologies for domain specific systems (smart edge devices, smart sensors, energy harvesting,sensor networks, sensor fusion etc.);

 

Submit a 2-page presentation abstract to a web-based submission system (https://cmt3.research.microsoft.com/DoSSA2025) by August 26, 2025.
For additional information regarding paper submissions, please contact the organizers.

Important Dates

  • Abstract submission August 26, 2025
  • Author notification September 15, 2025
  • Final camera-ready paper October 6, 2025
  • Workshop October 19, 2025

 

Organizers

Hyesoon Kim, Georgia Tech.
Gi-Ho Park, Sejong Univ.
Jaewoong Sim, Seoul National Univ


Note: The Call for Paper type has not been set for this item!

Call for Papers: HASP @ MICRO 2025
https://www.haspworkshop.org/2025/
Submitted by Shuwen Deng

The 14th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP)
October 18 or 19, 2025
HASP is intended to bring together researchers, developers, and practitioners from academia and industry, to share practical implementations and experiences related to all aspects of hardware and architectural support for security and privacy, and to discuss future trends in research and applications.
Topics of interest
• Secure hardware processor architectures and implementations
• Side-channel attacks, evaluations, and defenses
• Secure cache designs and evaluation, focusing on side-channels
• Commercial TEE systems and security solutions
• Hardware-enhanced cloud security
• Security of emerging architectures, such as Quantum Computers
• Hardware support for secure Internet-of-Things
• Smartphone hardware security
• Hardware fingerprinting and PUFs
• Hardware and architectural support for trust management
• Hardware trojan threat evaluation, detection, and prevention
• Attack resilient hardware and architectural design
• Cryptographic hardware design, implementation, and evaluation
• Security simulation, testing, validation and verification
Authors can submit the following types of papers:
I. Regular Paper (8 Pages, including the bibliography and appendices)
• Research Paper
• SoK: Systemization-of-Knowledge papers should concisely, but exhaustively, systematize and conceptualize existing knowledge (similar to SoK papers in S&P conferences, but focusing on hardware and architecture). Papers should use “SoK Paper:” as their title prefix.
• Position Paper: Position papers should define new problems in hardware or architecture security and privacy topics. Papers should use “Position Paper:” as their title prefix.
II. Short Paper (4 Pages, including the bibliography and appendices)
• Research Paper: Papers should use “Short Paper:” as their title prefix.
• WiP: Papers should use “WiP:” as their title prefix. Work-in-Progress papers will not appear in the proceedings, but the title and authors will be listed on the HASP web page as a public record of the presentation.
Important Dates
Submission Deadline: Jul 27, 2025, by end of day Anywhere on Earth (AoE)
Notification of Acceptance: September 2, 2025
Camera-ready Version: September 15, 2025
Workshop Date: October 18 or 19, 2025 (tentative)
Submission Information
Papers can be submitted on the EasyChair web page: https://easychair.org/conferences/?conf=hasp2025 . All submissions must be using the double-column ACM ICPS template. Please use the ACM Standard template in the usual two-column format. The submissions should be anonymized for double-blind review. Regular paper and short paper submissions must be at most 8 or 4 pages respectively (including the bibliography and appendices). Short research papers, position papers, SoK papers and Work-in-Progress papers should have “Short Paper”, “Position Paper”, “SoK”, and “WiP” as the title prefix.
All accepted research papers, short papers, position papers, and SoK papers will be included in the ACM Digital Library; Work-in-Progress papers are not included. The proceedings will be published through ACM ICPS and available through the ACM Digital Library
HASP 2025 Co-Chairs:
Prof. Wenjie Xiong, Virginia Tech, USA – wenjiex@vt.edu
Prof. Tianwei Zhang, Nanyang Technological University, Singapore
Prof. Shuwen Deng, Tsinghua University, China

Call for Presentations: Job Candidate Showcase @ MICRO 2025
https://sites.google.com/bu.edu/micro-showcase2025
Submitted by Sabrina Neuman

We are inviting submissions to the MICRO 2025 Job Candidate Showcase, a conference session for PhD students to present their dissertation research and gain visibility within the computer architecture community as they prepare for the job market. The presentation format will be a lightning talk and poster session. The showcase welcomes presentations on any topic in computer architecture (e.g., see MICRO call for papers).

Eligibility:
Students should have published in the community’s rigorously peer-reviewed conferences or journals. Students should be within 1-2 years, before or after, of dissertation completion. Students closer to graduation will be given priority as other students can attend a future forum with more mature results. Interested participants will submit (a) two-page research statement; (b) published or accepted first-author paper from ASPLOS, HPCA, ISCA, or MICRO; and (c) curriculum vitae.

Important Dates:
Submissions deadline: August 22, 2025
Author notification: September 5, 2025

Details and Submission Webpage:
https://sites.google.com/bu.edu/micro-showcase2025


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Akanksha Jain
SIGARCH Content Editor

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