This is the 1st January 2019 digest of SIGARCH Messages.

In This Issue


Call for Nominations: SIGARCH Executive Committee Elections

Submitted by Sarita Adve

Call for Nominations for SIGARCH Executive Committee Elections

The SIGARCH elections nominating committee invites nominations (including self-nominations) for candidates to serve on the SIGARCH Executive Committee (EC). The nominating committee will select the final slate of candidates for elections to be held according to ACM rules. The initial term for the EC is for two years, beginning July 1, 2019, with a possible extension for another two years.

The EC positions are:
Chair
Vice-chair
Secretary/Treasurer
Board of Directors (4 members)

The SIGARCH EC is a working committee where each member is responsible for at least one substantive project in the service of the architecture community. In addition to overseeing our rich portfolio of conferences and awards, the current EC initiated many new initiatives such as the Computer Architecture Today blog, lightning mentoring sessions, the CARES committee, the dissertation award, the visioning workshops, and more – see the last SIGARCH annual report for the portfolio of current activities. Joining the SIGARCH EC therefore requires a significant time commitment in exchange for an opportunity to make an impact on our community and enjoy a rewarding service experience.

The nominating committee will select the final slate of candidates based on enthusiasm, vision, past record of service (commensurate with seniority), and multiple dimensions of diversity.

Please submit a nomination with the following information to chair_sigarch@acm.org by 5pm CST January 10, 2019.
– Name, affiliation, and email address of the nominee.
– Position sought (chair/vice-chair/treasurer/director).
– Previous significant service to SIGARCH and ACM.
– Other significant service and relevant experience.
– A brief biography or curriculum vitae.
– Recent institutional affiliations.
– Areas of research expertise within computer architecture.
– A brief statement from the nominee (e.g., 150 words) in support of the nomination; e.g., a description of their ideas and commitment if elected.

All final candidates must be professional ACM members and SIGARCH members by the time of final selection.

The nominating committee consists of current and past SIGARCH chairs: Sarita Adve (chair), Norm Jouppi, David Wood.


Call for Participation: HPCA 2019
http://hpca2019.seas.gwu.edu
Submitted by Duo Liu

2019 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Washington D.C., USA
February 16-20, 2019

Early registration deadline: Jan 15, 2019
Please check the Registration Page: http://hpca2019.seas.gwu.edu/registration.html

The 25th International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field.

HPCA-25 will be held at Marriott Marquis Washington, D.C., in conjunction with the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP-2019), the 17th International Symposium on Code Generation and Optimization (CGO-2019) and the 10th International Conference on Compiler Construction (CC-2019).

KEYNOTES:
Feb. 18 (Monday): Srini Devadas, MIT, “Towards Secure High-Performance Computer Architectures”
Feb. 19 (Tuesday): Karin Strauss, Microsoft Research
Feb. 20 (Wednesday): Michael O’Boyle, University of Edinburgh, “Rethinking Compilation in a Heterogeneous World”

WORKSHOPS & TUTORIALS
Workshops & Tutorials will take place on Saturday and Sunday from Feb. 16 to Feb. 17. Please note that workshops/tutorials are not included with the main conference registration. If you would like to attend the workshops/tutorials, but are not attending the general conference, please select the appropriate “Workshop/Tutorials” option only during the registration process.

Workshop Information
– The 5th Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB 2019)
– The 2nd workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications(EMC2-2019)
– The 2nd Workshop on Accelerators Architecture for Computational Biology and Bioinformatics (AACBB-2019)
– The 1st Workshop on Heterogeneous Computation in Specific Domain Accelerations (HCSDA-2019)
– The 1st Young Architect Workshop (YArch-2019)
– Built-in Security: Architecture, Chip and System (SecArch-2019)
– Workshop on Architectures and Systems for Autonomous Devices (ASAD-2019)

Tutorial Information
– FPGA-based Accelerated Cloud Computing with SDAccel
– MAERI-Enabling Rapid Design Space Exploration and Prototyping of DNN Accelerators
– BigDataBench: A Scalable and Unified Big Data and AI Benchmark Suite
– Device, Circuit, and Architecture Challenges for Super Conducting Chips
– Principles of Secure Processor Architecture Design

TECHNICAL SESSIONS:
Please check the session information page. http://hpca2019.seas.gwu.edu/main_program.html

SPONSORS:
Technical Sponsors: IEEE
Industry Sponsors: IMO Ventures, Huawei, Bitmain, Intel, AMD, Qualcomm,
Facebook, IBM, Microsoft, Alibaba, VMWare

ORGANIZERS:
General Co-chairs:
Ahmed Louri (GWU)
Guru Prasadh Venkataramani (GWU)

Program Co-chairs:
Rajeev Balasubramonian (Utah)
Vijayalakshmi Srinivasan (IBM Corp.)


Call for Participation: CGO 2019
http://cgo.org/cgo2019/
Submitted by Jagadish Kotra

International Symposium on Code Generation and Optimization (CGO)
co-located with PPoPP, HPCA and CC
Washington DC, USA
February 16-20, 2019

Early registration deadline: January 31, 2019

The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

This year’s conference includes a strong technical program, keynote talks, 7 workshops, and 1 tutorial.

List of accepted papers: http://cgo.org/cgo2019/accepted/
List of workshops and tutorials: http://cgo.org/cgo2019/acceptedWorkshopTutorial/

Registration site: http://cgo.org/cgo2019/registration/


Call for Participation: Workshop on Accelerator Architecture in Computational Biology and Bioinformatics
https://aacbb-workshop.github.io
Submitted by Roman Kaplan

2nd Workshop on Accelerator Architecture in Computational Biology and Bioinformatics
in conjunction with HPCA 2019
Washington DC, USA
February 16, 2019

Over the last decade, the advent of high-throughput sequencing techniques brought an exponential growth in biosequence database sizes. With increased throughput demand and popularity of computational biology tools, reducing time-to-solution during computational analysis has become a significant challenge in the path to scientific discovery. Conventional computer architecture is proven to be inefficient for computational biology and bioinformatics tasks. For example, aligning even several hundred DNA or protein sequences using progressive multiple alignment tools consumes several CPU hours on high performance computer. Hence, computational biology and bioinformatics rely on hardware accelerators to allow processing to keep up with the increasing amount of data generated from biology applications.

In a typical application, dominant portion of the runtime is spent in a small number of computational kernels, making it an excellent target for hardware acceleration. The combination of increasingly large datasets and high performance computing requirements make computational biology prime candidate to benefit from accelerator architecture research. Potential directions include 3D integration, near-data processing, automata processing, associative processing and reconfigurable architectures.

Topics of interest:
– Impact of bioinformatics and biology applications on computer architecture research
– Bioinformatics and computational biology accelerator architecture and design
– 3D memory-logic stack based accelerators
– Automata processing in bioinformatics and computational biology applications
– Associative processing in bioinformatics and computational biology applications
– Near-data (in-memory) acceleration bioinformatics and computational biology applications
– Emerging memory technologies and their impact on bioinformatics and computational biology
– Embedded and reconfigurable architectures
– Field programmable logic based accelerators
– Bioinformatics and computational biology-inspired hardware/software trade-offs
– Software acceleration of computational biology and bioinformatics

Keynote talks by: Bill Dally (Stanford & NVIDIA), Onur Mutlu (ETH & CMU).
We will also have an invited talk by Ananth Kalyanaraman (WSU).
Full schedule can be found in Workshop’s website: https://aacbb-workshop.github.io/


Call for Participation: Workshop on Emerging Deep Learning Accelerators
http://workshops.inf.ed.ac.uk/edla/
Submitted by José Cano

1st Workshop on Emerging Deep Learning Accelerators (EDLA)
in conjunction with the HiPEAC 2019 Conference
January 21, 2019
Valencia, Spain

Early Registration Deadline: December 25, 2018

Deep Learning is receiving much attention these days due to remarkable performance achieved in several fields (e.g. Computer Vision, Speech, Translations, etc), although this brings some challenges to hardware architects and computation optimization researchers. Deep Learning models are generally very large in memory and require many computation instructions to train and perform inferences. Accelerating these operations has obvious advantages, first by reducing the energy consumption (e.g. in data centers) and secondly, making these models usable on smaller devices at the edge of the Internet. This workshop on Emerging Deep Learning Accelerators (EDLA) is intended to bring together researchers from academia and industry to discuss requirements, opportunities, challenges and next steps in developing novel approaches for accelerating deep neural networks. The timing of this workshop is ideal, with European regulations tightening data privacy, thus forcing more computations/inferences to be performed at the Edge.

WORKSHOP PROGRAM:

14:00–14:05 Welcome (José Cano, Valentin Radu)

14:05–15:00 Keynote: Milliwatt Human-Quality Speech Recognition (Antonio González, Universitat Politècnica de Catalunya, Barcelona, Spain)

15:00–15:30 Paper presentations

Exploring NEURAghe: A Highly Parameterized APSoC-based CNN Inference Accelerator (15 min)
(Paolo Meloni, Alessandro Capotondi, Deriu Gianfranco, Michele Brian, Francesco Conti, Davide Rossi, Daniela Loi, Marco Carreras, Luigi Raffo and Luca Benini)

Towards Mapping Lift to Deep Neural Network Accelerators (15 min)
(Naums Mogers, Aaron Smith, Dimitrios Vytiniotis, Michel Steuwer, Christophe Dubach and Ryota Tomioka)

15:30–16:00 Coffee break

16:00–17:30 Paper presentations

Energy Efficient Binarized Neural Networks with Adaptive Voltage and Frequency scaling (20 min)
(Jose Nunez-Yanez)

A Streaming Deep Learning Accelerator with Selective Binarization (20 min)
(Sumanta Chaudhuri, Xuecan Yang, Laurence Likforman and Lirida Naviner)

AI Accelerator Latencies in Hybrid Vehicular Simulation (20 min)
(Jussi Hanhirova, Vesa Hirvisalo, Anton Debner and Matias Hyyppä)

Towards efficient mapping of BNNs onto embedded targets using Tensorflow/XLA (15 min)
(Christoph Gratl, Manfred Mücke, Günther Schindler and Holger Fröning)

AI Pipeline – bringing AI to you (15 min)
(Miguel de Prado, Jing Su, Rozenn Dahyot, Rabia Saeed, Lorenzo Keller and Noelia Vallez)

17:30–17:30 Closing remarks (José Cano, Valentin Radu)

ORGANIZERS:
José Cano – University of Glasgow
Valentin Radu – University of Edinburgh
David Gregg – Trinity College Dublin
Nuria Pazos – University of Applied Sciences (HES-SO)
Elliot Crowley – University of Edinburgh
Miguel de Prado – ETH Zurich
Jack Turner – University of Edinburgh
Andrew Mundy – ARM Research
Tim Llewellynn – NVISO


Call for Participation: Workshop on ACM SIG Heritage

Submitted by Sarita Adve

Workshop on ACM SIG Heritage
Minneapolis, Minnesota, USA
May 20-21, 2019

The Association for Computing Machinery, founded in 1947, is the oldest and largest educational and scientific society dedicated to the computing profession, and today has more than 100,000 members around the world. The ACM History Committee is sponsoring a SIG Heritage workshop to help diffuse knowledge of professional archival practices into ACM’s membership and to others with an active interest in preserving our computer heritage/history.

Applications are invited to a one-and-a-half day workshop to be held 20-21 May 2019 at the Charles Babbage Institute (CBI) in Minneapolis, Minnesota. For each successful application, one person’s expenses for workshop travel, lodging, and meals will be paid by the ACM History Committee.

This is a hands-on workshop with detailed examples. The workshop will be kept small to maximize hands-on aspects and personal interaction. At most 20 attendees.

Who should attend?
ACM members and others who are planning or actually doing SIG history/heritage (archiving/documentation/oral history/publishing) projects. The workshop should be of special interest to ACM officers and staff, SIG leaders, historically minded ACM members, and others working on SIG history projects. Priority will be given to ACM members and members of other national computer societies affiliated to the ACM, but others who are actively engaged in preserving ACM SIG-related history are also encouraged to apply.

Workshop activities include:
a) presentations on basic SIG history preservation, including identification, ACM support, priorities, assessment, and example projects; privacy and legal issues; preparing for public deposit
b) hands-on individual exploration of CBI holdings, including ACM records
c) short presentations on each attendee’s SIG heritage project/plans, with group discussion
d) CBI archival cavern tour
e) ample networking time, including lunches and workshop dinner

Participants will leave with a “tool kit” of practical, useful procedures as well as insight into other SIG heritage techniques, projects, and practices.

Applicants should send a 2-page CV as well as a 250-word project description that
– explains the significance of the existing or planned archiving/history project and its importance;
– describes the archiving/history project’s raw materials including types of images, documents, reports, publications, oral histories (including format of digital materials)
– affirms the applicant’s willingness to make a short presentation to the workshop and participate fully in its day and a half agenda

The ACM History Committee will fund accepted invitees (travel, hotel, meals).

SUBMISSION GUIDELINES:
Applications are due by February 1, 2019.
Applications should be submitted as a single pdf-format document to history-webmaster@acm.org. Notification of project acceptance will be made within six weeks.

Questions about the workshop or requests for clarification may be directed, at any time, to history-webmaster@acm.org.


Call for Papers: ASAP 2019
https://asap2019.csl.cornell.edu/
Submitted by Zhenman Fang

30th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
New York, USA
July 15-17, 2019

IMPORTANT DATES:
Submission deadline: April 8, 2019
Decision notification: May 6, 2019
Camera ready version: May 29, 2019

The 30th IEEE International Conference on Application-specific Systems, Architectures and Processors 2019 will take place in Cornell Tech, New York, United States.

The history of the event traces back to the International Workshop on Systolic Arrays, organized in 1986 in Oxford, UK. It later developed into the International Conference on Application Specific Array Processors. With its current title, it was organized for the first time in Chicago, USA in 1996. Since then it has alternated between Europe and North-America. The conference will cover the theory and practice of application-specific systems, architectures, and processors. The 2019 conference will build upon traditional strengths in areas such as computer arithmetic, cryptography, compression, signal and image processing, network processing, reconfigurable computing, application-specific instruction-set processors, and hardware accelerators.

Topics of interest (but not limited to):
– Big data analytics
– Cloud computing infrastructures and acceleration
– Heterogeneous computing in data centers
– Accelerating data center workloads
– FPGA-based deep learning
– Embedded systems and domain-specific solutions (digital media, gaming, automotive applications)
– Accelerating genomic computations
– Acceleration of data analytics
– Reconfigurable computing in the IoT era
– Applications in finance
– Wireless and mobile systems
– Application-aware controller synthesis
– Emerging technologies (optical models, 3D Interconnects, devices)
– Reconfigurable accelerators
– Hardware and software architectures for cyber-physical systems
– Distributed systems & networks
– Critical issues (security, energy efficiency, fault-tolerance)
– Autonomous and semi-autonomous large-scale CPS
– Autonomic computing systems
– High-level design methods (hardware/software co-design, compilers)
– Simulations and prototyping (performance analysis, verification tools)
– Socio-technical systems

SUBMISSION GUIDELINES:
All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. Manuscript for full paper should not exceed 8 single-space, double-column pages using 10-point size font on 8.5×11 inch pages (IEEE conference style) including references, figures, and tables. Manuscript for short papers should not exceed 4 single-space, double-column pages. Manuscripts for posters should not exceed 2 single-spaced, double-column pages. Submitted papers should not have appeared in or be under submission for a different workshop, conference or journal. It is also expected that all accepted papers (full, short or poster) will be presented at ASAP by one of the authors. Accepted full and short papers will be included in the proceedings and published in IEEE Xplore. Failure to present will result in the removal of the submission from the proceedings before publication. All papers must be submitted electronically in PDF format.

Submission website: https://asap2019.csl.cornell.edu/submission/

ORGANIZERS:
General Chair: Zhiru Zhang, Cornell University
Program Chair: Yun (Eric) Liang, Peking University
Publicity Chair: Zhenman Fang, Xilinx/Simon Fraser University
Finance Chair: Jieming Yin, AMD Research
Sponsorship Chair: Guojie Luo, Peking University
Local Chair: Bo Yuan, Rutgers University


Call for Papers: Workshop on High-Level Parallel Programming Models and Supportive Environments
http://hosting.cs.vt.edu/hips2019
Submitted by Neha Gholkar

The 24th International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS)
in conjunction with IPDPS 2019
Rio de Janeiro, Brazil
May 20, 2019

The 24th HIPS workshop, to be held as a full-day meeting on May 20th at the IEEE IPDPS 2019 conference in Rio de Janeiro, Brazil, focuses on high-level programming of multiprocessors, compute clusters, and massively parallel machines. Like previous workshops in the series, which was established in 1996, this event serves as a forum for research in the areas of parallel applications, language design, compilers, runtime systems, and programming tools. It provides a timely and lightweight forum for scientists and engineers to present the latest ideas and findings in these rapidly changing fields. In our call for papers, we especially encouraged innovative approaches in the areas of emerging programming models for large-scale parallel systems and many-core architectures.

Topics:
– Programming models for heterogeneous compute capabilities and deep memories
– Languages and runtime support for multi-science/coupled codes
– New programming languages and constructs for exploiting parallelism/locality
– Experience with and improvements for existing parallel languages and run-time
environments such as MPI, OpenMP, Cilk, UPC, Co-array Fortran, X10, Chapel,
Charm++, and OpenCL
– Parallel compilers, programming tools, and environments
– Parallelism in emerging fields such as analytics, cloud, and machine learning
– (Scalable) tools for power & performance analysis, modeling, monitoring, and
debugging and core correctness
– OS and architectural support for parallel programming and debugging
– Software and system support for extreme scalability including fault tolerance
and power-aware HPC
– Programming environments for heterogeneous multicore systems and accelerators
such as GPUs, FPGAs, and MICs
– Performance portability in heterogeneous parallel programming environment
– Performance Reproducibility in HPC: tools for quantifying and minimizing
performance variability

SUBMISSION GUIDELINES:
HIPS 2019 accepts two types of submissions:

1. Full papers (10 pages max)
Submission deadline: Jan 22, 2019
Notification of acceptance: Feb 8, 2019
Camera-ready papers due: Feb 26, 2019

2. Short papers (4 pages max)
Submission deadline: Jan 29, 2019
Notification of acceptance: Feb 19, 2019
Camera-ready papers due: Feb 26, 2019

Submissions are handled through the EasyChair conference management system: https://www.easychair.org/conferences/?conf=hips2019

ORGANIZERS:
Workshop Co-chairs:
Neha Gholkar, Intel – Santa Clara, CA
Changhee Jung, Virginia Tech – Blacksburg, VA

Program Committee:
Sriram Krishnamoorthy, Pacific Northwest National Laboratory
Devesh Tiwari, Northeastern University
Barry Rountree, Lawrence Livermore National Laboratory
Qingrui, Liu Xilinx
Simone Atzeni, NVIDIA
Pedro Valero-Lara, The University of Manchester
Xu Liu, College of William and Mary
Shuaiwen Song, Pacific Northwest National Laboratory
Bin Ren, College of William and Mary
Seyong Lee, Oak Ridge National Laboratory
Dongyoon Lee, Virginia Tech
Joachim Protze, RWTH Aachen University
Thomas Scogland, Lawrence Livermore National Laboratory
Yun Liang, Peking University
Ryan Grant, Sandia National Laboratories
Tapasya Patki, Lawrence Livermore National Laboratory
Allen Malony, University of Oregon
Uday Khedker, IIT Bombay
Mitsuhisa Sato, RIKEN
Mark Hoemmen, Sandia National Laboratories


Call for Papers: GPGPU 2019
https://insight-archlab.github.io/gpgpu.html
Submitted by Ashutosh Pattnaik

12th Workshop on General Purpose Processing Using GPU (GPGPU 2019)
in conjunction with ASPLOS 2019
Providence, RI, USA
April 13, 2019

IMPORTANT DATES:
Papers due: February 4, 2019
Notification: March 4, 2019 (note: early bird registration for ASPLOS’19 is March 22)
Final paper due: March 18, 2019

The goal of this workshop is to provide a forum to discuss new and emerging general-purpose programming architectures, environments, and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. This year’s workshop is particularly interested in security, new heterogeneous architecture or platforms, new forms of concurrency, and novel or irregular applications that can leverage these platforms.

Papers are being sought on many aspects of GPUs or accelerators, including (but not limited to):
– GPU applications
– GPU programming environments
– GPU runtime systems
– GPU compilation
– GPU architectures
– Multi-GPU systems
– GPU power/efficiency
– GPU reliability
– GPU benchmarking/measurements
– Heterogeneous architectures/platforms
– GPU security (NEW)
– Non-von Neumann architectures (NEW)
– Domain-specific architectures (NEW)

SUBMISSION GUIDELINES:
Full paper submissions must be in PDF format for US letter-size paper. They must not exceed 10 pages (all inclusive) in standard ACM two-column conference format (preprint mode, with page number). Templates for ACM format are available for Microsoft Word, and LaTeX can be found here. The submission site will be up soon.

ORGANIZERS:
Adwait Jog (co-chair), College of William & Mary
Onur Kayiran (co-chair), AMD Research
Ashutosh Pattnaik (submission/web chair), Penn State

Please contact the organizers if you have any questions.

HISTORY AND IMPACT
David Kaeli (Northeastern) and John Cavazos (Delaware) very successfully organized the previous versions of the GPGPU workshop. GPGPU workshop was first held in 2007 at Northeastern University. In 2008, the meeting was held with ASPLOS 2008. This trend continued and the GPGPU workshop was held with ASPLOS for the next 6 years. From 2015 and 2018, GPGPU workshop was co-located with PPoPP. GPGPU 2019 workshop returns to ASPLOS. The average citation count (as per Google Scholar), for a GPGPU workshop paper, is currently 37.5, where there have been 8 influential papers with 100+ citations.


Call for Papers: FastPath: Workshop on Performance Analysis of Machine Learning Systems
https://tinyurl.com/2019-FastPath
Submitted by Erik Altman

FastPath: International Workshop on Performance Analysis of Machine Learning Systems
in conjunction with ISPASS 2019
Madison, Wisconsin, USA
March 24, 2019

FastPath 2019 brings together researchers and practitioners involved in cross-stack hardware/software performance analysis, modeling, and evaluation for efficient machine learning systems. Machine learning demands tremendous amount of computing. Current machine learning systems are diverse, including cellphones, high performance computing systems, database systems, self-driving cars, robotics, and in-home appliances. Many machine-learning systems have customized hardware and/or software. The types and components of such systems vary, but a partial list includes traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators, hybrid systems, converged infrastructure, and IT appliances. Designing efficient machine learning systems poses several challenges.

These include distributed training on big data, hyper-parameter tuning for models, emerging accelerators, fast I/O for random inputs, approximate computing for training and inference, programming models for a diverse machine-learning workloads, high-bandwidth interconnect, efficient mapping of processing logic on hardware, and cross system stack performance optimization. Emerging infrastructure supporting big data analytics, cognitive computing, large-scale machine learning, mobile computing, and internet-of-things, exemplify system designs optimized for machine learning at large.

FastPath seeks to facilitate the exchange of ideas on performance optimization of machine learning/AI systems and seeks papers on a wide range of topics including, but not limited to:
– Workload characterization, performance modeling and profiling of machine learning applications
– GPUs, FPGAs, ASIC accelerators
– Memory, I/O, storage, network accelerators
– Hardware/software co-design
– Efficient machine learning algorithms
– Approximate computing in machine learning
– Power/Energy and learning acceleration
– Software, library, and runtime for machine learning systems
– Workload scheduling and orchestration
– Machine learning in cloud systems
– Large-scale machine learning systems
– Emerging intelligent/cognitive system
– Converged/integrated infrastructure
– Machine learning systems for specific domains, e.g., financial, biological, education, commerce, healthcare

SUBMISSION GUIDELINES:
Prospective authors must submit a 2-4 page extended abstract electronically at: https://easychair.org/conferences/?conf=fastpath2019

Authors of selected abstracts will be invited to give a 30-min presentation at the workshop.

IMPORTANT DATES:
Submission: February 8, 2019
Notification: February 22, 2019
Final Materials / Workshop: March 24, 2019

ORGANIZERS:
General Chair:
Erik Altman

Program Committee Chairs:
Zehra Sura
Parijat Dube


Call for Papers: Embedded Systems Week 2019
https://www.esweek.org
Submitted by Lars Bauer

Embedded Systems Week (ESWEEK)
New York City, USA,
October 13 – 18, 2019

Embedded Systems Week (ESWEEK) is the premier event covering all aspects of embedded systems and software. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), a special IoMT Day, a symposium (NOCS), and hot-topic workshops and tutorials, ESWEEK presents attendees a wide range of topics unveiling the state of the art in embedded systems design and HW/SW architectures.

Registered attendees are entitled to attend sessions of all conferences CASES, CODES+ISSS, EMSOFT, and the IoMT Day. Symposia, workshops, and tutorials require separate registration.

IMPORTANT DATES:
Journal Track:
– Abstract Submission: April 5, 2019
– Full Paper Submission: April 12, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Work-in-Progress Track:
– Paper Submission: June 7, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Workshop Proposals: April 18, 2019
Tutorial Proposals: April 30, 2019
Special Session Proposals: April 30, 2019

SUBMISSION GUIDELINES:
ESWEEK 2019 continues a dual publication model comprising the Journal track and the Work-in-Progress (WiP) track. Journal track papers, which are full-length (10-page) papers describing mature work, will be published in the ACM Transactions on Embedded Computing Systems (TECS). The WiP track papers, which are short (2-page) papers representing not-yet-mature but promising research, will be published in the ESWEEK proceedings and will be listed as regular publications within the IEEE and/or ACM digital libraries. Authors of WiP papers have the opportunity to publish the extended form of their work in any conference or journal they prefer. Journal and WiP papers are mutually exclusive, i.e., a work can only be in submission in one of the two tracks.
For more information, please refer to: https://www.esweek.org/author-information

* CASES: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
CASES is a premier forum where researchers, developers and practitioners exchange information on the latest advances in compilers and architectures for high-performance, low-power embedded systems. The conference has a long tradition of showcasing leading edge research in embedded processor, memory, interconnect, storage architectures and related compiler techniques targeting performance, power, predictability, security, reliability issues for traditional and emerging applications. In addition, we invite innovative papers that address design, synthesis, and optimization in heterogeneous and accelerator-rich architectures.
https://esweek.org/sites/default/files/2019-CASES-cfp_0.pdf

CASES Program Chairs:
Akash Kumar, Technical University of Dresden, DE
Partha Pande, Washington State University, US

* CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis
The International Conference on Hardware/Software Codesign and System Synthesis is the premier event in system-level design, modeling, analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hardware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design. High-quality original papers will be accepted for oral presentation followed by interactive poster sessions.
https://esweek.org/sites/default/files/CODES%2BISSS-2019-CFP.pdf

CODES+ISSS Program Chairs:
Sudeep Pasricha, Colorado State University, US
Roman Lysecky, Arizona State University, US

* EMSOFT: International Conference on Embedded Software
The ACM SIGBED International Conference on Embedded Software (EMSOFT) brings together researchers and developers from academia, industry, and government to advance the science, engineering, and technology of embedded software development. Since 2001, EMSOFT has been the premier venue for cutting-edge research in the design and analysis of software that interacts with physical processes, with a long-standing tradition for results on cyber-physical systems, which compose computation, networking, and physical dynamics.
https://esweek.org/sites/default/files/EMSOFT2019_CfP_0.pdf

EMSOFT Program Chairs:
Sriram Sankaranarayanan, University of Colorado Boulder, US
Timothy Bourke, Inria Paris, FR

* IoMT: Internet of Medical Things
The Internet of Medical Things (IoMT) paves the foundations for intelligent and reliable personalized precision medicine. Grounded in the mathematical and physical modeling of human anatomy and physiology, it offers accurate multiscale medical monitoring through smart sensing, enabling continuous diagnosis via on-fly communication with medical experts. It provides hyperspectral and hyperdimensional processing and restores health through patient-specific actuation. The IoMT special day provides a forum for academic and industry representatives from areas such as medical and bio-engineering and embedded systems to discuss innovative ideas and solutions for precise personalized medicine. Sub-missions to the IoMT day are via the three conferences.
https://esweek.org/iomt/about

IoMT Chairs:
Insup Lee, University of Pennsylvania, US
Paul Bogdan, University of Southern California, US

* Call for Workshop Proposals
ESWEEK 2019 will host several workshops on Oct. 17/18th. ESWEEK workshops are excellent opportunities to bring together researchers and practitioners from different communities to share their experiences in an interactive atmosphere.
We invite you to submit workshop proposals on any topic related to the broad set of research, education, and application areas in embedded systems before the deadline of April 18, 2019.
https://esweek.org/sites/default/files/ESWEEK2019_CfP_1.pdf

Workshop Chair:
Laura Pozzi, USI Lugano, CH

* Call for Tutorial Proposals
ESWEEK 2019 is looking for high-quality tutorials that will take place on Oct. 13th. Tutorials offer a unique opportunity where presenters can interact with attendees and attendees can gain in-depth knowledge on specific topics. Tutorials on all topics related to embedded system design, analysis and development are welcome and can be either half or full day, lecture style or hands on.
We invite you to submit tutorial proposals before the deadline of April 30, 2019.

* Call for Special Session Proposals
ESWEEK 2019 will host several special sessions. They should cover hot, contemporary topics that are complementary to regular sessions and can constitute individual presentations, panels or other formats. Participants of each accepted special session will have the opportunity to co-author an overview paper (maximum 10 pages) of the session, published in the ESWEEK proceedings. We invite you to submit special session proposals on any topic related to the broad areas of interest of the conference or beyond before the deadline of April 30, 2019.
https://esweek.org/sites/default/files/ESWEEK2019_CfP_1.pdf

Tutorials and Special Sessions Chair:
Andreas Gerstlauer, University of Texas Austin, US

ESWEEK ORGANIZERS:
Petru Eles, Linköping University, SE
Tulika Mitra, National University of Singapore, SG (Vice General Chair)
Soonhoi Ha, Seoul National University, KR (Past Chair)

ESWEEK Local Arrangement Chairs:
Ramesh Karri, New York University, US
Siddarth Garg, New York University, US

www.esweek.org


Call for Papers: Workshop on High-Level Parallel Programming Models and Supportive Environments
http://hosting.cs.vt.edu/hips2019/
Submitted by Changhee Jung

24th International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS 2019)
in conjunction with IPDPS 2019
Rio de Janeiro, Brazil
May 20, 2019

The 24th HIPS workshop, to be held as a full-day meeting on May 20th at the IEEE IPDPS 2019 conference in Rio de Janeiro, Brazil, focuses on high-level programming of multiprocessors, compute clusters, and massively parallel machines. Like previous workshops in the series, which was established in 1996, this event serves as a forum for research in the areas of parallel applications, language design, compilers, runtime systems, and programming tools. It provides a timely and lightweight forum for scientists and engineers to present the latest ideas and findings in these rapidly changing fields. In our call for papers, we especially encouraged innovative approaches in the areas of emerging programming models for large-scale parallel systems and many-core architectures.

Topics:
– Programming models for heterogeneous compute capabilities and deep memories
– Languages and runtime support for multi-science/coupled codes
– New programming languages and constructs for exploiting parallelism/locality
– Experience with and improvements for existing parallel languages and run-time environments such as MPI, OpenMP, Cilk, UPC, Co-array Fortran, X10, Chapel, Charm++, and OpenCL
– Parallel compilers, programming tools, and environments
– Parallelism in emerging fields such as analytics, cloud, and machine learning
– (Scalable) tools for power & performance analysis, modeling, monitoring, and debugging and core correctness
– OS and architectural support for parallel programming and debugging
– Software and system support for extreme scalability including fault tolerance and power-aware HPC
– Programming environments for heterogeneous multicore systems and accelerators such as GPUs, FPGAs, and MICs
– Performance portability in heterogeneous parallel programming environment
– Performance Reproducibility in HPC: tools for quantifying and minimizing performance variability

SUBMISSION GUIDELINES:
HIPS 2019 accepts two types of submissions:

1. Full papers (10 pages max)
Submission deadline: Jan 22, 2019
Notification of acceptance: Feb 8, 2019
Camera-ready papers due: Feb 26, 2019

2. Short papers (4 pages max)
Submission deadline: Jan 29, 2019
Notification of acceptance: Feb 19, 2019
Camera-ready papers due: Feb 26, 2019

Submissions are handled through the EasyChair conference management system:
https://www.easychair.org/conferences/?conf=hips2019

More information at http://cs.vt.edu/hips2019/

ORGANIZERS:
Workshop Co-chairs:
Neha Gholkar, Intel – Santa Clara, CA
Changhee Jung, Virginia Tech – Blacksburg, VA

Program Committee:
Sriram Krishnamoorthy, Pacific Northwest National Laboratory
Devesh Tiwari, Northeastern University
Barry Rountree, Lawrence Livermore National Laboratory
Qingrui, Liu Xilinx
Simone Atzeni, NVIDIA
Pedro Valero-Lara, The University of Manchester
Xu Liu, College of William and Mary
Shuaiwen Song, Pacific Northwest National Laboratory
Bin Ren, College of William and Mary
Seyong Lee, Oak Ridge National Laboratory
Dongyoon Lee, Virginia Tech
Joachim Protze, RWTH Aachen University
Thomas Scogland, Lawrence Livermore National Laboratory
Yun Liang, Peking University
Ryan Grant, Sandia National Laboratories
Tapasya Patki, Lawrence Livermore National Laboratory
Allen Malony, University of Oregon
Uday Khedker, IIT Bombay
Mitsuhisa Sato, RIKEN
Mark Hoemmen, Sandia National Laboratories


Call for Posters: ISPASS 2019
https://www.ispass.org/ispass2019/
Submitted by Thomas Wenisch

2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
Madison, WI, USA
March 24-26, 2019

IMPORTANT DATES:
Extended poster abstract submission: January 25, 2019
Notification: February 1, 2019

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software. ISPASS 2019 will be held March 24 through 26, 2019 in Madison, WI. Authors are invited to submit ongoing or late breaking research, tools or benchmarks extended poster abstracts in any of the following fields:

1) Performance and power evaluation methodologies
– Analytical modeling
– Statistical approaches
– Tracing and profiling tools
– Simulation techniques
– Hardware (e.g., FPGA) accelerated simulation
– Hardware performance counter architectures
– Power, temperature, variability and/or reliability models for computer systems
– Microbenchmark-based hardware analysis techniques
2) Foundations of performance and power analysis
– Metrics
– Bottleneck identification and analysis
– Visualization
3) Power and performance analysis of commercial and experimental hardware
– Multithreaded, multicore and many-core architectures
– Accelerators and graphics processing units
– Memory systems, including storage-class memory
– Embedded and mobile systems
– Enterprise systems and data centers
– Supercomputers
– Computer networks
4) Power and performance analysis of emerging workloads and software
– Software written in managed languages
– Virtualization and consolidation workloads
– Internet-sector workloads
– Embedded, multimedia, games, telepresence
– Deep learning and convolutional neural networks
5) Application and system code tuning and optimization
6) Confirmations or refutations of important prior results

In addition to ongoing or late breaking research, the conference is an ideal forum to publicize new tools and benchmarks to the community. These extended poster abstracts, which can detail tools and benchmarks in any of the above fields of interest, will be judged primarily on their potential impact and use rather than on their research contribution.

See http://www.ispass.org for details.

SUBMISSION GUIDELINES:
ISPASS 2019 extended poster abstract submission website: https://easychair.org/conferences/?conf=ispass2019posters

Please make sure that your submission satisfies all the requirements listed below.
– The extended poster abstract must be original material that has not been previously published in another conference or journal, nor is currently under review by another conference or journal. Note that you may submit material presented previously at a workshop without copyrighted proceedings.
– The content of the submission is limited to two (2) 8.5″x11″ single-spaced double-column pages using 10 pt or larger font, excluding references. Submissions that exceed the length limit or deviate from the formatting requirements may be rejected without review.
– References must list all authors for any reference with fewer than 10 co-authors. Complete author lists facilitate the review process.
– Do not omit references to provide anonymity, as this leaves the reviewer unable to grasp the context. Instead, if you reference your own work, do it in third person, as if you were referencing someone else’s research.
– Your submission must be formatted in such a way that it is clear to understand (including plots and diagrams) with a black-and-white print-out.
– The extended poster abstract must be submitted in PDF format. We cannot accept any other format, and we must be able to print the document just as we receive it.
– We strongly suggest that you use only the four widely-used printer fonts: Times, Helvetica, Courier, and Symbol.
– You may use IEEE Conference templates (http://www.ieee.org/conferences_events/conferences/publishing/templates.html), as long you use the conference version of the template and follow the formatting requirements above.


SIGARCH 2019 Elections

Submitted by Sarita Adve

The SIGARCH 2019 elections nominating committee is delighted to announce the following slate of candidates for the upcoming SIGARCH elections.

Chair:
Babak Falsafi
Gabe Loh

Vice-chair:
Natalie Enright Jerger
Mattan Erez

Treasurer:
Rajeev Balasubramonian
Karin Strauss

Director (4 positions):
Yungang Bao
Abhishek Bhattacharjee
Reetupurna Das
Joel Emer
Boris Grot
Martha Kim
Jose Martinez
Andreas Moshovos
Tim Sherwood
Tom Wenisch

Our thanks to all the candidates who stepped up for this service!

All SIGARCH members should receive another email from ACM with the above slate and describing the process to nominate additional candidates by petition according to SIGARCH bylaws.

Respectfully,

Sarita Adve
Norm Jouppi
David Wood


AutomataZoo: a Benchmark Suite for Automata Processing
https://github.com/hplp/AutomataZoo
Submitted by Tommy Tracy II

AutomataZoo

High performance automata processing engines are traditionally evaluated against a limited set of regular expression rulesets. These serve as valid, real-World example use cases, but they only represent a small proportion of all automata-based applications. With the recent availability of architectures and software frameworks for automata processing, many new applications have been discovered that benefit from automata processing. These demonstrate a broad variety of characteristics that differ from prior regular expression-based applications and warrant their own benchmarks.

We released an earlier benchmark suite, ANMLZoo, in 2016 to fulfill this need. We have improved upon ANMLZoo with AutomataZoo [Wadden et al., IISWC 2018] in the following ways:

– The suite of benchmarks is no longer standardized to a particular architecture, and does not inherit the same architectural biases as ANMLZoo.
– The benchmarks implement full kernels, which allows for comparisons between automata and non-automata approaches.
– The suite includes open-source tools for generating benchmark automata and inputs of various sizes, allowing for design space explorations.

BENCHMARKS:
– Snort: A widely used network intrusion detection system.
– ClamAV: A virus-detection tool that relies on a publicly-available database of malware patterns.
– Protomata: An automata-based application that searches for a set of 1309 protein motif patterns from the PROSITE database.
– Brill Tagging: A rule-based approach to part-of-speech tagging.
– Random Forest: A machine learning model based on ensembles of decision trees.
– Hamming Distance: A string-scoring kernel that accepts inputs that are within a set hamming distance of a configured pattern.
– Levenshtein Distance: A string-scoring kernel that accepts inputs that are within a set edit distance of a configured pattern.
– Sequence Matching: An automata application that counts sorted sequences of item sets to identify frequently-occurring sets.
– Entity Resolution: An automata application that attempts to find duplicate entries in a streaming database.
– CRISPR/Cas9: An automata application that enabled gene editing by identifying targeted locations.
– YARA: An automata application that discovers malware described in the YARA malware pattern description language.
– File Carving: An automata application that identifies files in a stream of input bytes.
– Pseudo Random Number Generation (PRNG): An automata application that models Markov Chains with finite automata to generate high-throughput PRNG streams.

The benchmark suite can be found here: https://github.com/hplp/AutomataZoo

[Wadden et al., IISWC 2018] Wadden, J., Tracy II, T., Sadredini, E., Wu, L., Bo, C., Du, J., Wei, Y., Wallace, M., Udall, J., Stan, M., and Skadron, K. “ANMLZoo: A Benchmark Suite for Exploring Bottlenecks in Automata Processing Engines and Architectures.” 2018 IEEE International Symposium on Workload Characterization (IISWC’18). IEEE, 2018.

We hope this new benchmark suite will fulfill your current and future research efforts related to automata computing.


Announcement: ACM Digital Library usage
http://www.acm.org/publications/acm-author-izer-service
Submitted by Natalie Enright Jerger

The SIGARCH EC would like to encourage further use of the ACM Digital library (dl.acm.org) by our members. Downloading papers published in SIGARCH-sponsored conferences from the ACM DL provides a revenue stream back to SIGARCH. This revenue stream supports existing programs such as student travel grants and allows SIGARCH to develop new programs to further support its members. Please use the ACM DL in your research and use the ACM Authorizer to post ACM DL links to your own papers on your website (http://www.acm.org/publications/acm-author-izer-service). To encourage use of the ACM DL, we will be highlighting the top 10 papers from SIGARCH (co-)sponsored conferences downloaded over the last 6 weeks in each monthly SIGARCH newsletter. Happy reading!

Top 10 Downloaded papers in SIGARCH-sponsored publications (as of Jan 3, 2019):

1. In-Datacenter Performance Analysis of a Tensor Processing Unit – 2017, ISCA
Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia,Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau,Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho,Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary,Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan,Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg,Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon
Downloaded 226 times

2. Secure remote sensing and communication using digital pufs – 2014, ANCS
Teng Xu, James Bradley Wendt, Miodrag Potkonjak
Downloaded 206 times

3. 3D Localization for Sub-Centimeter Sized Devices – 2018, SenSys
Rajalakshmi Nandakumar, Vikram Iyer, Shyamnath Gollakota
Downloaded 188 times

4. Minimal and maximal exposure path algorithms for wireless embedded sensor networks – 2003, SenSys
Giacomino Veltri, Qingfeng Huang, Gang Qu, Miodrag Potkonjak
Downloaded 152 times

5. PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory – 2016, ISCA
Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie
Downloaded 137 times

6. TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory – 2017, ASPLOS
Mingyu Gao, Jing Pu, Xuan Yang, Mark Horowitz, Christos Kozyrakis
Downloaded 135 times

7. ProvChain: A Blockchain-based Data Provenance Architecture in Cloud Environment with Enhanced Privacy and Availability – 2017, CCGrid
Xueping Liang, Sachin Shetty, Deepak Tosh, Charles Kamhoua, Kevin Kwiat, Laurent Njilla
Downloaded 120 times

8. The gem5 simulator – 2011, CAN
Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, David A. Wood
Downloaded 119 times

9. Improving the future by examining the past: ACM Turing Award Lecture – 2010, ISCA
Charles P. Thacker
Downloaded 107 times

10. CapBand: Battery-free Successive Capacitance Sensing Wristband for Hand Gesture Recognition – 2018, SenSys
Hoang Truong, Shuo Zhang, Ufuk Muncuk, Phuc Nguyen, Nam Bui, Anh Nguyen, Qin Lv, Kaushik Chowdhury, Thang Dinh,Tam Vu
Downloaded 103 times


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Boris Grot
SIGARCH Content Editor

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