This is the 1st August 2018 Digest of SIGARCH Messages. (Items posted after the newsletter sent on Friday, July 6, 2018 at 7:54 PM)

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Call for Workshops/Tutorials: IISWC 2018 Workshops/Tutorials/Panels
Submitted by Nandhini Chandramoorthy

IEEE International Symposium on Workload Characterization (IISWC)
Workshops/Tutorials/Panels/Special Sessions
Raleigh, North Carolina, USA
September 30 – October 2, 2018

Researchers from both academia and industry are invited to submit proposals for Tutorials, Panels, and Special Sessions for the IISWC 2018. See below for each specific call. Proposals must be sent via e-mail to the Workshop/Tutorials Chair (Arkaprava Basu ). While submitting a proposal, please indicate whether the proposal is for a tutorial, panel, or special session.

– Tutorial/Panel/Special Session proposals due: August 10, 2018 (23:59 GMT)
– Acceptance notification: August 13, 2018
– Presentation Material Deadline: September 22, 2018
– Workshop/Tutorials/Panels/Special Sessions date: September 30, 2018 (only one day)

In general, tutorial, panel, and special session proposals will be evaluated in terms of their quality and technical/scientific contribution. Sessions strengthening and/or extending the conference program will be prioritized.

The workshop proposals should focus on the topic areas which are of interest to the IISWC audience as described in the call for papers.

The workshop proposal (length limit: 2 pages in 11-point font) should include:
– Title of the workshop
– Organizers and their affiliations
– Sample call for papers
– Duration – Half-Day or Full Day
– If the workshop was previously held, the location (conference), date, and number of attendees

The purpose of tutorials is to educate attendees about specific topics or to provide the background necessary to understand technical advances in relevant areas. The tutorial should be attractive to a wide audience. Possible topics of interest include, but are not limited to emerging workloads, new simulation/profiling infrastructures, evaluation methodologies etc. Tutorial sessions can be proposed for half or full day durations.

The tutorial proposal (length limit: 2 pages in 11-point font) should include:
– Title of the tutorial
– Contact information for the presenter(s) (name, email address, affiliation)
– Keywords
– Short description of the target audience
– A detailed outline of the tutorial
– A short biography of the presenter(s)
– If the tutorial has been offered previously at a conference, provide the conference information (location, date) and number of attendees.

The evaluation of the proposal will include its general interest for IISWC attendees, the quality of the proposal, and the expertise of the presenters. Further, the selected tutorials are expected to adhere to the following guidelines:

Speakers are required to provide tutorial material to the Chair on the dates provided above and prior to the conference.
The symposium will reproduce the tutorial material for the attendees.
The program committee reserves the right to cancel any tutorial if too few attendees are registered for a given tutorial.

Proposals are solicited for panels that will address major topics of interest to IISWC attendees. An ideal panel will not be so broad as to be unfocused or too narrow as to be uninteresting to the majority of the attendees. It will engage a discussion among panelists and attendees with a strategy making focus that can illuminate challenges, new areas of research enquiry, and cross-disciplinary research endeavors for the broader community. Typically panelists will be leading experts in the panel topic or closely related discipline and will offer their opinions, share their insights and be willing to engage the other panelist and audience in debate and interaction.

A special session is devoted to either a traditional core IISWC topic, or a topic of future interest to the audience. An example topic could be workloads for deep learning/machine learning. The session typically consists of 3-4 speakers providing a coherent set of presentations with depth in a specific topic.

A complete submission should list at least three inspiring speakers who can address the various issues within the topic.

Special session proposals require an overall title, abstract for the special session plus a title, short abstract, and name of the speaker (with full contact information and short biography) for each of the proposed talks. Note that the organizer/submitter of the special session may also be a speaker for the session.

Call for Papers: DATE 2019
Submitted by Frank Hannig

Design, Automation and Test in Europe (DATE)
Florence, Italy
Mar 25-29, 2019

Paper submission deadline: Sep 9, 2018

We would like to announce the conference DATE 2019, which will take place from 25 to 29 March 2019 at Firenze Fiera, Fortezza da Basso, in Florence, Italy, and will be chaired by Professor Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany.

Join us in celebrating another exciting edition of the DATE conference – the top scientific event in Design, Automation, and Test of microelectronics and embedded systems for the academic and industrial research communities worldwide!

The Organizing Committee will prepare an exciting and profound conference programme, focusing on areas that are bringing new challenges to the system design community. The DATE conference covers the design process, test, and automation tools for electronics, ranging from integrated circuits to distributed embedded systems. The conference scope includes both hardware and embedded software design issues. It also includes the elaboration of design requirements and new architectures for challenging application fields such as internet of things, multimedia, healthcare, smart energy, and automotive systems.

Topics are arranged according to four tracks:
D – Design Methods & Tools
A – Application Design
T – Test and Dependability
E – Embedded and Cyber-Physical Systems

Two Special Days in the programme will focus on two areas bringing new challenges to the system design community:
Embedded meets Hyperscale and HPC, and
Model-Based Design of Intelligent Systems

The vivid accompanying exhibition provides a unique networking opportunity for vendors of tools and services for hardware and embedded software for the design, development and test of Systems-on-Chip, IPs, Embedded Systems, ASICs, FPGAs and PCBs. Furthermore, it is a great venue for industry representatives to meet university professors to foster their university programmes and especially for PhD students to meet their future employers. A full programme in the Exhibition Theatre will again combine presentations by exhibiting companies, best-practice reports by industry leaders on their latest design projects and selected conference special sessions. Additional hot-spots in the exhibition are the University Booth, where the leading universities and research institutes will present their latest research results with hardware and software demonstrators, as well as the dedicated European Projects Booth and the Exhibition Campus.

The whole DATE Executive Committee cordially invites you to join us at this occasion and welcomes all paper submissions for standard oral presentation or for interactive presentation. Furthermore, it encourages proposals for Special Sessions, Monday Tutorials, Friday Workshops, European Projects, the University Booth, PhD Forum, and Exhibition Theatre.

All papers have to be submitted electronically via the conference web page by Sunday, 9 September 2018.

It is mandatory that each paper shall be accompanied by at least one different full conference registration at the speaker rate (i.e., two speaker registrations are needed for two accepted papers, e.g. from the main author or a co-author of the paper). Furthermore, at least one author of each accepted paper shall attend the conference in person to present the work. In case of no attendance/presentation in person on-site, the paper will be deleted from the proceedings afterwards (despite of full payment at the speaker rate).

To review the official Call for Papers, please click here:

For any questions concerning the technical programme, please contact the Programme Chair Franco Fummi, University of Verona, IT at

Call for Papers: Workshop on Heterogeneous High-performance Reconfigurable Computing
Submitted by Jason D. Bakos

Fourth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)
in conjunction with Supercomputing 2018
Dallas, TX, USA
November 11, 2018

Submission Deadline: August 15, 2018
Acceptance Notification: September 18, 2018
Camera-ready Manuscripts Due: October 15, 2018
Workshop Date: November 11, 2018

As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier to use high-level programming models for FPGAs.

Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now its fourth year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on how newly-available high-level programming models, including OpenCL, are already empowering HPC software developers to directly leverage FPGAs, and to identify future opportunities and needs for research in this area.

H2RC is a half-day Sunday workshop. It will be comprised of:
– Keynote and invited talks
– Talks selected among paper submissions
– Panel discussion on research opportunities and needs

Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance compute architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers. A non-comprehensive list of potential topics of interest is given below:
1. FPGAs in the cloud and data center
2. Cloud and data center applications
3. Leveraging reconfigurability
4. Benchmarks
5. Implementation studies
6. Programming languages, tools, and frameworks
7. Future-gazing
8. Community building

Special theme for 2018:
For this year’s workshop we especially encourage the submission of papers on the topic of FPGA-based support for non-volatile memory and near-memory computing. Non-volatile memory (NVM) technologies such as Flash and Phase-Change memory potentially facilitate shared storage in the microsecond regime. In emerging systems, NVM may serve as a new level of memory hierarchy or as a networked resource. To this end, early work in developing both system-level interfaces to NVM (such as NVMe) and network-level interfaces to NVM (such as RDMA over Converged Ethernet 2) rely heavily on FPGAs as low-latency intermediaries.

Prospective authors are invited to submit relevant contributions as an extended abstract in ACM SIG Proceedings format of up to four pages.

You can submit your contribution(s) through a link on the H2RC website:

The authors of accepted papers will be invited to present their work at the workshop.

Michaela Blott, Xilinx
Franck Cappello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Jason D. Bakos, University of South Carolina

Call for Papers: CGO 2019
Submitted by Adwait Jog

International Symposium on Code Generation and Optimization (CGO)
co-located with PPoPP and HPCA
Washington DC, USA
Feb 16-20, 2019

The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

Abstract Submission: August 31, 2018
Paper Submission: Sept 7, 2018
Artifact Submission: Sept 22, 2018
Author Rebuttal Period: Oct 15-17, 2018
Paper Notification: Oct 30, 2018

Original contributions are solicited on, but not limited to, the following topics:
– Code Generation, Translation, Transformation, and Optimization for performance, energy, virtualization, portability, security, or reliability concerns, and architectural support
– Efficient execution of dynamically typed and higher-level languages
– Optimization and code generation for emerging programming models, platforms, domain-specific languages
– Dynamic/static, profile-guided, feedback-directed, and machine learning based optimization
– Static, Dynamic, and Hybrid Analysis for performance, energy, memory locality, throughput or latency, security, reliability, or functional debugging
– Program characterization methods
– Efficient profiling and instrumentation techniques; architectural support
– Novel and efficient tools
– Compiler design, practice and experience
– Compiler abstraction and intermediate representations
– Vertical integration of language features, representations, optimizations, and runtime support for parallelism
– Solutions that involve cross-layer (HW/OS/VM/SW) design and integration
– Deployed dynamic/static compiler and runtime systems for general purpose, embedded system and Cloud/HPC platforms
– Parallelism, heterogeneity, and reconfigurable architectures
– Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA
– Compiler support for vectorization, thread extraction, task scheduling, speculation, transaction, memory management, data distribution and synchronization

Authors should carefully consider the difference in focus with the co-located conferences when deciding where to submit a paper. CGO will make the proceedings freely available via the ACM DL platform during the period from two weeks before to two weeks after the conference. This option will facilitate easy access to the proceedings by conference attendees, and it will also enable the community at large to experience the excitement of learning about the latest developments being presented in the period surrounding the event itself.

The Artifact Evaluation process is run by a separate committee whose task is to assess how the artifacts support the work described in the papers. To ease the organization of the AE committee, we kindly ask authors to indicate at the time they submit the paper, whether they are interested in submitting an artifact, should the paper be accepted. Artifacts must be submitted within 15 days after paper submission. This submission is voluntary, but reproducible artifacts may influence the final decision regarding the papers. Papers that go through the Artifact Evaluation process successfully will receive a seal of approval printed on the papers themselves. Additional information is available on the CGO AE web page. Authors of accepted papers are encouraged to make these materials publicly available upon publication of the proceedings, by including them as “source materials” in the ACM Digital Library.

General Chair:
Mahmut Taylan Kandemir, Penn State

Program Chairs:
Alexandra Jimborean, Uppsala University
Tipp Moseley, Google

Workshop and Tutorials Chair:
Xipeng Shen, North Carolina State University

Artifact Evaluation Chairs:
Bruce Childers, University of Pittsburgh
Luis Oliveria, University of Pittsburgh

Student Research Competition Chair:
Jagadish Kotra, AMD

Student Travel Grants Chair:
Jack Sampson, Penn State

Publicity Chair:
Adwait Jog, The College of William and Mary

Sponsorship Chair:
Zehra Sura, IBM

Proceedings Chair:
Jennifer Sartor, Vrije Universiteit Brussel and Ghent University

Treasurer/Finance Chair:
Zheng Zhang, Rutgers University

Registration Chair:
Mila Dalla Preda, University of Verona

Web Chair:
Gang Tan, Penn State

Steering Committee:
Aaron Smith, Microsoft Research
Carol Eidt, Microsoft
Fabrice Rastello, Inria
Jack W. Davidson, University of Virginia
Jason Mars, University of Michigan
Kunle Olukotun, Stanford University
Michael O’Boyle, University of Edinburgh
Scott Mahlke, University of Michigan
Teresa Johnson, Google
Vijay Janapa Reddi, University of Texas at Austin

Program Committee:
Aaron Smith, Microsoft
Albert Cohen, Inria
Antoniu Pop, University of Manchester
Apan Qasem, AMD/Texas State University
Ayal Zaks, Intel Haifa
Ben Zorn, Microsoft Research
Bettina Heim, Microsoft
Carol Eidt, Microsoft
Changhee Jung, Virginia Tech
Chen Ding, University of Rochester
Christophe Dubach, University of Edinburgh
Derek Bruening, Google
Dongyoon Lee, Virginia Tech
Erven Rohou, INRIA Rennes
Evelyn Duesterwald, IBM
Gregory Diamos, NVidia
Grigori Fursin, Dividiti/ctuning
Guilherme Ottoni, Facebook
Guoyang Chen, Alibaba Group US Inc
Hiroshi Inoue, IBM Japan
Jeronimo Castrillon, Technical University of Dresden
Jingling Xue, UNSW
Michael Carbin, MIT
Michel Steuwer, UK
Naila Farooqui, NVidia
Peng Wu, Huawei
Rafael Auler, Unicamp
Rajkishore Barik, Startup
Robert Cohn, Intel
Santosh Nagarakatte, Rutgers
Sebastian Hack, University of Saarland
Simone Campanoni, Northwestern University
Taewook Oh, Facebook
Tatiana Shpeisman, Google
Teresa Johnson, Google
Tobias Grosser, ETH Zurich
Tomofumi Yuki, Inria
Walter Binder, University of Lugano (USI)
Xu Liu, College of William and Mary
Yufei Ding, UC Santa Barbara

Call for Papers: PPoPP 2019
Submitted by Matt Sinclair

24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)
collocated with HPCA-2019 and CGO-2019
Washington DC, USA
Feb 16 – 20, 2019

– Paper registration and abstract submission: August 13, 2018
– Full paper submission: August 20, 2018
– Author response period: October 28–November 1, 2018
– Author Notification: November 15, 2018
– Artifact submission to AE committee: November 23, 2018
– Artifact notification by AE committee: December 20, 2018
– Final paper due: January 4, 2019

All deadlines are at midnight anywhere on earth (AoE), and are firm.

PPoPP is the premier forum for leading work on all aspects of parallel programming, including theoretical foundations, techniques, languages, compilers, runtime systems, tools, and practical experience. In the context of the symposium, “parallel programming” encompasses work on concurrent and parallel systems (multicore, multi-threaded, heterogeneous, clustered, and distributed systems; grids; datacenters; clouds; and large scale machines). Given the rise of parallel architectures in the consumer market (desktops, laptops, and mobile devices) and data centers, PPoPP is particularly interested in work that addresses new parallel workloads and issues that arise out of extreme-scale applications or cloud platforms, as well as techniques and tools that improve the productivity of parallel programming or work towards improved synergy with such emerging architectures.

Specific topics of interest include (but are not limited to):
– Compilers and runtime systems for parallel and heterogeneous systems
– Concurrent data structures
– Development, analysis, or management tools
– Fault tolerance for parallel systems
– Formal analysis and verification
– High-performance / scientific computing
– Libraries
– Middleware for parallel systems
– Parallel algorithms
– Parallel applications and frameworks
– Parallel programming for deep memory hierarchies including nonvolatile memory
– Parallel programming languages
– Parallel programming theory and models
– Parallelism in non-scientific workloads: web, search, analytics, cloud, machine learning
– Performance analysis, debugging and optimization
– Programming tools for parallel and heterogeneous systems
– Software engineering for parallel programs
– Software for heterogeneous architectures
– Software productivity for parallel programming
– Synchronization and concurrency control

Papers should report on original research relevant to parallel programming and should contain enough background materials to make them accessible to the entire parallel programming research community. Papers describing experience should indicate how they illustrate general principles or lead to new insights; papers about parallel programming foundations should indicate how they relate to practice.

PPoPP submissions will be evaluated based on their technical merit and accessibility. Submissions should clearly motivate the importance of the problem being addressed, compare to the existing body of work on the topic, and explicitly and precisely state the paper’s key contributions and results towards addressing the problem. Submissions should strive to be accessible both to a broad audience and to experts in the area.

Please see the call for papers for details about submitting a paper:

Jeff Hollingsworth, General Chair, University of Maryland, USA
Idit Keidar, Program Chair, Technion – Israel institute of technology, Israel
Todd Gamblin, Financial Chair, Lawrence Livermore National Laboratory, USA
Michael Lam, Web Chair, James Madison University, United States
Torsten Hoefler, Publicity Chair, ETH Zurich, Switzerland
Sally McKee, Industry Liason
Richard Vuduc, Publicity Chair (Americas), Georgia Tech
Rio Yokota, Publicity Chair (Asia)

VTA: An Open, Customizable Deep Learning Acceleration Stack
Submitted by Thierry Moreau

The Versatile Tensor Accelerator (VTA) is an extension of the TVM framework designed to advance deep learning and hardware innovation. VTA is a programmable accelerator that exposes a RISC-like programming abstraction to describe compute and memory operations at the tensor level. We designed VTA to expose the most salient and common characteristics of mainstream deep learning accelerators, such as tensor operations, DMA load/stores, and explicit compute/memory arbitration.

VTA is more than a standalone accelerator design: it’s an end-to-end solution that includes drivers, a JIT runtime, and an optimizing compiler stack based on TVM. The current release includes a behavioral hardware simulator, as well as the infrastructure to deploy VTA on low-cost FPGA hardware for fast prototyping. By extending the TVM stack with a customizable, and open source deep learning hardware accelerator design, we are exposing a transparent end-to-end deep learning stack from the high-level deep learning framework, down to the actual hardware design and implementation. This forms a truly end-to-end, from software-to-hardware open source stack for deep learning systems.

VTA is a component of TVM, which was a research project at the SAML group of Paul G. Allen School of Computer Science & Engineering, University of Washington. The project is now driven by an open source community involving multiple industry and academic institutions. The project adopts Apache-style merit based governance model.

Call for Nominations: 2018 MICRO Test of Time Award
Submitted by Saugata Ghose

MICRO Test of Time Award

Nominations deadline: July 31, 2018

The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the fifth MICRO ToT Award to be given at the International Symposium on Microarchitecture in October 2018, to be held in Fukuoka, Japan. This award recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field.

The award will recognize an influential MICRO paper whose influence is still felt 18-22 years after its initial publication. In other words, the award will be given to at most one paper that was published at MICRO conferences in any of the years N-22, N-21, N-20, N-19, or N-18. This year, N = 2018, so only papers published at MICRO conferences held in 1996, 1997, 1998, 1999, or 2000 are eligible. An eligible paper that has received at least 100 citations (according to Google Scholar) is automatically nominated, but explicit nominations of such papers are still encouraged.

To nominate a paper, send an email to by July 31, 2018, with the following:
1. The title, the author list, and publication year of the nominated paper
2. A 100-word (maximum) nomination statement, describing why the paper deserves the Test of Time Award
3. The name, title, affiliation of the nominator, and if appropriate, the relationship of the nominator to the authors

Only one paper can be nominated in a single email. There is a maximum of five nominations per person. You cannot nominate a paper that you are a co-author on. One paper will be selected as the award winner from the pool of nominees by the award committee. The award committee members are Tor Aamodt, Pradip Bose (committee chair), Reetuparna Das, Daniel Jiménez, and Onur Mutlu.

For more information on the nomination and selection process, a list of all eligible papers, prior award winners, and other information, please visit