This is the 1st May 2024 digest of SIGARCH Messages.

In This Issue

Call for Papers: CogArch @ ISCA 2024 - (Note: The Call for Paper type has not been set for this item!)

Call for Papers: XTensor @ ASPLOS 2024 - (Note: The Call for Paper type has not been set for this item!)

Call for Papers: ICCD 2024 - (Note: The Call for Paper type has not been set for this item!)


Call for Nominations: Call for Nominations: ACM SIGARCH Maurice Wilkes Award
https://www.sigarch.org/benefit/awards/acm-sigarch-maurice-wilkes-award
Submitted by Martha Kim

The award is given annually for an outstanding contribution to computer architecture made by an individual whose computer-related professional career started no more than 20 years prior to the year of the award. The award is presented annually at the International Symposium on Computer Architecture (ISCA) Awards Banquet. This year’s recipient will be invited to accept the award at ISCA 2024.

For full details, including nomination instructions, visit: https://www.sigarch.org/benefit/awards/acm-sigarch-maurice-wilkes-award

Deadline: March 1, 2024


Call for Nominations: Call for Nominations: ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award
https://www.sigarch.org/benefit/awards/acm-sigarch-ieee-cs-tcca-outstanding-dissertation-award/
Submitted by Martha Kim

The SIGARCH/TCCA Outstanding Dissertation award will recognize excellent thesis research by doctoral candidates in the field of computer architecture. Dissertations will be reviewed for technical depth and significance of the research contribution, potential impact on computer architecture, and quality of presentation.

For full details, including nomination instructions, visit: https://www.sigarch.org/benefit/awards/acm-sigarch-ieee-cs-tcca-outstanding-dissertation-award/


Call for Participation: PAW-ATM 2023: Parallel Applications Workshop, Alternatives To MPI+X
https://sourceryinstitute.github.io/PAW/
Submitted by Karla Vanessa Morris Wright

Alternatives to MPI+X are worth exploring as programmer productivity becomes a major component of the time
to science. Alternatives include parallel programming languages (e.g. Chapel, Regent, Fortran 2018), general purpose
libraries (e.g. Charm++, COMPSs, HPX, Legion, UPC++), and domain specific libraries (e.g. Arkouda, Dask, Spark).
With many options to choose from, it is hard for programmers to know which alternative models are appropriate
for their application and for programming model developers to understand the opportunities for improvement.

Through discussion of specific applications, PAW-ATM brings together application experts and programming model
developers to improve applications and models.

Program

9:00 – 9:02 Karla V. Morris Wright, Elliott Slaughter, Engin Kayraklioglu, Irene Moulitsas, Bill Long, and Daniele Lezzi
“PAW-ATM2023 Introduction”

9:02 – 10:00 Survey of Technologies for Developers of Parallel Applications:
Open discussion after presentations on SHMEM, Julia, Swift/T, and cuNumeric
Session Chair: Jan Ciesko – Sandia National Laboratories
Barbara Chapman – Hewlett Packard Enterprise
Justin Wozniak – Argonne National Laboratory
Johannes Blaschke – Lawrence Berkeley National Laboratory
Rohan Yadav – NVIDIA

10:00 – 10:30 Morning Break (30 min)

10:30 – 12:30 Session 1
Session Chair: Henry Monge Camacho – Oak Ridge National Laboratory
10:30 – 10:54 Tom Westerhout and Bradford L. Chamberlain
“Implementing Scalable Matrix-Vector Products for the Exact Diagonalization Methods in Quantum Many-Body Physics”

10:54 – 11:18 Scott Bachman, Rebecca Green, Anna Bakker, Helen Fox, Sam Purkis, and Ben Harshbarger
“High-Performance Programming and Execution of a Coral Biodiversity Mapping Algorithm Using Chapel”

11:18 – 11:42 Jiakun Yan, Hartmut Kaiser, and Marc Snir
“Design and Analysis of the Network Software Stack of an Asynchronous Many-Task System – The LCI Parcelport of HPX”

11:42 – 12:06 Marcin Rogowski, Jeff R. Hammond, David E. Keyes, and Lisandro Dalcin
“shmem4py: High-Performance One-Sided Communication for Python Applications”

12:06 – 12:30 James Psota, and Armando Solar-Lezama
“Pure: Evolving Message Passing to Better Leverage Shared Memory Within Nodes”

12:30 – 2:00 Lunch Break (90 min)

2:00 – 3:00 Session 2
Session Chair: Damian Rouson – Lawrence Berkeley National Laboratory
Distinguished Speaker: Ethan Gutmann – National Center for Atmospheric Research
“Trials, Tribulations and Joys of Developing with Alternative Parallel Frameworks”

3:00 – 3:30 Afternoon Break (30 min)

3:30 – 3:54 Session 3
Session Chair: Engin Kayraklioglu
Julian Bellavita, Mathias Jacquelin, Esmond Ng, Dan Bonachea, Johnny Corbino, and Paul H Hargrove
“symPACK: A GPU-Capable Fan-Out Sparse Cholesky Solver”

3:54 – 5:30 Panel Discussion: Charting a Path to Success with Alternatives to MPI+X
Panel Chair: Michelle Strout – Hewlett Packard Enterprise
Panelists:
Ewa Deelman – University of Southern California
Jonathan Graham – Los Alamos National Laboratory
Ethan Gutmann – National Center for Atmospheric Research
Laxmikant Kale – University of Illinois Urbana-Champaign
George Karypis – University of Minnesota


Call for Participation: I2Q @ ISCA 2024
https://www.epiqc.cs.uchicago.edu/i2q-24
Submitted by Lennart Maximilian Seifert

Tutorial: I too can Quantum (I2Q): Full Stack Fault Tolerant Quantum Computing
Co-located with ISCA 2024
https://www.epiqc.cs.uchicago.edu/i2q-24

Quantum computing is a rapidly evolving field which in recent years has turned its focus to designing and engineering error-corrected, fault-tolerant machines at scale. In this tutorial we will give a thorough overview of the quantum computing stack from the bottom up, discussing various hardware platforms, promising quantum error correction schemes, and high-level applications.
Basic quantum computing knowledge is helpful but not required, therefore our tutorial is ideal for computer science students and researchers of all backgrounds!

Call for Participation: Memory-Centric Computing Systems @ ISCA 2024
https://events.safari.ethz.ch/isca24-memorycentric-tutorial/
Submitted by Tracy Ewen

Memory-Centric Computing Systems Tutorial
In conjuction with ISCA 2024 at Buenos Aires, Argentina
Saturday, June 29

The Memory-Centric Computing Systems tutorial will cover the latest advances in PIM technology, spanning both hardware and software, including novel PIM ideas, different tools and frameworks to conduct PIM research, and programming techniques and optimization strategies for PIM kernels. We will (1) provide an introduction to PIM and the taxonomy of PIM systems, (2) give an overview and a rigorous analysis of existing PIM hardware from industry and academia, (3) provide and describe hardware and software infrastructures that can enable new and experienced researchers to conduct research in PIM systems, and (4) shed light on how to improve future PIM systems for emerging memory-bound workloads. The tutorial will also incorporate invited talks from leading industry and academic researchers in PIM systems.

Website: https://events.safari.ethz.ch/isca24-memorycentric-tutorial/
Livestream : https://www.youtube.com/watch?v=KV2MXvcBgb0

Organizers: Geraldo F. Oliveira, Mohammad Sadrosadati, Ataberk Olgun, Onur Mutlu


Call for Participation: ARCS 2024
https://arcs-conference.org/home
Submitted by Lars Bauer

37th GI/ITG International Conference on Architecture of Computing Systems
May 14-16, 2024, Potsdam, Germany
https://arcs-conference.org

The ARCS conferences series has over 36 years of tradition reporting
leading edge research in computer architecture and operating systems.

High performance computing represents an important tool for tackling
climate change. In many other HPC application fields, the need for
more high computing power has increased enormously in recent years,
especially due to the high demand of AI-specific workloads. The
operation of correspondingly powerful computing systems therefore
represents an increasing problem in terms of energy requirements and
the associated CO2 emissions. HPC is therefore not only part of the
solution to tackling climate change, but also part of the overall
problem.

Heterogeneous computer architectures promise a significant increase
in the energy efficiency of HPC systems. The selection of different
accelerator architectures can contribute significantly to increasing
efficiency, but there is currently a lack of appropriate concepts
for their seamless and scalable integration, as well as the support
through appropriate programming models.

The focus of the ARCS’24 conference will be on novel accelerator
architectures, which are suited for the integration into HPC systems.
This includes fine and coarse grain reconfigurable architectures as
well as new ideas for their integration to achieve higher energy
efficiency as typical homogeneous architectures. In addition, the
topics cover HPC-specific research at the level of computer architec-
tures, runtime and operating systems, design tools and HPC programming
models and algorithms.

In addition to the main conference, ARCS will host special tracks on
Organic Computing and Dependability and Fault Tolerance.

The registration is open! See you in Potsdam!
https://arcs-conference.org/registration
https://arcs-conference.org/local-arrangements

Full program can be found at https://arcs-conference.org/program

– General Chairs
Dietmar Fey, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
Benno Stabernack, Universität Potsdam / Fraunhofer Heinrich Hertz Institut


Call for Participation: SEED 2024

Submitted by Fan Yao

International Symposium on Secure and Private Execution Environment Design (SEED)
Orlando, Florida, USA
May 16 – 17, 2024

Registration link http://seed-symposium.org

The IEEE International Symposium on Secure and Private Execution Environment Design (SEED) is a forum which brings together researchers from the computer architecture and computer security communities into one venue that focuses on the design of architectural and system primitives which provide secure and private execution environments for applications, containers, or virtual machines.   

For more details about the program, please visit the main conference website at: https://seed-symposium.org/2024/

 


Call for Participation: ISPASS 2024
https://ispass.org/ispass2024/
Submitted by Fangjia Shen

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
May 5-7, 2024
Indianapolis, Indiana, USA

Register for the Conference: https://cvent.me/YDklbE
Student travel grants are also open for application until April 19

Hotel room reservation at Marriot: https://book.passkey.com/event/50785988/owner/2211/home
We strongly encourage you to reserve the hotel room as soon as possible. The hotel has a 48-hour cancellation policy. Please book the hotel room by April 15th.

***
Some fun facts about Indianapolis:

  • Indianapolis is called the “Crossroads of America”. It has the most interstate legs in the United States.
  • The Indianapolis Zoo is the only one in the country to be accredited as a zoo, an aquarium, and a botanical garden together – it’s a trinity!
  • Indy is home to the world’s largest Children’s Museum. 
  • Indianapolis is home to the largest single-day sporting event in the world, the Indy 500.
  • Indianapolis hosts one of the only 30 IMAX movie theatres worldwide that could play ‘Oppenheimer’ in its original 70mm film.

Call for Participation: BioSys @ ASPLOS 2024
https://biosys-workshop.github.io/
Submitted by Yatish Turakhia

Inaugural BioSys workshop, Emerging Computer Systems Challenges and Applications in Biomedicine,
In conjuction with ASPLOS 2024 at San Diego.

This workshop presents a unique platform to discuss and explore exciting advancements in hardware accelerators, neural interfaces, machine learning, and web and software tools for biomedical applications.

🗓 Workshop Date: 27th April 2024
📍 Workshop Venue: Hilton La Jolla Torrey Pines, San Diego, CA
🗒 Registration: https://www.asplos-conference.org/asplos2024/attend/#registration
Workshop Website: https://biosys-workshop.github.io/


Call for Participation: gem5 Architecture Simulator Tutorial @ HPCA 2024
https://www.gem5.org/events/hpca-2024
Submitted by Bobby Bruce

6th gem5 Tutorial
In conjunction with HPCA 2024
Register for the tutorial via HPCA’s registration process: https://hpca-conf.org/2024/.
Early registration deadline: February 2nd.

gem5 is the leading open-source computer  architecture simulator, used in computer system design by academia, industry for research, and in teaching. Co-located at HPCA ’24 in Edinburgh Scotland, gem5 developers from UC Davis will be running a tutorial to educate the computer architecture community on using gem5 and how it can utilized in their own work.

This will be a full-day event and focus on teaching those new to gem5 how to use the latest version, v23.1. This tutorial will assume no prior experience using computer architecture simulators and can be considered a “crash course” in using gem5. The tutorial will focus heavily on new features in gem5, such as the gem5 “suites” and other gem5 standard library features, so will also be suitable for those who have used gem5 before but wish to refresh their skills.

The preliminary schedule for this event includes:

* A short history of gem5.
* Overall (software) architecture of gem5.
* Compiling gem5.
* Using SCons and Kconfig.
* Ruby Protocols, ISAs, and other options.
* Introduction to running a gem5 simulation using prebuilt systems
* First time running gem5 and interpreting the output.
* Building a gem5 simulation using stdlib components.
* Simple example to show select statistical outputs.
* Adding `DEBUG` flags to gem5.
* SE-mode vs simulations: Pros, cons, Limitations and use-cases.
* Building an FS mode simulation in the stdlib.
* Creating your gem5 SimObject.
* Structure of gem5 C++ code.
* Writing a simple SimObject.
* Creating your own component, extending from the stdlib.
* Running simulations using your SimObject/component.
* Creating your own stdlib compoent.
* Creating your own ISA instruction.
* gem5 Resources
* Binaries, kernels, and disk images.
* Workloads and suites.
* Contributing to gem5.

For the most up-to-date information on this event going-forward please visit the gem5 Tutorial event page: https://www.gem5.org/events/hpca-2024


Call for Participation: ISCA 2024
https://iscaconf.org/isca2024/
Submitted by Xiaochen Guo

International Symposium on Computer Architecture (ISCA)
June 29 – July 3 2024
Buenos Aires, Argentina

The  is the premier forum for new ideas and experimental results in computer architecture. The conference seeks particularly forward-looking and novel submissions. In 2024, the 51st edition of ISCA will be held in Buenos Aires, Argentina, at the Hilton Buenos Aires during June 29 – July 3, 2024. This is a historic event as ISCA will be held in Latin America for the first time ever. Let’s make history together!

Registration for the conference is now open at: https://www.iscaconf.org/isca2024/attend/register.php

Hotel registration is now open at: https://www.iscaconf.org/isca2024/attend/

For those of you requiring a Visa we strongly encourage to start the process as soon as possible. Visa information is now available at:
https://www.iscaconf.org/isca2024/attend/visa.php

For more details on ISCA 2023, please visit the main conference website at:
https://iscaconf.org/isca2024/

Student travel grants are available, find out the details at: https://www.iscaconf.org/isca2024/attend/travelgrants.php

Companion Assistance Program and the Childcare Travel Support Program are available, find out the details at: https://www.iscaconf.org/isca2024/attend/childcare.php


Call for Participation: gem5 bootcamp 2024
https://www.gem5.org/events/bootcamp-2024
Submitted by Ivana Mitrovic

We are happy to announce the gem5 bootcamp 2024.

The bootcamp spans five full days, featuring an engaging workshop focused on learning gem5. The workshop is designed to be inclusive, assuming no prior experience with gem5. The goal is to equip participants with a strong foundation in gem5 for conducting advanced research in computer architecture.

The schedule accommodates both students and professionals. Students are encouraged to participate for the entire five days, while professionals are targeted for a three-day attendance from Tuesday to Thursday. The first day (Monday) is dedicated to introducing gem5 to students and familiarizing them with the environment. Days 2 through 4 cover more advanced aspects of gem5 development. The final day (Friday) focuses on practical exercises, including writing tests and contributing to gem5.

The workshop will give attendees the opportunity to:

  • Learn how to create SimObjects.
  • Learn how to use the gem5 Standard Library to create simulations.
  • Familiarize themselves with gem5-resources.
  • Understand the gem5 statistics module and how to use it in experiments.
  • Create full system simulations capable of running real-world operating systems and software benchmarks.
  • Network with others in the computer architecture research community.
  • And much, much more!

For the most up-to-date information on this event going-forward please visit the gem5 bootcamp event page: https://www.gem5.org/events/hpca-2024

Feel free to reach out to the organizers (imitrovic@ucdavis.edu), if you have any questions.


Call for Participation: ASPLOS 2024
https://www.asplos-conference.org/asplos2024/
Submitted by Rajiv Gupta

ASPLOS, the ACM International Conference on Architectural Support for Programming Languages and Operating Systems, is the premier academic forum for multidisciplinary computer systems research spanning hardware, software, and their interaction. It focuses on computer architecture, programming languages, operating systems, and associated areas such as networking and storage.
ASPLOS’24 is being held in San Diego, in beautiful Southern California April 27th-May 1st 2024.     Early registration is now open until March 22: you can find the links to register and reserve your hotel room on the conference website: https://www.asplos-conference.org/asplos2024/attend/
Because ASPLOS moved to a three-deadline model, the program will not be finalized with papers under review from the third deadline.  We will be filling in program details as this review process is completed.  Please check the conference website for details: https://www.asplos-conference.org/asplos2024/
On behalf of the organizing committee, we look forward to seeing in San Diego!
Rajiv Gupta and Nael Abu-Ghazaleh
General Chairs, ASPLOS’24

Call for Participation: NVMW 2024
http://nvmw.ucsd.edu/
Submitted by Hung-Wei Tseng

Nonvolatile Memories Workshop (NVMW 2024)
San Diego, California, USA
March 11-12, 2024

Registration for the 2024 Nonvolatile Memories Workshop (NVMW) is now open. The conference will be held March 11-12 in San Diego, CA. Student and postdoc travel grants are available. Please see http://nvmw.ucsd.edu/attending for information about attending and registration.

The 15th Annual Non-Volatile Memories Workshop (NVMW 2024) provides a unique showcase for outstanding research on solid state, non-volatile memories, including devices, error coding, architectures, systems, theory, and applications.

For additional information, please contact the NVMW general chair, Hung-Wei Tseng, at htseng@ucr.edu


Call for Participation: ISFPGA 2024
https://www.isfpga.org/
Submitted by Aman Arora

The 32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
March 3-5, 2024
Monterey, California, USA
http://www.isfpga.or

EARLY REGISTRATION ENDS FEBRUARY 8, 2024
https://www.isfpga.org/registration/
BOOK HOTEL NOW
https://www.isfpga.org/travel/

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for advances in all aspects of FPGA technology. We have a fully in-person conference in Monterey spread over three days, including two keynotes, a banquet, a panel discussion, multiple tutorials, a workshop, paper presentations, and posters.

The preliminary technical program is now available at: https://www.isfpga.org/program/

The conference kicks off Sunday with seven tutorials and one workshop. A social hour at the end of the day will allow guests to network and mingle. The main technical session begins Monday with an opening keynote by Tim Sherwood from University of California, Santa Barbara, followed by paper presentations and a poster session. A banquet will be held in the evening on Monday. The banquet will include an exciting panel discussion, and food and beverages will be served. The program on Tuesday will feature another keynote from P.K. Gupta from Innovex, followed by paper presentations and a poster session. The best paper award ceremony will conclude the conference program Tuesday evening.

Important logistics:

We look forward to seeing you in Monterey!

FPGA 2024 Organizing Committee:

  • General Chair: Zhiru Zhang (Cornell University)
  • Program Chair: Andrew Putnam (Microsoft)
  • Publications Chair: Grace Zgheib (Intel)
  • Finance Chair: Paolo Ienne (EPFL)
  • Workshop Chair: Dustin Richmond (UC Santa Cruz)
  • Workshop Co-Chair: Tyler Sheaves (UC Davis)
  • Website & Publicity Chair: Aman Arora (ASU)

Call for Participation: HPCA 2024
https://www.hpca-conf.org/2024/
Submitted by Christina Giannoula

30th IEEE International Symposium on High-Performance Computer Architecture (HPCA)
H P C A   2 0 2 4 
Edinburgh, UK
March 2 – March 6, 2024
https://www.hpca-conf.org/2024/

The International Symposium on High-Performance Computer Architecture (HPCA) is the premier forum for new ideas and research results in computer architecture. In 2024, the 30th edition of HPCA will be held in Edinburgh, Scotland, UK.

Main Program
The main program is available on our website: https://www.hpca-conf.org/2024/program/main.php It includes outstanding keynotes, a compelling lineup of papers from Monday 4 to Wednesday 6, March 2024. We have also prepared an enjoyable social program at the National Museum of Scotland.

Workshops & Tutorials Program
The workshops and tutorials program is available on our website: https://www.hpca-conf.org/2024/program/workshops-tutorials.php It features cutting-edge sessions on benchmarking and simulation methodologies, as well as the latest advancements in computer architecture and generative AI on Saturday 2 and Sunday 3 March, 2024.

Registration
The registration for HPCA 2024 is officially open: https://www.hpca-conf.org/2024/attend/register.php Take advantage of our early bird pricing until February 2, 2024. If you need an invitation letter, please contact the conference organisers by emailing ieee-acm2024@in-conference.org.uk.

Conference Venue
HPCA 2024 will be held at the Edinburgh International Conference Centre (EICC). The Exchange, 150 Morrison St, Edinburgh EH3 8EE, United Kingdom. EICC is located in the historic center of Edinburgh with numerous hotel, restaurant and sight-seeing options in its immediate vicinity.

Travel & Accomodation
There are many available options for travel and accommodation near the conference venue. Please check out more information in our website: https://www.hpca-conf.org/2024/attend/travelinfo.php

We look forward to seeing you in HPCA 2024!


Call for Participation: FPGA 2024
https://www.isfpga.org/
Submitted by Aman Arora

The 32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
March 3-5, 2024
Monterey, California, USA
http://www.isfpga.org

 EARLY REGISTRATION ENDS FEBRUARY 8, 2024
https://www.isfpga.org/registration/

BOOK HOTEL NOW
https://www.isfpga.org/travel/
  
 

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for advances in all aspects of FPGA technology. We have a fully in-person conference in Monterey spread over three days. Tutorials, presentations, and posters will share the latest research results on many exciting topics. More details of the technical program, along with workshops and tutorials, will be available soon.

Important logistics:

We look forward to seeing you in Monterey!

FPGA 2024 Organizing Committee:

  • General Chair: Zhiru Zhang (Cornell University)
  • Program Chair: Andrew Putnam (Microsoft)
  • Publications Chair: Grace Zgheib (Intel)
  • Finance Chair: Paolo Ienne (EPFL)

Call for Participation: ISCA 2024 Call for Workshops & Tutorials
https://www.iscaconf.org/isca2024/submit/workshops.php
Submitted by Xiaochen Guo

The dates for the workshops/tutorials are June 29-30, 2024. Proposals should be one to two pages long and must include at least the following information:

  • Title of the workshop/tutorial
  • Organizers and their affiliations (including short bios)
  • Expected duration of the workshop/tutorial (i.e., half day or full day)
  • If the workshop/tutorial was previously held, provide the location (i.e., which conference), date, number of published papers (if any), and number of attendees at the last event
  • Expected minimum and maximum number of participants
  • For a workshop proposal, provide a sample call for papers and workshop main topic(s)
  • For a tutorial proposal, provide the abstract of the tutorial

Proposals should highlight a plan for ensuring diversity in invited speakers, tutorial presenters, and organizing and selection committees (if applicable).

Please submit workshop proposals to the Workshops Chair and tutorial proposals to the Tutorials Chair.


Call for Papers: ESWEEK 2024
https://esweek.org/
Submitted by Lars Bauer

EMBEDDED SYSTEMS WEEK
Call for Papers: CASES, CODES+ISSS, EMSOFT, MEMOCODE

About Embedded Systems Week (ESWEEK)
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent and connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), one symposium (MEMOCODE), and several workshops and tutorials, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development.

Registered attendees can attend sessions in any of the ESWEEK conferences (CASES, CODES+ISSS, EMSOFT). Tutorials, symposium
(MEMOCODE), and workshops require can be registered individually or in addition with the ESWEEK registration.

Important Dates

Journal Track:
– Abstract Submission: March 24, 2024 (AoE)
– Full Paper Submission: March 31, 2024 (AoE, firm)
– Notification of Acceptance: July 14, 2024

Work-in-Progress and Late Breaking Tracks:
– Paper Submission: June 02, 2024 (AoE, firm)
– Notification of Acceptance: June 30, 2024

Workshops, Tutorials, Education Classes, and Special Sessions:
– Submission: March 24, 2024

Review Process
ESWEEK has three publication venues:

1. Journal Track: Full-length papers describe mature work and are limited to 12 pages in IEEE double column format. Accepted papers will
be published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) after two stages of
review. Articles not accepted after the second stage will still have the possibility of continuing as regular journal papers in TCAD (pending a decision from the TPC chairs).

2. Late Breaking (LB) Result Track: LB papers disseminate complete and mature works written in a condensed form and are limited to 4 pages in IEEE double column format. Accepted papers will be published in IEEE Embedded Systems Letters (ESL) after one stage of review. Articles not accepted after this stage will still have the possibility of continuing as regular journal papers in ESL (pending a decision from the TPC chairs).

3. Work-in-Progress (WiP) Track: WiP papers present not-yet-mature but promising research work, and are limited to extended abstracts of 1
page in IEEE double column format. Accepted WiP papers will be published in the ESWEEK Proceedings of CASES, CODES+ISSS, or EMSOFT, depending on where they have been submitted.

These three venues are mutually exclusive, i.e., a work can only be in submission to one of the three categories. Authors of WiP papers have the opportunity to publish the extended final form of their work when it has matured in any conference or journal they prefer. Special
Session papers, Keynote/Tutorial abstracts, etc. are also published in the ESWEEK Proceedings of the respective conferences. All these
publications will be listed as regular publications within the ACM and/or IEEE digital libraries. For more information on the publishing process, refer to:

CASES: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems

CASES is a premier forum where researchers, developers and practitioners
exchange information on the latest advances in compilers and
architectures for high-performance, low-power embedded systems. The
conference has a long tradition of showcasing leading edge research
in embedded processor, memory, interconnect, storage architectures
and related compiler techniques targeting performance, power,
predictability, security, reliability issues for both traditional
and emerging application domains. In addition, we invite innovative
papers that address design, synthesis, and optimization challenges
in heterogeneous and accelerator-rich architectures.

CASES Program Chairs:
Jana Doppa, Washington State University, US
Jeronimo Castrillon, TU Dresden, DE

CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis

The International Conference on Hardware/Software Codesign and System Synthesis is the premier event in system-level design, modeling,
analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hard-ware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design.

CODES+ISSS Program Chairs:
Muhammad Shafique, New York University, US
Prabhat Mishra, University of Florida, US

EMSOFT: International Conference on Embedded Software

The ACM SIGBED International Conference on Embedded Software (EMSOFT) brings together researchers and developers from academia, industry, and government to advance the science, engineering, and technology of embedded software development. Since 2001, EMSOFT has been the premier venue for cutting-edge research in the design and analysis of software that interacts with physical processes, with a long-standing tradition for results on cyber-physical systems, which compose computation, networking, and physical dynamics.

EMSOFT Program Chairs:
Alessandro Biondi, Scuola Superiore Sant’Anna, IT
Martina Maggio, Lund University, SW & Saarland University, DE

MEMOCODE: International Symposium on Formal Methods and Models for System Design

MEMOCODE focuses on formal methods and models for developing computer systems and their components. MEMOCODE’s objective is to emphasize the importance of models and methodologies in correct system design and development.

MEMOCODE Program Chairs:
Qi Zhu, Northwestern University, US
Srinivas Pinisetty, IIT Bhubaneswar, IN

Call for Workshop Proposals

ESWEEK 2024 will host several workshops on Thursday October 3rd and Friday October 4th and is soliciting proposals for new and recurring workshops. Workshops can be half-day to two-day long. We invite you to submit workshop proposals on any topic related to the broad set of research and education.

Workshop Chair:
Heiko Falk, TU Hamburg, DE

Call for Tutorial Proposals
ESWEEK 2024 is looking for high-quality tutorials that will take place on Sunday, September 29th, 2024. Tutorials on all topics related to embedded system design, analysis, and development are welcome. Tutorials can be either half/full-day, lecture style or hands-on.

Tutorials Chair:
Christian Pilato, Politecnico di Milano, IT

Call for Education Proposals
ESWEEK 2024 will host several education lectures virtually on Thursday September 26th and Friday September 27th, and is soliciting proposals for such lectures. We invite you to submit education proposals on any topic related to ESWEEK.

Education Chairs:
Anup Das, Drexel University, US
Qingfeng (Karen) Zhege, East China Normal University, CN

Call for Special Session Proposals

We invite you to submit special session proposals on any topic relevant to the broad areas of interest of ESWEEK. The special session should cover a topic that is contemporary, hot, and complementary to the regular sessions. The special session should be able to generate enthusiasm among the ESWEEK participants.

Special Sessions Chair:
Pi-Cheng Hsiu, Academia Sinica, TW

Software Competition

Following their first introduction in 2023, we will host several software competitions. More details will be available soon.

Software competition chairs
Ganapati Bhat, Washington State University, US
Biresh Kumar Joardar, University of Houston, US
Wanli Chang, Hunan University, CN

Panels: Celebrating the 20th ESWEEK conference

The ESWEEK series started in 2005 in Jersey City, so ESWEEK 2024 will be the 20th edition! This will be the occasion of celebrating the best moments with a chosen panel of people who contributed to the past editions. Two panels will be organized in 2024, one devoted to this
celebration, and another one devoted to the complex interrelations between embedded systems and the environmental crisis (which encompasses the climate change, the biodiversity collapse, the mineral resource depletion), where we will bring some answers to the complex issues of whether embedded systems shall be part of the solution to the environmental crisis, or whether they are part of the problem.

Panel chair
Marilyn Wolf, University of Nebraska-Lincoln, US

Organization

ESWEEK 2024 General Chairs:
Alain Girault, Inria & Univ. Grenoble Alpes, FR (General Chair)
Tei-Wei Kuo, National Taiwan University, TW (Vice General Chair)

Conference and Local Arrangement Chair:
Frank Mueller, North Carolina State University, US


Call for Papers: ASAP 2024
http://www.asap2024.org/
Submitted by Suhaib Fahmy

The 35th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2024

Important dates:

Abstracts Due: 21 Mar 2024
Papers Due: 28 Mar 2024
Notification: 2 May 2024
Camera Ready: 29 May 2024

Topics:

  • Accelerator design including for AI, big data, bioinformatics, finance, network processing, compression, image and signal processing, cryptography and security, etc.
  • Application-specific instruction-set processors and architectures
  • Approximate computing
  • Computer arithmetic
  • Emerging architectures: neuromorphic and quantum
  • Cloud computing accelerator
  • Edge computing, wireless, mobile, IoT
  • Cyber-physical, embedded, and autonomous systems
  • Heterogeneous computing: from embedded to HPC systems and data centers
  • Reconfigurable and custom computing (FPGAs, CGRAs, etc.)
  • Design methods, tools, and compilers, domain-specific languages, simulation and prototyping
  • System quality attributes, e.g., energy efficiency, fault tolerance, security, etc.
  • Emerging technologies, e.g., optical computing and communication, 3D devices and interconnects, memristors for storage and logic, in-memory computing

Organizing Committee

General Chair: Prof Ray Cheung, CityU, Hong Kong
General Co-Chair: Prof Wei Zhang, HKUST, Hong Kong
TPC Co Chairs: Prof Florent de Dinechin, INSA, Lyon, France
Prof Martin Herbordt, Boston University, USA
Finance Chair: Prof Shiqi Wang, CityU, Hong Kong
Registration Chair: Prof Donglong Chen, BNU-HKBU United International College, Zhuhai, China
Tutorial Chair: Prof Xin Yao, Guangzhou University, China
Publicity Chair: Prof Suhaib A. Fahmy, KAUST, Saudi Arabia
Local Arrangement Chair: Prof Yao Liu, SYSU, China
Publication Chair: Prof Haoliang Li, CityU, Hong Kong
Sponsorship Chair: Dr Patrick Hung, IEEE HK Computer Chapter, Hong Kong
Webchair: Prof Matthew Tang, Queen Mary University of London, UK
Student Volunteer Chair: Dr Sanka Abdurrashid Ibrahim, CityU, Hong Kong

Please find more information on the conference website: http://www.asap2024.org/


Call for Papers: MICRO 2024
https://microarch.org/micro57/
Submitted by George Tzimpragos

57th IEEE/ACM International Symposium on Microarchitecture – MICRO 2024
November 2 – 6, 2024
Austin, Texas, USA

The IEEE/ACM International Symposium on Microarchitecture® (MICRO) is the premier forum for for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and we aim to continue this tradition at MICRO-57. In 2024, MICRO goes to Austin, Texas, USA.

Important Dates:
Abstract Submission Deadline: April 11, 2024
Full Paper Deadline: April 18, 2024
Notification: July 19, 2024

 

Papers are solicited on a broad range of topics, including (but not limited to):
  • Microarchitectural, architectural, compiler, and hybrid techniques for improving system performance, power, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, or sustainability
  • Processor, memory, and storage architectures
  • Multicore and multiprocessor systems
  • Instruction-, thread-, and data-level parallelism
  • Prediction and Speculation
  • Memory Hierarchy
  • Cloud and datacenter-scale computing
  • IoT, mobile, and embedded architecture
  • Interconnection network, router, and network interface architecture
  • Accelerator-based, application-specific, and reconfigurable architectures
  • Architectural support for programming languages, compilation, software development, security and privacy, virtualization
  • Architectures for emerging technologies and applications
  • Architectural support for non-volatile/persistent memory
  • Quantum computing
  • In-/near-memory or in-/near-storage processing
  • Approximate computing and architectural support for approximation
  • Effects of circuits and technology on architecture
  • Architecture modeling and simulation methodologies
  • Evaluation and measurement of real computing systems

More information on solicited topics is available at https://microarch.org/micro57/submit/papers.php.


Call for Papers: ISMM @ PLDI 2024
https://conf.researchr.org/home/ismm-2024
Submitted by Jae W. Lee

ACM International Symposium on Memory Management (ISMM) 2024 – 
co-located with PLDI 2024

Important changes in ISMM 2024. We are excited to announce an expanded scope of ISMM this year to encourage submissions and participation from related fields such as computer architecture and systems in addition to the PL community!

Call for Papers

The 2024 ACM SIGPLAN International Symposium on Memory Management (ISMM 2024) is soliciting full-length submissions on all memory management related topics in both software and hardware, as well as papers presenting confirmations or refutations of important prior results. In addition to regular papers, traditionally submitted to ISMM, we also invite submissions of the following kinds:

  • Surveys and comparative analyses that shed new light on previously published techniques.
  • Practitioner reports, describing experience with memory management in production. Such papers are not expected to provide novel research contributions, but they should not have been previously published.
  • Intellectual abstracts, where researchers share designs, algorithms, or theory that may be interesting to the memory management community, but not yet evaluated.

Please indicate whether the paper is a regular paper, a survey, a practitioner report, or an intellectual abstract, by using a subtitle. For example, for a regular paper, include on of the following on the line below the title line: subtitle{This submission is a regular paper}, subtitle{This submission is a survey}, subtitle{This submission is a practitioner report}, or subtitle{This submission is an intellectual abstract}.

Important Dates

Paper Submission: March 22, 2024
Author Response Period: April 29-30, 2024
Author Notification: May 10, 2024
Camera-Ready Deadline: May 20, 2024

Areas of Interest

Areas of interest include but are not limited to (with this year’s changes highlighted) :

  • Caches
  • Cache coherence and memory consistency
  • Processing in memory and near memory processing
  • Memory device architectures (SRAM, DRAM, flash, NVM)
  • Security and privacy of memory systems
  • Reliability of memory systems
  • Garbage collection algorithms and implementations
  • Memory allocation and de-allocation
  • Memory system design and analysis
  • Hardware support for memory management
  • Memory management for large-scale data-intensive systems
  • Memory management at datacenter and cloud scales
  • Formal analysis and verification of memory management algorithms
  • Compiler analyses to aid memory management
  • Tools to analyze memory usage of programs
  • Empirical analysis of memory intensive programs
  • Formal analysis and verification of memory intensive programs
  • Memory management for machine learning systems
  • Programming and management of emerging or persistent memories

The symposium welcomes industry practitioners presenting their recent practice and findings in memory management related to real-world deployments.

Submission guidelines can be found at https://conf.researchr.org/home/ismm-2024#Call-for-Papers

Contact Information

PC Co-chairs of ISMM 2024
Jae W. Lee, Seoul National University – jaewlee@snu.ac.kr 
Hannes Payer, Google – hpayer@google.com 


Call for Papers: IISWC 2024
https://iiswc.org/iiswc2024/cfp.html
Submitted by Dmitrii Ustiugov

IEEE International Symposium on Workload Characterization

IISWC invites manuscripts that present original unpublished research in all areas related to the characterization and analysis of computing system workloads, including translational research related to production-oriented commercial systems. Work focusing on emerging technologies and interdisciplinary work are especially welcome. Topics of interest include (but are not limited to) characterization of applications in traditional and emerging domains, characterization of system software and middleware, implications of workloads in system design, benchmarking methodologies and suites, and tools for computer systems. A detailed list of the topics can be found at https://iiswc.org/iiswc2024/cfp.html#topics-of-interest

Important dates:

  • Submission Deadline: June 3, 2024
  • Decision Notification: July 16, 2024
  • Camera-ready Deadline: August 9, 2024

Submission Guidelines

https://iiswc.org/iiswc2024/cfp.html#submission-guidelines

Submissions to IISWC can be made in one of the following two categories: (1) regular papers and (2) tool and benchmark papers. The primary focus of regular papers (submission length: 10 pages, excluding references) should be to describe new research ideas supported by experimental implementation and evaluation of the proposed research ideas. The primary focus of tool and benchmark papers should be to describe the design, development, and evaluation of new open-source tools and benchmarks suites. Submissions in the regular papers category are also encouraged to open-source their software or hardware artifacts.

The authors are required to indicate the category of the paper as a part of the submitted manuscript’s title. On the submission system entry, we ask the authors to add a prefix to the title indicating the type of the submission as follows: 1. regular papers: “Regular-TITLE” and 2. tool and benchmark papers: “Tools-TITLE”.

Papers in the tool and benchmark category with relatively shorter length (6 pages) are welcome if the contributions can be well articulated and substantiated. However, all submissions in the tool and benchmark category have the flexibility of using all 10 pages (excluding references). The submissions in both categories will be evaluated to the same standards in terms of novelty, scientific value, demonstrated usefulness, and potential impact to the field. The nature of the contribution differs between the two categories (new research idea vs. new open-source benchmark-suite / tool) and papers will be evaluated based on the intended nature of the contribution, as declared by the chosen paper category at the time of the submission. The chosen category at the time of the submission cannot be changed after the submission deadline.

Double-blind submission guidelines apply to the submissions in both categories. Open-source benchmarks and tools that have not been previously published (but may have been open-sourced) are eligible for submission in the tool and benchmark papers category.

When including source code links in their submission, we require the authors to use new or anonymized code repositories to preserve the integrity of double-blind review process. All submitted papers should have obtained legal permission (if applicable) to open-source the benchmark-suite / tool at the time of submission.


Call for Papers: PACT 2024
https://pact2024.github.io/index
Submitted by Rajiv Gupta

The International Conference on Parallel Architectures and Compilation Techniques (PACT) is a unique technical conference sitting at the intersection of hardware and software, with a special emphasis on parallelism. The PACT conference series brings together researchers from computer architectures, compilers, execution environments, programming languages, and applications, to present and discuss their latest research results.

PACT 2024 will be held as an in-person event in Long Beach, California, USA. At least one of the authors of accepted papers will be required to attend the conference, and we encourage all the authors to participate.

Specific topics of interest include (but are not limited to):

  • Parallel architectures, including accelerator architectures for AI or other domains
  • Compilers and tools for parallel architectures (as above)
  • Applications and experimental systems studies of parallel processing
  • Computational models for concurrent execution
  • Multicore, multithreaded, superscalar, and VLIW architectures
  • Compiler and hardware support for hiding memory latencies
  • Support for correctness in hardware and software
  • Reconfigurable parallel computing
  • Dynamic translation and optimization
  • I/O issues in parallel computing and their relation to applications
  • Parallel programming languages, algorithms, and applications
  • Middleware and run time system support for parallel computing
  • Application-specific parallel systems
  • Distributed computing architectures and systems
  • Heterogeneous systems using various types of accelerators
  • In-core and in-chip accelerators and their exploitation
  • Applications of machine learning to parallel computing
  • Large scale data processing, including computing in memory accelerators
  • Insights for the design of parallel architectures and compilers from modern parallel applications

PACT for Quantum and Neurmorphic

  • Neuromorphic computing both as an application for and a tool applied to architectures and compilers
  • Quantum computing architectures and compilers.

In addition to the regular research papers, PACT 2024 has a special category of papers called “tools and practical experience” (TPE). Such papers are subject to the same page length guidelines and will be reviewed by the same Program Committee. TPE papers focus on applicability (such as traditional methods employed in emerging fields), exposing challenges and experiences the industry is facing as an opportunity to steer the research. A TPE paper must clearly explain its functionality, provide a summary about the practice experience with realistic case studies, and describe all the supporting artifacts available (if relevant). The selection criteria are:

  • Originality: Papers should present PACT-related technologies applied to real-world problems with scope or characteristics that set them apart from previous solutions.
  • Usability: The presented Tools or compilers should have broad usage or applicability. They are expected to assist in PACT-related research, or could be extended to investigate or demonstrate new technologies. If significant components are not yet implemented, the paper will not be considered.
  • Documentation: The tool or compiler should be presented on a web-site giving documentation and further information about the tool.
  • Benchmark Repository: A suite of benchmarks for testing should be provided.
  • Availability: Preferences will be given to tools or compilers that are freely available (at either the source or binary level). Exceptions may be made for industry and commercial tools that cannot be made publicly available for business reasons.
  • Foundations: Papers should incorporate the principles underpinning Parallel Architectures and Compilation Techniques (PACT). However, a thorough discussion of theoretical foundations is not required; a summary of such should suffice.

Submitting your work

Paper submissions are due March 27, 2024 by posting on the conference submission site. Please make sure that your paper satisfies all the following requirements before being submitted. Submissions not adhering to these submission guidelines will be rejected by the submission system and/or subject to an administrative rejection.

  • Mark TPE papers clearly by preceding their title with “TPE: ” both in the submission site and in the submitted pdf
  • The paper must have an abstract under 300 words.
  • The paper must be original material that has not been previously published in another conference or journal, nor is currently under review by another conference or journal. You may submit material presented previously at a workshop without copyrighted proceedings.
  • The submission is limited to ten (10) pages in the ACM 8.5” x 11” format (US letter size paper) using 9pt font, with no more than 7 lines per inch. This page limit applies to all content NOT INCLUDING references, and there is no page limit for references. Your paper must print satisfactorily on both Letter paper (8.5”x11”) and A4 paper (8.27”x11.69”). The box containing the text should be no larger than 7.15”x9” (18.2cm x 22.9cm). Templates are available on the ACM Author Gateway.
  • Paper submission is double-blind to reduce reviewer bias against authors or institutions. Thus, the submissions cannot include author names, institutions or hints based on references to prior work. If authors are extending their own work, they need to reference and discuss the past work in third person, as if they were extending someone else’s research. We realize that for some papers it will still reveal authorship, but as long as an effort was made to follow these guidelines, the submission will not be penalized.
  • Anonymized supplementary material may be provided in a single PDF file uploaded at paper submission time, containing material that supports the content of the paper, such as proofs, additional experimental results, data sets, etc. Reviewers are not required to read the supplementary material but may choose to do so.
  • Please make sure that the labels on your graphs are readable without the aid of a magnifying glass.
  • The paper must be submitted in PDF. We cannot accept any other format, and we must be able to print the document just as we receive it. We suggest that you use only the four widely used printer fonts: Times, Helvetica, Courier and Symbol.

Poster submissions must conform to the same format restrictions, but may not exceed 2 pages in length. Paper submissions that are not accepted for regular presentations will automatically be considered for posters; authors who do not want their paper considered for the poster session should indicate this in their abstract submission. Two-page summaries of accepted posters will be included in the conference proceedings.


Call for Papers: ASPLOS 2025
https://www.asplos-conference.org/asplos-2025-call-for-papers/
Submitted by Zhibin Yu

Scope and Expectations

The scope of ASPLOS 2025 covers all practical aspects related to the three main ASPLOS disciplines: computer architecture, programming languages, and operating systems, as well as closely-related associated areas. We seek original, high-quality research submissions that improve and further the knowledge of applied computer systems, with emphasis on the intersection between the main ASPLOS disciplines. Research submission may be applicable to computer systems of any scale, ranging from small, ultra-low power wearable devices to large scale parallel computers and data centers. We embrace research that directly targets new problems in innovative ways. The research may target diverse goals, such as throughput, latency, energy, and security. Non-traditional topics are encouraged, and the review process will be sensitive to the challenges of multidisciplinary work in emerging areas. We welcome submission of “experience papers” that have a novel component and that clearly articulate the lessons learned. We likewise welcome submissions whereby novelty lies in furthering our understandings of existing systems, e.g., by uncovering previously unknown, valuable insights or by convincingly refuting prior published results and common wisdom. We value submissions more highly if they are accompanied by clearly defined artifacts not previously available, including traces, original data, source code, or tools developed as part of the submitted work. We particularly encourage new ideas and approaches.

Alphabetically sorted areas of interest related to practical aspects of computer architecture, programming languages, and operating systems include but are not limited to:

  • Existing, emerging, and nontraditional compute platforms at all scales
  • Heterogeneous architectures and accelerators
  • Internet services, cloud computing, and datacenters
  • Memory, storage, networking, and I/O
  • Power, energy, and thermal management
  • Profiling, debugging, and testing
  • Security, reliability, and availability
  • Systems for enabling parallelism and computation on big data
  • Virtualization and virtualized systems

A good submission will typically: motivate a significant problem; propose a practical solution or approach that makes sense; demonstrate not just the pros but also the cons of the proposal using sound experimental methods; explicitly disclose what has and has not been implemented; articulate the new contributions beyond previous work; and refrain from overclaiming, focusing the abstract and introduction sections primarily on the difference between the new proposal and what is already available. The latter statement should be interpreted broadly to also encompass studies that broaden our understanding of existing systems (rather than suggest new ones), which may constitute a significant problem in its own right. Submissions will be judged on relevance, novelty, technical merit, and clarity. Submissions are expected to adhere to SIGPLAN’s Empirical Evaluation Guidelines and all the policies specified below.

Resubmissions

Authors of resubmitted work must describe in a separate note – to be uploaded to the submission site at submission time – the changes since the previous submission(s). This description helps reviewers who may have reviewed a previous draft of the work to appreciate any improvements to the currently submitted work. Please try to limit this document to one page.

Submissions rejected from ASPLOS must not be submitted to the next two subsequent review cycles. The corresponding restrictions on ASPLOS ‘25 submissions are thus:

  • Papers rejected in 2024 Spring, or earlier, are now eligible for resubmission to ASPLOS.
  • Papers rejected in 2024 Summer may not resubmit until ASPLOS 2025 Summer (or later).
  • Papers rejected in 2024 Fall may not resubmit until ASPLOS 2025 Fall (or later).

These resubmission rules are strict and hold even if a submission has undergone extensive revision.

Major Revisions

In addition to Accept and Reject outcomes, ASPLOS 2025 will offer some submissions a “Major Revision” decision. The authors of such submissions will be given the opportunity to apply a major revision to their work and resubmit it at the camera ready deadline (6 weeks from notification). These submissions will be provided with clear and actionable reviewer feedback for their revision, and they will be typically reviewed by the same reviewers as the original submission. If the revision requirements are satisfactorily met, the revised submission will be accepted.

Anonymization

ASPLOS employs a double-blind review process, keeping author identities concealed from reviewers and vice versa. You must therefore make a good faith attempt to anonymize your submission by avoiding identifying yourself or your institution/affiliation in any of the submitted documents (except in specific fields on the HotCRP submission form designated for this purpose), either explicitly or by implication, e.g., through references, acknowledgments, online repositories that are referenced by the submission, or interaction with committee members.

Do not include a “reference removed for blind review” text or similar in your submission. When it is necessary to cite your own studies, cite them as written by a third party.  Only if that is not possible, they can be uploaded and cited as anonymized supplemental material (see below). This applies to workshop papers that are being extended by your current ASPLOS submission, and related submissions of your own that are simultaneously under review or awaiting publication at other venues. Publication as a technical report or in an online repository does not constitute a violation of this policy, and some other exceptions apply; see the “originality and concurrent submissions” section below for details.

Please make sure not to reveal author and/or affiliation information through side channels and other less obvious means. For example, the metadata included in the PDF should not give away such information. If you’d like to point to a repository of, e.g., the working code of your system (which is great and much appreciated), this repository should, of course, be anonymized. It is okay and often makes sense to create anonymized repositories merely for the sake of an anonymous submission. If your system is already released to the public, rename it in your submission. You should likewise avoid inadvertently revealing affiliation in your submission by identifying your company’s name in situations where, e.g., it is clear that the authors of the submission most probably work for the company that manufactures the device or provides the service that constitutes the topic of your work; instead, please use a generic name, like “a computer server vendor X,” “a cloud service provider Y,” and such like.

If concealing system name or affiliation would make your paper difficult to understand, contact the program chairs to discuss exceptions to this policy. Submissions that are not properly anonymized will likely be rejected without review.

Anonymized Supplemental Material

Supplemental material may be submitted as a single-but-separate anonymized PDF file without page limit. The nature of such material is explained in the above “anonymization” section. We permit uploading such material exclusively for the purpose of handling specific anonymity issues.

The submission must be self-contained within the page limit, and the supplemental material mechanism should not be used as a way to circumvent this limit. The reviewers are neither required nor encouraged to read such material when making their decision.

Declaring Conflicts of Interest

Authors must register all their conflicts in their HotCRP submission page. Conflicts are needed to ensure appropriate assignment of reviewers. If a submission is found to have an undeclared conflict that causes a problem or if a paper is found to declare false conflicts in order to abuse or “game” the review system, the submission will be summarily rejected.

Both people and institutions (companies, universities, and other relevant organizations) may be declared as having a conflict of interest (COI) with respect to an author. Please declare a COI with the following for any author of your submission; please do so with respect to all your conflicts, not just restricted to program committee (PC) and extended review committee (ERC) members, as we may occasionally ask for external reviews from people outside the PC/ERC.

  • Your current institution(s) and other institutions that you were affiliated with in the past four years relative to the submission deadline; also, an institution that is about to become your employer.
  • Your PhD advisor(s), post-doctoral host(s), PhD students, and post-doctoral advisees; these COIs are forever.
  • Family relations by blood or marriage and close personal friends (who may potentially be reviewers); these COIs are likewise forever.
  • People with whom you have collaborated in the last four years, including co-authors of accepted/rejected/pending paper submissions and co-PIs of accepted/rejected/pending grant proposals.
  • Potential reviewers who shared your primary institution(s) in the last four years, or where one is actively engaged in discussions about employment with the other person’s institution.
  • When there is a direct funding relationship between an author and a potential reviewer (e.g., the reviewer is a sponsor of an author’s research on behalf of his/her company or vice versa).
  • Among PIs of research structures supported under the same umbrella funding award who (1) participate regularly in non-public meetings sponsored by that umbrella award, and (2) are regularly exposed to presentations or discussions of unpublished work at such meetings.

Do not declare a COI for the following cases:

  • You must not declare a COI with a reviewer just because that reviewer works on topics similar to or related to those in your paper.
  • “Service” collaborations such as co-authoring a report for a professional organization or an open-source community, serving on a program committee, or co-presenting tutorials, do not themselves create a COI.
  • Co-authoring a paper that is a compendium of various projects without direct collaboration among the projects does not constitute a conflict among the authors of the different projects.
  • Internships constitute a conflict of interest during the period of employment of the intern, but not thereafter, unless some other provision applies (e.g., co-authorship or ongoing research collaboration after the internship). Graduate students are not presumed to have an automatic COI with their undergraduate institution. On the other hand, prospective graduate students do have a COI with any institution they have applied to if they are actively engaged in discussions with any faculty member at that institution. Once they join an institution to pursue graduate studies, automatic COIs with any other prospective institutions sunset. In all these cases, the collaboration COI above still applies.

When in doubt, contact the program chairs and ask.

Declaring Authors

Declare all the authors of the submission upfront. Addition/removal of authors once the submission is accepted will have to be approved by the program chairs, since it potentially undermines the goal of eliminating conflicts for reviewer assignment.

Declaring Areas and Topics

ASPLOS emphasizes multidisciplinary research. Submissions should ideally – albeit not necessarily – emphasize synergy of two or more of the three main ASPLOS disciplines: computer architecture, programming languages, and operating systems (broadly interpreted). Authors should therefore indicate at least one of these areas on the submission form and, preferably, more than one.

Authors should also indicate on the submission form more focused topics matching their work, which will be used for reviewer assignment.

Originality and Concurrent Submissions

By submitting a manuscript to ASPLOS, the authors guarantee that the manuscript has not been previously published or accepted for publication in a substantially similar form in any conference, journal, or workshop. The only exceptions are (1) workshops without archived proceedings such as in the ACM digital library (or where the authors chose not to have their paper appear in the archived proceedings), or (2) venues such as IEEE CAL where there is an explicit policy that such publication does not preclude longer conference submissions. These are not considered prior publications. Technical reports and papers posted on public social media sites, web pages, or online repositories such as arxiv.org are not considered prior publications either. In these cases, the submitted manuscript may ignore the posted work to preserve author anonymity.

The authors additionally guarantee that no manuscript that contains significant overlap with the contributions of the submitted document is or will be under review for any other conference, journal, or workshop during the ASPLOS review cycle for which it was submitted. Violation of any of these conditions will lead to rejection and possibly additional actions against the offending authors.

You should also adhere to the ACM Plagiarism Policy (http://www.acm.org/publications/policies/plagiarism_policy), which covers a range of ethical issues concerning the misrepresentation of other works or one’s own work.

As usual, if in doubt, consult with the program chairs.

Ethical and Other Obligations

  • Authors are not allowed to break anonymity when interacting with known ASPLOS PC/ERC members, e.g., by mentioning/identifying work that they plan to submit to ASPLOS or have already submitted and is currently under review.
  • Authors are not allowed to contact reviewers or PC/ERC members in order to encourage or solicit them to bid on any submission; to attempt to sway a reviewer or PC/ERC member to review any submission positively or negatively; to contact reviewers or PC/ERC members requesting any type of information about the reviewing process, either in general or specifically about submitted manuscripts; to contact reviewers or PC/ERC members to ask about the outcomes of any submission.
  • Authors are not allowed to advertise their work during the period starting two weeks before the submission deadline and ending when the results of the review cycle are publicized. The work includes the submission itself and closely related documents such as technical reports or arxiv.org uploads. Advertisement pertains to such communication channels such as social media, community blogs, and web pages. To clarify, authors are indeed allowed to upload their submission to arxiv.org and other such online repositories; the restriction relates to advertising such postings.
  • Authors are not allowed to post in the aforementioned channels about the content of the reviews they may have received until the results of the corresponding review cycle are publicized; “shaming” (and thus potentially applying pressure on) reviewers before the review process terminates is considered unethical.
  • Authors must abide by the ACM ethics policy (https://www.acm.org/code-of-ethics).

Violation of these policies might result in rejection of the submission and possible additional action by the ACM.

ACM requires that all submitting authors will be aware of the following policies in particular:

By submitting your article to an ACM publication, you are hereby acknowledging that you and your co-authors are subject to all ACM Publications Policies, including ACM’s new Publications Policy on Research Involving Human Participants and Subjects. Alleged violations of this policy or any ACM Publications Policy will be investigated by ACM and may result in a full retraction of your paper, in addition to other potential penalties, as per ACM Publications Policy.

Formatting and Editing

We will use the same format template for submission and camera-ready versions. Submissions must be printable PDF files. When creating your submission, you must use the sigplan proceedings template of ACM’s acmart Latex class available on the official ACM site. You may start with the sample file available in this zip file, which will ensure that your submission adheres to the formatting details specified below. Specifically, your main LaTeX file should have the following structure:

    % use the base acmart.cls
    % use the sigplan proceeding template with the default 10 pt fonts
    % nonacm option removes ACM related text in the submission. 
    documentclass[sigplan,nonacm]{acmart}

    % enable page numbers
    settopmatter{printfolios=true}
    
    % make references clickable 
    usepackage[]{hyperref}

    begin{document}
    title{...}

    begin{abstract}
    ...
    end{abstract}

    maketitle % should come after the abstract
    pagestyle{plain} % should come right after maketitle

    % add the paper content here

    % use the plain bibliography style
    bibliographystyle{plain}
    bibliography{...}

Your final submission should visually look similar to this sample produced from the zip file above.

“Squeezing” Space is Forbidden. Refrain from tweaking the aforementioned template and from formatting your text in a manner that violates its settings. Notably, refrain from squeezing additional space, e.g., by using vspace or packages that manipulate vertical space. The template already generates a very dense document, and you must not make it denser. Your submission will be visually and automatically inspected using tools developed for this purpose, and it will be rejected if you violate the formatting policy, even if your PDF passed the HotCRP format check (which is unable to verify much of the requirements).

Page Layout and Limit.  Full submissions must not exceed 11 pages of single-spaced two-column text. This page limit applies to all text, figures, tables, footnotes, appendices, etc. The only exception is the bibliographic references section, which is not included in the page limit. The submission must be self-contained within the page limit, allowing reviewers to evaluate the work without having to consider any external or supplementary material outside this limit. The reviewers greatly value conciseness, so if you can describe your work with fewer pages than the limit, please do. All pages should be numbered.

Page Limit of Accepted Papers and Major Revisions.  The authors of an accepted paper are allowed to use +2 pages in the camera-ready version beyond the aforementioned page limit. The same applies to major revisions, to accommodate added experiments and such. In addition to this +2 automatic page limit increase, authors of accepted papers may purchase 1–2 more pages, if they wish (payment will be processed when registering to the conference).

Font Size, Tables, and Figures.  The submission’s text must use a 10pt font (not 9pt) or bigger. Labels, captions, and text within figures, graphs, and tables must use reasonable font sizes that, as printed, do not require extra magnification beyond “100%” to be legible. In particular, text inside figures/tables should generally use what appears to readers as a 9pt font or bigger after any intra-document scaling has been applied. Fonts appearing smaller than 8pt are not permitted. As noted, this and other requirements are not checked automatically by the HotCRP format checker, so it is the authors’ responsibility to check it. Figures can and should use colors but should also be color-blind friendly and readable when printed in monochrome. Spacing between figures/tables/captions/text should be determined by the latex template.

References.  Because references do not count against the page limit, the space they occupy should not be “optimized” away. Notably, the full, non-abbreviated first and last names of all co-authors of all citations must be specified (no “et al.”). The reference citations within the submission (numbers in square brackets) should be hyperlinked to the corresponding items in the references section, to ease the job of reviewers. Also, reviewers will very much appreciate clickable links (preferably DOIs) associated with each entry in your references section.

Specifications.  The following table specifies some of the main typeset requirements. Use our mandatory latex template and follow the above instructions to make sure that these and other formatting requirements are met.

aspect requirement
file format PDF with numbered pages
page limit 11 pages, not including references
paper size US Letter 8.5in x 11in
top margin 1in
bottom margin 1in
left margin 0.75in
right margin 0.75in
column separation 0.333in
body 2-column, single-spaced
body font size 10pt
abstract font 10pt
section heading font 12pt, bold
subsection heading font 10pt, bold
space between section heading and text ≥ 6pt
caption font 9pt
fonts in figures and tables ≥ 8pt, preferably ≥ 9pt
reference entries 8pt; no page limit; list full names of all author (no “et al.”); include link to document (preferably DOI); make references to citations clickable
appendices count towards the page limit

Submissions that violate any of these restrictions might be rejected without being reviewed.

Author Response Period

ASPLOS 2024 will provide an opportunity for authors to respond to reviews prior to final consideration of the submissions at the program committee meeting; see exact dates specified above. Authors should generally focus their rebuttal on (1) correcting factual errors in the reviews and (2) directly addressing questions posed by reviewers. When a major revision is a realistic possibility, in addition to clarifying the submitted work, rebuttals may describe new experiments and data, if doing so addresses the reviewers’ concerns. Rebuttals are optional but strongly encouraged, and their absence might indicate to reviewers that authors are not interested in improving the work. There is no explicit word limit to a rebuttal, but authors are strongly encouraged to keep it under 1200 words, and reviewers are not expected to read words that exceed this limit. Authors are not allowed to attach files to the rebuttal HotCRP comment.

Accepted Papers

Submissions selected by the program committee will be conditionally accepted, subject to revision and approval by a committee member acting as a shepherd. Accepted papers will be allowed two additional pages in the proceedings (and up to two more with a fee of $200 per page). We expect that one author of each accepted paper will physically attend the conference and present the work in a dedicated time slot (unless all authors have difficulty traveling due to such serious limitations as visa restrictions, care-giving responsibilities, and disability). By default, all accepted papers will be made available online to registered attendees before the conference at a date that depends on the review cycle. Papers accepted to the spring and summer deadlines will be published in separate volumes in advance of the conference.

ACM requires that all authors of accepted papers will adhere to the following policy. Please ensure that you and your co-authors obtain an ORCID ID, so you can complete the publishing process for your accepted paper. ACM has made a commitment to collect ORCID IDs from all published authors to improve author discoverability, ensure proper attribution, and contribute to ongoing community efforts around name normalization; your ORCID ID will help in these efforts.

Artifact Evaluation

Artifact evaluation will continue in 2025 as has become a tradition at ASPLOS. More information will be linked from here when they are available.

Poster and Lightning Sessions

In addition to the regular presentations, the program may include poster and lightning sessions. If those are included, details can be found here when they become available.

Wild and Crazy Ideas Session

The program will also tentatively include a WACI session. Details will become available later.

Debate Session

Should the program include a debate session, details will be posted here.

Best Paper Award

The committee will select a handful of papers to receive a Best Paper Award. The decision may or may not be communicated to the winning authors prior to the official announcement at the opening session of the conference.

Program and Registration

Complete program and registration information will be available on the conference website as soon as it becomes available.

Confidentiality

All submissions will be treated as confidential prior to publication. Rejected submissions will be permanently treated as confidential.

Acknowledgement

Several ideas in this document and parts of the text have been taken from previous conferences, so we thank their program chairs. In particular, Dan Tsafrir and Madan Musuvathi (ASPLOS ‘24), Natalie Enright Jerger and Michael Swift (ASPLOS ’23), Shan Lu and Thomas Wenisch (ASPLOS ’22), Emery Berger and Christos Kozyrakis (ASPLOS ’21), Luis Ceze and Karin Strauss (ASPLOS ’20), Emmett Witchel and Alvy Lebeck (ASPLOS ’19), Dahlia Malkhi and Dan Tsafrir (ATC ’19), Ricardo Bianchini and Vivek Sarkar (ASPLOS ’18), John Carter (ASPLOS ’17), Yuanyuan Zhou (ASPLOS ’16), Sandhya Dwarkadas (ASPLOS ’15), Sarita Adve (ASPLOS ’14), Steve Keckler (ISCA ’14), Margaret Martonosi (ISCA ’13), Onur Mutlu (MICRO ’12), and Michael L. Scott (ASPLOS ’12).

Questions?

Please direct any questions to the program co-chairs at asplos2025pcchairs@gmail.com.


Call for Papers: SYSTOR 2024
https://www.systor.org/2024/cfp/
Submitted by Oleg Kolosov

The ACM International Systems and Storage Conference (SYSTOR) is an international forum for interaction across the systems research community. The program includes innovative, peer-reviewed research papers in the broad area of systems, as well as distinguished keynote lecturers, a poster session, and social events. ACM SYSTOR is designed to engage academic and industrial researchers and practitioners, welcoming both students and seasoned professionals.

Topics:

SYSTOR welcomes academic and industrial papers in systems including storage, cloud and distributed systems, networking, and systems security, broadly construed. SYSTOR encourages submissions that describe results from experimental system prototypes, as well as experience papers describing practical deployments, and valuable lessons learned from them.

This year, we are broadening the scope to also include research on systems issues in AI and/or sustainability, including those that involve workload optimization, data processing, lifecycle of systems, carbon footprint transparency, and system re-designs.

Topics of interest include, but are not limited to:

  • Systems and workload optimization for AI/ML systems
  • Sustainability/carbon footprint of computer and network systems
  • System security and trust
  • Big Data infrastructure
  • Cloud, edge, data center, and distributed systems
  • Embedded and real-time systems
  • Fault tolerance, reliability, and availability
  • File and storage systems
  • Networked, mobile, wireless, peer-to-peer, and sensor systems
  • Operating systems, computer architecture, and their interactions
  • Performance evaluation and workload characterization
  • Runtime systems and compiler/programming-language support
  • System deployment, usage, and experience
  • System design or adaptation for emerging storage technologies
  • Virtualization and containers
  • Storage 3.0

Attendance:

The conference this year will be physical.

By submitting a research paper you agree to make the maximal effort that at least the presenting author will attend in person. However, in case of justifiable circumstances, we may allow a video-recorded presentation with online availability for Q&A.

Highlight papers must be presented in person, therefore by submitting a highlight paper you agree that at least the presenting author will attend in person.

Tracks and Submission Dates:

Full Papers Track – original research, at most 12 pages, excluding references: March 13, 2024

Short Papers Track – original research, at most 5 pages, excluding references: March 13, 2024

Highlight Papers Track – papers accepted at top-tier conferences in 2023:  April 3, 2024

Posters with Extended Abstract Track – original work presented as a poster, accompanied by an extended abstract in the conference proceedings: April 11, 2024

Program Chairs:

Sam Noh (Virginia Tech, USA)
Aviad Zuck (Technion, Israel)

General Chair:

Dalit Naor (The Academic College of Tel Aviv-Yaffo, Israel)
Ofer Biran (IBM Research – Haifa, Israel)


Call for Papers: ARCS 2024: HPC – Challenges for Sustainable Computing
https://arcs-conference.org
Submitted by Lars Bauer

ARCS 2024
37th GI/ITG International Conference on Architecture of Computing Systems
May 14-16, 2024, Potsdam, Germany
https://arcs-conference.org

THIS YEAR’S FOCUS: *HPC – Challenges for Sustainable Computing*

The ARCS conferences series has over 36 years of tradition reporting leading edge research in computer architecture and operating systems.

High performance computing represents an important tool for tackling climate change. In many other HPC application fields, the need for more high computing power has increased enormously in recent years, especially due to the high demand of AI-specific workloads. The
operation of correspondingly powerful computing systems therefore represents an increasing problem in terms of energy requirements and
the associated CO2 emissions. HPC is therefore not only part of the solution to tackling climate change, but also part of the overall problem.

Heterogeneous computer architectures promise a significant increase in the energy efficiency of HPC systems. The selection of different
accelerator architectures can contribute significantly to increasing efficiency, but there is currently a lack of appropriate concepts for their seamless and scalable integration, as well as the support through appropriate programming models.

The focus of the ARCS’24 conference will be on novel accelerator architectures, which are suited for the integration into HPC systems. This includes fine and coarse grain reconfigurable architectures as well as new ideas for their integration to achieve higher energy efficiency as typical homogeneous architectures. In addition, the topics cover HPC-specific research at the level of computer architectures, runtime and operating systems, design tools and HPC programming models and algorithms.

In addition to the main conference, ARCS will host special tracks on Organic Computing and Dependability and Fault Tolerance.

The proceedings of ARCS 2024 will be published in the Springer Lecture Notes on Computer Science (LNCS) series. A best paper and best presentation award will be presented at the conference.

Important Dates
* Paper submission deadline: February 29, 2024
* Notification of acceptance: March 28, 2024
* Camera-ready papers: May 2, 2024
* Conference (in Potsdam, Germany): May 14 – 16, 2024

Topics of Interest
Paper submission: Authors are invited to submit original, unpublished research papers on one or more of the following topics:

**Hardware Architectures**
* HPC-workload specific accelerator architectures
* Reconfigurable architectures
* Advanced computing architectures
* System-on-chip
* Distributed systems
* High performance systems
* Heterogeneous multi- and many-core architectures
* Architectures for real-time and mixed-criticality systems
* Coarse- and fine-grained reconfigurable architectures
* Flexible I/O support
* Advanced computing architectures
* Using new non-volatile memory for energy-efficient architectures
* New smart network technologies (e.g. SmartNICs, SmartSwitches)

**Programming Models and Runtime Environments**
* HPC programming models for heterogeneous computing
* Tools to monitor and to optimize the power consumption of HPC architecture
* Operating systems, programming models, algorithms, and data structures for heterogeneous HPC architectures
* Operating systems, hypervisors and middleware for homogeneous and heterogeneous multi-/many-core computing platforms
* System management including but not limited to scheduling, memory management, power/thermal management, and RTOS
* Domain-specific languages and programming models
* Architecture specific code generation and optimization
* Architectural simulation

**Cross-sectional Topics**
* Near-memory and in-memory computing
* Memory and network compression technologies
* Organic computing
* Pervasive systems
* Autonomous systems
* Approximate Computing
* Mixed-criticality systems
* Support for safety and security
* Hardware in the loop simulations

Submission guidelines
Submissions should be done through the link that is provided on the conference website https://easychair.org/conferences/?conf=arcs2024.
Papers must be submitted in PDF format.

They should be formatted according to Springer LNCS style (see: https://www.springer.com/gp/computer-science/lncs/conference-proceedings-guidelines) and must not exceed 15 pages, including references and figures.

Organizers

General Chairs
Dietmar Fey, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
Benno Stabernack, Universität Potsdam / Fraunhofer Heinrich Hertz Institut

Program Chairs
Stefan Lankes, RWTH Aachen University, Aachen, Germany
Mathias Pacher, Goethe-University Frankfurt, Frankfurt am Main, Germany

Proceedings Chair
Thilo Pionteck, Magdeburg University, Germany

Publicity and Web Chair
Lars Bauer, Karlsruhe Institute of Technology (KIT), Germany
https://arcs-conference.org


Call for Papers: SEED 2024 Wild and Emerging Ideas (WEI)

Submitted by Dongrui Zeng

2024 IEEE International Symposium on Secure and Private Execution Environment Design (SEED)
https://seed-symposium.org/2024/

Wild and Emerging Ideas (WEI) papers are intended for breaking contributions and do not limit the authors from publishing a full paper on the topic in the future. They will appear in the conference proceedings. A submission should include the title and a brief abstract (2 pages total, including references). 

Deadlines

WEI submission deadline: Jan 10th, 2024, 11:59pm AOE

Submission 

The submission website is: https://seed24.hotcrp.com/

Manuscripts must be submitted in printable PDF format and must use the two-column IEEE Proceedings format. References must include all authors to facilitate the reviewing process (no et al.). Text must be in minimum 10pt Times font. Please number the pages of your submission. Double-blind submission guidelines apply to the submissions in all categories. 

General co-chairs 

Fan Yao, University of Central Florida  
Omer Khan, University of Connecticut

Program co-chairs

Nael Abu-Ghazaleh, UC Riverside
Gary Tan, Penn State University

Publicity Chairs

Khaled N. Khasawneh, George Mason University
Dongrui Zeng, Palo Alto Networks


Call for Papers: ICS 2024
https://ics2024.github.io/
Submitted by Murali Annavaram

The ACM International Conference on Supercomputing (ICS) is the premier international forum for the presentation of research results in high-performance computing systems. The 38th edition of ICS will be held in Kyoto, Japan from June 4-7, 2024.

Papers are solicited on all aspects of the architecture, software, and applications of high-performance computing systems of all scales (from chips to supercomputing systems), including but not limited to:

  • Processor, accelerator, memory, storage, interconnect and system architectures, including architectures based on future and emerging hardware (e.g. quantum, superconducting,  photonic, neuromorphic).
  • Programming languages, paradigms and execution models, including domain-specific languages and scientific problem-solving software environments.
  • Compilers, runtime systems and system software, including optimization and support for hardware resources and energy management.
  • High-performance algorithms and applications including machine learning and large-scale data analytics, as well as the implementation and deployment of algorithms and applications on large-scale systems.
  • Tools for measurement, modeling, analysis and visualization of performance, energy, or other quantitative properties of high-performance computing systems.

Abstract submission: January 11th, 2024
Paper submission: January 18th, 2024


Call for Papers: ISCA 2024 Industry Track
https://www.iscaconf.org/isca2024/submit/industry.php
Submitted by Xiaochen Guo

The 51st International Symposium of Computer Architecture includes a separate industry session in the main program following the success of the industry track inaugurated inISCA 2020. The ISCA Industry Track was established under a different vision and motive to bringing the values, trends, and perspectives of real hardware product and system design from the industries. It also serves as a venue to encourage more participation from industries to interact with academia for forward-looking research challenges and solutions. In light of the very specific purpose of the industry track, the submission guidelines are also very specific.

Submission Guidelines

  • The papers ideally include (1) retrospective evaluations of real working products, (2) upcoming industry products on their roadmaps, and/or (3) planned products that were canceled but present interesting insights or lessons learned.
  • The following types of submissions will not be considered: (1) students’ short-term internship projects in industries, or (2) speculation about hardware that might be built.
  • The first and most of the authors of such papers must work in industry.
  • The submissions are required to disclose the affiliations of all authors. Reviewers want to know which product is being evaluated and which company is writing the paper. Review assignments will still follow common practice to avoid conflicts of interest.
  • All formatting guidelines for the general submission (including page limits) must also be followed by any paper submitted to the industry track. The accepted paper will be labelled as an “Industry Product” in the conference proceedings.

Submissions that fail to abide by the guidelines will be rejected without review.

Important Dates

The program committee recognizes that industry papers need to be approved by management (often involving multiple rounds of redaction) before they can be submitted, and there can be restrictions about filing patents before submitting a paper. Therefore, a later deadline schedule is adopted to increase the chances of receiving such papers.

  • Abstract Deadline: January 5, 2024 at 11:59 PM EST
  • Full Paper Deadline: January 12, 2024 at 11:59 PM EST

Topics of Interest

Paper topics are not limited to hardware tapeouts. In particular, papers that are software-centric papers relevant to the ISCA audience are welcome in this track (e.g. datacenter software work, compiler work, accelerator software stack work), but they should adhere to the tenet that they must be industry papers about production-level work – whether retrospective, planned and on the roadmap, or planned but canceled.

  • Processors, SoCs, GPUs, and domain-specific accelerators
  • Systems and interconnect technologies for HPC, cloud, or data centers
  • Embedded, mobile, and IoT processors
  • FPGA or reconfigurable architectures
  • Storage and emerging memory systems
  • Architectures using emerging technology
  • Architectures for emerging applications including generative AI and bioinformatics
  • Architectures for commercialization of quantum computing

Call for Papers: FCCM 2024
https://www.fccm.org/call-for-papers-2024/
Submitted by Peipei Zhou

FCCM 2024 Call for Papers
https://www.fccm.org/call-for-papers-2024/
The 32nd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)

Feel free to follow FCCM Linkedin Page and join the FCCM Linkedin Group!

** New for FCCM 2024 – Journal Track submission.  See details below. **

The IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware.

FCCM 2024 is planned to be an in-person event. Please refer to the FCCM website (https://www.fccm.org/) for updates and details. At least one author will be required to register and attend the conference. Failure to present at the conference may result in the removal of the submission from IEEE Xplore.

Submissions are solicited on the following topics related to Field-Programmable Custom Computing Machines (FCCMs) including, but not limited to:

Architectures

  • Novel reconfigurable architectures, including overlay architectures
  • Architectures for high performance and/or low power computing
  • Security assessment and enhancements for reconfigurable computing
  • Specialized memory systems including volatile, non-volatile, and hybrid memory subsystems
  • Emerging technologies with in-field reconfiguration abilities
  • Clusters, data centers, or large systems of reconfigurable devices
  • Heterogeneous programmable architectures

Abstractions, Programming Models, and Tools

  • Abstractions, programming models, interfaces, and runtimes, including virtualization
  • New languages and design frameworks for spatial or heterogeneous applications
  • High-level synthesis and designer productivity in general
  • Software-Defined-systems (e.g. radio, networks, frameworks for new domains)
  • Customizable soft processors systems

Reconfiguration

  • Run-time management of reconfigurable hardware
  • System resilience/fault tolerance for reconfigurable hardware
  • Evolvable, adaptable, or autonomous reconfigurable computing systems
  • Security assessment and enhancement of run-time reconfiguration

Applications

  • Datacenter or cluster with reconfigurable applications
  • New uses of run-time reconfiguration in applications-specific systems
  • Applications that utilize reconfigurable technology for performance and efficiency, and particularly submissions that make comparisons with other highly parallel architectures such as GPUs or DSPs
  • Novel use of state-of-the-art commercial FPGAs

_Journal Track Submission_

For the first time, FCCM introduces an exciting Journal Track working with the ACM Transactions on Reconfigurable Technology and Systems (TRETS). The Journal Track is specifically intended for original contributions (i.e., no conference-paper extensions are allowed) that would benefit from the longer articles possible in TRETS (up to 32 ACM-style single-column pages).

Submission Procedure: To submit to the Journal Track, please use the ACM TRETS submission system (https://mc.manuscriptcentral.com/trets) to submit to the “FCCM 2024 Journal Track”, which you can select after logging into your TRETS account. To prepare a TRETS manuscript for such a submission, please follow the ACM TRETS Author Guidelines (https://dl.acm.org/journal/trets/author-guidelines).

Review Process: If your submission is not rejected during the first TRETS review process, you can submit it for a second round of review after adequately addressing the reviewers’ comments. The authors of accepted Journal-Track papers will be invited to present their work at the FCCM’24 conference and contribute an abstract of their TRETS paper to the FCCM proceedings. The actual paper will be published by TRETS. If the paper is not accepted in the Journal Track after the second round of review but still worth publication, it will continue as a regular TRETS submission.

Important Dates – Journal Track Submission:

Submission to TRETS: Dec 20, 2023
Initial review: January 20, 2024
Revision submission deadline: February 20, 2024
Notification of acceptance: Mar 14, 2024

All deadlines apply to the Anywhere on Earth (UTC – 12) timezone

Direct FCCM Submission

Authors may also choose to submit through the direct FCCM paper submission route as usual.
Submission Website: https://fccm24.hotcrp.com/

Important Dates – Direct Submission:

All deadlines apply to the Anywhere on Earth (UTC – 12) timezone

Abstracts Due (All Papers)                                     January 9, 2024 (NO EXTENSIONS)
Submissions Due (All Papers)                               January 15, 2024 (NO EXTENSIONS)
Workshop Proposals Due                                       February 16, 2024
Rebuttal Period                                                        February 15 – 22, 2024
Notification of Acceptance (All Papers)                March 14, 2024
Artifact Evaluation (All Papers)                              March 21, 2024
Demo Night Submissions                                       March 28, 2024
Notification of Acceptance (Demo Night)             April 4, 2024
Camera-Ready Submission                                   April 11, 2024
Early Registration Deadline                                    April 19, 2024
Conference                                                               May 5, 2024

Organizing Committee:

General Chair: Christophe Bobda (University of Florida)
Program Chair: Hayden So (University of Hong Kong)
Program Vice Chairs:
– Callie Hao (Geogia Tech)
– Lana Josipovic (ETHZ)
– John Wickerson (Imperial College, London)
Artifacts Chairs:
– Miriam Leeser (Northwestern University)
– Chris Lavin (AMD)
Finance Chair: Andrew Schmidt (AMD)
Sponsorship Chair: Naveen Purushotham (AMD)
Publications Chair: Ali Ahmadinia (California State University, San Marcos)
Workshops Chair: Jeff Goeders (BYU University)
Publicity and Website Chair: Peipei Zhou (University of Pittsburgh)
Demo-Night Chair: Estelle Kao (Intel)
PhD Forum Chair: Dirk Koch (University of Heidelberg)
Local Arrangements Chair: Sujan Sah Kumar (University of Florida)

Paper Types:

Submissions can be made for any of the two paper types:

  1. Traditional technical papers that introduce and evaluate new technologies. These papers must have strong empirical results and address significant challenges of the corresponding problem.
  2. Practical papers that make significant practical contributions, including industry papers, as opposed to introducing and evaluating new technologies. For example, new tools built on existing technologies that help practitioners better use FPGAs. Practical papers will be reviewed based on the significance and technical soundness of the practical contribution.

Paper Formats:

Long papers are limited to 10 pages (excluding references). Short papers are limited to 6 pages (excluding references). Authors are encouraged to submit preliminary work as a short paper. This category is intended for new projects and early results or work that can be concisely presented in the 6-page budget. Submissions accepted as posters will have a one-page extended abstract.

Page restrictions for all formats exclude references, which may use additional pages.

Submissions violating the formatting requirements may be automatically rejected. Do not submit the same work in more than one of the formats.

Accepted papers will have the same page lengths as initial submissions. Short papers will have short oral presentations, and long papers may have long or short presentations based on committee decisions on the time required to present the material.

All submissions should be written in English. An online submission link will be available on the FCCM website. Papers must conform to the US letter-sized IEEE conference proceedings format to be reviewed and published.

Paper Preparation:

Across all topics (and especially for application papers), successful manuscripts will include sufficient details to reproduce the results presented (e.g., full part numbers, software versions). Application papers should not just be an implementation of an application on an FPGA but should show how reconfigurable technology is leveraged by the application and should ideally contain insights and lessons that can be carried forward into future designs. Additional suggestions and guidelines are available on www.fccm.org. See the ACM/TCFPGA Hall-of-Fame (hof.tcfpga.org) and the set of previous FCCM Best Paper winners (wiki.tcfpga.org/FCCMBest) for outstanding examples of FCCM papers.

Simultaneous Submissions:

Papers must not be simultaneously under review or waiting to appear at another conference or in a journal and must not be essentially the same as any paper that has been previously published. If a paper contains text or technical content that is similar to a previously published or submitted paper, that other paper should be cited in the FCCM submission, and the differences should be made clear.

Reviewer Conflicts

Authors must register any program-committee conflicts as they submit their paper. Conflicts can include those that have co-authored a paper in the past 3 years, those that have current or shared institutional affiliation within the past year, or other situations in which the relationship would prevent a reviewer from being objective. Note that if an undeclared conflict is discovered, or a conflict is declared in an attempt to “game” the review process, the submission may be rejected. If you believe you may have a conflict with the program chair, please contact the program chair well in advance of the submission deadline.

Review Process:

FCCM uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations. Authors are encouraged to cite their work but must not implicitly identify themselves. For example, references that clearly identify the authors (“We build on our previous work…”) should be written as “This work builds on XYZ [citation]”. Do not put a “deleted for double-blind” entry in the reference section.

In the case of widely-available Open Source software, authors should cite the website(s) but not claim to own them. Authors should also remember to mask grant numbers and other government markings during the review process. Note that there are resources to blind open-source repositories for review, such as https://github.com/tdurieux/anonymous_github. Papers that attempt to identify authors or leverage prior work or institutional support fora competitive advantage in the peer review process will not be considered. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged; just because a paper can be unblinded by active search will not undermine the spirit of the double-blind review. Artifacts, including open-source designs and tools, are encouraged; if there are questions about handling the blind-review process, contact the program chair.

FCCM 2024 includes a rebuttal phase. Specific questions from reviewers will be made available by February 15, 2024. Authors have the option to provide an up to 500-word response by February 22, 2024. Reviewers will consider the responses during final paper deliberations.

Artifact Evaluation:
Authors of accepted full length papers can optionally participate in an artifact evaluation process. The inclusion of artifacts with a paper submission is not required for submission nor elevates the submission beyond those without. However, the goal of artifact evaluation is to encourage the availability and reproducibility of published results.

Artifacts that are included with submission will be subjected to a separate and independent review process from their accompanying papers. Papers submitted with artifacts must preserve the double-blind nature of the review process and all relevant links should be removed for blind review. Artifacts will be disclosed in a separate form that will be evaluated after paper acceptance.

Note: Artifact submission is optional, and authors are not required to open source their work for submission to FCCM.

More information about Artifact Evaluation can be found from the FCCM website.

Best Paper Award and a Special Section for the Best FCCM 2024Papers in ACM TRETS:

FCCM 2024 will continue the tradition of having a best long and short paper award. We will also invite the authors of the best papers to extend their work to be considered for publication in a special section of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS) for FCCM 2024.

Questions:

Questions about this call, submissions, and potential submissions should be directed to the program chair, Hayden So (hso@eee.hku.hk)

IEEE Privacy Policy


Call for Papers: ISPASS 2024
http://www.ispass.org/ispass2024/
Submitted by Fangjia Shen

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research focused on performance analysis in the design of computer systems and software. ISPASS 2024 will be held on May 5-7, 2024 in Indianapolis, Indiana. Authors are invited to submit previously unpublished work for possible presentation at the conference.

Papers are solicited in fields that include the following:

  • Performance and efficiency (power, area, etc.) evaluation methodologies
    • Analytical modeling
    • Statistical approaches
    • Tracing and profiling tools
    • Simulation techniques
    • Hardware (e.g., FPGA) accelerated simulation
    • Hardware performance counter architectures
    • Power, temperature, variability and/or reliability models for computer systems
    • Microbenchmark-based hardware analysis techniques
  • Foundations of performance and efficiency analysis
    • Metrics
    • Bottleneck identification and analysis
    • Visualization
  • Efficiency and performance analysis of commercial and experimental hardware
    • Multi-threaded, multicore and many-core architectures
    • Accelerators and graphics processing units
    • Memory systems, including storage-class memory
    • Embedded and mobile systems
    • Enterprise systems and data centers
    • HPC and Supercomputers
    • Computer networks
    • Quantum computing
    • Emerging technologies
  • Efficiency and performance analysis of emerging workloads and software
    • Software written in managed languages
    • Virtualization and consolidation workloads
    • Datacenter, internet-sector workloads
    • Embedded, multimedia, games, telepresence
    • Deep learning and convolutional neural networks
  • Application and system code tuning and optimization
  • Confirmations or refutations of important prior results

In addition to research papers, ISPASS welcomes tool and benchmark paper submissions. The conference is an ideal forum to introduce new tools and benchmarks to the community. These papers, which can detail tools and benchmarks in the above fields of interest, will be judged primarily on their potential to enable and amplify future research, which should be clearly motivated in the paper. We also expect that authors of accepted tools/benchmark papers open-source their tool/benchmark before the conference.

Important Dates

  • Paper abstract submission deadline: December 8, 2023, 11:59:59 PM Anywhere on Earth
  • Full submission deadline: December 15, 2023, 11:59:59 PM Anywhere on Earth
  • Rebuttal: February 9-13, 2024
  • Paper notification: February 29, 2024

Call for Papers: ARC 2024
https://arc2024.av.it.pt/
Submitted by Zhenman Fang

The 20th International Symposium on Applied Reconfigurable Computing (ARC 2024)
March 20 – 22, 2024, Aveiro, Portugal (https://arc2024.av.it.pt/)
Symposium information
Applied Reconfigurable Computing focuses on the use of reconfigurable hardware, such as field-programmable gate arrays (FPGAs), to accelerate and optimize various computational tasks and applications. It involves designing and implementing hardware configurations that can be dynamically adapted to specific workloads, improving performance and efficiency in a wide range of applications. The 20th edition of the symposium aims to bring together researchers and practitioners of reconfigurable computing with an emphasis on practical applications of this technology.
The ARC’2024 proceedings will be published as a volume in Springer’s Lecture Notes in Computer Science (LNCS) series and will also be available through the SpringerLink online service.
Selected papers will be invited to be submitted for consideration in a special issue at a publishing venue to be announced shortly (please check the symposium website).
Submission Information
Authors are invited to submit original contributions in English including, but not limited to, the areas of interest mentioned below. Submission must be up-loaded to the ARC website and identify the format of the contribution as either
– Long Papers:  (12 pages maximum) should include mainly accomplished results
                (oral presentation).
– Short Papers: (6 pages maximum) to be composed of work in progress or
          reporting recent developments (poster presentation).
The format of the paper should be according to the Springer-Verlag LNCS Series format rules (see: http://www.springer.com/comp/lncs/authors.html).
Important Dates
Submission deadline:                  11 December 2023
Decision Notification:                10 January  2024
Author Registration:                  30 January  2024
Camera-Ready Paper Submission:       07 February 2024
Topics of Interest
Papers in English in all areas of applied reconfigurable computing are invited, with particular emphasis on:
» Design Methods & Tools
   High-level languages & compilation
   Simulation & synthesis
   Design space exploration
» Applications
   Security & cryptography
   Embedded computing & DSP
   Robotics, space, bioinformatics
   Deep learning & neural networks
» Architectures
   Computation in/near memory
   Self-adaptive, evolvable PSoCs & adaptive SoCs
   Low-power designs
   Approximate computing
   Fine-/coarse-/mixed-grained
   Interconnect (NoCs, …)
   Resilient & fault tolerant
Organizing Committee
General Chairs:    Pedro C. Diniz   (Univ. of Porto, Portugal)
Program Chairs:
   Iouliia Skliarova      (University of Aveiro, Portugal)
   Piedad Brox Jiménez    (Microelectronics Inst. of Seville, Spain)
Proceedings Chair: Mário Véstias          (ISEL, Lisboa, Portugal)
Local Chair:    Arnaldo Oliveira   (University of Aveiro, Portugal)
Special Issue Chair: Christian Hochberger (TU Darmstadt, Germany)

Call for Papers: International Workshop on LLM-Aided Design
https://www.islad.org/
Submitted by Jeff Goeders

1st IEEE International Workshop on LLM-Aided Design (LAD 2024)
June 28-29 2024, Almaden, CA
(In cooperation with ACM SIGDA)

This new international workshop will focus on how to use LLM (Large Language Model) as a methodology to help design circuits, software, and computing systems with improved quality, productivity, robustness, and cost. It is the first of its kind international workshop in the community that will focus on discussing results that leverage the significant advancement and innovation captured by the generative AI and LLM technology to offer new methods and solutions for design automation targeting various applications. The workshop will be a timely venue that will host leading researchers and thought leaders in this fast-growing area and will provide a forum for researchers and practitioners to present their latest results, contribute open-source LLM models, datasets, tool flows, and offer benchmarking, testing and validation methods and solutions. Topics of interest include but are not limited to new methodologies, datasets, and benchmarks, pertaining to:
• LLM-aided hardware/software design specification and code generation
• System-level design methodology development with LLMs
• Security and robustness of LLM-generated designs
• LLM-aided security verification and bug-fixing
• Finetuning of large foundation models for specialization in design automation
• New Datasets and Benchmarks of relevance to LLM-aided design • LLMs for EDA, including HLS, physical design, and EDA scripting
• LLMs for reasoning and math used in design process
• Computational efficiency of LLM-aided design tools
• Privacy, copyright and other regulatory concerns around LLM-aided design
• Data science and data analytics for LLM-aided design
• Evaluation and testing of LLM-aided design models and methods

SUBMISSION INSTRUCTIONS
The workshop invites 4-page regular papers in the IEEE Conference format. Page limits do not include references. Papers should be anonymized for double-blind peer review. We strongly encourage papers with a commitment to open and reproducible research, including datasets and methods. Papers with open-source implementations will be highlighted at the workshop. All papers will be published on IEEEXplore. Papers can be submitted via OpenReview (https://openreview.net/group?id=IEEE.org/LAD/2024) starting March 1st, 2024. See the workshop website (https://www.islad.org/) for more details.

DATASETS AND BENCHMARKS PAPERS
LAD’24 welcomes papers describing new Datasets and Benchmarks of relevance to LLM-Aided Design community. Papers describing new datasets and benchmarks must follow the exact same rules and procedures as regular 4 page papers, will be peer reviewed and published in the proceedings. Datasets and Benchmark papers must include an explicit commitment to releasing all artifacts publicly if accepted. The commitment should be added to the Conclusion section of the paper. Accepted papers will be highlighted at the workshop, and separate Best Dataset and Benchmarks paper prizes will be awarded.

IMPORTANT DATES
Full paper submission: April 1st, 2024 (Submission website opens March 1st, 2024)
Notification of acceptance: May 1st, 2024
Camera ready paper due: May 15th, 2024

PAPER FORMATTING
Authors should follow the recommended IEEE Conference format for their submissions (https://www.ieee.org/conferences/publishing/templates.html) to ensure compatibility with IEEEXplore. Manuscripts should be blinded so as to not disclose author identities. LAD’24 encourages open-source and reproducible research. Authors can provide anonymized URLs to their datasets and methods in the paper, or commit to open release on paper acceptance. However, this is not mandatory.

POLICY ON SUBMISSIONS TO OTHER VENUES
LAD’24 expects previously unpublished papers describing original research. Accepted LAD’24 papers will appear on IEEEXplore and count as formal, archival publications. LAD’24 papers can be enhanced and submitted for publication in other conferences or journals; the enhancements should be significant and consistent with the policies of these venues.

ORGANIZING COMMITTEE
General Chairs Ruchir Puri (IBM), Deming Chen (UIUC)
Program Chairs Siddharth Garg (NYU), Haoxing (Mark) Ren (NVidia)
Finance Chair Callie Hao (GaTech)
Special Sessions Chair Azalia Mirhoseini (Stanford)
Industrial Liaison Yong Liu (Cadence)
Open Community Chair Yingyan (Celine) Lin (GaTech)
Industry Outreach Chair David Z Pan (UT Austin)
Publicity Chair Jeff Goeders (BYU)
Local Arrangements Ehsan Degan (IBM)
Publication Chair Kanad Basu (UT Dallas)
Webmaster Kaiwen Cao (UIUC)

SPONSORS
IBM, NVIDIA, Synopsys, Cadence, NSF, IEEE, CEDA, (more to come)


Call for Papers: BioSys @ ASPLOS 2024
https://biosys-workshop.github.io/
Submitted by Yatish Turakhia

Call For Papers: 1st Workshop on Emerging Computer Systems Challenges and Applications in Biomedicine (BioSys),
in conjunction with the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2024)

Workshop websitehttps://biosys-workshop.github.io/

The advent of new biotechnologies, such as high-throughput DNA sequencing, single-cell sequencing, gene therapies, spatial transcriptomics, CRISPR, AI, and Brain-Computer Interfaces, are enabling the generation of vast amounts of high-quality biological datasets. These technologies are revolutionizing the fields of medicine, drug discovery, epidemiology, metagenomics, evolutionary biology, and neuroscience, among others. However, they also pose new challenges in data storage, analysis, and scalability for current computer systems. Moreover, due to the sensitive nature of several biomedical datasets, coupled with the rapid advances in generative AI and quantum computing technologies, the development of new computing systems that ensure data privacy and security in biomedicine is of paramount importance.

This workshop aims to provide a platform for discussing the latest research and developments in all aspects of computer systems (such as data storage, hardware accelerators, cloud computing, privacy, security, and AI/ML integration.) for applications in biomedicine. It also aims to explore new opportunities and challenges at the intersection of the two fields and to facilitate networking and collaboration among participants from diverse backgrounds. The workshop will feature distinguished keynote speakers, paper presentations, expert panel discussions, and interactive sessions, and will provide networking opportunities.

Submission Guidelines

For submissions, we invite authors to submit their latest work that belongs to the intersection of the following computer systems and biomedical applications:

Computer Systems (include, but are not limited to):

  • Hardware accelerators
  • FPGAs and reconfigurable computing
  • Cloud and data center scale computing
  • Scalable Deep Learning and AI models
  • Security and Privacy Parallel and Distributed Algorithms
  • Parallel and Heterogenous Architecture
  • 3D memory-logic stack, Near-memory, and in-memory processing
  • Biomedical Circuits and Devices
  • Brain-Computer Interfaces

Biomedical Applications (include, but not limited to):

  • Bioinformatics
  • Genomics
  • Drug Design and Discovery
  • Proteomics
  • Structural Biology
  • Evolutionary Biology
  • Metagenomics
  • Epidemiology and genomic surveillance
  • Precision Medicine and Healthcare
  • Rapid Sequencing and Diagnosis
  • Neuroscience

Important Notes

Presenting a paper in the workshop does not preclude publication in other venues.

Keynote Speakers: 

  • Satish Narayanasamy (Professor, University of Michigan) – Website
  • Duygu Kuzum (Associate Professor, UC San Diego) – Website
  • Abhishek Bhattacharjee (Professor, Yale University – Website

Contact

  1. Yatish Turakhia (yturakhia@ucsd.edu)
  2. Sumit Walia (swalia@ucsd.edu)
  3. Anshu Gupta (ang037@ucsd.edu)
  4. Pranav Gangwar (pgangwar@ucsd.edu)
  5. Kyle Smith (kws001@ucsd.edu)

Call for Papers: CAV @ ASPLOS 2024
https://sites.google.com/g.harvard.edu/cav-asplos24/home
Submitted by Tom St. John

Workshop on Compute Platforms for Autonomous Vehicles 2024 –
Co-located with ASPLOS 2024

The global market for autonomous vehicles is expected to surpass $300 billion by the end of the decade.  Due to the unique requirements of simultaneously providing sufficient computational power to run the necessary workloads needed to support autonomous driving, achieving the efficiency necessary to run the system in the resource-constrained environment of an on-road vehicle, and ensuring reliable execution, specialized compute platforms are required for this domain.

We welcome submissions focused on compute platforms for autonomous vehicles (cars/drones/robots).  Key topics that we seek to address in the workshop include:

We solicit both full papers (8-10 pages), as well as short/position papers (2-4 pages).  Submissions are not double-blind (author names must be included).  The page limit includes figures, tables, and appendices, but excludes references.  Please use standard IEEE Word or LaTex templates.  All submissions will need to be made via EasyChair.

Each submission will be reviewed by at least three reviewers from the program committee.  Papers will be reviewed for novelty, quality, technical strength, and relevance to the workshop.  All accepted papers will be made available online.


Call for Papers: ARC-LG @ ISCA 2024
https://llm-gnn.org/
Submitted by Pavana Prakash

ARC-LG: New Approaches for Addressing the Computing Requirements of LLMs and GNNs.
In conjunction with ISCA 2024
June 30, 2024 @ Buenos Aires, Argentina

https://llm-gnn.org/

Overview:
Training and deployment of huge machine learning models, such as GPT, Llama, or large GNNs, require a vast amount of compute resources, power, storage, memory. The size of such models is growing exponentially, as is the training time and the resources required. The cost to train large foundation models has become prohibitive for everyone but very few large players. While the challenges are most visible in training, similar considerations apply to deploying and serving large foundation models for a large user base.
The proposed workshop aims to bring together AI/ML researchers, computer architects, and engineers working on a range of topics focused on training and serving large ML models. The workshop will provide a forum for presenting and exchanging new ideas and experiences in this area and to discuss and explore hardware/software techniques and tools to lower the significant barrier of entry in the computation requirements of AI foundation models.
We are seeking innovative, evolutionary and revolutionary ideas around software and hardware architectures for training such challenging models and strive to present and discuss new approaches that may lead to alternative solutions.

Submissions:
Authors can submit either 8-page full papers or up to 4-page short papers. In the short paper format, out-of-the box ideas and position papers are especially encouraged.  See the website for submission details.

Topics:
The workshop will present original works in areas such as (but not inclusive to): workload characterization, inference serving at scale, distributed training, novel networking and interconnect approaches for large AI/ML workloads, addressing resilience of large training runs, data reduction techniques, better model partitioning, data formats and precision, efficient hardware and competitive accelerators.

Important dates: All times below are 11:59 pm (anywhere on earth):

  • Paper submission due:  April 22, 2024
  • Acceptance notification: May 10, 2024
  • Workshop date: June 30, 2024

Call for Papers: EMC2 – Energy Efficient Machine Learning and Cognitive Computing
https://www.emc2-ai.org/asplos-24
Submitted by Sushant Kondguli

The goal of this Workshop is to provide a forum for researchers and industry experts who are exploring novel ideas, tools and techniques to improve the energy efficiency of MLLMs as it is practised today and would evolve in the next decade. We envision that only through close collaboration between industry and the academia we will be able to address the difficult challenges and opportunities of reducing the carbon footprint of AI and its uses. We have tailored our program to best serve the participants in a fully digital setting. Our forum facilitates active exchange of ideas through:

  • Keynotes, invited talks and discussion panels by leading researchers from industry and academia
  • Peer-reviewed papers on latest solutions including works-in-progress to seek directed feedback from experts
  • Independent publication of proceedings through IEEE CPS

We invite full-length papers describing original, cutting-edge, and even work-in-progress research projects about efficient machine learning. Suggested topics for papers include, but are not limited to the ones listed below.

  • Neural network architectures for resource constrained applications
  • Efficient hardware designs to implement neural networks including sparsity, locality, and systolic designs
  • Power and performance efficient memory architectures suited for neural networks
  • Network reduction techniques – approximation, quantization, reduced precision, pruning, distillation, and reconfiguration
  • Exploring interplay of precision, performance, power, and energy through benchmarks, workloads, and characterization
  • Simulation and emulation techniques, frameworks, tools, and platforms for machine learning
  • Optimizations to improve performance of training techniques including on-device and large-scale learning
  • Load balancing and efficient task distribution, communication and computation overlapping for optimal performance
  • Verification, validation, determinism, robustness, bias, safety, and privacy challenges in AI systems

 


Call for Papers: HotCarbon 2024
https://hotcarbon.org/cfp
Submitted by Romain Jacob

The HotCarbon Workshop on Sustainable Computer Systems aims to engage researchers and practitioners in a lively discussion on new ideas to improve the sustainability of computer systems.

The research community has had a relentless focus on the implications of increased scale and raw performance of consumer devices, cloud systems, datacenters, and networks. We must address the negative aspects of computing’s proliferation – through innovative approaches to how we build, deploy, operate, and retire our creations. For example, software-driven hardware obsolescence that increases e-waste and embodied carbon suggests we must challenge computing’s endemic upgrade and throwaway practices and mindset.

The workshop’s third edition aims to foster the scientific discussion around the sustainability of computer systems. We look forward to reading your contributions to the field! See the CfP for details on format and scope.

  • Call for papers: https://hotcarbon.org/cfp
  • Submission deadline: May 8, 2024 (AoE)
  • Notifications: June 12, 2024
  • Workshop: July 9, 2024

Call for Papers: LAD’24: International Workshop on LLM-Aided Design
https://www.islad.org/
Submitted by Jeffrey Goeders

CALL FOR PAPERS – LAD’24
1st IEEE International Workshop on LLM-Aided Design
June 28-29 2024, Almaden, CA 

This new international workshop will focus on how to use LLM (Large Language Model) as a methodology to help design circuits, software, and computing systems with improved quality, productivity, robustness, and cost. It is the first of its kind international workshop in the community that will focus on discussing results that leverage the significant advancement and innovation captured by the generative AI and LLM technology to offer new methods and solutions for design automation targeting various applications. The workshop will be a timely venue that will host leading researchers and thought leaders in this fast-growing area and will provide a forum for researchers and practitioners to present their latest results, contribute open-source LLM models, datasets, tool flows, and offer benchmarking, testing and validation methods and solutions. Topics of interest include but are not limited to:

  • LLM-aided hardware/software design specification and code generation
  • System-level design methodology development with LLMs
  • Security and robustness of LLM-generated designs
    • LLM-aided security verification and bug-fixing
  • Finetuning of large foundation models for specialization in design automation
  • LLMs for EDA, including HLS, physical design, and EDA scripting
  • LLMs for reasoning and math used in design process 
  • Computational efficiency of LLM-aided design tools
  • Privacy, copyright and other regulatory concerns around LLM-aided design
  • Data science and data analytics for LLM-aided design

SUBMISSION INSTRUCTIONS

The workshop invites 4-page regular papers in the IEEE Conference format. Page limits do not include references. Papers should be anonymized for double-blind peer review. We strongly encourage papers with a commitment to open and reproducible research, including datasets and methods. Papers with open-source implementations will be highlighted at the workshop. All papers will be published on IEEEXplore. Papers can be submitted via OpenReview (https://openreview.net/group?id=IEEE.org/LAD/2024) starting March 1st, 2024. See the workshop website (https://www.islad.org/) for more details. 

IMPORTANT DATES

Full paper submission: April 1st, 2024 (Submission website opens March 1st, 2024)
Notification of acceptance:     May 1st, 2024
Camera ready paper due:      May 15th, 2024

PAPER FORMATTING

Authors should follow the recommended IEEE Conference format for their submissions (https://www.ieee.org/conferences/publishing/templates.html) to ensure compatibility with IEEEXplore. Manuscripts should be blinded so as to not disclose author identities. LAD’24 encourages open-source and reproducible research. Authors can provide anonymized URLs to their datasets and methods in the paper, or commit to open release on paper acceptance. However, this is not mandatory. 

POLICY ON SUBMISSIONS TO OTHER VENUES

LAD’24 expects previously unpublished papers describing original research. Accepted LAD’24 papers will appear on IEEEXplore and count as formal, archival publications. LAD’24 papers can be enhanced and submitted for publication in other conferences or journals; the enhancements should be significant and consistent with the policies of these venues.

ORGANIZING COMMITTEE

General Chairs Ruchir Puri (IBM), Deming Chen (UIUC)
Program Chairs Siddharth Garg (NYU), Haoxing (Mark) Ren (NVidia)
Finance Chair Callie Hao (GaTech) 
Special Sessions Chair        Azalia Mirhoseini (Stanford) 
Industrial Liaison                    Yong Liu (Cadence)
Open Community Chair Yingyan (Celine) Lin (GaTech)
Publicity Chair                      Jeff Goeders (BYU) 
Local Arrangements Ehsan Degan (IBM)
Webmaster Kaiwen Cao (UIUC)


Call for Papers: ASPLOS’24 Young Architect Workshop
https://www.cs.cmu.edu/~yarch2024/
Submitted by Martin Maas

YArch 2024: The Sixth Young Architect Workshop
April 27 or 28, 2024 (Co-located with ASPLOS)
Website: https://www.cs.cmu.edu/~yarch2024/
Submissions Due: January 19th, 2024

YArch is a workshop for junior researchers with an interest in computer architecture (broadly defined) who may have early research ideas they’d like to get feedback on. The goal of YArch is to facilitate contacts between junior computer architecture researchers and more senior researchers in the field. It is also an opportunity to get feedback on early research ideas.

Two-page double-blind submissions should describe the scope of the problem, the proposed idea/solution, the intended evaluation methodology, and related work.

Topics of interest include, but are not limited to:

  • Datacenter systems
  • Hardware acceleration
  • Memory hierarchy
  • Virtualization
  • Security
  • Microarchitecture
  • GPUs
  • Parallel architectures
  • Emerging technologies

To qualify, a researcher must have completed fewer than 3 years of graduate studies. YArch is primarily targeting early graduate students in computer science/engineering, but exceptional undergrads with research experience are also welcome to submit ideas. We intend to cover the travel and registration costs for presenters of accepted submissions.

The workshop is not a venue for publication; there will be no published proceedings. Simultaneous submissions are allowed from the perspective of YArch.

More information can be found on the workshop’s website: https://www.cs.cmu.edu/~yarch2024/

For any questions, please contact us at youngarchitectw@gmail.com

Organizers
Caroline Trippel, Stanford
Dimitrios Skarlatos, CMU
Martin Maas, Google DeepMind

Important dates
Paper registration deadline: January 12th, 2024
Paper submission deadline: January 19th, 2024
Notification of acceptance: March 15th, 2024
Workshop date: April 27 or 28, 2024 (Co-located with ASPLOS)


Call for Papers: 6th AccML Workshop at HiPEAC 2024
https://accml.dcs.gla.ac.uk/
Submitted by Jose Cano

6th Workshop on Accelerated Machine Learning (AccML)
Co-located with the HiPEAC 2024 Conference
(https://www.hipeac.net/2024/munich/)
January 17, 2024
Munich, Germany

CALL FOR CONTRIBUTIONS

The remarkable performance achieved in a variety of application areas (natural language processing, computer vision, games, etc.) has led to the emergence of heterogeneous architectures to accelerate machine learning workloads. In parallel, production deployment, model complexity and diversity pushed for higher productivity systems, more powerful programming abstractions, software and system architectures, dedicated runtime systems and numerical libraries, deployment and analysis tools. Deep learning models are generally memory and computationally intensive, for both training and inference. Accelerating these operations has obvious advantages, first by reducing the energy consumption (e.g. in data centers), and secondly, making these models usable on smaller devices at the edge of the Internet. In addition, while convolutional neural networks have motivated much of this effort, numerous applications and models involve a wider variety of operations, network architectures, and data processing. These applications and models permanently challenge computer architecture, the system stack, and programming abstractions. The high level of interest in these areas calls for a dedicated forum to discuss emerging acceleration techniques and computation paradigms for machine learning algorithms, as well as the applications of machine learning to the construction of such systems.

LINKS TO THE WORKSHOP PAGES
Organizers: https://accml.dcs.gla.ac.uk/
HiPEAC: https://www.hipeac.net/2024/munich/#/program/sessions/8090/

TOPICS
Topics of interest include (but are not limited to):

– Novel ML systems: heterogeneous multi/many-core systems, GPUs and FPGAs;
– Software ML acceleration: languages, primitives, libraries, compilers and frameworks;
– Novel ML hardware accelerators and associated software;
– Emerging semiconductor technologies with applications to ML hardware acceleration;
– ML for the construction and tuning of systems;
– Cloud and edge ML computing: hardware and software to accelerate training and inference;
– Computing systems research addressing the privacy and security of ML-dominated systems;
– ML techniques for more efficient model training and inference (e.g. sparsity, pruning, etc);
– Generative AI and their impact on computational resources

INVITED SPEAKERS

– Giuseppe Desoli (STMicroelectronics): Revolutionizing Edge AI: Enabling Ultra-low-power and High-performance Inference with In-memory Computing Embedded NPUs

Abstract: The increasing demand for Edge AI has led to the development of complex cognitive applications on edge devices, where energy efficiency and compute density are crucial. While HW Neural Processing Units (NPUs) have already shown considerable benefits, the growing need for more complex algorithms demands significant improvements. To address the limitations of traditional Von Neumann architectures, novel designs based on computational memories are being developed by industry and academia. In this talk, we present STMicroelectronics’ future directions in designing NPUs that integrate digital and analog In-Memory Computing (IMC) technology with high-efficiency dataflow inference engines capable of accelerating a wide range of Deep Neural Networks (DNNs). Our approach combines SRAM computational memory and phase change resistive memories, and we discuss the architectural considerations and purpose-designed compiler mapping algorithms required for practical industrial applications and some challenges we foresee in harnessing the potential of In-memory Computing going forward.

– John Kim (KAIST): Domain-Specific Networks for Accelerated Computing

Abstract: Domain-specific architectures are hardware computing engine that is specialized for a particular application domain. As domain-specific architectures become widely used, the interconnection network can become the bottleneck for the system as the system scales. In this talk, I will present the role of domain-specific interconnection networks to enable scalable domain-specific architectures. In particular, I will present the impact of the physical/logical topology of the interconnection network on communication such as AllReduce in domain-specific systems. I will also discuss the opportunity of domain-specific interconnection networks and how they can be leveraged to optimize overall system performance and efficiency. As a case study, I will present the unique design of the Groq software-managed scale-out system and how it adopts architectures from high-performance computing to enable a domain-specific interconnection network.

– Adam Paszke (Google): A Multi-Platform High-Productivity Language for Accelerator Kernels

Abstract: Compute accelerators are the workhorses of modern scientific computing and machine learning workloads. But, their ever increasing performance also comes at a cost of increasing micro-architectural complexity. Worse, it happens at a speed that makes it hard for both compilers and low-level kernel authors to keep up. At the same time, the increased complexity makes it even harder for a wider audience to author high-performance software, leaving them almost entirely reliant on high-level libraries and compilers. In this talk I plan to introduce Pallas: a domain specific language embedded in Python and built on top of JAX. Pallas is highly inspired by the recent development and success of the Triton language and compiler, and aims to present users with a high-productivity programming environment that is a minimal extension over native JAX. For example, kernels can be implemented using the familiar JAX-NumPy language, while a single line of code can be sufficient to interface the kernel with a larger JAX program. Uniquely, Pallas kernels support a subset of JAX program transformations, making it possible to derive a number of interesting operators from a single implementation. Finally, based on our experiments, Pallas can be leveraged for high-performance code generation not only for GPUs, but also for other accelerator architectures such as Google’s TPUs.

– Ayse Coskun (Boston University): ML-Powered Diagnosis of Performance Anomalies in Computer Systems

Abstract: Today’s large-scale computer systems that serve high performance computing and cloud face challenges in delivering predictable performance, while maintaining efficiency, resilience, and security. Much of computer system management has traditionally relied on (manual) expert analysis and policies that rely on heuristics derived based on such analysis. This talk will discuss a new path on designing ML-powered “automated analytics” methods for large-scale computer systems and how to make strides towards a longer term vision where computing systems are able to self-manage and improve. Specifically, the talk will first cover how to systematically diagnose root causes of performance “anomalies”, which cause substantial efficiency losses and higher cost. Second, it will discuss how to identify applications running on computing systems and discuss how such discoveries can help reduce vulnerabilities and avoid unwanted applications. The talk will also highlight how to apply ML in a practical and scalable way to help understand complex systems, demonstrate methods to help standardize study of performance anomalies, discuss explainability of applied ML methods in the context of computer systems, and point out future directions in automating computer system management.

SUBMISSION
Papers will be reviewed by the workshop’s technical program committee according to criteria regarding the submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions in the context of accelerating machine learning. Research papers, case studies, and position papers are all welcome.

In particular, we encourage authors to submit work-in-progress papers: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and spark productive discussions.

The workshop does not have formal proceedings.

IMPORTANT DATES
Submission deadline: November 17, 2023
Notification of decision: December 8, 2023

ORGANIZERS
José Cano (University of Glasgow)
Valentin Radu (University of Sheffield)
José L. Abellán (University of Murcia)
Marco Cornero (DeepMind)
Ulysse Beaugnon (Google)
Juliana Franco (DeepMind)


Call for Papers: GPGPU-16
https://mocalabucm.github.io/gpgpu2024/
Submitted by Daniel Wong

Call for Papers for GPGPU-16
Held in cooperation with PPoPP’24
Full-Day Workshop (March 2 or 3, 2024)

Overview:
GPUs are delivering more and more computing power required by modern society. With the growing popularity of massively parallel devices, users demand better performance, programmability, reliability, and security. The goal of this workshop is to provide a forum to discuss massively parallel applications, environments, platforms, and architectures, as well as infrastructures that facilitate related research.

Authors are invited to submit papers of original research in the general area of GPU computing and architectures. Topics include, but are not limited to:

  • GPU Architecture and Hardware
    • Next-generation GPU architectures
    • Energy-efficient GPU designs
    • Scalable multi-GPU systems
    • GPU memory hierarchies and management
  • Programming Models and Compilers
    • High-level programming abstractions for GPUs
    • Compiler optimizations for GPU codes
    • Source-to-source translations and tools
    • Debugging and profiling tools for GPUs
  • GPU Algorithms and Data Structures
    • Parallel algorithms tailored for GPUs
    • Data structures optimized for GPU memory hierarchies
    • Algorithmic primitives and building blocks
  • Performance Optimization Techniques
    • Performance modeling and benchmarking
    • Auto-tuning and performance portability
    • Techniques for reducing communication overheads
  • GPU Applications
    • Case studies of real-world GPU applications
    • GPU applications in scientific computing, machine learning, graphics, and emerging field (e.g., quantum, neuromorphic, bioinformatics and genomics)
    • Performance comparisons between GPU and other parallel computing platforms
  • Integration of GPUs with Other Technologies
    • GPU and FPGA co-processing
    • Hybrid systems (e.g., CPU-GPU, GPU-TPU integration)
    • Cloud-based GPU computing
  • Challenges and Future Trends
    • Reliability and fault tolerance in GPU systems
    • Security and privacy concerns in GPU computing
    • The future of heterogeneity in computing platforms
    • GPU programming and architecture education

Important Dates (Tentative) (11:59 pm, Anywhere on Earth)
Papers due: Nov 28, 2022
Notification: Jan 6, 2023
Final paper due: Feb 17, 2023

Submission Guidelines

Full paper submissions must be in PDF format for A4 or US letter-size paper. They must not exceed 6 pages (excluding references) in standard ACM two-column sigplan format (review mode, sigplan template). Authors can select if they want to reveal their identity in the submission.

Templates for ACM format are available for Microsoft Word, and LaTeX at: https://www.acm.org/publications/proceedings-template.


Call for Papers: IEEE JETCAS Special Issue: Chip and Package-Scale Communication-Aware Architectures for General-Purpose, Domain-Specific and Quantum Computing Systems
https://ieee-cas.org/files/ieeecass/2023-10/JETCAS_CFP_Final.pdf
Submitted by Abhijit Das

We are entering a new golden age of computer architecture, which is challenging but also exciting at the same time. The eminent end of Moore’s law and Dennard scaling compelled everyone to conceive forthcoming computing systems once transistors reach their limits. Three leading approaches to circumvent this situation are using the chiplet paradigm, domain customisation and quantum computing. However, these architectural and technological innovations have shifted the fundamental bottleneck from computation to communication. Hence, on-chip and on-package communication play a pivotal role in determining the performance, efficiency and scalability of general-purpose, domain-specific and quantum computing systems. Due to this increasing significance, chip and package-scale communication has drawn a lot of attention from both academia and industry. This special issue promises a broad avenue to bring together academic and industrial explorations in chip and package-scale communications from multiple domains. Specifically, it will target the following:

  • General-Purpose Computing Systems: Data sharing and synchronisation between different cores (processors) demand efficient communication infrastructure within and between chips. Design practices like Network-on-Chip (NoC), Network-on-Package (NoP), and hierarchical interconnects are commonly used to optimise communication performance while reducing power consumption. Wireless, Optical, and 3D NoCs are some of the popular innovations proposed over the years. The first focus of this special issue is to present novel communication-aware architectures for adaptable general-purpose computing systems.
  • Domain-Specific Computing Systems: They are tailored to particular application domains with specific communication requirements. Customised interconnects, accelerators and memory hierarchies are designed to minimise data movement and maximise computation efficiency. Chipletisation to integrate heterogenous Intellectual Properties (IPs) and In-Memory Computing (IMC) are recent innovations. The second focus of this special issue is to present novel communication-aware architectures for efficient domain-specific computing systems.
  • Quantum Computing Systems: They promise to tackle problems beyond the ability of the fastest classical computing systems using the principle of superposition and entanglement. However, this will require millions of qubits, and we stand at around 500 qubits today. Hence, scaling a quantum computing system will require a communication infrastructure which is cryo-compatible and allows qubit synchronisation and entanglement. It should also reduce the effects of noise and quantum decoherence. The third and final focus of this special issue is to present breakthrough communication frameworks for scalable quantum computing systems.

Topics of interest:

This special issue will explore academic and industrial research related to chip and package-scale communication for various computing paradigms. Topics include, but are not limited to:

  • NoC and NoP designs for general-purpose computing systems
  • Cache coherent interconnects for I/O and compute devices (CXL, CCIX, etc.)
  • Network interface designs for intra/inter-chip and rack-scale networks
  • Emerging interconnect technologies, like wireless, optical, Carbon NanoTubes (CNT), 2.5D/3D
  • Co-optimisations of communications with OS, compilers and programming models
  • Security, reliability and scalability of on-chip and on-package communications
  • Communications at large scales like data center, edge, and fog computing
  • Modeling, characterisation, benchmarking, simulation and verification of communications
  • Novel interconnection networks for domain-specific computing systems
  • In-package die-to-die interconnects for chiplet integration (UCIe, BoW, etc.)
  • New design methodologies (including ML-based) for chip and package-scale communications
  • Communication/traffic-aware neural network architectures
  • Data movement optimisation through task scheduling in domain-specific computing systems
  • Near- and In-memory computing techniques for saving data movement
  • Cryo-compatible communication infrastructures for scalable quantum computing systems
  • Quantum intranet, internet and networking
  • Quantum switches, routers, repeaters and other components for communication
  • Communication-enabled architectures for multi-core quantum computing systems
  • Interconnects for quantum neural network architectures

Submission procedure:

Prospective authors are invited to submit their papers following the instructions provided on the IEEE JETCAS website: https://ieee.atyponrex.com/journal/jetcas. The submitted manuscripts should not have been previously published, nor should they be currently under consideration for publication elsewhere.

Important dates:

  • Manuscript submissions due: March 04, 2024
  • First round of reviews completed: April 22, 2024
  • Revised manuscripts due: June 03, 2024
  • Second round of reviews completed: July 01, 2024
  • Final manuscripts due: July 22, 2024

Guest Editors:

  • Abhijit Das, Universitat Politècnica de Catalunya, Spain
  • Maurizio Palesi, University of Catania, Italy
  • John Kim, Korea Advanced Institute of Science & Technology, South Korea
  • Partha Pratim Pande, Washington State University, USA

Request for information:

Corresponding Guest Editor: Abhijit Das (abhijit.das@upc.edu)


Note: The Call for Paper type has not been set for this item!

Call for Papers: CogArch @ ISCA 2024
http://cogarchworkshop.org
Submitted by Ananda Samajdar

8th Workshop on Cognitive Architectures (CogArch) – 
Co-located with ISCA 2024

The CogArch workshop solicits formative ideas and new product offerings in the general space of AI systems that are applied towards designing of next generation processing systems, at every stage of conceptualization, design, testing, verification and manufacturing.

Topics of interest include (but are not limited to):

  • Application of AI models towards hardware design
  • AI-enabled architecture design and exploration
  • AI for efficient EDA optimizations, place-and-route
  • AI-enabled optimizations for compilers, firmware and middleware
  • AI for test bench generation for hardware
  • AI techniques for leveraging emerging device technologies, 2.5D/3D stacking, chiplet architectures, novel packaging technologies
  • AI/ML for fast system modeling and simulation
  • AI for improving efficiency and coverage of verification methodologies
  • Demonstrations (live or recorded) showcasing prototypes, tools and methodologies for AI-inspired hardware design

Submission guidelines: 2 pages, including references, with same formatting guidelines as the ISCA 2024 main conference.

Submissions must be made at the following site: https://easychair.org/my/conference?conf=cogarch2024

Important dates:

  • Paper submission deadline: April 11th, 2024
  • Notification of acceptance: April 25th, 2024
  • Final paper submission: May 8th, 2024
  • Workshop date: June 29/30th 2024

Note: The Call for Paper type has not been set for this item!

Call for Papers: XTensor @ ASPLOS 2024
http://fruitfly1026.github.io/static/files/xtensor-asplos24.html
Submitted by Jiajia Li

XTensor 1st Workshop on Cross-stack Optimization of Tensor Methods
In conjunction with ASPLOS 2024
April 27 1-5pm, 2024 @ San Diego, CA, USA

Please find details and submission link here: http://fruitfly1026.github.io/static/files/xtensor-asplos24.html
Please contact Jiajia Li at jiajia.li@ncsu.edu if you have any questions.

Tensor problems are becoming ever more important to represent data and analyze its inherent properties, as the correlation of data gains importance in many domains. The application of tensor methods covers machine learning/deep learning, quantum chemistry/physics, quantum circuit simulation, social networks, and healthcare, to name a few. The research on tensor methods comes from multiple domains, including computer architecture, programming languages, compilers, and parallel computing.  This workshop aims to gather researchers from diverse computer system backgrounds to present and communicate their work on tensor methods, and then seek a cross-stack solution to improve the performance of tensor algorithms.

Scope
XTensor is a venue for discussion and brainstorming at the intersection of software and hardware research.
Research topics includes, but not limited to:

Research angles:

  • Programming abstractions
  • Compiler techniques
  • Runtime optimization
  • Libraries/frameworks
  • High-performance algorithms
  • Hardware architecture
  • Performance model
Tensor methods:
  • Data: dense, sparse, structured, symmetric layout; random or non-negative values; etc.
  • Randomized, approximate, etc.
  • Tensor operators, such as tensor products, tensor-matrix multiplication, tensor-tensor multiplication, matrix-matrix multiplication
  • Tensor decompositions, such as Canonical polyadic decomposition (CPD), Tucker decomposition, etc.
  • Tensor networks, such as tensor train, tensor ring, hierarchical Tucker, the projected entangled pair states (PEPS), etc.
  • Tensor regression, tensor component analysis, tensor-structured dictionary learning, etc.

Platforms:

  • CPUs
  • GPUs (e.g., NVIDIA, AMD, Intel)
  • AI accelerators (e.g., SambaNova, Graphcore, Habana, GroqRack)
  • Wafer-scale system (e.g., Cerebras)
  • FPGAs
  • ASICs
  • Any kinds of simulators

Position Papers
Discussion and communication are the primary goals of the workshop. Thus, we only ask for 2-page position papers. The submitted work is very flexible in content. It could be early, in-progress research; could have not very complete experiments or results; could be a valuable survey of recent research trends or tools; could propose an important open question and call for solution; could be an experience report even with failed approaches but with some lessons learned. Submitted papers will undergo peer review by a program committee of experts from diverse research domains working on tensor problems.

Papers should follow the two-column formatting guidelines for SIGPLAN conferences (the acmart format with the sigplan two-column option) and up to 2 pages, excluding references. Review is single-blind, please include authors’ names on the submitted PDF.

Paper submission will be via EasyChair. The accepted papers will not be published in a proceeding. Presentation slides will show on the workshop website.

Important Dates
Paper submission: March 25, 2024
Author Notification: April 8, 2024
Workshop: April 27 1-5pm, 2024


Note: The Call for Paper type has not been set for this item!

Call for Papers: ICCD 2024
https://www.iccd-conf.com/
Submitted by Christina Giannoula

ICCD encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology. We especially encourage submissions that look forward to future systems and technologies. Authors are asked to submit technical papers in accordance with the submission guidelines (https://www.iccd-conf.com/Submission_guide.html)

in one of the following tracks:
Track 1: Computing Systems
System architectures; System support for multi/many cores, co-processors, and accelerators; System support for security, reliability, and energy efficiency and proportionality; Virtual memory; System support for emerging technologies, including NVM, quantum, neuromorphic, bio-inspired computing, machine learning, and artificial intelligence applications; Storage systems for data center and cloud/edge computing, high-performance computing (HPC), exascale systems, and serverless computing.

Track 2: Software Architectures, Compilers, and Tool Chains
Software architectures, compilers, programming language/model, firmware, OS, hypervisor, runtime design, and co-design for embedded/real-time systems; middleware for embedded systems, including resource awareness, reconfiguration, and energy/power management; compiler support for enhanced debugging, profiling, and traceability.

Track 3: Hardware Architectures
Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining, caches, branch prediction, multithreading, and networks-on-chip; Techniques for low-power, secure, and reliable processor architectures; Hardware acceleration for emerging applications including NVM, quantum, neuromorphic, bio-inspired; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, retrospectives.

Track 4: Test, Verification, and Security
Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods; Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs;
Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation; Hardware security primitives and methodologies; Side-channel analysis, attacks and mitigations for processors and accelerators; Interaction between test,
security and trust.

Track 5: Electronic Design Automation
System-level design and synthesis; High-level, logic, and physical synthesis; Analysis and optimization of timing, power, variability/yield, temperature, and noise; Physical design, including partitioning, floorplanning, placement, and routing; Clock tree synthesis; Verification methods at different levels of the EDA flow; Tools for multiple-clock domains, asynchronous, and mixed-timing methodologies; CAD support for accelerators, FPGAs, SoCs, ASICs, NoC, and general-purpose processors; CAD for manufacturing, test, verification, and security; Tools and design methods for emerging technologies (photonics, MEMS, spintronics, nano, quantum); interaction of EDA and AI/ML.

Track 6: Logic and Circuit Design
Circuit design techniques for digital, memory, analog, and mixed-signal systems; Circuit design techniques for high performance and low power; Circuit design techniques for robustness under process variability, electromigration, and radiation; Design techniques for emerging and maturing
technologies (MEMS, nano-spintronics, quantum, flexible electronics, multi-gate devices, in-memory computing); Asynchronous circuit design; Signal-processing, graphic-processor, and datapath circuits. A complete version of the paper should be submitted as a PDF file following the submission guidelines.

IMPORTANT DATES:
May 5 Abstract submission
May 12 Full paper submission
Aug 1 Notification of acceptance

Any questions about submission should be directed tothe Program Chairs, Benjamin Carrion Schaefer and Sara Vinco.
Please consult the ICCD 2024 website for additional information about the conference and submission details.


Call for Presentations: WACI @ ASPLOS 2024
https://www.asplos-conference.org/asplos2024/call-for-waci/
Submitted by Phitchaya Mangpo Phothilimthana

The Wild and Crazy Ideas (WACI) session is a time-honored tradition at ASPLOS that frees researchers from the shackles of realism, removes the blinders of short-term thinking, and opens the scientific mind to uncharted frontiers. Since 1998, WACI has provided a counterweight to the conservative impulses wrought by the traditional peer review path.

This is your moment to propose something huge—something no one else is talking about. Craft a talk that:

  • Falls within the ASPLOS purview and is related to architecture, programming languages, and operating systems in some capacity. Interdisciplinary ideas that touch on multiple topics are preferred, but not required.
  • Is not (yet) publishable research. Propose something neither you nor anyone else in the community is actually working on—for example, because it seems only barely feasible, because it requires thinking far into the future, because it strays into intellectual domains too far from core ASPLOS expertise, or because it directly contradicts the conventional wisdom.
  • Might change the world. Your idea must be enormous. Unshackle your ambition.
  • Ideas may also be funny—we encourage it!—but really great WACI talks contain an element of real, world-changing, convention-challenging research thought.

This year, we’re soliciting submissions as short videos. Think of this as a beta-quality teaser for what your real, on-stage talk would be like. Upload a video at most 5 minutes in length to the submission form by March 16 (AoE). We will select talks based on their potential to provoke thoughts and discussion, not their production value—so it’s OK to submit a rough prototype.

If the WACI chairs select your talk, here’s what you can expect:

  1. You write a longer version of your idea (limit: two pages) for publication on the WACI website.
  2. The WACI chairs work with you to craft an excellent, compact, entertaining talk for the WACI session.

Contact the WACI chairs, Sara Achour and Mangpo Phothilimthana, with any questions.


Call for Presentations: OSCAR @ ISCA 2024
https://oscar-workshop.github.io/
Submitted by Luca Carloni

3rd Workshop on Open-Source Computer Architecture Research (OSCAR) 2024
Co-located with ISCA 2024
https://oscar-workshop.github.io/

The workshop is aimed at fostering the community of researchers who are interested in developing and sharing open-source hardware and software for the design of next-generation computer architectures. The goal of OSCAR is to bring together a community of researchers from academia, industry and government labs who are interested in open-source computer architectures. The recent past has seen significant progress in this direction, including contributing open-source hardware components, software tools, as well as integration platforms to simplify the realization of system prototypes with FPGA or ASIC technologies. The number of developers and users of these open-source artifacts has increased substantially.

Scope: Topics of interest of the OSCAR workshop include, but are not limited to:

  • Open-source processors (CPU, GPU, AI processors…)
  • Open-source accelerators (programmable, configurable, fixed-function…)
  • Open-source components (e.g., caches, busses, network-on-chip, peripherals, sensors…)
  • Software aspects of heterogeneous component integration
  • Security, reliability, and verification of open-source architectures and components
  • CAD tools and methodologies for design and integration of open-source components
  • Full-system simulation of open-source architectures
  • Infrastructures specialized for FPGA prototyping or chip designs of open-source architectures
  • Design experiences with the use of open-source components, tools, and platforms
  • Discussion of case studies, applications that benefit from open-source architecture research

Workshop Format: OSCAR will have a mix of invited talks and presentations selected from the submissions to this call for participation. Abstract should be submitted in PDF format (max 2 pages) and include title, authors, affiliations and e-mail address of the contact author. Submissions of early works and position papers are encouraged. Workshop submissions do not preclude publishing at future conference venues. While no formal proceedings are planned, the OSCAR organizers may seek the realization of a journal special issue collecting a subset of the contributions, after the workshop.

Organizers:

  • Pradip Bose (IBM)
  • Luca Carloni (Columbia University), chair
  • Sophia Shao (UC Berkeley)
  • Caroline Trippel (Stanford University)

Important Dates:

  • Abstract submissions: April 29, 2024
  • Author notification: May 13, 2024
  • Workshop date: June 29 or June 30, 2024

 


Call for Workshops/Tutorials: PACT 2024
https://pact2024.github.io/workshops/
Submitted by Khaled Khasawneh

Parallel Architectures and Compilation Techniques – PACT 2024 

Workshop/Tutorials to be held on October 13, 2024 (full day) and October 16, 2024 (afternoon).

Important Dates
* Submission deadline for workshops: July 3rd, 2024.
* Submission deadline for tutorials: August 9th, 2024.
Proposals should be sent via email to: Hoda Naghibijouybari (hnaghibi@qti.qualcomm.com)
* Notification: rolling acceptances and encourage potential organizers to contact us as soon as possible.

Proposal Format
Proposals should include the following information in a PDF file (2-3 pages):

For a Workshop

* Title, scope, format and the main topics of the workshop
* Invited or keynote speakers (if any)
* Panel discussion (if any)
* Organizers’ bio and affiliation, and a tentative list of PC members
*  Duration (half day / full day)
* Expected and maximum number of participants
* Information on past workshops on the same topic with statistics on the number of attendees/submissions

For a tutorial
* Title and abstract of the tutorial
* An outline of tutorial content and objectives
* Prerequisite knowledge
* Special requirements (if any)
* Organizers’ bio and affiliation
* Duration (half day / full day)
* Expected and maximum number of participants
* Information on past workshops on the same topic with statistics on the number of attendees/submissions


Call for Workshops/Tutorials: MICRO 2024
https://microarch.org/micro57/submit/workshops.php
Submitted by Gururaj Saileshwar

57th International Symposium on Microarchitecture – MICRO 2024   

Workshops and tutorials will take place on Saturday/Sunday, November 2/3, before the main symposium days.

Important Dates
Proposal Submission Deadline: May 31, 2024 
Notification: June 14, 2024
Proposals should be sent via email to: gururaj@cs.toronto.edu and ttambe@stanford.edu

Proposal Format
Proposals should be 1–2 pages long and include the following information:
* Title of the workshop/tutorial
* Organizers and their affiliations (including short bios)
* Expected duration of the workshop/tutorial; i.e., half day or full day
* If the workshop/tutorial was previously held, provide the location (i.e., which conference), date, number of published papers (if any), and number of attendees at the last event. Please also highlight what new/different content would be covered in this edition.
* Expected number of attendees
* For a workshop proposal, provide a sample call for papers and workshop main topics
* For a tutorial proposal, provide the abstract of the tutorial

Proposals should highlight a plan for ensuring diversity in invited speakers, tutorial presenters, and organizing and selection committees (if applicable).


Call for Workshops/Tutorials: SSH-SoC @ DAC 2024
https://ssh-soc-workshop.github.io/2024/
Submitted by Pasquale Davide Schiavone

2nd SSH-SoC: Safety and Security in Heterogeneous Open System-on-Chip Platforms
In conjunction with Design and Automation Conference (DAC) 2024
June 23th, 2024

The workshop welcomes work-in-progress contributions and novel directions to tackle the challenges and profit from the opportunities provided by open hardware designs and architectures for the development of next-generation heterogeneous SoCs.
The topics for the workshop include, but are not limited to:

  • Security verification for hardware designs and system architectures
  • Architectural aspects of secure system integration
  • Secure system integration of third-party hardware components
  • Automated firmware generation supporting secure system execution
  • Security aspects of reconfigurable designs
  • Time-predictable system execution in open-hardware designs●
  • Performance analysis, timing analysis, and worst-case analysis supporting
  • time-predictable system execution and/or communications in open-hardware designs
  • Automated firmware generation supporting time-predictable execution
  • Fault tolerance and execution in harsh conditions leveraging open-hardware designs
  • System architectures and methodologies supporting energy efficient/performant system execution in open-hardware designs
  • Hardware/software co-design, co-integration and co-verification of open-source processors, accelerators, and components
  • Open architectures for reconfigurable platforms and open CAD tools
  • Tools and analysis for open FPGAs and reconfigurable platform

Submission deadline:  April 22th, 2024
All of the information regarding the workshop is available at the website:
https://ssh-soc-workshop.github.io/2024/


Call for Workshops/Tutorials: ISC High Performance 2024 Call for Tutorials
https://www.isc-hpc.com/submissions-tutorials-2024.html
Submitted by Diana Moise

Deadline for submission is December 8th, 2023
The ISC High Performance 2024 Conference call for tutorials is now open! (https://www.isc-hpc.com/submissions-tutorials-2024.html)
The ISC tutorials are interactive courses and collaborative learning experiences focusing on key topics of high performance computing, machine learning, data analytics and quantum computing. Renowned experts in their respective fields will give attendees a comprehensive introduction to the topic as well as providing a closer look at specific problems. Tutorials are encouraged to include a “hands-on” component to allow attendees to practice prepared materials.
Submitted tutorial proposals will be reviewed by the ISC 2024 Tutorials Committee, which is chaired by Shadi Ibrahim, Inria, France, with Diana Moise, HPE, Switzerland as Deputy Chair.
All tutorial attendees require a tutorial pass. For accepted tutorials, ISC will provide a limited number of complimentary tutorial participation passes to tutorial presenters.
ISC 2024 registration fees will be published in early 2024.
AREAS OF INTEREST
Tutorial submissions are encouraged on the following topics:
 – Any area of interest listed in the call for research papers (https://www.isc-hpc.com/submissions-research-papers-2024.html).
 – Additional topics that expand broader community engagement.
 – Innovative and emerging HPC technologies, e.g., cloud technologies for HPC, quantum computing, artificial intelligence, and machine learning.
 – Introductory tutorials for attendees new to HPC
We encourage tutorials that serve a broad audience over tutorials that focus solely on the research in a limited domain or a particular group. Practical tutorials are preferred to completely theoretical ones and we encourage organizers to incorporate hands-on sessions where appropriate.
REVIEW
– Each tutorial will be reviewed by a minimum of 3 reviewers.
– Criteria for review include originality, significance, timeliness, impact, community interest, attendance in prior years (if applicable), quality, hands-on activity, and clarity of the proposal.
– Reviews will include actionable feedback related to the length of the tutorials and the organization of the content (for example, suggestions to add and remove some contents).
IMPORTANT DATES
Submission Deadline December 8, 2023 23:59pm AoE
Notification of Acceptance February 9, 2024
Working Materials for Tutorial Attendees due April 30, 2024
Tutorials May 12, 2024
Half-day: 9:00 am – 1:00 pm, 2:00 pm – 6:00 pm
Full-day: 9:00 am – 6:00 pm
PROGRAM COMMITTEE
Shadi Ibrahim, Inria, France (Chair)
Diana Moise, Cray, HPE, Switzerland (Deputy Chair)
Olivier Beaumont, Inria, France
Jalil BOUKHOBZA, ENSTA Bretagne, Lab-STICC CNRS UMR 6285, France
Suren Byna, The Ohio State University, Lawrence Berkeley National Laboratory, United States of America
Philip Carns, Argonne National Laboratory, United States of America
Ewa Deelman, USC Information Sciences Institute, United States of America
Aniello Esposito, HPE, Switzerland
Ana Gainaru, Oak Ridge National Laboratory, United States of America
Bilel Hadri, KAUST Supercomputing Laboratory, Saudi Arabia
Heike Jagode, University of Tennessee Knoxville, United States of America
Michael Kuhn, Otto von Guericke University Magdeburg, Germany
Jay Lofstead, Sandia National Laboratories, United States of America
Sarah Neuwirth, Johannes Gutenberg University Mainz, Jülich Supercomputing Centre (JSC), Germany
Gabriel Noaje, NVIDIA, Singapore
George Pallis, University of Cyprus, Cyprus
Antonio J. Peña, Barcelona Supercomputing Center (BSC), Spain
Anna Queralt, Polytechnic University of Catalonia, Barcelona Supercomputing Center, Spain
Ana-Lucia Varbanescu, University of Twente, University of Amsterdam, Netherlands
Amelie Chi Zhou, Hong Kong Baptist University, Hong Kong
For more complete and up-to-date information, please see the online call for tutorials here: https://www.isc-hpc.com/submissions-tutorials-2024.html

Call for Workshops/Tutorials: ISC High Performance 2024: Call for Tutorials
https://www.isc-hpc.com/submissions-tutorials-2024.html
Submitted by Diana Moise

ISC High Performance 2024
Call for Tutorials
Deadline for submission is December 8th, 2023
The ISC High Performance 2024 Conference call for tutorials is now open! (https://www.isc-hpc.com/submissions-tutorials-2024.html)
The ISC tutorials are interactive courses and collaborative learning experiences focusing on key topics of high performance computing, machine learning, data analytics and quantum computing. Renowned experts in their respective fields will give attendees a comprehensive introduction to the topic as well as providing a closer look at specific problems. Tutorials are encouraged to include a “hands-on” component to allow attendees to practice prepared materials.
Submitted tutorial proposals will be reviewed by the ISC 2024 Tutorials Committee, which is chaired by Shadi Ibrahim, Inria, France, with Diana Moise, HPE, Switzerland as Deputy Chair.
All tutorial attendees require a tutorial pass. For accepted tutorials, ISC will provide a limited number of complimentary tutorial participation passes to tutorial presenters.
ISC 2024 registration fees will be published in early 2024.
AREAS OF INTEREST
Tutorial submissions are encouraged on the following topics:
 – Any area of interest listed in the call for research papers (https://www.isc-hpc.com/submissions-research-papers-2024.html).
 – Additional topics that expand broader community engagement.
 – Innovative and emerging HPC technologies, e.g., cloud technologies for HPC, quantum computing, artificial intelligence, and machine learning.
 – Introductory tutorials for attendees new to HPC
We encourage tutorials that serve a broad audience over tutorials that focus solely on the research in a limited domain or a particular group. Practical tutorials are preferred to completely theoretical ones and we encourage organizers to incorporate hands-on sessions where appropriate.
REVIEW
– Each tutorial will be reviewed by a minimum of 3 reviewers.
– Criteria for review include originality, significance, timeliness, impact, community interest, attendance in prior years (if applicable), quality, hands-on activity, and clarity of the proposal.
– Reviews will include actionable feedback related to the length of the tutorials and the organization of the content (for example, suggestions to add and remove some contents).
IMPORTANT DATES
Submission Deadline December 8, 2023 23:59pm AoE
Notification of Acceptance February 9, 2024
Working Materials for Tutorial Attendees due April 30, 2024
Tutorials May 12, 2024
Half-day: 9:00 am – 1:00 pm, 2:00 pm – 6:00 pm
Full-day: 9:00 am – 6:00 pm
PROGRAM COMMITTEE
Shadi Ibrahim, Inria, France (Chair)
Diana Moise, Cray, HPE, Switzerland (Deputy Chair)
Olivier Beaumont, Inria, France
Jalil BOUKHOBZA, ENSTA Bretagne, Lab-STICC CNRS UMR 6285, France
Suren Byna, The Ohio State University, Lawrence Berkeley National Laboratory, United States of America
Philip Carns, Argonne National Laboratory, United States of America
Ewa Deelman, USC Information Sciences Institute, United States of America
Aniello Esposito, HPE, Switzerland
Ana Gainaru, Oak Ridge National Laboratory, United States of America
Bilel Hadri, KAUST Supercomputing Laboratory, Saudi Arabia
Heike Jagode, University of Tennessee Knoxville, United States of America
Michael Kuhn, Otto von Guericke University Magdeburg, Germany
Jay Lofstead, Sandia National Laboratories, United States of America
Sarah Neuwirth, Johannes Gutenberg University Mainz, Jülich Supercomputing Centre (JSC), Germany
Gabriel Noaje, NVIDIA, Singapore
George Pallis, University of Cyprus, Cyprus
Antonio J. Peña, Barcelona Supercomputing Center (BSC), Spain
Anna Queralt, Polytechnic University of Catalonia, Barcelona Supercomputing Center, Spain
Ana-Lucia Varbanescu, University of Twente, University of Amsterdam, Netherlands
Amelie Chi Zhou, Hong Kong Baptist University, Hong Kong
For more complete and up-to-date information, please see the online call for tutorials here: https://www.isc-hpc.com/submissions-tutorials-2024.html

Call for Workshops/Tutorials: Call of Workshops and Tutorials for FPGA’24
https://www.isfpga.org/call-for-workshops/
Submitted by Aman Arora

The 32nd edition of FPGA ​invites the submission of half-day and full-day tutorial and workshop proposals. The workshops will be held on​ March 3, 2024 in Monterey, California, USA. The aim of the conference workshops is to emphasize emerging topics related but not limited to FPGA architectures and tools, reconfigurable computing, and custom hardware acceleration for applications such as communications, machine learning, networking, and other problems. The tutorials are expected to enable beginning researchers to enter the area, current researchers to broaden their scope, and practitioners to gain new insights and applicable skills. The workshops should highlight current topics related to technical and/or industry issues and should include a set of invited presentations and/or panels that encourage the participation of attendees in active discussion.

Workshop Proposal Format:

Each workshop proposal (maximum 2 pages) must include:

  • Title of the tutorial or workshop
  • Organizers: names, affiliation, contact information
  • Scope and topics
  • Rationale: Why is the topic current and important? Why would the tutorial/workshop attract attendees?
  • Duration: Half-day, Full-day and a tentative schedule (up to 3.5 hours for half day; the event can be shorter than the allotted time)
  • Names of potential speakers

Proposal Submission:

Proposals should be submitted as a single PDF file via email to the FPGA Workshop Chair workshopchair@isfpga.org (with a subject line “FPGA Workshop/Tutorial Proposal:”) by December 1, 2023. Should you have any questions regarding this call, please address the same email.


Call for Posters: ISPASS 2024
http://www.ispass.org/ispass2024/
Submitted by Fangjia Shen

ISPASS 2024 is calling for additional posters.
The extended deadline for poster abstract submission is Wednesday March 20th, 2024.
https://ispass.org/ispass2024/

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research focused on performance analysis in the design of computer systems and software. ISPASS 2024 will be held on May 5-7, 2024 in Indianapolis, Indiana, U.S.A. Authors are invited to submit extended poster abstracts encompassing ongoing or late breaking research, tools or benchmarks in any of the following fields:

#Performance and efficiency (power, area, etc.) evaluation methodologies
– Analytical modeling
– Statistical approaches
– Tracing and profiling tools
– Simulation techniques
– Hardware (e.g., FPGA) accelerated simulation
– Hardware performance counter architectures
– Power, temperature, variability and/or reliability models for computer systems
– Microbenchmark-based hardware analysis techniques

 

#Foundations of performance and efficiency analysis
– Metrics
– Bottleneck identification and analysis
– Visualization

 

#Efficiency and performance analysis of commercial and experimental hardware
– Multi-threaded, multicore and many-core architectures
– Accelerators and graphics processing units
– Memory systems, including storage-class memory
– Embedded and mobile systems
– Enterprise systems and data centers
– HPC and Supercomputers
– Computer networks
– Quantum computing
– Emerging technologies

 

#Efficiency and performance analysis of emerging workloads and software
– Software written in managed languages
– Virtualization and consolidation workloads
– Datacenter, internet-sector workloads
– Embedded, multimedia, games, telepresence
– Deep learning and convolutional neural networks

#Application and system code tuning and optimization

#Confirmations or refutations of important prior results

In addition to research papers, ISPASS welcomes tool and benchmark paper submissions.
The conference is an ideal forum to introduce new tools and benchmarks to the community. These extended poster abstracts, which can detail tools and benchmarks in the above fields of interest, will be judged primarily on their potential to enable and amplify future research.


SIGARCH team updates

Submitted by Boris Grot

We are pleased to announce the following recent changes to team SIGARCH:

  • Blog editor: Dmitry Ponomarev (taking over from Brandon Lucia and Christina Delimitrou)
  • Content editor: Adarsh Patil (taking over from Akanksha Jain)
  • Social Media editors: Elba Garza and Jonathan Balkind (taking over from Adrian Sampson)

We extend a big ‘thank you’ to Brandon, Christina, Akanksha and Adrian for their past service, and are grateful to Dmitry, Adarsh, Elba and Jonathan for stepping in.


Episode 15 of the Computer Architecture Podcast released! Featuring Guest Dr. Karu Sankaralingam
https://comparchpodcast.podbean.com/e/ep-15-the-hardware-startup-experience-from-business-case-to-software-with-dr-karu-sankaralingam/
Submitted by Lisa Hsu

Computer Architecture Podcast:a series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.

Announcing the release of Episode 15: The Hardware Startup Experience from Business Case to Software with Dr. Karu Sankaralingam, who is a is a Professor at the University of Wisconsin-Madison, an entrepeneur, inventor, as well as a Principal Research Scientist at NVIDIA. His work has been featured in industry forums of Mentor and Synopsys, and has been covered by the New York Times, Wired, and IEEE Spectrum. He founded the hardware startup SimpleMachines in 2017 which developed chip designs applying dataflow computing to push the limits of AI generality in hardware and built the Mozart chip. In his career, he has led three chip projects: Mozart (16nm, HBM2 based design), MIAOW open source GPU on FPGA, and the TRIPS chip as a student during his PhD. In his research he has pioneered the principles of dataflow computing, focusing on the role of architecture, microarchitecture and the compiler. He has published over 100 research papers, has graduated 9 PhD students, is an inventor on 21 patents, and 9 award papers. He is a Fellow of IEEE.

Listen to the episode at https://comparchpodcast.podbean.com/. Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.


Episode 14 of Computer Architecture Podcast Released! Featuring guest Dr. Gabriel Loh, AMD
https://comparchpodcast.podbean.com/
Submitted by Suvinay Subramanian

Computer Architecture Podcast: a series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.

Announcing the release of Episode 14: System Design for Exascale Computing and Advanced Memory Technologies with Dr. Gabriel Loh, who is a Senior Fellow at AMD Research and Advanced Development. Gabe is known for his contributions to 3D die-stacked architectures, memory organization and caching techniques, and chiplet multicore architectures. His ideas have influenced multiple commercial products and industry standards. He is a recipient of ACM SIGARCH’s Maurice Wilkes Award, is a Hall of Fame member for MICRO, HPCA, ISCA, and a recipient of the NSF CAREER award.

Listen to the episode at https://comparchpodcast.podbean.com/. Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Akanksha Jain
SIGARCH Content Editor

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