This is the 1st March 2019 digest of SIGARCH Messages.

In This Issue


Call for Nominations: ACM/IEEE-CS Eckert-Mauchly Award
https://www.computer.org/web/awards/eckert-mauchly
Submitted by Milagros Lovos

ACM and the IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which was initiated in 1979. The award is known as the computer architecture community’s most prestigious award. The award recognizes outstanding contributions to computer and digital systems architecture. It comes with a certificate and a $5,000 honorarium. The award was named for John Presper Eckert and John William Mauchly, who collaborated on the design and construction of the Electronic Numerical Integrator and Computer (ENIAC), the first large-scale electronic computing machine, which was completed in 1947.

NOMINATION GUIDELINES:
– Open to all. Anyone may nominate.
– Self-nominations are not accepted.
– This award requires 3 endorsements.
– Submit your nomination by 30 March 2019 to www.computer.org/web/awards/eckert-mauchly.
– New nomination form: https://ieee.secure-platform.com/a/solicitations/home/157 (LOGIN REQUIRED)

The award will be presented at ISCA 2019 (ACM/IEEE International Symposium on Computer Architecture), taking place in Phoenix, Arizona, USA, June 22–26, 2019.

Questions?
Write to IEEE Computer Society Awards Administrator at awards@computer.org.


Call for Nominations: 2019 Alan D. Berenbaum Distinguished Service Award
https://www.sigarch.org/benefit/awards/acm-sigarch-distinguished-service-award
Submitted by Natalie Enright Jerger

ACM SIGARCH Alan D. Berenbaum Distinguished Service Award

This annual award is presented to an individual who has contributed important service to the computer architecture community.

The award is presented annually at the International Symposium on Computer Architecture Awards Banquet. This year’s recipient will be invited to accept the award at ISCA 2019. Recipients receive a memento engraved with their name along with a $1000 honorarium. The award recipient also receives up to $2000 towards support for travel costs, including airfare, hotel, and conference registration for ISCA. The recipient is listed with a citation for their award on the SIGARCH Alan D. Berenbaum Distinguished Service Award webpage.

Nominations should consist of:

1. Name, address, phone number and email of person making the nomination.
2. Name, affiliation, address, email, and telephone number of candidate for whom the award is recommended.
3. A statement (between 200 and 500 words long) explaining why the nominee deserves the award in question. Note that the award is given for service that goes above and beyond traditional service.
4. 4-7 letters of support. Include the name, affiliation, email address, and telephone number of the letter writer(s). Supporters of multiple candidates are strongly encouraged to compare the candidates in their letters.
5. State any conflicts of interest (COI) between the nominee and any committee members. Refer to the ACM COI guidelines (item 7) to determine what constitutes a COI. Please state explicitly if there are no conflicts.

Please send all your nomination materials as one pdf file no later than April 1, 2019 to the Chair of the Nominating Committee (Matthew Farrens farrens@cs.ucdavis.edu).


Call for Nominations: 2019 Maurice Wilkes Award
https://www.sigarch.org/benefit/awards/acm-sigarch-maurice-wilkes-award
Submitted by Sarita Adve

ACM SIGARCH Maurice Wilkes Award

The award of $2,500 is given annually for an outstanding contribution to computer architecture made by an individual whose computer-related professional career (graduate school or full-time employment, whichever began first) started no earlier than January 1st of the year that is 20 years prior to the year of the award.*

The award is presented annually at the International Symposium on Computer Architecture Awards Banquet. This year’s recipient will be invited to accept the award at ISCA 2019.

Nominations should consist of:

1. Name, address, and phone number of person making the nomination.
2. Name, affiliation, address, email, and telephone number of candidate for whom the award is recommended.
3. A statement (between 200 and 500 words long) as to why the candidate deserves the award. Note that since the award is for an outstanding contribution, the statement and supporting letters should address what the contribution is and why it is both outstanding and significant.
4. A maximum of five letters of support. Include the name, affiliation, email address, and telephone number of the letter writer(s). Supporters of multiple candidates are strongly encouraged to compare the candidates in their letters.
5. A statement regarding the nominee’s specific year of eligibility. That is, when did they begin their computer-related professional career, and are there any circumstances for which the 20 years of eligibility should be adjusted?
6. State any conflicts of interest (COI) between the nominee and any committee members. Refer to the ACM COI guidelines (item 7) to determine what constitutes a COI. Please state explicitly if there are no conflicts.

Please send all your nomination materials as one pdf file no later than April 1, 2019 to wilkes_sigarch@acm.org.

*At the discretion of the SIGARCH Executive Committee, eligibility may be adjusted for documented career interruptions (e.g., family-related or medical leaves, military service). Questions about eligibility should be directed to the SIGARCH Chair (chair_sigarch@acm.org).


Call for Participation: Tutorial on Post-Moore Computing
https://crnch-rg.gitlab.io/asplos-2019/
Submitted by Jason Riedy

Post-Moore Computing Tutorial
in conjunction with ASPLOS 2019
Providence, RI, USA
Apr 14, 2019

This tutorial will provide an overview of the new “Post-Moore” testbed hosted by Georgia Tech, the CRNCH Rogues Gallery in the Center for Research into Novel Computing Hierarchies (CRNCH). Attendees will gain detailed technical knowledge of platforms along with the lessons learned so far from current research. The tutorial includes hands-on work with rogue systems in our gallery including the Emu Chick and an analog neuromorphic platform, the Field Programmable Analog Array (FPAA). Attendees will be able to work with the Emu toolchain and will learn more about what post-Moore computing systems might look like and how they will be used. In addition, this tutorial will provide attendees an overview or related tools and benchmarks so they can continue research with post-Moore computing after the event.

ORGANIZERS:
Jason Riedy and Jeffrey Young (Georgia Institute of Technology)


Call for Participation: ASPLOS 2019
https://asplos-conference.org
Submitted by Jishen Zhao

The 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
Providence, Rhode Island, USA
April 13-17, 2019

This is a friendly reminder to register for ASPLOS’19. If you haven’t registered yet, there is still time! The early registration deadline for ASPLOS’19 is on March 22. We have also negotiated a group rate at the conference hotel, The Providence Biltmore hotel. Group rates ($174/night for standard King or Queen rooms) apply to stays between 4/12 and 4/16. Reservations must be made on or before Friday, March 22, to guarantee this rate.

Conference page: https://asplos-conference.org
Conference program: https://asplos-conference.org/programs/
Registration: https://asplos-conference.org/registration/#reg
Hotel reservation: https://asplos-conference.org/registration/#venue


Call for Participation: VEE 2019
https://conf.researchr.org/home/vee-2019
Submitted by Jennifer B. Sartor

The 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE’19)
in conjunction with ASPLOS
Providence, Rhode Island, United States
April 14, 2019

The International Conference on Virtual Execution Environments (VEE’19) brings together researchers and practitioners from different computer systems domains to interact and share ideas in order to advance the state of the art of virtualization and broaden its applicability. Virtualization techniques encompass the underlying hardware, the operating system, and the runtime system.

We are excited to host a keynote address on Amazon’s emerging Firecracker hypervisor, written in Rust, which is specialized for current cloud trends such as serverless compute.

Registration is open, and early bird registration is until March 22, 2019.


Call for Participation: ISPASS 2019
https://www.ispass.org/ispass2019/
Submitted by Thomas Wenisch

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
Madison, Wisconsin, USA
March 24-26, 2019

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software. ISPASS 2019 will be held March 24 through 26, 2019 in Madison, WI.

The preliminary conference program has been posted, and registration and hotel reservations are now open. A detailed program is available on the conference website at https://www.ispass.org/ispass2019/

The early registration and discount hotel reservation deadlines are Feb. 15.
Registration: https://www.regonline.com/ispass-2019
Hotel: https://www.hilton.com/en/hi/groups/personalized/M/MSNMHHF-IEEE-20190324/index.jhtml?WT.mc_id=POG

Through the generous support of the sponsoring IEEE Technical Committees, the conference is pleased to offer travel grants to enable students to attend. Travel grant applications are due Feb. 11. See the conference website for details.

We invite all to attend the conference and hope to see you in Madison.

ORGANIZERS:
General Chair: Thomas F. Wenisch
Program Chair: Kelly Shaw


Call for Papers: FPL 2019
http://fpl2019.bsc.es
Submitted by Xavier Martorell

29th International Conference on Field-Programmable Logic and Applications (FPL)
Barcelona, Spain
September 9-13, 2019

The International Conference on Field-Programmable Logic and Applications is the premier conference covering the area of field-programmable logic architectures, reconfigurable computing and applications. The conference continues to bring together researchers and practitioners from both academia and industry and from around the world, to discuss about topics related to those areas. During the past 28 years, many of the advances in reconfigurable system architectures, applications, embedded processing, design automation methods and tools have been first published in the proceedings of the FPL conference series.

The 29th edition will be held in the premises of the Universitat Politecnica de Catalunya (UPC) in Barcelona, also hosting the Barcelona Supercomputing Center (BSC). The event will take place at the UPC Vertex Building on the North Campus of the University (Dulcet Street, no. 1, Barcelona).

SUBMISSION GUIDELINES:
Paper Submission at Easychair: https://easychair.org/conferences/?conf=fpl20190

Authors are invited to submit original and unpublished papers in IEEE double column format. *Submitted papers must be limited to 6 pages plus references* (i.e. the references do not count in the 6 pages; and references must not exceed two pages). This is a strict limit, and papers exceeding this limit will be rejected automatically.

Authors are required to use the standard IEEE templates in format A4 and not to include page numbers, to ensure compatibility with IEEE Xplore. Templates for LaTeX and Microsoft Word 2003 are available directly from IEEE:

http://www.ieee.org/conferences_events/conferences/publishing/templates.html

All contributions must be submitted electronically in PDF format. FPL 2019 uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. Exceptions may be allowed with prior approval of the Programme Chairs, in cases where the authors’ identity is vital to evaluating the paper (e.g., papers presenting updates of infrastructure used by the FPGA community). References to the authors’ prior work should be made in the 3rd person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as “Removed for blind review”, but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission.

For more information, please visit the FPL2019 website.

ORGANIZERS:
General Chair:
Xavier Martorell

Technical Program Co-Chairs:
Ioannis Sourdis, Carlos Alvarez, and Christos-Savvas Bouganis


Call for Papers: PACT 2019
http://pactconf.org/
Submitted by Anne C. Elster

28th International Conference on Parallel Architectures and Compilation Techniques (PACT 2019)
Seattle, USA
September 23-26, 2019

Abstracts due: April 11, 2019

Sitting uniquely at the intersection of classical parallel architectures and compilers, the enduring PACT conference brings together researchers from architecture, compilers, programming languages, and applications to present and discuss their latest research results.

We solicit contributions in a broad range of topics, including (but not limited to) the following:
– Parallel architectures and computational models
– Compilers and tools for parallel computer systems
– Multicore, multithreaded, superscalar, and VLIW architectures
– Compiler/hardware support for hiding memory latencies
– Support for correctness in hardware and software
– Reconfigurable parallel computing
– Dynamic translation and optimization
– I/O issues in parallel computing and their relation to applications
– Parallel programming languages, algorithms and applications
– Middleware and run time system support for parallel computing
– Application-specific parallel systems
– Applications and experimental systems studies of parallel processing
– Relevant aspects of distributed computing and mobile computing
– Heterogeneous systems using various types of accelerators
– Insights for the design of parallel architectures and compilers from modern parallel applications (e.g., machine learning, data analytics, and computational biology)
– Future parallel systems for beyond Moore’s law and/or beyond Exascale

SUBMISSION GUIDELINES:
Information for Authors: Paper submissions are due April 15, 2019, with abstracts due April 11, 2019. Detailed instructions for electronic submission and other important dates will be posted on the PACT conference web site (http://www.pactconf.org). For additional information regarding paper submissions, please contact the Program Chairs.

Tutorials / Workshops: Proposals are solicited for tutorials and workshops to be held immediately before and/or after the conference. Interested individuals are invited to contact the Workshops and Tutorials Chair.

Artifact Evaluation: An important foundation of many PACT papers is the software used to support the reported results. To recognize the effort involved in developing high-quality software and to foster a culture of reproducibility, PACT19 will include a separate artifact evaluation process.

ACM Student Research Competition: The ACM Student Research Competition (SRC) is a forum for graduate and undergraduate students to share their research results, exchange ideas, and improve their communication skills while competing for prizes. The SRC consists of three rounds: Online abstract submission authored by the student alone, poster session at PACT19 by authors selected abstracts, and presentation at PACT19 by authors of the top 3 posters selected by judges at the conference.

IMPORTANT DATES:
Conference Papers:
Abstract: April 11, 2019
Full Paper: April 15, 2019
Round 1 Rebuttal Period: May 19 – 22, 2019
Round 2 Rebuttal Period: June 23 – 26, 2019
Author Notification: July 8, 2019
Artifact Submission: July 15, 2019
Camera Ready Final Papers: August 23, 2019

Workshops and Tutorials Proposals due: April 15, 2019

ORGANIZERS:
General Chair: Andrew Lumsdaine, Pacific Northwest National Laboratory and the University of Washington
Program Chair: P. Sadayappan, The Ohio State University
Workshops/Tutorials Chair: Cindy Phillips, Sandia National Lab
Artifact Evaluation Chair: Jeffrey Carver, University of Alabama
Publicity Chairs: Anne Elster, Norwegian Institute of Science and Technology; James Lin, Shanghai Jiao Tong University
Web / Social Media Chair: Jiajia Li, Pacific Northwest National Laboratory

Sponsored by IEEE Computer Society


Call for Papers: IISWC 2019
http://ddl.escience.cn/f/RYDd
Submitted by Lei Liu (ICT, CAS)

2019 Annual IEEE International Symposium on Workload Characterization (IISWC’19)
Orlando, Florida, USA
November 3-5, 2019

This symposium is dedicated to the understanding and characterization of workloads that run on all types of computing systems. New applications and programming paradigms continue to emerge rapidly as the diversity and performance of computers increase. On one hand, improvements in computing technology are usually based on a solid understanding and analysis of existing workloads. On the other hand, computing workloads evolve and change with advances in microarchitecture, compilers, programming languages, and networking communication technologies. Whether they are smart phones and deeply embedded systems at the low end or massively parallel systems at the high end, the design of future computing machines can be significantly improved if we understand the characteristics of the workloads that are expected to run on them. This symposium, sponsored by IEEE Computer Society and the Technical Committee on Computer Architecture, will focus on characterizing and understanding emerging applications in consumer, commercial and scientific computing.

Additional details, including submission guidelines, are available at the conference web site.

ORGANIZERS:
General Co-chairs:
Yan Solihin, Univ of Central Florida
Amro Awad, Univ of Central Florida

Program Co-chairs:
Ravi Iyer, Intel
Vijay Janapa Reddi, Harvard


Call for Papers: NAS 2019
http://www.nas-conference.org/NAS-2019/index.html
Submitted by Rujia Wang

14th International Conference on Networking, Architecture, and Storage (NAS)
Enshi, China
August 15-17, 2019

IMPORTANT DATES:
Paper Submission Deadline: April 23, 2019 (AoE)
Author Notification: May 31, 2019
Camera-ready Paper: June 20, 2019

The 14th International Conference on Networking, Architecture, and Storage (NAS 2019) will be held from August 15-17, 2019 at Enshi, China. NAS 2019 provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on networking, high-performance computer architecture, and parallel and distributed data storage technologies. NAS 2019 will expose participants to the most recent developments in the interdisciplinary areas. Authors are invited to submit previously unpublished work for possible presentation at the conference. The program committee will nominate best papers for recognition in the three conference topic areas. All papers will be evaluated based on their novelty, fundamental insight, experimental evaluation, and potential for long-term impact; new-idea papers are encouraged. All accepted papers will be published in IEEE digital library. Selected and extended papers will be recommended to the special issue of Concurrency and Computation: Practice and Experience (SCI indexed).

Topics of interest include, but are not limited to the following:
– Accelerator-based architectures
– Ad hoc and sensor networks
– Application-specific, reconfigurable or embedded architectures
– Architecture for handheld or mobile devices
– Architecture, networking or storage modeling and simulation methodologies
– Big Data infrastructure
– Big Data services and analytics
– Cloud and grid computing
– Cloud storage
– Data-center scale architectures
– Effects of circuits and emerging technology on architecture
– Energy-aware storage
– File systems, object-based storage
– GPU architecture and programming
– HW/SW co-design and tradeoffs
– Mobile and wireless networks
– Network applications and services
– Network architecture and protocols
– Network information theory
– Network modeling and measurement
– Network security
– Non-volatile memory technologies
– Parallel and multi-core architectures
– Parallel I/O
– Power and energy efficient architectures and techniques
– Processor, cache, memory system architectures
– Software defined networking
– Software defined storage
– SSD architecture and applications
– Storage management
– Storage performance and scalability
– Storage virtualization and security
– Virtual and overlay networks

ORGANIZERS:
General Co-Chairs:
Dan Feng, Huazhong University of Science and Technology
Minghui Zheng, Hubei University for Nationalities

Program Chair:
Yu Hua, Huazhong University of Science and Technology

Vice Program Chairs:
Networking Track:
Cong Wang, City University of Hong Kong
Joongheon Kim, Chung-Ang University
Architecture Track:
Christopher Stewart, The Ohio State University
Shaolei Ren, University of California, Riverside
Storage Track:
Vaneet Aggarwal, Purdue University
Ziliang Zong, Texas State University

Lightning Talks and Pannel Chairs:
Yuhao Zhu, University of Rochester
Jingwen Leng, Shanghai Jiao Tong University

Publication Chairs:
Zhiyong Xu, Suffolk University
Weijun Xiao, Virginia Commonwealth University

Publicity Chairs:
Edith Ngai, Uppsala University
Rujia Wang, Illinois Institute of Technology
Zhenhua Li, Tsinghua University

Local Arrangement Chair:
Lingfang Zeng, Huazhong University of Science and Technology

Registration Chair:
Wei Tong, Huazhong University of Science and Technology

Steering Committee:
Xubin He, Temple University, USA (Chair)
Andre Brinkmann, University of Mainz, Germany
Hong Jiang, University of Texas at Arlington, USA
Xiaofeng Liao, Chongqing University, China
Jun Wang, University of Central Florida, USA
Changsheng Xie, Huazhong University of Science and Technology, China
Zhiyong Xu, Suffolk University, USA
Qing Yang, University of Rhode Island, USA
Jiwu Shu, Tsinghua University, China
Yuanyuan Yang, Stony Brook University, USA
Songtao Guo, Chongqing University, China
Howie Huang, The George Washington University, USA


Call for Papers: Workshop on Computer Architecture Education
https://projects.ncsu.edu/wcae/ISCA2019/wcae2019.html
Submitted by Ed Gehringer

Workshop on Computer Architecture Education (WCAE)
in conjunction with ISCA’19
Phoenix, Arizona, USA
June 22, 2019

IMPORTANT DATES:
Submissions Due: May 20, 2019
Author Notification: May 29, 2019
Final Paper Due: June 14, 2019

WCAE provides a forum for educators in computer architecture to discuss and share their experiences and teaching philosophy. Past WCAEs have been held in conjunction with HPCA, ISCA, and Micro. Over 210 papers on computer architecture education have been presented at the workshop since its inception in 1995. Participants will come away from the workshop with new ideas on delivering courses in computer architecture. Topics of interest include, but are not limited to, the following.

Topics of interest:
– Approaches to introductory courses
– Advanced courses
– Online resources
– Resources for “flipped” classes
– Materials for active learning
– Lecture vs. hybrid vs. flipped classes
– Lab support for distance education

– Textbook development
– Critical evaluation of textbook approaches

– Metrics for evaluating learning gains
– Integration of research into teaching
– Industrial support for teaching
– Resources & techniques for teaching (e.g., GPU architecture & programming, multicore/many-core issues; comp. arch. concepts with FPGAs, architectural & software issues specific to embedded systems)

– Hardware tools
– Simulators and other software tools
– Prototyping
– Visualization aids
– Broadening participation in computer architecture
– Encouraging undergraduate research
– Encouraging students to pursue a Ph.D.

For an idea of what we have published in the past, see the WCAE archive, made possible with funding from the SIGCSE Special Projects fund. Many of these papers are also in the ACM Digital Library.

SUBMISSION GUIDELINES:
Authors should submit a full paper (not to exceed 8 pages), following the IEEE manuscript templates.

We encourage participation by book publishers, computer manufacturers, software vendors, or companies which develop or market products used in the delivery of computer architecture education. Any company interested in participating in the workshop should contact the organizer at the address above.

Copies of papers presented at the workshop will be made available through the ACM Digital Library.

ORGANIZERS:
Workshop Chair:
Ed Gehringer, North Carolina State University, efg@ncsu.edu

Program Committee:
Emmanuel Arzuaga, University of Puerto Rico at Mayaguez
João Cardoso, FEUP/University of Porto, Portugal
Henry Duwe, Iowa State University
Mark Fienup, University of Northern Iowa
Xinfei Guo, University of Virginia
Sarah Harris, University of Nevada-Las Vegas
Lei Jiang, Indiana University
David Kaeli, Northeastern University
Zach Kurmas, Grand Valley State University
Michael Manzke, Trinity College, Dublin
Yale Patt, University of Texas at Austin
Diane Rover, Iowa State University
Cristina Silvano, Politecnico di Milan
Devesh Tiwari, Northeastern University
Wei Xue, Tsinghua University


Call for Papers: Workshop on Energy-Secure System Architectures
http://www.essa-workshop.org
Submitted by David

Workshop on Energy-Secure System Architectures (ESSA)
in conjunction with HOST 2019
McLean, VA, USA
May 9-10, 2019

IMPORTANT DATES:
Submission Deadline: March 15, 2019 (extended)
Acceptance Decision: March 22, 2019
Final Submission: April 12, 2019
Presentation Slides: April 26, 2019 (unchanged)

The “power wall” has forced chip and system architects to design with smaller margins between nominal and worst-case operating points. Dynamic power, voltage noise and thermal management control loops have already become an integral part of chip and system design. New research papers in “wear out” and general reliability management have recently been published.

These new generation management protocols have, however, opened up other sources of concern: e.g. control loop stability and robustness of the management protocols. The potential security holes exposed by the integrated control loops and system safety issues triggered by potential violations of power or thermal limits are other areas of concern. Also, side channel attack scenarios enabled by modulated power profiles have been documented in prior research.

We seek to motivate the research community into adopting a holistic approach to mitigating the power wall and the concomitant reliability-security wall. We have coined the term “Energy-Secure System Architectures” to cover the range of research being pursued within industry and academia in order to ensure robust and secure functionality, while meeting the energy-related constraints of the “green computing” era. This segmented workshop offering, composed of lectures provided by experts in the areas of power/thermal management, reliability and security, provides a comprehensive view of the hardware and software aspects of Energy-Secure System Architectures

Topics of interest (but not limited to):
– Power, noise and thermal management solutions for modern multi-core platforms: with a focus on reliability and security challenges. 
– Verification and design for verification of system-level power, noise and thermal managers: predeployment safeguards against security breaches. 
– Reliability and security holes exposed by power/thermal management protocols: specific examples of attack scenarios. 
– Security-aware dynamic power management: software-hardware architectural concepts. 
– Use of machine learning/deep learning (ML/DL) principles in safeguarding against energy attacks in processors, server systems and data-centers. 
– Architectural implications of and system software support for energy-secure systems. 
– Security and reliability issues in emerging low power processor and memory technology. 
– Resilience and security challenges of ultra-low power cognitive IoT systems Energy-secure artificial intelligence (AI) systems. 
– Metrics for quantifying energy-security of computing systems. 

SUBMISSION GUIDELINES:
Extended Abstracts must be in English and up to 4 pages.
Accepted papers will be presented at the workshop and included in the workshop report.
Selected papers presented in the workshop will be invited to submit revised (updated) versions to a peer-reviewed special issue of IEEE Security and Privacy

ORGANIZERS:
Saibal Mukhopadhyay, Georgia Tech University, saibal@ece.gatech.edu
Pradip Bose, IBM T.J.Watson Research Center, pbose@us.ibm.com

Program Committee:
Saibal Mukhopadhyay, Georgia Tech University
Pradip Bose, IBM Research
Alper Buyuktosunoglu, IBM Research
Augusto Vega, IBM Research
Francisco J. Cazorla, Barcelona Supercomputing Center
Simha Sethumadhavan, Columbia University
Moinuddin Qureshi, Georgia Tech University
Edward Suh, Cornell University
Sanu Matthew, Intel Corporation


Call for Papers: Workshop on Resource Disaggregation
http://word19.ece.cornell.edu/
Submitted by Jishen Zhao

1st Workshop on Resource Disaggregation (WORD)
in conjunction with ASPLOS’19
Providence, Rhode Island, USA
April 13, 2019

IMPORTANT DATES:
Paper submissions due: March 6, 2019 (extended!)
Notification: March 17, 2019
Final paper due: April 5, 2019

Recent hardware developments and application trends are challenging the long-standing datacenter architecture where a server is the unit of deployment, operation, and failure. With the current server-centric datacenter architecture, it is fundamentally difficult to fully utilize, add, remove, or reorganize hardware components. A promising solution to these issues is to physically or virtually disaggregate hardware resources. Physical resource disaggregation breaks a computer server into independent, network-attached hardware devices. Virtual resource disaggregation maintains existing server model and uses resources on remote machines virtually.

The 1st Workshop on Resource Disaggregation (WORD’19) will bring together researchers and practitioners in hardware, software, networking, programming language, and application domains to engage in a lively discussion on a wide range of topics in the broad definition of resource disaggregation, including both physical and virtual resource disaggregation. We solicit both position papers that explore new challenges and design spaces and short papers that include completed or early-stage work.

Topics of interest include but are not limited to:
– Hardware design for resource disaggregation
– Network for resource disaggregation
– Disaggregated and remote memory
– Disaggregated and remote storage
– Simulation and measurement of disaggregated cluster
– Resource management of disaggregated cluster
– Deployment of disaggregated cluster
– Application and programming models for resource disaggregation
– Virtualization of disaggregated hardware

We encourage researchers from all institutions to submit their work for review. Preliminary results of interesting ideas and work-in-progress are welcome.
Submissions that are likely to generate vigorous discussion will be favored!

ORGANIZERS:
Yiying Zhang, Purdue University
Christina Delimitrou, Cornell University
Hakim Weatherspoon, Cornell University

Program Committee:
Irina Calciu, VMWare
Mosharaf Chowdhury, University of Michigan
Paolo Costa, Microsoft
Alex Daglis, Georgia Tech
Christina Delimitrou, Cornell University
Ionel Gog, UC Berkeley
Haris Volos, Google
Wei Wang, University of Texas, San Antonio
Hakim Weatherspoon, Cornell University
Yiying Zhang, Purdue University
Noa Zilberman, University of Cambridge


Call for Papers: Workshop on Computer Architecture Research with RISC-V
https://carrv.github.io
Submitted by Silviu Chiricescu

Third Workshop on Computer Architecture Research with RISC-V
in conjunction with ISCA’19
Phoenix, Arizona, USA
June 22, 2019

IMPORTANT DATES:
Abstract submission deadline: March 22, 2019
Full paper submission deadline: March 29, 2019 23:59 PST
Author notification: April 19, 2019

The Third Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work is encouraged.

The topics of specific interest for the workshop include, but are not limited to:
– RISC-V cores and SoC architectures
– RISC-V simulation/emulation infrastructure
– RISC-V ISA extensions
– RISC-V-based Hardware accelerators
– Security architectures and techniques
– Formal methods
– Verification methodologies
– Hardware/software interfaces
– RISC-V ISA and implementation performance analysis
– RISC-V compilers and dynamic translation tools

Submission instructions are available at the workshop web site.


Call for Papers: Third Data Prefetching Championship
https://dpc3.compas.cs.stonybrook.edu/
Submitted by Alaa Alameldeen

Third Data Prefetching Championship
in conjunction with ISCA 2019
Phoenix, Arizona, USA
June 23, 2019

IMPORTANT DATES:
Submission Deadline (paper & code): May 3, 2019, 11:59:59PM EDT
Notification: May 17, 2019

The Third Data Prefetching Championship (DPC3) is a competition for data prefetching algorithms. Contestants will be given a fixed storage budget to implement their best prefetching algorithms on a common evaluation framework provided by the DPC3 organizing committee. The goal for this competition is to compare different data prefetching algorithms in a common framework. Prefetchers for L1, L2, and L3 data caches must be implemented within a fixed storage budget as specified in the competition rules. Submissions will be evaluated based on their performance on a set of benchmarks using the framework provided by the organizing committee. Each contestant is allowed a maximum of three submissions to the competition. Each submission should include the following an abstract, a paper and prefetcher code.

Further details are available at the workshop webpage.


Call for Papers: Special Session on Edge Computing and Storage Systems at CPSCom
http://cse.stfx.ca/~cybermatics/2019/cpscom/CPSComECSS.php
Submitted by Xianzhang Chen

Special session of Edge Computing and Storage Systems (ECSS)
at the 12nd IEEE International Conference on Cyber, Physical and Social Computing (CPSCom)
Atlanta, USA
July 14-17, 2019

IMPORTANT DATES:
Paper submission deadline (extended): March 1, 2019
Acceptance Notification: April 1, 2019
Camera-Ready Paper Due: June 1, 2019

The ECSS special session of the 12nd edition of CPSCom will be held in Atlanta. Original, unpublished papers describing research in the general areas of edge computing and storage systems are solicited.

The topics of interests for this special issue include, but are not limited to:
-Edge computing and edge storage architecture
-Real-time data processing and storage
-Fault models and fault tolerances in edge computing and storage system
-Energy efficiency issues in edge computing and storage
-Security and privacy issues in edge computing and storage
-Availability and reliability in edge computing and storage
-Intelligence in edge computing and storage
-Design methodologies, benchmarks, measurement, and tools for edge computing and storage
-Applications of edge computing and storage systems (including internet of vehicles, communication, manufacturing, smart civil infrastructures, and healthcare)
-Data profile of edge computing and storage systems

SUBMISSION GUIDELINES:
Papers are limited to 8 pages (regular paper), or 6 pages (short paper), and 2-4 pages for a poster paper following the IEEE proceedings format, and are to be submitted as PDF via the site: http://edas.info/N25496. Please select the CPSComECSS track in submission system.

Accepted conference papers will be published by IEEE (IEEE-DL and EI indexed). At least one author of each accepted paper is required to register and present their work at the conference; otherwise the paper will not be included in the proceedings. Selected papers, after further extensions and revisions, will be recommended to special issues. More details at the conference website: Accepted conference papers will be published by IEEE (IEEE-DL and EI indexed). At least one author of each accepted paper is required to register and present their work at the conference; otherwise the paper will not be included in the proceedings. Selected papers, after further extensions and revisions, will be recommended to special issues. More details at the conference website: http://cse.stfx.ca/~cybermatics/2019/cpscom/.

ORGANIZERS:
Xianzhang Chen, Chongqing University, xzchen@cqu.edu.cn
Chun Jason Xue, City University of Hong Kong, jasonxue@cityu.edu.hk


Call for Papers: Workshop on Edge Computing for Cyber Physical Systems
https://cyberedge.dei.unipd.it/
Submitted by Angel F. Gambin

Workshop on Edge Computing for Cyber Physical Systems (CyberEdge)
in conjunction with IEEE SECON 2019
Boston, MA, USA
June 10, 2019

IMPORTANT DATES:
Paper Submission Deadline: April 5, 2019
Acceptance Notification: May 7, 2019
Camera Ready Deadline: May 17, 2019

CyberEdge will provide a forum for practitioners and researchers from diverse backgrounds to exchange and discuss their recent ideas, research achievements, design and implementation experiences within the CPS and edge computing spaces.

Edge computing within CPS is a vivid research field, with immediate impact on real life applications and products. Many research questions are still open such as the integration of edge computing facilities with energy harvesting systems and mobility prediction, e.g., to provide computation for fleets of vehicles. A fully online, flexible load balancing of computing services at the edge, while meeting all deadlines, requires further theoretical and especially experimental developments. Other aspects that are of interest are the investigation of joint physical (PHY)/channel access(MAC) and edge computing systems, especially assessing the impact of PHY/MAC protocols, how much and what kind of data should be measured given the following computing step, whether and how computation may be split between the data sources and the edge servers, e.g., computing functionality split. Other open issues are application specific, e.g., such as in visual sensor networks or user/object tracking systems, where user/object/scene detection shall be performed at the network edge to provide ultra-low latency services.

The workshop welcomes contributions on these and other aspects, a non-exhaustive list follows:
– Joint PHY/MAC and edge computing designs.
– Edge computing architectures and orchestration of computing resources.
– Integration of edge computing algorithms with energy harvesting systems.
– Edge computing for mobile/vehicular networks.
– Data storage, processing algorithms and management for CPS.
– Machine learning based approaches to edge computing within CPS.
– Application of learning and control techniques to edge computing systems.
– Economic models for edge computing in CPS.
– Security and privacy issues.

Information on paper submission is available at the workshop web site.


Call for Papers: IEEE Micro Special Issue on Secure Architectures

Submitted by Lizy K John

Hardware is the bedrock on which all computing systems are built. Recently developed hardware ideas for enhancing software security from both academia and industry hold significant promise to improve software security. At the same time, recent hardware attacks on current commodity hardware has shown hardware to be a weak foundation for building secure systems. As we enter Post-Moore’s-Law era, there are significant questions surrounding what would make security techniques more practical.

IEEE Micro seeks articles on hardware enhanced security and privacy seeks papers on a range of topics, including but not limited to:
– Microarchitectural side-channel attacks and defenses; fault attacks and defenses
– Architectures for key management, attestation, patching and updating firmware and software
– Architectures for isolation and compartmentalization/tamper-proof execution
– Architectures for metadata based approaches to security and privacy
– Architectures for introspection, debugging, and root cause analysis
– Microarchitectural techniques for malware detection and adversarial resistance
– Secure storage, e.g. using emerging non-volatile memories
– Metrics and evaluation methodologies for secure architectures including languages/frameworks for early design stage security exploration
– Approaches to Post-Moore’s-Law security (secure-accelerator designs will ideally be in the context of an end-to-end application)
– Microarchitectural design patterns for security
– Social processes for creating security in large scale designs
– Secure architectures for domains such as voting machines, implantable medical devices, automotives, Internet-of-Things, and data centers.

IMPORTANT DATES:
Submissions due: March 4, 2019
Initial notifications: Apr 4, 2019
Revised papers due: May 4, 2019
Final notifications: May 10, 2019
Final versions due: May 24, 2019
Publication date: July/Aug 2019

SUBMISSION GUIDELINES:
Please see the Write for Us page and the general author guidelines for more information. Please submit electronically through ScholarOne Manuscripts, selecting this special-issue option.

Questions?
Contact the guest editors at Simha Sethumadhavan (simha@columbia.edu) and Mohit Tiwari (tiwari@austin.utexas.edu) or the editor-in-chief at Lizy John (ljohn@ece.utexas.edu).


Call for Papers: IEEE Micro Special Issue on Machine Learning Acceleration

Submitted by Lizy K John

In recent years, machine learning (ML) has become one of the most important pillars of computing industry, driven by the remarkable advances in the theory and their extensive use in real-world applications. To accomplish the phenomenal success, research and industry communities have exploited acceleration solutions, which deliver orders-of-magnitude greater performance and efficiency by specializing hardware and software for ML. As the importance of ML in the emerging applications increases, the ML accelerators have become the critical component of every modern computing system–from data centers to mobile/IoT devices. The community has not only extensively explored new architectures to improve the performance and efficiency of these accelerators, but also put significant effort on raising usability and programmability by offering programming models, high-level language, compiler, runtime software, and tools.

This special issue of IEEE Micro will explore academic and industrial research on all topics, which relate to hardware and software acceleration solutions, specialized for ML. Such topics include, but are not limited to:
– New design methodologies for ML-centric or ML-aware hardware accelerators
– New microarchitecture designs of hardware accelerators for ML
– ML workload acceleration on existing accelerators such as GPU, FPGA, CGRA, or ASIC
– New compiler and optimization techniques for ML acceleration
– New tools to design/build/optimize/debug the accelerated systems
– New ML modeling, optimization, quantization, and compression for acceleration
– Acceleration for new ML algorithms
– ML acceleration for edge computing and IoT
– ML acceleration for cloud computing
– Comparison studies of different acceleration techniques
– Survey and tutorial studies of ML acceleration

IMPORTANT DATES:
Submissions due: April 12, 2019
Initial notifications: May 22, 2019
Revised papers due: June 21, 2019
Final notifications: June 28, 2019
Final versions due: July 12, 2019
Publication date: Sept/Oct 2019

SUBMISSION GUIDELINES:
Please see the Write for Us page and the general author guidelines for more information. Please submit electronically through ScholarOne Manuscripts, selecting this special-issue option.

Questions?
Contact the guest editors at Hadi Esmaeilzadeh (hadi@eng.ucsd.edu) and Jongse Park (jspark@gatech.edu) or the editor-in-chief at Lizy John (ljohn@ece.utexas.edu).


Call for Presentations: Workshop on Modeling & Simulation of Systems and Applications
https://www.bnl.gov/modsim2019/
Submitted by Jason Lowe-Power

Workshop on Modeling & Simulation of Systems and Applications (ModSim)
Seattle, USA
May 3, 2019

To promote advancements in modeling and simulation (ModSim) research, we are soliciting community input in the form of abstracts. If accepted, author(s) will be invited to offer a presentation at the annual gathering of our community, the ModSim 2019 Workshop.

Submission URL: https://easychair.org/conferences/?conf=modsim20190
EasyChair Submission Deadline: Friday, May 3, 2019 (11:59 PM, Anywhere on Earth [AOE])
Notification of Acceptance: Friday, May 31, 2019

The overarching theme for this year’s workshop is Full-system Modeling and Simulation. The emphasis will be on methodologies, tools, best practices, projects, and initiatives that aim to address the challenges and achieve the goal of modeling performance of full systems under a realistic application workload. Abstract contributions should focus on the following topical areas while maintaining a global view of “system” in consideration:

– Modeling and Simulation of Artificial Intelligence and Machine Learning as a Method of ModSim:
Artificial Intelligence (AI), in general, and Machine Learning (ML), in particular, have emerged as important application drivers in all forms of computing, including large-scale data- and numerically-intensive high-performance computing (HPC). The trend’s impact extends beyond the nature of architectures optimized for executing an ML workload. It also points the way toward applying AI/ML techniques as ModSim methodologies to support a range of systems (including but not limited to AI-centric systems). Thus, abstract submissions in this category should cover topics such as novel architectures to efficiently support AI/ML workloads, ML as a methodology for ModSim, and intelligent computational steering driven by dynamic and offline learning.

– Integrative Methodologies and Tools for Full-system Modeling and Simulation:
This category covers modeling and simulation technologies to predict performance, energy consumption, and cost of the whole system. A typical system comprises several subsystems with a breadth of architectures and exercises a broad spectrum of applications and workloads. It is highly desirable to optimize the whole system using ModSim with a level of effort commensurate with the resulting accuracy and precision. This workshop seeks abstracts that highlight how to further the state of the art, as well as future research directions in this field.

– Modeling and Simulation of Subsystems:
The blending of compute, memory devices, storage, and interconnect combined with application software profoundly impacts current and future computing systems in terms of performance, reliability, predictability, power consumption, and cost. Existing technologies are perceived as limited in terms of compute power, capacity, and bandwidth. Emerging technology approaches offer the potential to overcome both technology- and design-related limitations, addressing system requirements for many different applications. Modeling and simulating these subsystems is tremendously important, principally by affording the ability to characterize and quantify data movement, as well as estimate power consumption and other related behaviors in large-scale systems. Abstract submissions should relate to computer subsystem technologies and their characterization and/or provide use cases that describe how ModSim can help to overcome these significant challenges.

Please see workshop web site for further details, including submission guidelines.


Call for Presentations: Flash Memory Summit 2019
http://flashmemorysummit.com/
Submitted by Saugata Ghose

14th Annual Flash Memory Summit
Santa Clara, California, USA
August 6-9, 2019

IMPORTANT DATES
Poster Abstracts: March 31, 2019
Presentation Proposals: April 7, 2019

The Flash Memory Summit (FMS) is an annual conference where companies and researchers meet to discuss the latest innovations and products in solid-state storage, non-volatile memory, and related areas. The venue of choice for major announcements by key industry players, the summit attracts worldwide attention from both within and outside the storage industry. Each year, over 4,000 people attend the summit, which includes technical presentations on new industrial and academic innovations, and industrial exhibits. The summit has been held annually since 2006.

We invite academic presentations and posters on research related to one of the following topics:
– solid-state drives (SSDs)
– persistent memory
– enterprise storage systems
– non-volatile technologies and emerging storage devices
– performance/wear analysis
– NVMe and NVMe-oF controllers
– consumer/mobile or embedded applications
– security
– testing/endurance
– high-performance computing

SUBMISSION GUIDELINES:
Presentation proposals and abstracts can be submitted online at https://www.flashmemorysummit.com/English/For_Speakers/Submit_Presentation.html through April 7. Publication or presentation of work in a prior venue does not preclude its presentation at the Flash Memory Summit.

Students and postdocs should send poster proposals (with your name, affiliation, a title for the work, and a short abstract) to Saugata Ghose, the university coordinator for the conference, at ghose@cmu.edu by March 31. This year, we will have a best poster award at the conference.

Announcements on presentations and posters selected for presentation at the summit are expected to be made by April 30. Travel grant awards will be announced at the same time. Final materials will be due on July 1, 2019. Free conference registrations are available for academic attendees (two per presentation, and one for each poster presenter).


Announcement: ACM Digital Library usage
http://www.acm.org/publications/acm-author-izer-service
Submitted by Natalie Enright Jerger

The SIGARCH EC would like to encourage further use of the ACM Digital library (dl.acm.org) by our members. Downloading papers published in SIGARCH-sponsored conferences from the ACM DL provides a revenue stream back to SIGARCH. This revenue stream supports existing programs such as student travel grants and allows SIGARCH to develop new programs to further support its members. Please use the ACM DL in your research and use the ACM Authorizer to post ACM DL links to your own papers on your website (http://www.acm.org/publications/acm-author-izer-service). To encourage use of the ACM DL, we will be highlighting the top 10 papers from SIGARCH (co-)sponsored conferences downloaded over the last 6 weeks in each monthly SIGARCH newsletter. Happy reading!

Top 10 Downloaded papers in SIGARCH-sponsored publications (as of March 1, 2019):

1. Wildlife and environmental monitoring using RFID and WSN technology – 2009, SenSys
Vladimir Dyo, Stephen A. Ellwood, David W. Macdonald, Andrew Markham, Cecilia Mascolo, Bence Pásztor, Niki Trigoni,Ricklef Wohlers
Downloaded 1008 times

2. Secure remote sensing and communication using digital pufs – 2014, ANCS
Teng Xu, James Bradley Wendt, Miodrag Potkonjak
Downloaded 302 times

3. In-Datacenter Performance Analysis of a Tensor Processing Unit – 2017, ISCA
Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia,Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau,Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho,Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary,Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan,Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg,Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon
Downloaded 250 times

4. Minimal and maximal exposure path algorithms for wireless embedded sensor networks – 2003, SenSys
Giacomino Veltri, Qingfeng Huang, Gang Qu, Miodrag Potkonjak
Downloaded 240 times

5. Enabling trusted software integrity – 2002, ASPLOS
Darko Kirovski, Milenko Drinić, Miodrag Potkonjak
Downloaded 206 times

6. DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning – 2014, ASPLOS
Tianshi Chen, Zidong Du, Ninghui Sun, Jia Wang, Chengyong Wu, Yunji Chen, Olivier Temam
Downloaded 161 times

7. The gem5 simulator – 2011, CAN
Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, David A. Wood
Downloaded 145 times

8. Parasol and GreenSwitch: managing datacenters powered by renewable energy – 2013, ASPLOS
Íñigo Goiri, William Katsak, Kien Le, Thu D. Nguyen, Ricardo Bianchini
Downloaded 136 times

9. TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory – 2017, ASPLOS
Mingyu Gao, Jing Pu, Xuan Yang, Mark Horowitz, Christos Kozyrakis
Downloaded 119 times

10. Improving the future by examining the past: ACM Turing Award Lecture – 2010, ISCA
Charles P. Thacker
Downloaded 118 times


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Boris Grot
SIGARCH Content Editor

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