This is the 1st May 2020 digest of SIGARCH Messages.

In This Issue

ISCA 2020 Virtual Event Logistics
Submitted by Samira Khan

Dear attendees,

We are looking forward to welcoming you to the first-ever virtual ISCA! We believe the ecosystem we have put together will allow you to get the maximum out of this worldwide event. Here we would like to tell you a little about how things will work out.

Event Schedule: Main track events will take place at three different time slots each day, Monday through Wednesday (June 1–3). (We are still working out the details of workshops and tutorials.)

  • The “global slot” is 10 AM – noon New York time (UTC-4). This slot will host live keynote presentations, the new industry track session, the SIGARCH/TCCA business meeting, and the awards ceremony. We have picked this time slot so that it can be attended by the majority of the world during waking hours (7 AM – 9 AM San Francisco time; 4PM – 6 PM Brussels time; 10 PM – midnight Beijing time). All events will be recorded for those who miss them.
  • The “technical slots” are noon – 2:30 PM New York time (UTC-4), and 8 PM — 10:15 PM New York time (UTC-4). These will host the paper sessions, as well as mini-panels (see below). Unfortunately, Slot 1 is not ideal in many parts of Asia, whereas Slot 2 is not best for Europeans. Do no fret, however, as we have a plan for this—please keep reading.

Technical Sessions: All technical sessions will comprise three components:

  1. prerecorded presentation of the talk will be available a full week beforehand, as will the full papers. Therefore, attendees will have a chance to go over the program and watch the talks that interest them.
  2. Q&A forum and a discussion board, also available a full week in advance. In the Q&A forum, attendees may pose questions to speakers, read what other questions are being asked, and upvote the ones they like. In the discussion board, attendees can debate the work in free form throughout the conference.
  3. live Q&A session will take place during the assigned time slot, with the speaker present via video webinar. The speaker will give a live two-minute recap of the talk, and then answer questions from the Q&A forum, generally by popularity (number of attendee votes). This session will be recorded, and it will remain available to watch for those who may have missed the live event.

Mini-Panel “Coffee Breaks”: What could be better than a controversial panel on a hot research topic? How about a dozen panels? We have put together thirty-minute mini-panels, two at the end of each technical session. Their goal is to seed community discussion on topics that were “hot” among this year’s paper submissions. These will be broadcast live as well, and the interaction with each panel will be through its own Q&A forum and discussion board. will be typically Program Committee members, and each panel has been given latitude to self-organize.

Discussion Boards: As you may have noticed, every event has an associated discussion board (this is an obvious nod to our ASPLOS 2020 colleagues). Attendees will have access to all discussion boards from a week before the event through at least the end of June. Importantly, attendees will be able to form their own discussion boards. (This includes a discussion board about job opportunities.) We recognize that this may lead to a myriad of them, but we’d rather err on the side of letting attendees take discussions wherever they want. Think about it as zig-zagging around groups of people chatting during coffee breaks, trying to find one that looks interesting to you.

One-on-One Contact: The platform allows all attendees to fill out a “virtual business card” (this includes a LinkedIn profile, which can optionally be used to log into the platform), and to share it with others. It also makes it easy to search for other listed attendees and to contact them.

Registration Cost: ACM/IEEE member registration is US $30; student and life members receive a 50% discount. Registration for non-members is USD $60 and USD $30, respectively. Although it may seem that the ideal registration cost for a virtual event is zero, we do not believe this is the case:

  • First, the event does cost money; a few examples: Program Committee meeting costs were about $12,000; virtual event software will run about $5,000; technical paper production and publication costs about $2,000; etc.
  • Second, we’d really like to keep trolls away, so that people genuinely interested in the conference can enjoy it. Think about it this way: Typical completion rate of a MOOC course is 5%; the other 95% either never show up or use up resources but ultimately drop the class. We believe the most effective way to accomplish this is to assign a dollar value to the event.
  • Third, we will consider requests for registration waivers on a case-by-case basis. However, for each attendee asking for a waiver we will require that the request be sent as a digital letter (PDF, JPG, PNG, etc.) with a university or company letterhead, explaining the circumstances.
  • Fourth, we are deferring all industry sponsorship funds for the organization of ISCA 2021, which will take place in… wait for it… Valencia, Spain (yesss!). (Sponsors will be acknowledged in both ISCA 2020 and ISCA 2021.)

We are actually very excited at the low registration cost—about 5% of the cost of attending a physical conference. This was possible in part by SIGARCH’s and TCCA’s generous support at a moment’s notice. Our hope is that many more people will register to the conference as a result of its low cost (plus the savings from not having to travel). In particular, we are hoping that it will enable research groups to have every single student participate.

Availability of Technical Contributions: For the main track, we have negotiated with the IEEE Computer Society a very attractive dissemination plan that will ensure technical contributions are widely accessible:

  • All technical papers in the main track will generally be available worldwide for free download from May 22 to June 30. After that, they will be available through the ACM and the IEEE digital libraries (and, historically, the authors’ web sites).
  • All prerecorded technical presentations and materials will be available behind the conference paywall from May 22 to June 30. After that, they will become available worldwide for free (unless the authors tell us otherwise).
  • Recorded live performances (keynotes, Q&A sessions, and mini-panels) will be made public worldwide after June 30 only if expressly requested by speakers.

We would like to reiterate our excitement at the prospect of welcoming you to ISCA 2020. We hope that this setup will prove engaging, and that it will encourage everyone to register and help us make this a truly unique event, by posing and voting on questions for all presenters, and by contributing to the mini-panels and discussion boards.

See you soon,

José Martínez and José Duato, General Co-chairs
Lieven Eeckhout, Program Chair

Joint Investigative Committee (JIC) Update

Submitted by Boris Grot


I hope you are safe and well during this difficult time.

My name is Emily Reisbaum, I am a founding partner at Clarick Gueron Reisbaum LLP, and I am also outside legal counsel to the Joint Investigative Committee (JIC). The JIC was established by ACM and IEEE to investigate alleged policy violations in connection with the ISCA and HPCA conferences in 2019. I am writing to provide you with several important updates:

First, the work of the JIC’s outside counsel and investigator is underway, and the JIC recently had a productive initial meeting in which JIC members, outside counsel, and an external investigator discussed the scope and focus of the investigation.

Second, in the interest of transparency we wish to advise the community that the Director of Publications for ACM is serving as an observing member of the JIC. In that capacity the Director of Publications, along with external counsel and the investigator, receives communications sent to the JIC email address (

Third, in response to concerns about confidentiality that we have received from the computing community, and in an effort to ensure we gather as much helpful information as possible regarding these alleged violations, the JIC has created a dedicated tip line. This phone line is managed by the JIC’s external investigator, Laura Kirschstein at T&M Protection Resources LLC, and is not accessible by any ACM or IEEE employees. Anyone who has information that they believe will assist the JIC in investigating these specific allegations should leave a message at 914-306-3588; those who leave a message anonymously will have their anonymity protected. Although anyone who calls the hotline may remain anonymous, we remind you that the most helpful tips are ones that we can substantiate and follow-up on if we have questions. Therefore, if you feel comfortable including your contact information with your tip, we encourage you to do so or contact us at the JIC email address.

Please share this information with anyone you think may have information that will be helpful to our investigation, and feel free to reach out to me with additional questions or comments.

Emily Reisbaum

220 Fifth Avenue, New  York,  NY 10001

Main: 212.633.4310

Call for Nominations: 2020 ACM SIGARCH Alan D. Berenbaum Distinguished Service Award
Submitted by Boris Grot

ACM SIGARCH Alan D. Berenbaum Distinguished Service Award

Nominations deadline extended to May 15, 2020.

This annual award is presented to an individual who has contributed important service to the computer architecture community.

The award is presented annually at the International Symposium on Computer Architecture Awards Banquet. This year’s recipient will be invited to accept the award at ISCA 2020. Recipients receive a memento engraved with their name along with a $1000 honorarium. The award recipient also receives up to $2000 towards support for travel costs, including airfare, hotel, and conference registration for ISCA. The recipient is listed with a citation for their award on the SIGARCH Alan D. Berenbaum Distinguished Service Award webpage.

Nominations should consist of:

1. Name, address, phone number and email of person making the nomination.
2. Name, affiliation, address, email, and telephone number of candidate for whom the award is recommended.
3. A statement (between 200 and 500 words long) explaining why the nominee deserves the award in question. Note that the award is given for service that goes above and beyond traditional service.
4. 4-7 letters of support. Include the name, affiliation, email address, and telephone number of the letter writer(s). Supporters of multiple candidates are strongly encouraged to compare the candidates in their letters.
5. State any conflicts of interest (COI) between the nominee and any committee members. Refer to the ACM COI guidelines (item 7) to determine what constitutes a COI. Please state explicitly if there are no conflicts.

Please send all your nomination materials as one pdf file no later than May 15, 2020 to the Chair of the Nominating Committee (Lisa Hsu

Call for Papers: IISWC 2020
Submitted by Xiaochen Guo

2020 IEEE International Symposium on Workload Characterization
October 27-29, 2020

Submissions Due: July 10, 2020

IISWC invites manuscripts that present original unpublished research in all areas related to characterization and analysis of computing system workloads, including translational research related to production-oriented commercial systems. Work focusing on emerging technologies and interdisciplinary work are especially welcome. Topics of interest include (but are not limited to): Characterization of applications in traditional and emerging domains, characterization of system software and middleware, implications of workloads in system design, benchmarking methodologies and suites, and tools for computer systems. A detailed list of the topics can be found at the end of this CFP.


Submission Deadline: July 10, 2020

Decision Notification: Aug 24, 2020

Camera-ready deadline : Sep 15, 2020

New in 2020

This year, submissions to IISWC can be made in one of the following two categories: (1) regular papers (2) tool and benchmark papers. The primary focus of “regular papers” should be to describe new research ideas supported by experimental implementation and evaluation of the proposed research ideas. The primary focus of “tool and benchmarks papers” should be to describe the design, development, and evaluation of new open-source tools / benchmarks suites.

Authors are required to indicate the category of the paper as a part of the submitted manuscript’s title. The last line of the title should indicate the paper type by using one of the two phrases (1) Paper Type: Regular, or (2) Paper Type: Tool/Benchmark.

The paper categories primarily differ in terms of their focus (new research idea vs. new open-source benchmark-suite / tool) and length (regular papers can be up to 10 pages long excluding references; tool and benchmark papers can be up to 6 pages long excluding references). But, the submissions in both the categories will be evaluated to the same standards in terms of novelty, scientific value, demonstrated usefulness, and potential impact on the field. Submissions in the “regular papers” category are also welcome to open-source their software or hardware artifacts. But, the chosen category at the time of the submission can not be changed after the submission deadline.

Double-blind submission guidelines apply to the submissions in both the categories.

Open-source benchmarks and tools that have not been previously published (but may have been open-sourced) are eligible for submission in the “tool and benchmark papers” category. Even in cases where the benchmarks suite / tool is already being used in the community, the authors should demonstrate good faith effort to adhere to the double-blind submission guidelines. All submitted papers should have obtained the legal permission (if applicable) to open-source the benchmark-suite / tool at the time of submission.

Topics of Interest

Characterization of applications in domains including

  • Life sciences, bioinformatics, scientific computing, finance, forecasting
  • Machine learning, data analytics, data mining
  • Cyber-physical systems, pervasive computation and Internet of Things (IoT)
  • Security and privacy-preserving computing
  • Quantum computing
  • High performance computing
  • Cloud and edge computing
  • Mobile computing
  • User behavior and system-user interaction
  • Search engines, e-commerce, web services, and databases
  • Embedded, multimedia, real-time, 3D-graphics, gaming
  • Blockchain services


Emerging workloads and architectures, such as

  • Quantum computations and communication
  • Serverless computing
  • Near-threshold computing
  • Non-volatile memory
  • Near data processing architectures
  • Neuromorphic and brain-inspired computing
  • Artificial intelligence and transactional memory workloads


Characterization of OS, Virtual Machine, middleware and library behavior, including

  • Virtual machines, .NET, Java VM, databases
  • Graphics libraries, scientific libraries
  • Operating system and hypervisor effects and overheads


Implications of workloads in system design, such as

  • Power management, reliability, security, privacy, performance
  • Processors, memory hierarchy, I/O, and networks
  • Design of accelerators, FPGAs, GPUs, CGRAs, etc.
  • Large-scale computing infrastructures and facilities


Benchmark methodologies and suites, including

  • Representative benchmarks for emerging workloads
  • Benchmark cloning methods
  • Profiling, trace collection, synthetic traces
  • Validation of benchmarks


Measurement tools and techniques, including

  • Instrumentation methodologies for workload verification and characterization
  • Techniques for accurate analysis/measurement of production systems
  • Analytical and abstract modeling of program behavior and systems

Call for Papers: ESWEEK 2020: Call for WiP
Submitted by Lars Bauer

Call for Work-in-Progress Papers

CASES * CODES+ISSS * EMSOFT * Trustworthy IoT Day * NOCS * Workshops * Tutorials

Virtual Conference, September 20 – 25, 2020

Submission: June 5, 2020

* ESWEEK is going virtual:
In light of the continued uncertainty surrounding the Covid-19 situation, the safety and well-being of all the conference participants is our topmost priority. Therefore, the ESWEEK Steering Committee has decided to move to a virtual event format for this year to be held from Sept. 20-25. The 2020 paper review, WiP submission and acceptance processes will proceed normally. We are heartened by a more than 50% increase in number of submitted papers at ESWEEK this year that shows the resilience of our community. We will follow up with further details on conference registration, presentation formats, special sessions and tutorials.

About Embedded Systems Week (ESWEEK)
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent and connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), one symposium (NOCS), and several workshops and tutorials, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development.

Registered attendees can attend sessions in any of the ESWEEK conferences (CASES, CODES+ISSS, EMSOFT). Please note that tutorials, symposium (NOCS), and workshops may require separate registration.

Work-in-Progress Track:
– Paper Submission: June 5, 2020 (firm)
– Notification of Acceptance: July 6, 2020

WiP Paper Submission
ESWEEK 2020 continues a dual publication model comprising the Journal track and the Work-in-Progress (WiP) track. Journal track papers, which are full-length papers describing mature work, will be published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). The WiP track papers, which are short (2-page) papers representing not-yet-mature but promising research, will be published in the ESWEEK proceedings and will be listed as regular publications within the IEEE and/or ACM digital libraries. Authors of WiP papers have the opportunity to publish the extended form of their work in any conference or journal they prefer. Journal and WiP papers are mutually exclusive, i.e., a work can only be in submission in one of the two tracks. For more information on the publishing process, refer to

CASES: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
CASES is a premier forum where researchers, developers and practitioners exchange information on the latest advances in compilers and architectures for high-performance, low-power embedded systems. The conference has a long tradition of showcasing leading edge research in embedded processor, memory, interconnect, storage architectures and related compiler techniques targeting performance, power, predictability, security, reliability issues for both traditional and emerging application domains. In addition, we invite innovative papers that address design, synthesis, and optimization challenges in heterogeneous and accelerator-rich architectures.

CASES Program Chairs:
Partha Pande, Washington State University, US
Umit Ogras, Arizona State University, US

CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis
The International Conference on Hardware/Software Codesign and System Synthesis is the premier event in system-level design, modeling, analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hardware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design.

CODES+ISSS Program Chairs:
Roman Lysecky, University of Arizona, US
Jason Xue, City University of Hong Kong, HK

EMSOFT: International Conference on Embedded Software
The ACM SIGBED International Conference on Embedded Software (EMSOFT) brings together researchers and developers from academia, industry, and government to advance the science, engineering, and technology of embedded software development. Since 2001, EMSOFT has been the premier venue for cutting-edge research in the design and analysis of software that interacts with physical processes, with a long-standing tradition for results on cyber-physical systems, which compose computation, networking, and physical dynamics.

EMSOFT Program Chairs:
Timothy Bourke, Inria Paris, FR
Linh Thi Xuan Phan, University of Pennsylvania, US

ESWEEK 2020 General Chairs:
Tulika Mitra, National University of Singapore, SG
Andreas Gerstlauer, University of Texas Austin, US (Vice General Chair)
Petru Eles, Linköping University, SE (Past Chair)

Call for Papers: NAS 2020
Submitted by Adwait Jog

15th International Conference on Networking, Architecture, and Storage
Riverside, CA, USA
Novermber 8-11, 2020

Submissions Due: June 15, 2020

The International Conference on Networking, Architecture, and Storage provide a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on networking, high-performance computer architecture, and parallel and distributed data storage technologies. NAS 2020 will expose participants to the most recent developments in the interdisciplinary areas.

Each submission can have up to 8 pages, including all text, figures, tables, footnotes, appendices, references, etc. Authors are invited to submit previously unpublished work for possible presentation at the conference. The program committee will nominate the best papers for recognition in the three conference topic areas. All papers will be evaluated based on their novelty, fundamental insight, experimental evaluation, and potential for long-term impact; new-idea papers are encouraged. All accepted papers will be published in the IEEE digital library. Selected and extended papers will be recommended for journal publications.

Call for Papers: IEEE-iSES 2020
Submitted by Prof.A.K.Swain,ECE Dept., NIT Rourkela

IEEE International Symposium on Smart Electronic Systems (IEEE-iSES 2020)
December 14-16, 2020
Chennai, India

Submissions Due: July 31, 2020

The primary objective of IEEE-iSES is to provide a platform for both hardware and software researchers to interact under one umbrella for further development of smart electronic systems. Efficient and secure data sensing, storage, and processing play pivotal roles in current information age. The state-of-the-art smart electronic systems cater to the needs of efficient sensing, storage, and computing. At the same time, efficient algorithms and software used for faster analysis and retrieval of desired information are becoming increasingly important. Big data which are large, complex data sets, are now a part of the Internet world. Storing and processing needs of the enormous amount of structured and unstructured data are getting increasingly challenging. At the same time, Internet of Things (IoT) and cyber-physical systems (CPS) have been evolving with simultaneous development of hardware and software and span across everyday consumer electronics. The performance and efficiency of the present as well as the future generations of computing and information processing systems are largely dependent upon advances in both hardware and software. IEEE-iSES is a sponsored meeting of Technical Committee on VLSI, IEEE-CS that endorses a league of successful meetings including ASAP, ISVLSI, and ARITH, are now presented as “Sister Conferences”.

Nanoelectronic VLSI and Sensor Systems (NVS)
Energy-Efficient, Reliable VLSI Systems (ERS)
Hardware/Software for Internet of Things and Consumer Electronics (IoT)
Hardware for Secure Information Processing (SIP)
Hardware/Software for AI, Robotics, and Automation (AIR)
Hardware/Software for Vehicular Intelligent Systems (VIS)

IEEE-iSES technical program will include both contributed papers and contributions from invited speakers. IEEE-iSES 2020 will have keynote addresses, plenary talks, technical sessions, special sessions, expert panels, research demo session (RDS) and a student research forum (SRF).

TCVLSI sponsored several student travel and best paper awards available.

IEEE-iSES proceedings will be published by IEEE-CS conference publications services (CPS). Authors should submit their original unpublished work of maximum 6 pages using IEEE-CS double-column conference format-template. Manuscripts in PDF format with author information (optional) should be submitted using the link:

Selected papers from IEEE-iSES 2020 program will be invited for submission to a special issue peer-reviewed journal.

Special Sessions and Panels (SSP): iSES 2020 will consider proposals for special sessions as well as panels. Special session and panel proposals/papers can be submitted to “Special Sessions and Panels” track at the online submission link.
The submission deadline is the same as specified for the regular paper submissions.
All accepted special session papers will be published in the conference proceedings.

Student Research Forum (SRF): iSES 2020 will host a student research forum. Authors should submit their original unpublished work of maximum 4 pages using IEEE-CS double-column conference format-template. Manuscripts in PDF format with author information (optional) should be submitted to the “Student Research Forum” track
at the online submission link. The submission deadline is the same as specified for the regular paper submissions. All the accepted student research symposium papers will be published in the conference proceedings.

Research Demo Session (RDS); iSES 2020 will host a research demo session. In the Research Demo Session (RDS), authors can present live demonstrations and hardware prototypes of their research papers and projects. The research demo submission can be between 1-page (extended abstract) to a maximum of 4-pages (short paper).

Call for Papers: CAMAD 2020
Submitted by Claudio Fiandrino

IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks
September 14-16, 2020
Pisa, Italy

Submissions Due: May 20, 2020

The foundation of 5G and beyond mobile networks lies in the convergence between networking and computing. The most appealing realization of such convergence is the application of artificial intelligence (AI) and machine learning (ML) to optimize network functions. The latter has generated an increasing interest from academia and industry paving the path for the transformation from the 5G paradigm “connected things” into a “connected intelligence” vision for beyond 5G and 6G mobile networks. To this end, the role of AI/ML is to support zero-touch configuration and orchestration, thereby enabling self-configuration and self-optimization of the mobile network. Mobile networks are indeed becoming increasingly complex, heterogeneous, dynamic and dense, which makes extremely hard to model correctly their behavior. Model-free solutions that AI enable can overcome such challenge.

This Special Session seeks contributions from experts in areas such as network programming, distributed systems, machine learning, data science, data structures and algorithms, and optimization to discuss the latest research ideas and results on the application of AI/ML to networking. Specifically, this Special Session welcomes contributions in the following major areas (indicative list, other related topics will also be considered):

– Machine learning (ML) and big data analytics in networking
– Case studies showing (dis)advantages of AI/ML techniques for networking over traditional ones
– Edge-driven data analytics and applications to smart cities
– AI/ML assisted network optimization
– Resource-efficient machine learning for mobile networks
– Measurements and analysis of network traffic for AI/ML systems
– Efficient ML data structures, algorithms and network protocols to process network monitoring data
– Approaches for privacy-aware network traffic data collection
– Architectures for federated learning and its applications to networking
– Energy-efficient federated learning
– Incentive mechanisms of federated learning
– In-network computation for next generation wireless networks


Paper Submission Deadline: May 20, 2020
Author Notification: July 3, 2020
Camera Ready: July 31, 2020

Call for Papers: 2nd AccML Workshop at ISCA
Submitted by José Cano

2nd Workshop on Accelerated Machine Learning (AccML)

Co-located with the ISCA 2020 Conference

May 31, 2020
Valencia, Spain

Submissions Due: May 8, 2020 (Extended Deadline)

UPDATE: Due to COVID-19, AccML at ISCA 2020 will now take place virtually.

In the last 5 years, the remarkable performance achieved in a variety of application areas (natural language processing, computer vision, games, etc.) has led to the emergence of heterogeneous architectures to accelerate machine learning workloads. In parallel, production deployment, model complexity and diversity pushed for higher productivity systems, more powerful programming abstractions, software and system architectures, dedicated runtime systems and numerical libraries, deployment and analysis tools. Deep learning models are generally memory and computationally intensive, for both training and inference. Accelerating these operations has obvious advantages, first by reducing the energy consumption (e.g. in data centers), and secondly, making these models usable on smaller devices at the edge of the Internet. In addition, while convolutional neural networks have motivated much of this effort, numerous applications and models involve a wider variety of operations, network architectures, and data processing. These applications and models permanently challenge computer architecture, the system stack, and programming abstractions. The high level of interest in these areas calls for a dedicated forum to discuss emerging acceleration techniques and computation paradigms for machine learning algorithms, as well as the applications of machine learning to the construction of such systems.

Links to the Workshop pages


Invited Speakers
– Antonio Gonzalez (Universitat Politècnica de Catalunya)
– David Kaeli (Northeastern University)
– Tushar Krishna (Georgia Tech)
– Cliff Young (Google)

Topics of interest include (but are not limited to):

– Novel ML systems: heterogeneous multi/many-core systems, GPUs, FPGAs;
– Novel ML hardware accelerators and associated software;
– Emerging semiconductor technologies with applications to ML hardware acceleration;
– ML for the construction and tuning of systems;
– Cloud and edge ML computing: hardware and software to accelerate training and inference;
– Computing systems research addressing the privacy and security of ML-dominated systems.

Papers will be reviewed by the workshop’s technical program committee according to criteria regarding a submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions on the topics mentioned above. Research papers, case studies, and position papers are all welcome.

The workshop does not have formal proceedings, so accepted papers do not preclude publishing at future conferences and/or journals.

Important Dates
Submission deadline: May 8, 2020 (Extended Deadline)
Notification of decision: May 20, 2020

José Cano (University of Glasgow)
José L. Abellán (Catholic University of Murcia)
Albert Cohen (Google)
Alex Ramirez (Google)

Call for Papers: 3rd Workshop on AI-assisted Design for Architecture (AIDArc) at ISCA 2020
Submitted by Lizhong Chen

The 3rd International Workshop on AI-assisted Design for Architecture (AIDArc-3)
in conjunction with ISCA 2020
Valencia, Spain (Now taking place virtually due to COVID-19)
May 30, 2020

Submissions Due: May 15, 2020 (extended)

Given the success of AIDArc workshops in 2019 and 2018, and the significantly increased interest in utilizing AI to improve computer architecture in past years, we are thrilled to organize the 3rd AIDArc workshop in 2020, held in conjunction with ISCA-47.

Recent advancements in machine learning algorithms, fueled by increased data availability and high-performance computing infrastructure, have led to successful applications of machine learning (and AI in general) in numerous disciplines and domains. Although much attention has been drawn in the computer architecture community on accelerating machine learning, limited research has been conducted to utilize the power of AI/ML to help architects design better computer architectures and systems.

The AIDArc Workshop is intended to bring together researchers, scientists and practitioners across academia and industry, to share early discoveries, successful examples, and opinions on opportunities and challenges regarding utilizing AI to assist computer architecture designs. Research along this line may potentially transform the way computers are designed and optimized. It may also lead to interesting “self-evolving architecture”, where AI helps to speed up computers which, in turn, are used to speed up the AI.

Topics of submitted papers include, but not limited to, the exploration of artificial intelligence in assisting the design and optimization of:

– Various components of computer system architecture, e.g., branch predictor, cache, memory, I/O, interconnection networks, etc.
– Various design objectives of computer system architecture, e.g., power/energy, performance, resource, reliability, security, etc.
– Different types of computer architectures and systems, e.g., embedded/mobile/wearable devices, CPUs, GPUs, special-purpose accelerators, datacenters, HPCs, etc.
– Interaction of computer architecture with other layers, e.g., operating systems, compilers, circuit-level designs, etc.

Papers of 4 to 6 pages will be reviewed based on originality, novelty, technical strength, presentation quality, correctness and relevance to the workshop scope. Early but novel works on related topics are highly encouraged. Detailed submission instructions are available at the workshop website

Paper submission (extended): May 15, 2020
Notification of acceptance: May 22, 2020
Camera-ready papers due: May 26, 2020
Workshop date: May 30, 2020

Lizhong Chen, Oregon State University

Call for Papers: PAW-ATM 2020: Parallel Applications Workshop, Alternatives To MPI+X
Submitted by Karla Morris

PAW-ATM 2020: Parallel Applications Workshop, Alternatives To MPI+X
November 16, 2020
Held in conjunction with SC20
Atlanta, GA, USA

Submissions Due: July 24, 2020



Architectural hierarchy and heterogeneity makes programming supercomputers challenging. In practice, HPC applications tend to be written using a mix of programming models—like C++, MPI, CUDA, and/or OpenMP—each of which is becoming more complex over time. This negatively impacts the costs of developing, maintaining, and porting HPC applications.

Meanwhile, alternative HPC programming models strive to improve things by raising the level of abstraction; incorporating modern features; and/or leveraging the respective strengths of programmers, compilers, and runtimes. These alternatives take the form of new languages (e.g., Chapel, Regent, XcalableMP), frameworks for large-scale data science (e.g., Arkouda, Dask, Spark), or extensions to existing languages (e.g., Charm++, COMPSs, Fortran, Legion, UPC++).

PAW-ATM is a forum for discussing HPC applications written in alternatives to MPI+X. Its goal is to bring together application experts and proponents of high-level languages to present concrete example uses of such alternatives, describing their benefits and challenges.

Scope and Aims

The PAW-ATM workshop aims to serve as a forum for exhibiting parallel applications developed using high-level parallel programming models that serve as alternatives to MPI+X-based programming. We encourage the submission of papers and talks from the community detailing practical distributed-memory applications written using alternatives to MPI+X, including characterizations of scalability and performance, expressiveness and programmability, as well as any downsides or areas for improvement in such models. In doing so, our hope is to create a setting in which application authors, language designers, and architects can present and discuss the state of the art in alternative scalable programming models while also wrestling with how to increase their effectiveness and adoption. Beyond well-established HPC scientific simulations, we also encourage submissions exploring artificial intelligence, big data analytics, machine learning, and other emerging application areas.

Topics of interest include, but are not limited to:

* Novel application development using high-level parallel programming languages and frameworks.

* Examples that demonstrate performance, compiler optimization, error checking, and reduced software complexity.

* Applications from artificial intelligence, data analytics, bioinformatics, and other novel areas.

* Performance evaluation of applications developed using alternatives to MPI+X and comparisons to standard programming models.

* Novel algorithms enabled by high-level parallel abstractions.

* Experience with the use of new compilers and runtime environments.

* Libraries using or supporting alternatives to MPI+X.

* Benefits of hardware abstraction and data locality on algorithm implementation.


Submissions are solicited in two categories:

1) Full-length papers presenting novel research results:

* Full-length papers will be published in the workshop proceedings (+). Submitted papers must describe original work that has not appeared in, nor is under consideration for, another conference or journal. Papers shall be eight (8) pages minimum and not exceed ten (10) including text, appendices, and figures. Appendix pages related to the reproducibility initiative dependencies, namely the Artifact Description (AD) and Artifact Evaluation (AE), are not included in the page count.

+ The specific publisher of the proceedings is TBA pending acceptance of our proposal.

2) Extended abstracts summarizing preliminary/published results:

* Extended abstracts will be evaluated separately and will not be included in the published proceedings; they are intended to propose timely communications of novel work that will be formally submitted elsewhere at a later stage, and/or of already published work that would be of interest to the PAW-ATM audience in terms of topic and timeliness. Extended abstracts shall not exceed four (4) pages.

When deciding between submissions with similar merit, submissions whose focus relates more directly to the key themes of the workshop (application studies, computing at scale, high-level alternatives to MPI+X) will be given priority over those that don’t. In addition, full-length paper submissions will be given preference over extended abstracts.

Submissions shall be submitted through Linklings:

Submissions must use 10pt font in the IEEE format:

PAW-ATM follows the reproducibility initiative of SC20. For more information, please refer to:

Transparency and Reproducibility Initiative


* Karla Morris – Sandia National Laboratory


* Rosa M. Badia – Barcelona Supercomputing Center
* Bradford L. Chamberlain – HPE


* Bill Long – HPE
* Sean Treichler – NVIDIA


* Submission Deadline: July 24, 2020
* Author Notification: September 23, 2020
* Camera Ready: October 1, 2020
* Workshop Date: November 16, 2020

Call for Papers: Special Issue on Highlights of Computer Architecture
Submitted by Yan Solihin

IEEE TC Special Issue on Highlights of Computer Architecture
Submissions Due: July 15, 2020

IEEE Transactions on Computers seeks original manuscripts for a special issue on Highlights of Computer Architecture (HiCA). The special issue provides the top-quality journal venue for scientists and engineers to present their latest research findings in this rapidly changing field. Authors of computer architecture conferences in the past 12 months, including but not limited to HPCA 2020, ISCA 2019, and MICRO 2019, are encouraged to submit extended versions of their papers. All aspects of computer architecture are within the scope of this special issue. Topics of interest include, but are not limited to:

  • Accelerators
  • Architecture applications of machine learning
  • Caches
  • Cloud, datacenter, cluster/distributed systems
  • Embedded, IoT
  • Emerging technologies
  • FPGAs and reconfigurable GPUs
  • Hardware/software interactions/interface
  • ILP techniques (speculation, prediction, prefetching, etc.)
  • IO, storage
  • Memory – high level (VM/TLB, persistency, etc.)
  • Memory – low level (devices, organization, etc.)
  • Networking, interconnects
  • Parallel/multi-core architectures
  • Performance characterization/modeling
  • Power efficiency and management
  • Quantum architectures
  • Reliability and fault tolerance
  • Security

Submission Guidelines

Submitted papers must include new, significant, research-based technical contributions in the scope of the journal. Papers under review elsewhere are not acceptable for submission. Extended versions of published conference papers, including, but not limited to, HPCA2020, ISCA2019, and MICRO2019, are welcome, but there must be at least 40% new impacting technical/scientific material in the journal version and there should be less than 50% verbatim similarity level as reported by a tool (such as CrossRef). The submission must also include the original conference paper with a detailed summary of differences. Submit your paper through ScholarOne and select the HiCA special-issue option. As per TC policies, only full-length papers (12+ pages) can be submitted to the special issue (no brief contributions will be considered), and each author’s bio must not exceed 150 words. Papers that are not accepted into the special issue will be considered for a TC regular issue.

Important Dates

  • Submission Deadline: July 15, 2020
  • Reviews Completed: August 31, 2020
  • Major Revisions Due: September 15, 2020
  • Reviews of Revisions Completed: September 30, 2020
  • Notification of Final Acceptance: October 7, 2020
  • Publication Materials for Final Manuscripts Due: October 21, 2020
  • Publication: November 2020


Please address all correspondence regarding this special issue to Lead Guest Editor Yan Solihin at

Guest Editors
Yan Solihin
Director of Cyber Security & Privacy Cluster, Charles N. Milican Professor
University of Central Florida

Jun Yang
Professor, ECE
University of Pittsburgh

Corresponding Topical Editor (CTE)
Avinash Karanth
Professor, EECS
Ohio University

Call for Papers: Networks-on-chip again on the rise: From emerging applications to emerging technologies
Submitted by Jose L. Abellan

Micromachines Special Issue
Networks-on-chip again on the rise: From emerging applications to emerging technologies

Submissions Due: October 18, 2020

Special Issue Editors

Prof. Dr. Davide Bertozzi Website
Guest Editor
Engineering Department, University of Ferrara, 44122, Italy
Interests: interconnection networks, embedded computing, emerging technologies, design automation
Prof. Dr. José L. Abellán Website
Guest Editor
Computer Science and Engineering Department, Universidad Católica San Antonio de Murcia, 30107, Spain
Interests: computer architecture, interconnection networks, silicon photonics
Prof. Dr. Mahdi Nikdast Website
Guest Editor
Electrical and Computer Engineering Department, Colorado State University, Fort Collins, 80523, USA
Interests: silicon photonics, high-performance computing systems, interconnection networks

Special Issue Information

Dear Colleagues,

Twenty years after the advent of interconnection networks to tackle the on-chip communication bottleneck, integrated computing platforms are again interconnect-dominated. On the one hand, the future of computing beyond Moore’s law and Dennard scaling is moving towards Systems-in-Package (SiP) based computing platforms that leverage advanced integration technologies such as 2.5D or 3D stacking. On the other hand, the advent and consolidation of data-intensive applications from artificial intelligence and big data analytics is putting unprecedented pressure on interconnection fabrics at each layer of the compute hierarchy, such as networks-on-chip (NoCs) and networks-in-package (NiPs).

This Special Issue seeks contributions on the latest advancements on chip- and package-scale interconnection systems, architectures, and/or circuits, capable of addressing the communication bottleneck raised by emerging data-intensive applications. The interest is in interconnect solutions for big data architectures across the computing continuum (from Edge computing to HPC) pursuing synergistic goals such as effective system integration (e.g., architectures for 2.5D or 3D-stacking) or architecture specialization (e.g., deep learning accelerators), and in any case striving to push performance boundaries under constant power budgets (e.g., approximate communication). At the same time, we welcome contributions on emerging technologies for on-chip and on-package networking (e.g., silicon nanophotonic networks, wireless NoCs, RF interconnects) with a focus ranging from disruptive devices to novel system concepts through architecture design methods. At the intersection of the above research directions, topics of interest include interconnect solutions for unconventional computing paradigms, such as  in-memory computing, neuromorphic computing or reconfigurable computing.

Prof. Dr. Davide Bertozzi
Prof. Dr. José L. Abellán
Prof. Dr. Mahdi Nikdast
Guest Editors
Manuscript Submission Information

Manuscripts should be submitted online at by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI’s English editing service prior to publication or during author revisions.


  • Communication bottleneck
  • Big data architectures
  • Deep learning hardware
  • Networks-on-chip
  • Networks-in-package
  • Communication fabric customization
  • Approximate communication
  • 2.5D and 3D integration
  • Emerging interconnect technologies
  • Communication in unconventional computing
Published Papers
This special issue is now open for submission.

Call for Workshops/Tutorials: MICRO-53 Call for Workshops and Tutorial
Submitted by Dimitrios Skarlatos

MICRO-53 Workshops and Tutorial
Athens, Greece
October 17-18, 2020

Submission Deadline: May 20, 2020
Notification: June 10, 2020

We invite proposals for workshops and tutorials to be held on Saturday 17 and Sunday 18 October, 2020, before the main symposium days of 19-21 October, 2020.
Proposals should be one to two pages long and must include the following information:
  • Title of the workshop/tutorial
  • Organizers and their affiliations (including short bios)
  • Expected duration of the workshop/tutorial; i.e., half day or full day
  • If the workshop/tutorial was previously held, provide the location (i.e., which conference), date, number of published papers (if any), and number of attendees at the last event
  • Provide a sample call for papers and workshop main topics (for a workshop proposal)
  • Provide the abstract of the tutorial (for a tutorial proposal)

Proposals should highlight a plan for ensuring diversity in invited speakers, tutorial presenters, and organizing and selection committees (if applicable).

Submit workshop and tutorial proposals (1 to 2 pages) to

View as PDF

Introducing Computer Architecture Podcasts

Submitted by Lisa Hsu

Introducing the Computer Architecture Podcasts: a series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.

Listen to the first episode with Dr. Kim Hazelwood from Facebook on Systems for ML and having an agile career at:

Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.

Happy Hour with Architects!
Submitted by Samira Khan

“Happy Hour with Architects” is a Zoom session on different topics related to computer architecture. The quarantine and self-isolation have proved to be tough on many people. These sessions create a sense of community during this new normal mode of life. It is a platform to discuss and debate various topics and does not only focus on technical content. The sessions are all recorded and made available on YouTube.

Episode 1: Software-Based Microarchitectural Attacks

Daniel Gruss (@lavados), TUGraz,
Jon Masters (@jonmasters), VP Software, Nuvia

Episode 2: Virtual Conferences and PC Meetings

Natalie Enright Jerger (@nenrightjerger), University of Toronto,
Boris Grot, University of Edinburgh (@BorisGrot),

Episode 3: Persistent Memory (Coming soon!)
Steve Swanson, University of California at San Diego
Andy Rudoff, Intel

New Book – A Primer on Memory Consistency and Cache Coherence, Second Edition
Submitted by Brent Beckley

Morgan & Claypool is proud to announce a recently published book in our Computer Architecture series.

A Primer on Memory Consistency and Cache Coherence, Second Edition

Vijay Nagarajan, University of Edinburgh
Daniel J. Sorin, Duke University
Mark D. Hill, University of Wisconsin, Madison
David A. Wood, University of Wisconsin, Madison
ISBN: 9781681737096 | PDF ISBN: 9781681737102 | Hardcover ISBN: 9781681737119
Copyright © 2020 | 294 Pages

Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems.

This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

Find the book.


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- Samira Khan
SIGARCH Content Editor