This is the 1st February 2020 digest of SIGARCH Messages.

In This Issue


Information about the ISCA’19 investigation

Submitted by Babak Falsafi

Dear members of the computer architecture community,

We recently communicated an announcement about an ACM SIGARCH / IEEE TCCA jointly-appointed committee investigating the review process related to an accepted ISCA’19 paper. In this announcement, we would like to provide further information about how the investigation was conducted:

1. The investigation process, the questions the reviewers of the paper were asked, and the preparation of the report were each conducted by a committee that was established in consultation with leadership and ethics committee members from IEEE and ACM. The investigation process, the questions, and the participants in the investigation were reviewed and approved by the IEEE leadership in consultation with IEEE TCCA and ACM SIGARCH. At least one lawyer from the societies provided advice in the process.

2. The investigating committee was composed of two leading members of the ISCA’19 Program Committee and two senior members of our community who were neither in the ISCA 2019 Program Committee nor part of the ISCA Steering Committee. No member of the committee had reviewed the paper under investigation during the peer review process. As per the societies’ publications policy, the names of any and all participants involved in the investigation must remain anonymous.

​3. The investigation involved interviewing ISCA’19 Program Committee members. In all interviews conducted for the investigation, the ACM and IEEE representatives had an opportunity to ask additional questions and ensure that all questions, interviews, and interview summaries were handled fairly and without bias.

4. The investigation did not include any segments involving Program Committee members from ISCA’19 without additional oversight present from the IEEE and ACM representatives of the committee.

5. The investigation was not a self-investigation. Throughout the investigation, ACM and IEEE representatives participated.

If you have further questions about ACM’s or IEEE’s involvement in the investigation, please contact Scott Delman (ACM’s Director of Publications at scott.delman@hq.acm.org) and Melissa Russell (IEEE Computer Society’s Executive Director, at m.a.russell@computer.org) respectively.

SIGARCH & TCCA Chairs
Babak Falsafi & Josep Torrellas


Call for Nominations: SIGARCH/TCCA PhD Dissertation Award
https://www.sigarch.org/benefit/awards/acm-sigarch-ieee-cs-tcca-outstanding-dissertation-award/
Submitted by José F. Martínez

SIGARCH/TCCA PhD Dissertation Award
Nominations Due: February 1, 2020

The February 1 deadline for nominating a 2019 PhD dissertation to the SIGARCH/TCCA Outstanding Dissertation Award is fast approaching. Nominated dissertations must have been defended and deposited in 2019. Please note that self-nominations are disallowed; they must come from the PhD advisor.

Advisors, please consider nominating your recent PhD graduate!

Nomination for the award must include:

  1. English language copy of the thesis.
  2. Statement from the advisor limited to two pages addressing why the nominee’s dissertation should receive this award.  This should address the significance of the dissertation, not simply repeat the information in the abstract. The nomination must come from the advisor; self-nomination is not allowed.
  3. Three letters of support limited to two pages each. Supporting letters should be included from experts in the field who can provide additional insights or evidence of the dissertation’s impact.  (The nominator/advisor may not write a letter of support.)  The letter should also contain the qualification of the endorser and his/her role with respect to the nominee. If a letter writer is supporting more than one nomination, they may be asked to rank those nominations. At least one letter must come from an expert outside the nominee’s university. Additional letters beyond three will not be considered.
  4. List of publications contributing to the thesis.
  5. Member number for the nominee (Nominee must be a SIGARCH or TCCA member).
  6. Suggested citation if the candidate is selected. This should be a concise statement (maximum of 25 words) describing the key technical contribution for which the candidate merits this award. Note that the final wording for awardees will be at the discretion of the SIGARCH/TCCA Dissertation Award Committee.

Please send nominations (preferably electronically) no later than February 1, 2020 to the chair of the SIGARCH/TCCA Dissertation Award Committee, Antonio Gonzalez at antonio@ac.upc.edu. Nominations must be submitted in English. PDF format is preferred for all materials. Late submissions will not be considered.


Call for Nominations: TACO Editor-in-Chief: Call for Nominations

Submitted by Laura Lander

Call for Nominations: Editor-In-Chief
ACM Transactions on Architecture and Code Optimization (TACO)

Deadline for Nominations: February 1, 2020

The term of the current Editor-in-Chief (EiC) of the ACM Transactions on Architecture and Code Optimization (TACO) is coming to an end, and the ACM Publications Board has set up a nominating committee to assist the Board in selecting the next EiC. Nominations, including self-nominations, are invited for a three-year term as TACO EiC, beginning on May 1, 2020. The EiC appointment may be renewed at most one time. This is an entirely voluntary position, but ACM will provide appropriate administrative support. The EiC is responsible for maintaining the highest editorial quality, for setting technical direction of the papers published in TACO, and for maintaining a reasonable pipeline of articles for publication. He/she has final say on acceptance of papers, size of the Editorial Board, and appointment of Associate Editors. The EiC is expected to adhere to the commitments expressed in the policy on Rights and Responsibilities in ACM Publishing. For more information about the role of the EiC, see ACM’s Evaluation Criteria for Editors-in-Chief.

Nominations should include a vita along with a brief statement of why the nominee should be considered and a statement of the candidate’s vision for the future development of TACO. Self-nominations are encouraged. The deadline for submitting nominations has been extended to 1 February 2020, although nominations will continue to be accepted until the position is filled. Please send all nominations to the nominating committee chair, Per Stenstrom (per.stenstrom@chalmers.se).

The search committee members are:
● Per Stenstrom (Chalmers University of Technology), Chair
● Albert Cohen (Google)
● Tom Conte (Georgia Institute of Technology)
● Lizy John (University of Texas, Austin)
● David Whalley (Florida State University)
● Divesh Srivastava (AT&T Research) ACM Publications Board Liaison


Call for Nominations: HPCA 2020 Test of Time Award
http://ieeetcca.org/2020-hpca-test-of-time-award-call-for-nominations/
Submitted by Todd Austin, University of Michigan

HPCA 2020 Test of Time Award

Nominations Due: January 22, 2020

The HPCA Test of Time (ToT) Award Committee is soliciting nominations for the second HPCA ToT Award to be given at the International Symposium on High Performance Computer Architecture in February 2020, to be held in San Diego, CA. This award recognizes the most influential papers published in past HPCA conferences that have had significant impact in the field.

The award will recognize an influential HPCA paper whose influence is still felt 18-22 years after its initial publication. In other words, the award will be given to at most one paper that was published at HPCA conferences in any of the years N-22, N-21, N-20, N-19, or N-18. This year, N = 2020, so papers published at HPCA conferences held in 1998, 1999, 2000, 2001 or 2002 are eligible. An eligible paper that has received at least 100 citations (according to Google Scholar) is automatically nominated, but explicit nominations of such papers are still encouraged.

We invite anyone to submit a nomination by the deadline of January 22, 2020. Please submit your nomination via email to the committee chair (Todd Austin, austin@umich.edu). The following describes the nomination criteria, how to submit a nomination, and the selection process.

Which papers are eligible for the 2020 HPCA ToT (Test of Time) Award?

Only papers published at HPCA conferences that happened between 1998-2002 (inclusive). See the list of eligible papers.

Who can nominate a paper?

Anyone can nominate a paper except for the author or co-author(s) of the nominated paper.

When is the last day to submit a nomination?

Nominations must be received by January 22, 2020.

How should a nomination be submitted?

Nominations must be submitted via email to the award chair, Todd Austin at austin@umich.edu.

What should be included in the nomination email?

  • Please use the email subject: “HPCA 2020 ToT Nomination”
  • The title, the author list, and publication year of the nominated paper.
  • A 100-word (maximum) nomination statement, describing why the paper deserves the HPCA 2020 Test of Time Award.
  • The name, title, affiliation of the nominator, and if appropriate, the relationship of the nominator to the authors.
  • Only one paper can be nominated in a single email.

What is the selection process?

The HPCA ToT Award committee will evaluate all submitted nominations to select at most one paper for the 2020 HPCA ToT (Test of Time) Award. A strict conflict of interest policy will be followed. If a ToT Award Committee Member has a conflict of interest with a paper that is nominated, the member will recuse himself/herself from the discussion process and a substitute will be placed in. On occasion, papers will receive honorable mentions in the evaluation process, at the discretion of the award committee.

Who are the current HPCA ToT Award committee members?

  • Todd Austin, University of Michigan, chair
  • David Kaeli, Northeastern University
  • Reetuparna Das, University of Michigan
  • Natalie Enright Jerger, University of Toronto
  • Onur Mutlu, ETH Zurich

When will the award be announced and given?

The award will be presented to the authors of the selected paper at the Awards Ceremony during the International Symposium on High Performance Computer Architecture in February 2020, to be held in San Diego, CA.. Awardees will be invited to make a short presentation at the HPCA Awards Ceremony.

What does the award consist of?

An award certificate and peer recognition.

 


Call for Participation: Workshop on Accelerator Architecture in Computational Biology and Bioinformatics
https://aacbb-workshop.github.io/
Submitted by Divya Mahajan

Workshop on Accelerator Architecture in Computational Biology and Bioinformatics
co-located with HPCA 2020
San Diego, USA

February 23, 2020

This workshop focuses on the architecture and design of hardware and software accelerators for computational biology and bioinformatics problems.

Topics of interest include, but are not limited to the following:

  • Hardware and software algorithms/applications in the fields of computational biology, such as (but not limited to):
      • Bioinformatics
      • Genomics
      • Proteomics
      • Protein structure prediction
  • Bioinformatics and computational biology accelerator architecture and design based on (but not limited to):
      • 3D memory-logic stack
      • Automata processing
      • Near-data (in-memory) processing
      • FPGAs and reconfigurable
  • Emerging memory technologies and their impact on bioinformatics and computational biology
  • Impact of bioinformatics and biology applications on computer architecture research
  • Bioinformatics and computational biology-inspired hardware/software trade-offs

The full schedule can be found at https://aacbb-workshop.github.io/


Call for Participation: HPCA 2020
https://www.hpca-conf.org/2020/registration/
Submitted by Divya Mahajan

HPCA Registration Website is up (Early Registration ends on Jan 31) – https://www.hpca-conf.org/2020/registration/

Reserve the hotel at – https://www.hpca-conf.org/2020/venue-hotel/

-HPCA Team

See you all in San Diego!


Call for Participation: HPBDC 2020
http://web.cse.ohio-state.edu/~luxi/hpbdc2020
Submitted by Haiyang Shi

The 6th IEEE International Workshop on High-Performance Big Data and Cloud Computing (HPBDC)
In conjunction with the 34th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2020)
New Orleans, Louisiana, USA
Monday, May 18th, 2020

http://web.cse.ohio-state.edu/~luxi/hpbdc2020

WORKSHOP DESCRIPTION
—————————————

Managing and processing large volumes of data, or Big Data, and gaining meaningful insights is a significant challenge facing the parallel and distributed computing community. This has significant impact in a wide range of domains including health care, bio-medical research, Internet search, finance and business informatics, and scientific computing. As data-gathering technologies and data sources witness an explosion in the amount of input data, it is expected that in the future massive quantities of data in the order of hundreds or thousands of petabytes will need to be processed. Thus, it is critical that data-intensive computing middleware (such as Hadoop, Spark, Flink, etc.) to process such data are diligently designed, with high performance and scalability, in order to meet the growing demands of such Big Data applications.

The explosive growth of Big Data has caused many industrial firms to adopt High Performance Computing (HPC) technologies to meet the requirements of huge amount of data to be processed and stored. The convergence of HPC, Big Data, and Deep Learning is becoming the next game-changing business opportunity. Apache Hadoop, Spark, gRPC/TensorFlow, and Memcached are becoming standard building blocks in handling Big Data oriented processing and mining.

Modern HPC bare-metal systems and Cloud Computing platforms have been fueled with the advances in multi-/many-core architectures, RDMA-enabled networking, NVRAMs, and NVMe-SSDs during the last decade. However, Big Data and Deep Learning middleware (such as Hadoop, Spark, Flink, and gRPC) have not embraced such technologies fully. These disparities are taking HPC, Big Data, and Deep Learning into divergent trajectories.

International Workshop on High-Performance Big Data, Deep Learning, and Cloud Computing (HPBDC), aims to bring HPC, Big Data processing, Deep Learning, and Cloud Computing into a convergent trajectory. The workshop provides a forum for scientists and engineers in academia and industry to present their latest research findings in major and emerging topics for ‘HPC + Big Data + Deep Learning over HPC Clusters and Clouds’.

HPBDC 2020 will be held in conjunction with the 34th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2020).

HPBDC 2020 welcomes original submissions in a range of areas, including but not limited to:

* High-Performance Big Data analytics, Deep Learning, and Cloud Computing frameworks, programming models, and tools

* Performance optimizations for Big Data, Deep Learning, and Cloud Computing systems and applications with HPC technologies

* High-Performance in-memory computing technologies and abstractions

* Performance modeling and evaluation for emerging Big Data processing, Deep Learning, and Coud Computing technologies

* Big Data processing and Deep Learning on HPC, Cloud, and Grid computing infrastructures

* Fault tolerance, reliability, and availability for high-performance Big Data computing, Deep Learning, and Cloud Computing

* Green Big Data computing, Deep Learning, and HPC Clouds

* Scheduling and provisioning data analytics on HPC and Cloud infrastructures

* Scientific computing with Big Data and Deep Learning on HPC Clusters and/or Clouds

* Case studies of Big Data and Deep Learning applications on HPC systems and Clouds

* High-Performance streaming data processing architectures and technologies

* High-Performance graph processing with Big Data

* High-Performance SQL and NoSQL data management technologies

Papers should present original research. As the fields of Big Data, Deep Learning, and Cloud Computing span many disciplines, papers should provide sufficient background material to make them accessible to the broader community. One outstanding paper will be selected for the Best Paper Award.

SUBMISSION INFORMATION
—————————————-

All submissions should follow the IEEE standard 8.5×11 two-column format. The workshop will accept traditional research papers (8-10 pages) for in-depth topics and short papers (4 pages) for works in progress on hot topics.

– Long papers: 8-10 pages, with a full problem description, background and related work, design, and evaluation.

– Short papers: 4 pages, for works in progress on hot topics.

All the papers should be submitted through
https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=HPBDCWorkshopFullSubmission&site=ipdps2020.

All papers will be carefully reviewed by at least three reviewers. Papers should not be submitted in parallel to any other conference or journal.

The proceedings of this workshop will be published together with the proceedings of other IPDPS 2020 workshops by the IEEE Computer Society Press. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. At least one of the authors of each accepted paper must register as a participant of the workshop and present the paper at the workshop, in order to have the paper published in the proceedings.

IMPORTANT DATES
—————————-

– Abstract submission deadline (optional): January 16th, 2020 (Anywhere on Earth)
– Paper submission deadline (extended): February 1st, 2020 (Anywhere on Earth)
– Acceptance notification: March 1st, 2020
– Camera-ready deadline: March 15th, 2020
– Workshop: May 18th, 2020

WORKSHOP ORGANIZERS
————————————–

Xiaoyi Lu, The Ohio State University
Jianfeng Zhan, Institute of Computing Technology, Chinese Academy of Sciences, China

PUBLICITY CHAIR
————————————

Haiyang Shi, The Ohio State University

PROGRAM COMMITTEE (Confirmed So far)
————————————————————

Luiz F. Bittencourt, University of Campinas, Brazil
Jong Youl Choi, Oak Ridge National Laboratory
Shadi Ibrahim, Inria, France
Hyun-Wook Jin, Konkuk University, Korea
Jithin Jose, Microsoft
Zengxiang Li, Institute Of High Performance Computing, Singapore
Mingzhe Li, Facebook
Suzanne McIntosh, New York University
Manoj Nambiar, Tata Consultancy Services Ltd., India
Juan Touriño, University of A Coruña, Spain
Yunquan Zhang, Institute of Computing Technology, Chinese Academy of Sciences, China


Call for Papers: The First Instruction Prefetching Championship (with ISCA 2020)
https://research.ece.ncsu.edu/ipc/
Submitted by Alaa Alameldeen

The 1st Instruction Prefetching Championship with ISCA 2020
Valencia, Spain

Submission Due: April 3, 2020

The First Instruction Prefetching Championship (IPC-1) is a competition for instruction prefetching algorithms. The workshop is going to be held with ISCA-2020. Contestants are given a fixed storage budget to implement their best instruction prefetching ideas using a common simulator infrastructure. The organizing committee will evaluate all submitted prefetchers, and the top performers will be announced and awarded at the workshop.

 

For more information, please visit: https://research.ece.ncsu.edu/ipc/

Important dates:

Submission Deadline (Paper & Code): April 3, 2020

Notification: April 15, 2020

Workshop: May 30 or May 31, 2020 right before ISCA-2020 in Valencia, Spain.

 

 


Call for Papers: FastPath 2020: International Workshop on Performance Analysis of Machine Learning Systems
https://fastpath2020.github.io
Submitted by I-Ting Angelina Lee

FastPath 2020: International Workshop on Performance Analysis of Machine Learning Systems
In conjunction with ISPASS 2020
Boston, Massachusetts, United States
April 5, 2020

Submissions Due: February 21, 2020

https://fastpath2020.github.io

SUMMARY

FastPath 2019 brings together researchers and practitioners involved in crossstack hardware/software performance analysis, modeling, and evaluation for efficient machine learning systems. Machine learning demands tremendous amount of computing. Current machine learning systems are diverse, including cellphones, high performance computing systems, database systems, self-driving cars, robotics, and in-home appliances. Many machine-learning systems have customized hardware and/or software. The types and components of such systems vary, but a partial list includes traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators, hybrid systems, converged infrastructure, and IT appliances. Designing efficient machine learning systems poses several challenges.

These include distributed training on big data, hyper-parameter tuning for models, emerging accelerators, fast I/O for random inputs, approximate computing for training and inference, programming models for a diverse machine-learning workloads, high-bandwidth interconnect, efficient mapping of processing logic on hardware, and cross system stack performance optimization. Emerging infrastructure supporting big data analytics, cognitive computing, large-scale machine learning, mobile computing, and internet-of-things, exemplify system designs optimized for machine learning at large.

TOPICS

FastPath seeks to facilitate the exchange of ideas on performance optimization of machine learning/AI systems and seeks papers on a wide range of topics including, but not limited to:

o Workload characterization, performance modeling and profiling of machine learning applications

o GPUs, FPGAs, ASIC accelerators

o Memory, I/O, storage, network accelerators

o Hardware/software co-design

o Efficient machine learning algorithms

o Approximate computing in machine learning

o Power/Energy and learning acceleration

o Software, library, and runtime for machine learning systems

o Workload scheduling and orchestration

o Machine learning in cloud systems

o Large-scale machine learning systems

o Emerging intelligent/cognitive system

o Converged/integrated infrastructure

o Machine learning systems for specific domains, e.g., financial, biological, education, commerce, healthcare

SUBMISSION

Prospective authors must submit a 2-4 page extended abstract:

https://easychair.org/conferences/?conf=fastpath2020

Authors of selected abstracts will be invited to give a 30-min presentation at the workshop.

KEY DATES

Submission:   February 21, 2020

Notification: March 2, 2020

Final Materials / Workshop: April 5, 2020


Call for Papers: SECRISC-V Workshop 2020
https://ascslab.org/conferences/secriscv/index.html
Submitted by I-Ting Angelina Lee

Workshop on Secure RISC-V (SECRISC-V) Co-located with ISPASS 2020
Boston, Massachusetts, USA
April 5-7, 2020

Submissions Due: February 7, 2020

The first international workshop on Secure RISC-V (SECRISC-V) architecture design exploration seeks original research papers on the design, implementation, verification, and evaluation of micro-architecture security features, hardware-assisted security techniques, and secure executions around the RISC-V instruction set architecture (ISA).

Co-located with ISPASS 2020 – April 5-7, 2020 – Boston, Massachusetts

Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the workshop include, but are not limited to:

• Secure cores and multicores

• ISA extensions for Security

• Software and hardware obfuscation Techniques

Secure, efficient, and lightweight hardware implementations

• Hardware security solutions for machine learning

• Secure design for emerging applications: IoT, robotics, wearable computing

• Architectural designs and hardware security solutions for HPC, Data Centers and cloud computing

• Hardware virtualization and isolation for security

• Hardware-Software co-design solutions: graph analytics,

• Post-quantum cryptosystem designs

• Quantum Computing

• Neuromorphic Architectures

• Blockchain enabled secure computing

Classic and Modern encryption algorithms and hardware support

• Hardware security support for integrity and authentication, key distribution and management, and trust platform modules

• Software and core authentication

• Secure execution environment 

• Secure root of trust bios     

• Memory subsystem organization to secure data accesses

• Network-on-Chip (NoC) security feature to process and compute isolation

The paper must be submitted in PDF format. The content of the submission is limited to four (4) pages – 8.5″x11″ single-spaced double-column.

Deadlines

• Submission: February 7, 2020

• Notification: February 28, 2020

Final Version: March 20, 2020

Website

https://ascslab.org/conferences/secriscv/index.html


Call for Papers: SECRISC-V Workshop at ISPASS 2020
https://ascslab.org/conferences/secriscv/index.html
Submitted by Alexandra Jimborean

Workshop on Secure RISC-V (SECRISC-V) co-located with ISPASS 2020
Boston, Massachusetts
April 5-7, 2020

Submissions Due: February 7, 2020

The first international workshop on Secure RISC-V (SECRISC-V) architecture design exploration seeks original research papers on the design, implementation, verification, and evaluation of micro-architecture security features, hardware-assisted security techniques, and secure executions around the RISC-V instruction set architecture (ISA).

Co-located with ISPASS 2020 – April 5-7, 2020 – Boston, Massachusetts

Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the workshop include, but are not limited to:

  • Secure cores and multicores
  • ISA extensions for Security
  • Software and hardware obfuscation Techniques
  • Secure, efficient, and lightweight hardware implementations
  • Hardware security solutions for machine learning
  • Secure design for emerging applications: IoT, robotics, wearable computing
  • Architectural designs and hardware security solutions for HPC, Data Centersand cloud computing
  • Hardware virtualization and isolation for security
  • Hardware-Software co-design solutions: graph analytics,
  • Post-quantum cryptosystem designs
  • Quantum Computing
  • Neuromorphic Architectures
  • Blockchain enabled secure computing
  • Classic and Modern encryption algorithms and hardware support
  • Hardware security support for integrity and authentication, key distributionand management, and trust platform modules
  • Software and core authentication
  • Secure execution environment
  • Secure root of trust bios
  • Memory subsystem organization to secure data accesses
  • Network-on-Chip (NoC) security feature to process and compute isolationThe paper must be submitted in PDF format. The content of the submission is limited to four (4) pages – 8.5″x11″ single-spaced double-column.

Deadlines

  • Submission: February 7, 2020
  • Notification:  February 28, 2020
  • Final Version:  March 20, 2020Website: https://ascslab.org/conferences/secriscv/index.html

 

 


Call for Papers: Benchmarking Machine Learning Workloads on Emerging Hardware Workshop at MLSys’20
https://memani1.github.io/challenge20/
Submitted by Tom St. John

Benchmarking Machine Learning Workloads on Emerging Hardware
Co-located with MLSys 2020
Austin, TX, USA
March 4, 2020

Submissions Due: January 15, 2020

With evolving system architectures, hardware and software stacks, diverse machine learning (ML) workloads, and data, it is important to understand how these components interact with each other. Well-defined benchmarking procedures help evaluate and reason the performance gains with ML workload-to-system mappings. We welcome all novel submissions in benchmarking machine learning workloads from all disciplines, such as image and speech recognition, language processing, drug discovery, simulations, and scientific applications. Key problems that we seek to address are: (i) which representative ML benchmarks cater to workloads seen in industry, national labs, and interdisciplinary sciences; (ii) how to characterize the ML workloads based on their interaction with hardware; (iii) which novel aspects of hardware, such as heterogeneity in compute, memory, and networking, will drive their adoption; (iv) performance modeling and projections to next-generation hardware. Along with selected publications, the workshop program will also have experts in these research areas presenting their recent work and potential directions to pursue.

We solicit both full papers (8-10 pages) and short/position papers (4 page). Submissions are not double blind (author names must be included). The page limit includes figures, tables, and appendices, but excludes references. Please use standard LaTeX or Word ACM templates. All submissions will need to be made via EasyChair (submission website: here). Each submission will be reviewed by at least three reviewers from the program committee. Papers will be reviewed for novelty, quality, technical strength, and relevance to the workshop. All accepted papers will be made available online and selected papers will be invited to submit extended versions to a journal after the workshop.

 

Organizing Committee:

  • Murali Emani, Argonne National Laboratory/ALCF
  • Tom St John, Tesla Inc.

 

Program Committee:

  • Gregory Diamos, Landing AI
  • Cody Coleman, Stanford University
  • Farzad Khorasani, Tesla
  • Trevor Gale, Stanford University
  • Ilya Sharapov, Cerebras Systems
  • Lizy John, UT Austin
  • Vijay Janapa Reddi, Harvard University
  • Shuaiwen Leon Song, University of Sydney
  • Xiaoming Li, University of Delaware
  • Zheng Wang, University of Leeds
  • Prasanna Balaprakash, Argonne National Laboratory
  • Ramesh Radhakrishnan, Dell
  • Steve Farrell, Lawrence Berkeley National Laboratory/NERSC
  • Nikoli Dryden, ETH Zurich
  • Jesmin Jahan Tithi, Intel
  • Rong Ge, Clemson University
  • Lisa Wu Wills, Duke University

Call for Presentations: Wild and Crazy Ideas (WACI) at ASPLOS 2020
https://forms.gle/oCn7YMRjDyNdTKz28
Submitted by Adrian Sampson

Wild and Crazy Ideas (WACI) at ASPLOS 2020

Submissions Due: January 31, 2020

The Wild and Crazy Ideas (WACI) session is a time-honored tradition at ASPLOS that frees researchers from the shackles of realism, removes the blinders of short-term thinking, and opens the scientific mind to uncharted frontiers. Since 1998, WACI has provided a counterweight to the conservative impulses wrought by the traditional peer review path.

This is your moment to propose something huge—something no one else is talking about. Craft a talk proposal that:

  • Falls within the ASPLOS purview. Your idea should combine elements of at least two of architecture, programming languages, and operating systems.
  • Is not (yet) publishable research. Propose something neither you nor anyone else in the community is actually working on—for example, because it seems only barely feasible, because it requires thinking far into the future, because it strays into intellectual domains too far from core ASPLOS expertise, or because it directly contradicts the conventional wisdom.
  • Might change the world. Your idea must be enormous. Unshackle your ambition.

Ideas may also be funny—we encourage it!—but we think ideas are funniest when they build on an element of real, world-changing, convention-challenging research thought.

Submit a one-paragraph abstract of your idea by January 31 via the submission form. If the WACI chairs select your abstract for a talk, here’s what you can expect:

  • You write a longer version of your idea (limit: two pages) for publication on the WACI website.
  • The WACI chairs work with you to craft an excellent, compact, entertaining talk for the WACI session in Lausanne.

Contact the WACI chairs, Adrian Sampson and Christina Delimitrou, with any questions.


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Samira Khan
SIGARCH Content Editor

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