This is the 1st December 2018 digest of SIGARCH Messages.

In This Issue


Call for Nominations: HPCA Test of Time Award
http://ieeetcca.org/awards/hpca-test-of-time-award/
Submitted by David Kaeli

HPCA Test of Time Award 2019

Deadline for nominations: December 1, 2018.

Please visit http://ieeetcca.org/awards/hpca-test-of-time-award for details.

For questions, contact David Kaeli (kaeli@ece.neu.edu).


Call for Papers: Workshop On Energy Efficient Machine Learning And Cognitive Computing For Embedded Applications
https://www.emc2-workshop.com
Submitted by Michael Goldfarb

Workshop On Energy Efficient Machine Learning And Cognitive Computing For Embedded Applications (EMC^2)
in conjunction with HPCA 2019
Washington DC, USA
February 17, 2019

IMPORTANT DATES:
Paper Submission: Jan 18, 2019 (11:59 pm PST)
Notification and Rebuttals: Feb 5, 2019
Final Version Due: Feb 8, 2019

A new wave of intelligent computing, driven by recent advances in machine learning and cognitive algorithms coupled with process technology and new design methodologies, has the potential to usher unprecedented disruption in the way conventional computing solutions are designed and deployed. These new and innovative approaches often provide an attractive and efficient alternative not only in terms of performance but also power, energy, and area. This disruption is easily visible across the whole spectrum of computing systems ranging from low end mobile devices to large scale data centers and servers.

A key class of these intelligent solutions is providing real-time, on-device cognition at the edge to enable many novel applications including vision and image processing, language translation, autonomous driving, malware detection, and gesture recognition. Naturally, these applications have diverse requirements for performance, energy, reliability, accuracy, and security that demand a holistic approach to designing the hardware, software, and intelligence algorithms to achieve the best power, performance, and area (PPA).

The goal of this workshop is to provide a forum for researchers who are exploring novel ideas in the field of energy efficient machine learning and artificial intelligence for embedded applications. We also hope to provide a solid platform for forging relationships and exchange of ideas between the industry and the academic world through discussions and active collaborations.

Below is a set of suggested but not limited topics:
– Computing techniques for IoT, Automotive, and mobile intelligence
– Exploration new and efficient applications of machine learning
– Machine learning benchmarks, workloads and their characterization
– Energy efficient techniques and solutions for neural networks
– Efficient hardware proposals to implement neural networks
– Power and performance efficient memory architectures
– Exploring the interplay between precision, performance, power and energy
– Approximation, quantization and reduced precision computing techniques
– Improvements over conventional training techniques
– Hardware/software techniques to exploit sparsity and locality
– Security and privacy challenges and building secure systems

ORGANIZERS:
Raj Parihar, Tensilica/Cadence
Michael Goldfarb, Nvidia
Satyam Srivastava, Intel
Mahdi N. Bojnordi, University of Utah
Krishna Nagar, Intel
Tao Sheng, Amazon
Debu Pal, Cadence

Program Committee:
Raj Parihar, Tensilica/Cadence
Michael Goldfarb, Nvidia
Chen Ding, University of Rochester
Mahdi N. Bojnordi, University of Utah
Andy Glew, Nvidia
Sreepathi Pai, University of Rochester
Raj Jain, Washington University in St. Louis
Smruti R Sarangi, IIT Delhi
Shaoshan Liu, PerceptIn
Ali Shafiee, Samsung
Satyam Srivastava, Intel
Danian Gong, Cadence
Krishna Nagar, Intel
Tao Sheng, Amazon


Call for Papers: ALCHEMY 2019
https://sites.google.com/site/alchemyworkshop/
Submitted by Loïc CUDENNEC

Architecture, Languages, Compilation and Hardware support for EMerging and Heterogeneous sYstems (ALCHEMY)
in conjunction with ICCS 2019
Faro, Algarve, Portugal
June 12-14, 2019

Submission deadline: 31 January, 2019

The International Conference on Computational Science is an annual conference that brings together researchers and scientists from mathematics and computer science as basic computing disciplines, researchers from various application areas who are pioneering computational methods in sciences such as physics, chemistry, life sciences, and engineering, as well as in arts and humanitarian fields, to discuss problems and solutions in the area, to identify new issues, and to shape future directions for research.

ICCS is an A-rank conference in the CORE classification.
All accepted papers will be included in the Springer Lecture Notes in Computer Science (LNCS) series.

The future aims toward increasing parallelism and heterogeneity of systems to tackle the so-called power-wall while permitting a roadmap of increased performance. Several challenges rise for programming such systems. The ALCHEMY workshop goal is to show some of these relevant challenges and finding ways to tackle them, while permitting programmers to focus on important part of application designs and letting compilers or runtime optimization do most of the work toward good performance.

ALCHEMY is the track of ICCS addressing new distributed and parallel systems for compute-intensive applications, including heterogeneous aspects. It is also a good place of exchange between the traditional HPC domain of research and all the emerging HPES (High-Performance Embedded Systems) domain, since the programming issues are mostly the same, with a relatively high cost of communication and the difficulty to program hundreds of cores often under performance and power usage constraints.

Original high quality submission are encouraged on all topics related to parallel and distributed programming issues including (but not limited to):
– High-level Programming
– Programming models and languages
– Compilers for programming languages
– Runtime generation for parallel programming
– Handling heterogeneity in parallel and distributed systems

– Operational research and optimizations
– Application, runtime, system and hardware sizing
– Task scheduling
– Task placement, application mapping

– System and runtime
– New operating systems, dedicated OS
– Dedicated runtimes
– Shared memory, data consistency models and protocols

– Hardware architecture
– Architecture support for massive parallelism management
– Specific or reconfigurable accelerators (use of FPGA), many-cores
– Enhanced communications
– New memory technologies (NVRAM)

– Security
– Accelerators for security
– Crypto systems

– In-situ systems and user experiments
– User feedback on existing architectures
– Heterogeneous integration within HPC systems (micro-servers)
– Coping with heterogeneity at the user level

SUBMISSION GUIDELINES:
The manuscripts of 10-14 pages, written in English and formatted according to the Springer LNCS templates, should be submitted electronically via EasyChair. Templates are available for download in EasyChair horizontal menu “Templates”. Papers must be based on unpublished original work and must be submitted to ICCS only. Submission implies the willingness of at least one of the authors to register and present the paper. All accepted papers will be included in the Springer Lecture Notes in Computer Science (LNCS) series and indexed by Scopus, EI Engineering Index, Thomson Reuters Conference Proceedings Citation Index (included in ISI Web of Science), and several other indexing services.

Please use the ICCS submission system hosted by EasyChair and select the Architecture, Languages, Compilation and Hardware support for Emerging and Heterogeneous sYstems track.

ORGANIZERS:
General Co-Chairs:
Loïc CUDENNEC, CEA, LIST, France
Stéphane LOUISE, CEA, LIST, France

Program Committee:
Giovanni AGOSTA, Politecnico di Milano, Italy
Paul M. CARPENTER, BSC, Spain
Jeronimo CASTRILLON, CFAED, TU Dresden, Germany
Camille COTI, Université de Paris-Nord, France
Loïc CUDENNEC, CEA, LIST, France
Vianney LAPOTRE, Université de Bretagne-Sud, France
Stéphane LOUISE, CEA, LIST, France
Marco MATTAVELLI, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Raymond NAMYST, INRIA, Université de Bordeaux, France
Eric PETIT, Intel, France
Erwan PIRIOU, CEA, LIST, France
Antoniu POP, University of Manchester, UK
Mario PORRMANN, CITEC, Universität Bielefeld, Germany
Jason RIEDY, Georgia Institute of Technology, USA
Johanna SEPULVEDA, Institute for Security in Information Technology, TU Munich, Germany
(to be extended)


Call for Papers: Special Issue on Intelligent Embedded Systems Architectures and Applications
https://www.journals.elsevier.com/microprocessors-and-microsystems/call-for-papers/special-issue-on-intelligent-embedded-systems-architectures
Submitted by Lars Bauer

Special Issue on Intelligent Embedded Systems Architectures and Applications
Elsevier Microprocessors and Microsystems

IMPORTANT DATES:
Paper submission deadline: Jan 15, 2019
Notification of the first review: Mar 15, 2019
Revisions due: Apr 15, 2019
Final notice of acceptance: May 15, 2019
Final version manuscripts due: Jun 15, 2019
Special issue to appear: Sep 2019

The purpose of this special issue is to provide an up-to-date picture of intelligent embedded systems architectures and applications with emphasis on Smart IoT and Cyber Physical Systems, including hot topics such as accelerating deep learning. The proposal covers several aspects, from the hardware related ones to embedded software and application issues.

Topics include, but not limited to, the following:
– Special purpose hardware to support deep learning in embedded architectures
– Edge computing for smart embedded systems: hardware and software aspects
– Run-time resource management for smart IoT/Edge Computing systems
– HW/SW codesign of Cyber Physical Systems
– Programming models for IoT/Edge computing applications
– Applications and case studies of intelligent embedded systems
– Design methodologies and platforms for wearable computing
– In-memory computing for unsupervised learning

SUBMISSION GUIDELINES:
Submissions will be evaluated on Novelty, Generality, Significance, Clarity and Support criteria. We invite the submission of full length papers to this special issue that will details the state-of-the-art technology and trends in Intelligent Embedded Systems Architectures and Applications.

GUEST EDITORS:
Maurizio Martina, Politecnico di Torino, Italy
William Fornaciari, Politecnico di Milano, Italy


Book Release: The Datacenter as a Computer, 3rd Edition
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=1320
Submitted by Bebe

The Datacenter as a Computer: Designing Warehouse-Scale Machines, Third Edition
Luiz André Barroso, Google LLC
Urs Hölzle, Google LLC
Parthasarathy Ranganathan, Google LLC

Paperback ISBN: 9781681734330
eBook ISBN: 9781681734347
Hardcover ISBN: 9781681734354

October 2018, 209 pages

This book describes warehouse-scale computers (WSCs), the computing platforms that power cloud computing and all the great web services we use every day. It discusses how these new systems treat the datacenter itself as one massive computer designed at warehouse scale, with hardware and software working in concert to deliver good levels of internet service performance. The book details the architecture of WSCs and covers the main factors influencing their design, operation, and cost structure, and the characteristics of their software base. Each chapter contains multiple real-world examples, including detailed case studies and previously unpublished details of the infrastructure used to power Google’s online services. Targeted at the architects and programmers of today’s WSCs, this book provides a great foundation for those looking to innovate in this fascinating and important area, but the material will also be broadly interesting to those who just want to understand the infrastructure powering the internet.

The third edition reflects four years of advancements since the previous edition and nearly doubles the number of pictures and figures. New topics range from additional workloads like video streaming, machine learning, and public cloud to specialized silicon accelerators, storage and network building blocks, and a revised discussion of data center power and cooling, and uptime. Further discussions of emerging trends and opportunities ensure that this revised edition will remain an essential resource for educators and professionals working on the next generation of WSCs.

Table of Contents:
Acknowlegements / Introduction / Workloads and Software Infrastructure / WSC Hardware Building Blocks / Data Center Basics: Building, Power, and Cooling / Energy and Power Efficiency / Modeling Costs / Dealing with Failures and Repairs / Closing Remarks / Bibliography / Author Biographies


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Boris Grot
SIGARCH Content Editor

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