This is the 1st October 2021 digest of SIGARCH Messages.

In This Issue

Call for Nominations: ASPLOS 2022 Artifact Evaluation Committee: Call for Self-Nominations
Submitted by Suvinay Subramanian

ASPLOS is the premier forum for interdisciplinary systems research, intersecting computer architecture, hardware and emerging technologies, programming languages and compilers, operating systems, and networking (

We are looking for motivated students, researchers and engineers to be part of the ASPLOS’22 artifact evaluation committee. This year, you can nominate yourself or your students/postdocs or fellow engineers. You can find more information about ASPLOS’22 artifact evaluation here:

The (self-)nomination form is available at:, and open until 22nd October.

As a committee member, your responsibility will be to review artifacts submitted for already accepted papers, e.g. by inspecting and running code and checking whether it allows to reproduce the main results of the paper. All evaluators will be acknowledged in the proceedings. ASPLOS AE’22 will use the HotCRP submission website to communicate asynchronously with artifact authors to allow to resolve issues quickly. We expect the main work to take place between December 8th 2021 and January 17th 2022.

Call for Participation: ICCD 2021
Submitted by Dominik Stoffel

Call for Participation
The 39th IEEE International Conference on Computer Design (ICCD)
October 24 – 27, 2021
Virtual Conference

We invite you to join us for the International Conference on Computer Design (ICCD), which will take place in virtual space on October 24-27, 2021. ICCD encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. Its multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering system and computer architecture, test, verification and security, design tools and methodologies, circuit design, and technology.

The conference is open to all for free but requires a no-cost registration here. Registration details are available on the conference website at

The conference starts with two tutorial sessions and a special session. The conference features two keynotes on ”Computer Design: Question Everything” by Professor Mikko Lipasti (University of Wisconsin) and “Silicon Lifecycle Management: Challenges & Opportunities” by Dr. Yervant Zorian (Chief Architect and Fellow, Synopsys), and a special panel on “Computing Security for today, tomorrow and beyond”. The technical program is organized in 15 sessions, including a best papers session. The Best Paper Award will be announced during the closing session. The conference program details are on the conference website at

We hope that you will be able to join us for this exciting event and that you will find it rewarding. We are grateful to our sponsors: IEEE, Synopsys, Intel, Avery Design Systems, supporters, and volunteers to help make this year’s conference a success.

Maciej Ciesielski and Resit Sendag
General Chairs

Sponsored by
The IEEE Computer Society, Synopsys, Intel, Avery Design Systems

Call for Participation: ESWEEK 2021
Submitted by Lars Bauer

Virtual Conference, October 8 – 15, 2021


  • ESWEEK 2021 attendee registration is only USD 10 for IEEE/ACM members and USD 20 for others, and a limited number of free registrations are available (via a fee waiver) for attendees with demonstrated need:
  • ESWEEK 2021 features a new Education Track, which comprises of classes aimed at background knowledge of various topics in “embedded learning”:
  • Technical program:

About Embedded Systems Week (ESWEEK)
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent and
connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), one symposium (NOCS), and several workshops and tutorials, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development.

The registration covers all events at ESWEEK including CASES, CODES+ISSS, EMSOFT, NOCS, keynote, panel, workshops, tutorials, and educational classes. There will be pre-recorded 2-3min lightning talks and papers available through Whova before the conference for participants to comment and post questions. During the conference, will be used as main platform to access all live and interactive content throughout the conference week. You will be able to interact with other attendees, network, attend all talks or join poster sessions in the ESWEEK 2021 Gather space.

More details:


  • September 24, 2021: Papers and pre-recorded lightning videos will be online. Questions about papers can be asked through the Whova platform.
  • October 8–15, 2021: ESWEEK Virtual Conference with live sessions and interactive posters through


  • Monday Keynote: “Advances in Neuromorphic Computing for Fast, Efficient, and Intelligent Processing”, by Mike Davies, Intel Labs
  • Tuesday Keynote: “Safe Learning in Robotics”, by Claire Tomlin, University of California at Berkeley
  • Wednesday Keynote: “Why is Machine Learning on Embedded Systems so Important?”, by Pete Warden, Google

Special Interest Days

Tuesday, October 12: “Special Industry Day” (

  • Two special sessions on collaborative industry-academia European research projects
  • An industry pitch and poster session

Wednesday, October 13: “Special Edge AI Day” (

  • Keynote “Why is Machine Learning on Embedded Systems so Important?”
  • Topic-related journal-track papers
  • Two special sessions on “Automated Edge AI Design” and “New Applications, Systems, and Challenges toward Designing New ‘Things’ at the Edge”
  • A panel about “Machine Learning on the Edge: How deep can we ’embed’ it into the Cloud-Edge continuum?”


  • CASES: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (
    Program Chairs: Umit Ogras, University of Wisconsin-Madison, US
    Preeti Panda, IIT Delhi, IN
  • CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis (
    Program Chairs: Jason Xue, City University of Hong Kong, HK
    Chengmo Yang, University of Delaware, US
  • EMSOFT: International Conference on Embedded Software (
    Program Chairs: Linh Thi Xuan Phan, University of Pennsylvania, US
    David Broman, KTH Royal Institute of Technology, SE


Tutorials (T) and Industrial Tutorials (IT) (

  • T1. QuantumFlow: A Co-Design Framework of Neural Network and Quantum Circuit towards Quantum Advantage
  • T2. Fog Computing for Industrial IoT
  • T3. Deterministic Reactive Programming for Cyber-Physical Systems Using Lingua Franca
  •  IT1. Scalable SoC Architecture for Edge AI Products, Intel
  • IT2. Integrating Compute Acceleration Into Embedded System Design Using Vitis, Xilinx
  • IT3. GPU Code Generation from MATLAB and Simulink, Mathworks Inc.

Workshops (

  • International Workshop on Memory and Storage Computing (MSC)
  • International Workshop on Rapid System Prototyping (RSP)
  • Trustworthy and Reliable AI accelerator desigN (TRAIN)

Education Track (

  • “Edge AI Systems”, Lin Wang, VU Amsterdam
  • “Memory-Centric Computing”, Onur Mutlu, ETH Zurich and CMU
  • “Learn to Drive (and Race!) Autonomous Vehicles”, Rahul Mangharam and Johannes Betz, University of Pennsylvania
  • “TinyML on Edge”, Vijay Janapa Reddi, Harvard University
  • “Binarized Neural Network Inference”, Nicolas J Fraser, Xilinx
  • “Research Reproducibility in Embedded Learning”, Romain Jacob, ETH Zurich
  • “Spiking Neural Networks”, Priyadarshini Panda, Yale
  • “Neural Network Accelerator Design”, Yu Wang, Tsinghua University
  • “Introduction to Neuromorphic Computing”, Helen Li, Duke University
  • “DNNs on FPGAs”, Jaesun Seo, Arizona State University
  • “Machine Learning-Driven Manycore Systems”, Biresh Kumar, Duke University, Jana Doppa, Washington State University

Organization (

Andreas Gerstlauer, University of Texas at Austin, US (General Chair)
Aviral Shrivastava, Arizona State University, US (Vice General Chair)
Tulika Mitra, National University of Singapore, SG (Past Chair)

Virtual Conference Chairs:
Sudeep Pasricha, Colorado Statue University, US (Chair)
Hoeseok Yang, Ajou University, KR (Co-Chair)

Call for Participation: NOCS 2021
Submitted by Kun-Chih (Jimmy) Chen

15th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2021)
October 14-15, 2021, Virtual Conference

About NOCS
The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications, and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation.

NOCS 2021 will be co-located with ESWEEK 2021.
Registration link:

Keynote Speakers
Title: Ultra-energy efficient, multi-terabit photonic connectivity for disaggregated computing
Speaker: Keren Bergman (Columbia University)

Title: AMD Chiplet Technologies and Implications on Interconnect Architectures
Speaker: Gabriel (Gabe) Loh (AMD Research)

Call for Participation: MICRO 2021
Submitted by Dimitrios Skarlatos

IEEE/ACM International Symposium on Microarchitecture (MICRO-54)
18-22 October 2021, Global Online Event broadcast from Athens

The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. The symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and this tradition continues at MICRO-54. In 2021, MICRO will be held as a global online event, broadcast from the host city of Athens, Greece.

MICRO-54 Technical Program

MICRO-54 Registration

The MICRO-54 global online edition this year offers very low registration fees to maximize global participation. Registration gives full access to all the symposium live events (all keynotes and all regular paper sessions), all live workshops/tutorials, and all recordings that are made as part of MICRO. Information about the fees structure, along with details on when materials will be made available to registered attendees, can be found on the registration information page

Early registration ends on Sunday, October 17, at 11:59 PM PDT.

Dimitris Gizopoulos, MICRO-54 General Chair
Aamer Jaleel and Jishen Zhao, MICRO-54 Program Co-Chairs

Call for Participation: PACT 2021
Submitted by Xiaoming Li

PACT 2021 – The 30th International Conference on Parallel Architectures and Compilation Techniques
Virtual Event:

We invite you to participate in the virtual PACT 2021 conference. It starts with a workshop on September 26 and continues with a tutorial on September 27 and the main conference during September 27th – 29th. We have an exciting program this year with one keynote talk (Saman Amarasinghe, MIT) and 25 papers. The details are on the PACT 2021 website ( where you can register for the conference. We look forward to your participation.

Sitting at the intersection of parallel architectures and compilers,the PACT conference series brings together researchers from architecture, compilers, execution environments, programming languages, and applications to present and discuss their latest research results.

Registration Site:

The 2nd International Workshop on Machine Learning for Software Hardware Co-Design (MLSH’21)


How to Parallelize Your Own Language Using OpenCilk Components

PACT 2021 Organizing Committee:

General Chair: Jaejin Lee, Seoul National University
Program Chair: Albert Cohen, Google
Finance chair: John Kim, KAIST
Workshops chair: Bernhard Egger, Seoul National University
Tutorials chair: Byeong Kil Lee, the University of Colorado at Colorado Springs
Publications chair: Jungwon Kim, Oak Ridge National Laboratory
Video conferencing chair: Hyungmin Cho, Sungkyunkwan University
Registration chair: Jaewoong Sim, Seoul National University
ACM SRC chair: Changhee Jung, Purdue University
Artifact Evaluation Committee Co-chairs:
   Bingsheng He, National University of Singapore
   Jidong Zhai, Tsinghua University
Publicity Co-chairs:
   Zehra Sura (America), Bloomberg
   Xiaoming Li (Asia), University of Delaware
   Rio Yokota (Asia), Tokyo Institute of Technology
   Christophe Dubach (Europe), McGill University
Submission chair: Denys Shabalin, Google
Web chair: Wookeun Jung, Seoul National University



Sponsored by the IEEE Computer Society, ACM and IFIP.

Call for Participation: SEED 2021
Submitted by Rujia Wang

The IEEE International Symposium on Secure and Private Execution Environment Design (SEED)
September 20-21, 2021 – Virtual
Registration Link:

The IEEE International Symposium on Secure and Private Execution Environment Design (SEED) is a forum which brings together researchers from the computer architecture and computer security communities into one venue that focuses on the design of architectural and system primitives which provide secure and private execution environments for applications, containers, or virtual machines.

Keynote Speakers


Abstract: This talk will explore what we think of as analog side channels as being a form of sensing, and also argue that sensing using physical side-effects is present in both nature and various sciences outside of computing. The talk will then explore the lessons that can be learned from sensing in nature, medicine, and other scientific disciplines. Finally, the talk will discuss current trends in analog side channel attacks and mitigations and, just as importantly, in current research and the future of non-adversarial uses of side channels, with examples from our work on detection of anomalies in software execution and in the hardware itself, verifying correct operation of software/hardware systems, accurate attribution of execution time to program code and specific hardware events, etc.

Bio: Milos Prvulovic is a Professor and Associate School Chair in the School of Computer Science at Georgia Tech. His research focuses on hardware and software support for program monitoring, debugging, and security. His research on understanding the relationship between program execution and the resulting “side-channel” signals is has been funded by DARPA, NSF, OFOSR, and ONR, and has led to numerous publications, and a number of best paper awards and nominations, in top-tier venues across several research areas. Dr. Prvulovic is a senior member of Association of Computing Machinery (ACM) and Institute of Electrical and Electronics Engineers (IEEE), and has served as the chair of the IEEE Technical Committee on Microprogramming and Microarchitecture (TCuArch) in 2016.

Call for Papers: SYSTOR 22
Submitted by Arik Rinberg

15th ACM International Systems and Storage Conference
June 13 – 15, 2022, Haifa, Israel

The ACM International Systems and Storage Conference (SYSTOR) is an international forum for interaction across the systems research community. The program includes innovative, peer-reviewed research papers in the broad area of systems and storage, as well as distinguished keynote lecturers, a poster session, and social events. ACM SYSTOR is designed to appeal to academic and industrial researchers and practitioners, welcoming both students and seasoned professionals.

SYSTOR welcomes academic and industrial papers in systems and storage, broadly construed. SYSTOR encourages submissions that describe results from experimental system prototypes, as well as experience papers describing practical deployments, and valuable lessons learned from them. Topics of interest include, but are not limited to:

  • Big Data infrastructure
  • Cloud, edge, datacenter, and distributed systems
  • Deployment, usage, and experience
  • Embedded and real-time systems
  • Fault tolerance, reliability, and availability
  • File and storage systems
  • Networked, mobile, wireless, peer-to-peer, and sensor systems
  • Operating systems, computer architecture, and their interactions
  • Performance evaluation and workload characterization
  • Runtime systems and compiler/programming-language support
  • System security and trust
  • System design or adaptation for emerging storage technologies
  • Virtualization and containers

Full Papers track – original research, at most 10 pages excluding references
Short Papers Track – original research, at most 5 pages excluding references
Highlight Papers Track – papers accepted at top-tier conferences
Posters with Extended Abstract Track – original work presented as poster accompanied by the extended abstract

Important Dates

Full and Short Papers Track
Paper Submission              Tuesday, March 1, 2022
Acceptance Notification      Thursday, April 21, 2022
Camera-ready                     Monday, May 9, 202

Highlight Papers Track
Extended Abstract Submission  Friday, April 1, 2022
Acceptance Notification             Saturday, April 30, 202

Posters with Extended Abstract Track
Poster & Abstract Submission  Monday, March 14, 2022
Acceptance Notification            Thursday, April 14, 2022
Camera-ready                           Monday, May 9, 2022
Conference                               June 13-15, 2022

Program Chairs
Frank Bellosa (KIT, Germany)
Moshe (Mickey) Gabel (University of Toronto, Canada)

Program Committee
Abutalib Aghayev (The Pennsylvania State University)
Adam Morrison (Tel Aviv University)
Angela Demke Brown (University of Toronto)
Arpan Gujarati (University of British Columbia)
Aviad Zuck
Chia-Lin Yang (National Taiwan University)
Christian Wressnegger (Karlsruhe Institute of Technology (KIT))
Daniel Lohmann (Leibniz Universität Hannover)
Dejan Kostic (KTH Royal Institute of Technology)
Eran Gilad (Yahoo Reserach)
Fabio Pierazzi (King’s College London)
Gala Yadgar (Technion)
Geoff Kuenning (Harvey Mudd College)
Haris Volos (University of Cyprus)
Kento Sato (RIKEN)
Lluís Vilanova (Imperial College London)
Lukas Rupprecht (IBM Research – Almaden)
Nadav Amit (VMWare Research)
Orna Agmon Ben-Yehuda (CRI, University of Haifa)
Rüdiger Kapitza (TU Braunschweig)
Sam H. Noh (UNIST (Ulsan National Institute of Science and Technology))
Shadi A. Noghabi (Microsoft Research)
Shir Landau Feibish (The Open University of Israel)
Thanumalayan Sankaranarayana Pillai (Google)
Tianyin Xu (University of Illinois Urbana-Champaign (UIUC))
Youjip Won (Korea Advanced Institute of Science and Technology (KAIST))
Young-ri Choi (Ulsan National Institute of Science and Technology (UNIST))
Youngjae Kim (Sogang University)
Youyou Lu (Tsinghua University)
Yu Hua (Huazhong University of Science and Technology

General Chair
Michal Malka (IBM Research – Haifa, Israel)
Hillel Kolodner (IBM Research – Haifa, Israel)

Poster Chair
Dolev Adas (IBM Research – Haifa, Israel)

Publication Chair
Swati Goswami (University of British Columbia, Canada

Publicity Chair
Arik Rinberg (Technion, Israel

Steering Committee Head
Dalit Naor (The Academic College of Tel Aviv-Yaffo, Israel

Steering Committee
Michael Factor (IBM Research – Haifa, Israel)
Ethan Miller (University of California Santa Cruz, USA)
Liuba Shrira (Brandeis University, USA)
Dan Tsafrir (Technion, Israel & VMware Research Group, USA)
Erez Zadok (Stony Brook University, USA)

Call for Papers: FCCM 2022

Submitted by Callie Hao

The 30th IEEE International Symposium on Field-Programmable Custom Computing Machines
May 15th – May 18th, 2022 | New York
Feel free to follow FCCM Linkedin Page and join the FCCM Linkedin Group!

The IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware.

FCCM 2022 will be a hybrid event. There will be a live face-to-face conference at NYC and a virtual program. Please refer to the FCCM website for details. At least one author will be required to register and attend the conference. Failure to present at the conference may result in the removal of the submission from IEEE Xplore.

Submissions are solicited on the following topics related to Field-Programmable Custom Computing Machines (FCCMs) including, but not limited to:


  • Novel reconfigurable architectures, including overlay architectures
  • Architectures for high performance and/or low power computing
  • Security assessment and enhancements for reconfigurable computing
  • Specialized memory systems including volatile, non-volatile, and hybrid memory subsystems
  • Emerging technologies with in-field reconfiguration abilities
  • Clusters, data centers, or large systems of reconfigurable devices
  • Heterogeneous programmable architectures

Abstractions, Programming Models, and Tools

  • Abstractions, programming models, interfaces, and runtimes, including virtualization
  • New languages and design frameworks for spatial or heterogeneous applications
  • High-level synthesis and designer productivity in general
  • Software-Defined-systems (e.g. radio, networks, frameworks for new domains)
  • Customizable soft processors systems


  • Run-time management of reconfigurable hardware
  • System resilience/fault tolerance for reconfigurable hardware
  • Evolvable, adaptable, or autonomous reconfigurable computing systems
  • Security assessment and enhancement of run-time reconfiguration


  • Data center or cluster with reconfigurable applications
  • New uses of run-time reconfiguration in applications-specific systems
  • Applications that utilize reconfigurable technology for performance and efficiency, and particularly submissions that make comparisons with other highly parallel architectures such as GPUs or DSPs
  • Novel use of state-of-the-art commercial FPGAs

Submission Website:

Important Dates:

All deadlines apply to the Anywhere on Earth (UTC – 12) timezone
Abstracts Due (All Papers)                              January 3, 2022
Submissions Due (All Papers)                         January 10, 2022
Workshop Proposals Due                                February 13, 2022
Rebuttal Period                                                February 24 – 28, 2022
Notification of Acceptance (All Papers)            March 21, 2022
Demo Night Submissions                                 April 15, 2022
Notification of Acceptance (Demo Night)         April 18, 2022
Camera-Ready Submission                             April 11, 2022
Early Registration Deadline                             April 19, 2022
Conference                                                      May 15 – May 18, 2021

Organizing Committee:

General Chair                                     Zhiru Zhang (Cornell)
Program Chair                                    Eriko Nurvitadhi (Intel)
Finance Chair                                     Andrew Schmidt (USC ISI)
Hybridization Chair                             Ron Sass (UNCC)
Sponsorship Chairs                            Lana Josipovic (ETH), Guojie Luo (PKU)
Publications Chair                              Gabriel Weisz (Microsoft)
Workshops Chair                                Yun (Eric) Liang (PKU)
Publicity and Website Chair               Cong (Callie) Hao (Georgia Tech)
Expo and Demo-Night Chair              Grace Zgheib (Intel)
Panel Chair                                         Zhenman Fang (SFU)
Local Arrangement Chairs                 Mohamed Abdelfattah (Cornell Tech), Debjit Pal (Cornell)

Paper Formats:

Long papers are limited to 8 pages (excluding references). Short papers are limited to 4 pages (excluding references). Authors are encouraged to submit preliminary work as a short paper. This category is intended for new projects and early results or work that can be concisely presented in the 4-page budget. Submissions accepted as posters will have a one-page extended abstract.

Page restrictions for all formats exclude references, which may use additional pages. Submissions violating the formatting requirements may be automatically rejected. Do not submit the same work as more than one of the formats.

Accepted papers will have the same page lengths as initial submissions. Short papers will have short oral presentations and long papers may have long or short presentations based on committee decisions on time required to present the material.

All submissions should be written in English. An online submission link will be available on the FCCM website. Papers must conform to the US letter-sized IEEE conference proceedings format to be reviewed and published. A conformant LaTeX template is available here and a Microsoft Word template is available here. Overleaf users can find the LaTeX template here.

Review Process:

FCCM uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations. Authors are encouraged to cite their own work but must not implicitly identify themselves. For example, references that clearly identify the authors (“We build on our previous work…”) should be written as “This work builds on XYZ [citation]”. Do not put a “deleted for double-blind” entry in the reference section.

In the case of widely-available Open Source software, authors should cite the website(s) but not claim to own them. Authors should also remember to mask grant numbers and other government markings during the review process. Note that there are resources to blind open-source repositories for review such as:  Papers that attempt to identify authors or leverage prior work or institutional support for a competitive advantage in the peer review process will not be considered. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged; just because a paper can be unblinded by active search will not undermine the spirit of the double-blind review. Artifacts, including open-source designs and tools are encouraged; if there are questions about how to handle blind-review, contact the program chair.

FCCM 2021 includes a rebuttal phase. Specific questions from reviewers will be made available by February 24, 2022. Authors have the option to provide an up to 500-word response by February 28, 2022. Reviewers will consider the responses during final paper deliberations.

Simultaneous Submissions:

Papers must not be simultaneously under review or waiting to appear at another conference or in a journal, and must not be essentially the same as any paper that has been previously published. If a paper contains text or technical content that is similar to a previously published or submitted paper, that other paper should be cited in the FCCM submission, and the differences should be made clear.

Reviewer Conflicts

Authors must register any program-committee conflicts as they submit their paper. Conflicts can include those that have co-authored a paper in the past 3 years, those that have current or shared institutional affiliation within the past year, or other situations in which the relationship would prevent a reviewer from being objective. Note that if an undeclared conflict is discovered, or a conflict is declared in an attempt to “game” the review process, the submission may be rejected. If you believe you may have a conflict with the program chair, please contact the program chair well in advance of the submission deadline.

Best Paper Award and a Special Section for the Best FCCM 2022 Papers in ACM TRETS:

FCCM 2022 will continue the tradition of having a best long and short paper award. We will also invite the authors of the best papers to extend their work to be considered for publication in a special section of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS) for FCCM 2022.

Special Note to Authors:

Across all topics (and especially for application papers) successful manuscripts will include sufficient details to reproduce the results presented (e.g., full part numbers, software versions). Application papers should not just be an implementation of an application on an FPGA, but should show how reconfigurable technology is leveraged by the application, and should ideally contain insights and lessons that can be carried forward into future designs.  Additional suggestions and guidelines are available on See the ACM/TCFPGA Hall-of-Fame ( and the set of previous FCCM Best Paper winners ( for outstanding examples of FCCM papers.


Questions about this call, submissions, and potential submissions should be directed to the program chair, Eriko Nurvitadhi.

IEEE Privacy Policy

Call for Papers: ISCA 2022
Submitted by Zehra Sura

The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. In 2022, the 49th edition of ISCA will be held in New York City, New York, USA.

Important Dates:
Abstract Deadline: November 16, 2021 at 11:59 PM AoE
Full Paper Deadline: November 23, 2021 at 11:59 PM AoE
Rebuttal/Revision Period: February 7–17, 2022
Author Notification: March 2, 2022

Papers are solicited on a broad range of topics, including (but not limited to):
Processor, memory, and storage systems architecture
Multiprocessor systems
Datacenter-scale computing
IoT, mobile, and embedded architecture
Interconnection network, router, and network interface architecture
Accelerator-based, application-specific, and reconfigurable architecture
Architectural support for programming languages or software development
Architectural support for interfacing with accelerators
Architectural support for security, virtual memory, and virtualization
Instruction-, thread-, and data-level parallelism
Dependable processor and system architecture
Architecture for emerging technologies and applications, including machine learning, novel memory technologies, quantum computing, etc.
Effects of circuits or technology on architecture
Architecture modeling and simulation methodologies
Evaluation and measurement of real computing systems

Industry Track:
This year, ISCA has an industry track for submissions that provide retrospective evaluations of real working products, or of planned products that were cancelled but present interesting insights or lessons learned. Note that the industry track is not meant for student intern projects, and any such papers will be rejected without consideration. Industry track papers are due in January 2022.

General Chairs: Valentina Salapura (AMD) and Mohamed Zahran (NYU)
Program Chair: Fred Chong (UChicago)
Program Vice-Chair: Lingjia Tang (Michigan)

Call for Papers: MLSys 2022
Submitted by Carole-Jean Wu

The MLSys research community is rapidly growing, both in academia and industry. This area historically has not been particularly well addressed by existing Machine Learning or Systems focused conferences. To bridge this gap, we have the MLSys conference for research spanning ML and systems. The goal is to make a home for exceptional research by creating a venue to showcase the work that occurs at the intersection of systems and machine learning and a community with expertise in both areas to evaluate the work.

The MLSys conference aims to elicit new connections amongst these fields, including identifying best practices and design principles for learning systems, as well as developing novel learning methods and theory tailored to practical machine learning workflows.

Important Dates:

  • Paper submission deadline: Oct 08, 2021
  • Author rebuttal period: Dec 08 to Dec 15, 2021
  • Decision notification: Jan 14, 2022
  • Camera ready: Mar 04, 2022
  • Conference: Apr 11 to Apr 14, 2022

Topics: Papers are solicited on a broad range of topics, including (but not limited to):

  • Efficient model training, inference, and serving
  • Distributed and parallel learning algorithms
  • Privacy and security for ML applications
  • Testing, debugging, and monitoring of ML applications
  • Fairness, interpretability and explainability for ML applications
  • Data preparation, feature selection, and feature extraction
  • ML programming models and abstractions
  • ML compilers and runtime
  • Programming languages for machine learning
  • Visualization of data, models, and predictions
  • Specialized hardware for machine learning
  • Hardware-efficient ML methods
  • Machine Learning for Systems
  • Systems for Machine Learning

General Chair: Diana Marculescu
Program Chairs: Yuejie Chi and Carole-Jean Wu

Call for Papers: ACSMD Workshop@MICRO 2021
Submitted by Hyoukjun Kwon

Half-day virtual workshop at MICRO 2021
Friday, October 22, 2021
10:00 am – 1:00 pm (EDT)

Many platforms, from data centers to edge devices, deploy multiple DNNs to provide high-quality results for diverse applications in the domains of computer vision, speech, language, and so on. In addition, because some applications rely on multi-DNN pipelines performing different tasks, DNN workloads are becoming more diverse and heterogeneous. Supporting inferences of such diverse and heterogeneous DNN workloads with high energy efficiency and low latency is becoming a great challenge since the major approach to achieve inference efficiency is to specialize architecture, compiler, and systems for a small set of target DNN models within the same domain. In addition to such performance and efficiency, multimodel DNN workloads introduce new challenges such as security and privacy. Therefore, this workshop will explore innovations to efficiently and safely support multi-model DNN workloads from each of the three areas: architecture, compiler, and system. We solicit papers in the research fields listed below.

Topics of Interest

  • Heterogeneous hardware architectures to concurrent execution of multiple DNN models
  • Reconfigurable accelerator architectures (CGRA-style, FPGA, etc.) to adapt to different DNN models
  • Compiler runtime for multi-DNN workloads on heterogeneous or reconfigurable hardware architectures
  • End-to-end compilation flow and optimization techniques targeting multi-DNN workloads on heterogeneous or reconfigurable hardware architectures
  • Design automation tools for heterogeneous or reconfigurable hardware architectures targeting multi-DNN workloads
  • Techniques in each of architecture, compiler, and system domains to enhance security and privacy when a platform runs a multi-model DNN workload in multi-tenant style

Author Information

  • Submission site (link)
  • Template: Please use the MICRO 2021 template for submissions
  • Page limit: 4 pages (not including references)


  • Tushar Krishna (Georgia Institute of Technology)
  • Liangzhen Lai (Facebook)
  • Yu-Hsin Chen (Facebook)
  • Hyoukjun Kwon (Facebook)

Important Dates

  • Submission deadline: Sep 25, 2021 (AOE)
  • Notification: October 8, 2021 (AOE)
  • Camera-ready: October 14, 2021 (AOE)
  • Workshop date: October 22, 2021 (10:00 am – 1:00 pm EDT)

Program Committee

  • Hsien-Hsin Sean Lee (Facebook)
  • Jangwoo Kim (SNU)
  • Zhiru Zhang (Cornell)
  • Amir Yazdanbakhsh (Google)
  • Minsoo Rhu (KAIST)
  • Jongse Park (KAIST)
  • Hardik Sharma (Google)
  • Jie Wang (AWS)
  • Joel Hestness (Cerebras Systems)
  • Divya Mahajan (Microsoft Research)

For further information, please email Hyoukjun Kwon (

Call for Papers: IEEE Micro Top Picks 2022
Submitted by Radu Teodorescu

IEEE Micro will publish its annual “Top Picks from the Computer Architecture Conferences” issue in May/June 2022. This issue collects some of the most significant research papers in computer architecture based on novelty and potential for long-term impact. Any computer architecture paper published in the top conferences of 2021 (including MICRO-54) is eligible. Each Top Picks submission must be based on a single paper, not a combination of multiple papers. The Top Picks Selection Committee will recognize those significant and insightful papers that have the potential to influence the work of computer architects for years to come.

Important Dates
Submission website opens: October 1, 2021
Submission deadline: October 25, 2021
Author notification: January 11, 2022
Revised papers due: February 10, 2022
Publication: May/June 2022

Submission Guidelines
To simplify reviewing, there is a mandatory format for submissions. Please upload the following two documents combined into a single PDF:

  1. A three-page, two-column document using 10-point type. The first two pages should summarize the paper. The third page should argue for the potential of the work to have long-term impact, clearly articulating why and how it will influence other researchers and/or industry. On the third page, please also include what the citation of the paper would be if it won a Test of Time award in 10 years.
  2. The final version of the original conference paper.

Submissions that do not follow this format will not be reviewed. The first document should contain the names of the authors with a footnote that includes the title of the original conference paper, the full name of the conference, and date of publication. Please submit here:

Accepted Paper Guidelines
Authors of accepted papers will receive further instructions on how to prepare the final papers to conform to IEEE Micro‘s guidelines. Final papers should not exceed 5,000 words including references, with each average-size figure counting as 250 words toward this limit. Papers must have at least 30 percent new content. Final papers will be reviewed again before publication and edited for structure, style, clarity, and readability. February 10 is a hard deadline for final papers; papers received after that deadline will not be published.

Guest Editors (and Selection Committee Co-Chairs)
Sudhanva Gurumurthi, AMD, USA
Radu Teodorescu, The Ohio State University, USA

Contact the guest editors at

Call for Papers: Eye Tracking Techniques, Applications, and Challenges
Submitted by Fancy Chai

Eye tracking technology is becoming more widespread nowadays, thanks to the recent availability of cheap commercial devices (such as gaze detection sensors). At the same time, novel techniques are being continuously pursued to improve gaze detection precision, and new ways to fully exploit the potential of eye data are also continuously being explored.

The number of potential applications of eye tracking is also growing constantly, including health care (both medical diagnosing and treatment), Human-Computer Interaction, user behavior understanding, psychology, biometric identification, education, and many more.

The purpose of this Special Issue is to present the recent advancements in eye tracking research, including advancements in eye signal acquisition using different optical and nonoptical sensors, and different ways of eye movement signal processing. Any research that exploits eye tracking sensors for various purposes, be it Human-Computer Interaction, user behavior understanding, biometrics, or others, is also welcome.

The Special Issue will include extended versions of selected papers from the ETTAC 2020 Workshop, which was the first workshop to be held on eye tracking techniques, applications, and challenges. It was organized during the 25th International Conference on Pattern Recognition (ICPR 2020). However, we also solicit other contributions from researchers involved and interested in this research area.

Call for Workshops/Tutorials: CGO 2022
Submitted by Dongyoon Lee

CGO 2022 will host workshops and tutorials on Saturday and Sunday (2/12 – 2/13/2022) before the main conference. This is your event’s chance to take advantage of the interdisciplinary audience of CGO, HPCA, and PPoPP.


Email the proposal as a PDF file (1-2 pages) to the CGO 2022 Workshops and Tutorials Chair, Taewook Oh (, with the email subject containing “[CGO’2022wt]”.

Proposal submission deadline: Friday, October 29, 2021 (AoE)
Final notification of acceptance: Sunday, November 14, 2021
Workshop/tutorial dates: February 12-13, 2022

Contents for all proposals

  • Title: (name of workshop or tutorial)
  • Type: (workshop or tutorial)
  • Duration: (1/2 day or full day or two days)
  • Expected number of participants:
  • Advertisement: how do you plan to solicit participation to your workshop/tutorial (e.g., via social media, workshop/tutorial website, mailing lists etc.)
  • Information on past workshop/tutorials: (number of attendees/submissions) on the same topic held with this or other conferences (if any).

Additional contents of a Workshop Proposal

  • Sample call for papers, including workshop title, scope, format and the main topics of the workshop.
  • Invited or keynote speakers (if any).
  • Panel discussion (if any).
  • Organizers’ bios and affiliation.
  • A tentative list of PC members.
  • Whether the selected papers will be published (and, if so, where and how). Please note that workshops that wish to publish accepted submissions in the ACM Digital Library will require approval by the SIGPLAN executive committee.

Additional contents of a Tutorial Proposal

  • An outline of tutorial content and objectives.
  • Prerequisite knowledge.
  • Special requirements (if any).
  • A biography of the tutorial organizers and relevant experiences on the topic.

Call for Posters: Career Workshop for Inclusion and Diversity in Computer Architecture at MICRO-54
Submitted by Boris Grot

The MICRO Career Workshop brings together diverse members of the Computer Architecture community at different levels in academia, industry, research, government and students to promote the recruitment, retention and progression of women and under-represented groups with research interests in computer architecture. The workshop is the longest running diversity focused workshop in the computer architecture community (previously known as CWWMCA).

The workshop includes a student research poster session. Student posters are solicited for research related to any aspect of computer architecture. All researchers in the computer architecture fields are welcome to submit their work for presentation at this workshop.

Accepted posters will have the presenter’s MICRO conference registration fee covered.

Submission Guidelines

Each poster abstract will be reviewed by members of the community. Posters will not be published and hence can be under submission for other conferences or workshops. Each submission should be formatted as an extended abstract, describing the research to be presented in the poster. The length of the extended abstract should be at most TWO single-column pages (formatted into the US letter size of 8.5 x 11 inches with fonts no smaller than 10 point size), including all figures and references.

Submission site:

Abstract Submission Deadline: September 20th 2021 Septemeber 27th 2021 (EXTENDED)

Author Notification: October 4th 2021

Workshop Date: October 22nd 2021


All questions about submissions should be emailed to

Samsung Launches Open Innovation Contest for AXDIMM Technology
Submitted by Samsung Memory

If you have an idea on where the future of near-memory processing should be headed, Samsung Memory wants to hear from you.

On September 30th, the South Korean memory giant kicked off its first-ever Open Innovation Contest for AXDIMM Technology. Held to foster collaboration between industry and academia, the contest invites professors and students from universities in South Korea and the U.S. to propose innovative applications for one of Samsung Memory’s key areas of research focus: AXDIMM.

Short for “Acceleration DIMM,” AXDIMM is a powerful yet flexible near-memory acceleration platform. It allows researchers and developers to implement various functions in memory modules, and can be used to accelerate memory-intensive applications such as deep learning recommendation and genomic computation.

The goal of the contest is to identify ways that AXDIMM could be used to create future value. Students who are interested in joining the competition should form teams of up to five people, including a professor, and submit their proposals by November 15. Five finalists will be selected on December 15, and will be provided with a virtual AXDIMM system to perform R&D on their project until July 15, 2022. Proposals will be evaluated in each stage based on criteria including their level of innovation, the creativity of their use of AXDIMM, and the feasibility of their hardware and software architectures.

Each of the five finalists will receive a one-time R&D incentive of $10,000. Winning teams, announced on August 15, 2022, will receive $50,000 for first place, $30,000 for second, and $10,000 for third.

More information, including submission instructions, can be found on the contest’s webpage.

Webinar on ACM member grades and awards
Submitted by Boris Grot

Webinar “Getting Recognized by ACM Awards and Honors”
Organized by the ACM Europe Council through the ACM Europe RAISE Working Group
October 1, 2021, at 3pm CET / 9am EDT

Don’t miss this unique opportunity to get informed about the ACM member grades and awards and communicate directly with members of the ACM Awards and Member Grades Committees, getting better informed on how to prepare a successful nomination, providing feedback on the reasons that Europeans are willing to participate or not in these programmes, and helping us better understand the kind of support you find necessary in order to become more actively involved in these ACM programmes.

The webinar will take place, online. It will feature an open discussion with Gabriele Kotsis, the ACM President, and Panagiota Fatourou, the ACM Europe Council Chair, as well as a panel comprised by the following members of the ACM Awards and Member Grades Committees:

  • Jim Larus, Chair of ACM Fellows Committee
  • Roy Levin, Co-Chair of ACM Awards Committee
  • John R. White, Co-Chair of ACM Awards Committee
  • Nuria Oliver, Member of ACM Fellows Committee
  • Geraldine Fitzpatrick, Member of ACM Distinguished Member Committee
  • Anastasia Ailamaki, Chair of ACM Europe Fellows Working Group

Registration is free but required. To register (and see the programme) follow the link:
Register now! Your opinion does matter. We are looking forward to your participation.

Visioning Workshops in Computer Architecture
Submitted by Boris Grot

Next proposal deadline: October 7, 2021

SIGARCH invites proposals for visioning workshops that will catalyze and enable innovative research within computer architecture, and between computer architecture and other areas.

Successful activities will articulate new research visions, galvanize community interest in those visions, mobilize support for those visions from the computer architecture research community, government leaders, and funding agencies, and encourage broader segments of society to participate in computer architecture research and education.

SIGARCH encourages creative ideas from all segments of the computer architecture research community and beyond, on topics ranging from the formulation of new basic research areas and technologies to the use of new or existing research ideas and technologies to address important scientific or societal challenges.

Workshop organizers are expected to bring together a group of scientists and practitioners in the area of interest, and to formulate a program that encourages new ideas, innovative thinking, and broad discussion. Workshops will typically range from 20 to 100 participants. It is important that the participants cover a broad spectrum to ensure full coverage of the area, both in terms of content area representation and employment (academia, industry, research labs, and policy and funding organizations).

Workshops are expected to have a tangible output – for example, a whitepaper (or set thereof) or a workshop report. Workshop outcomes should be targeted to multiple audiences (the research community, science policy groups or funding agencies, the general public), and the deliverables should be tailored for easy dissemination. SIGARCH will help to support both workshop organization and the subsequent generation and communication of the output.

Note that the focus is to organize workshops that create visions for broad research agendas as opposed to seeking future funding for the participants.

Additional information, including advice on preparing a proposal, can be found at

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Samira Khan
SIGARCH Content Editor