Call for Papers: ICS 2025
https://hpcrl.github.io/ICS2025-webpage/call-for/call-for-papers.html
Submitted by Wenqian Dong
The 39th ACM International Conference on Supercomputing (ICS 2025)
Salt Lake City, Utah, USA
June 9th-11th, 2025
https://hpcrl.github.io/ICS2025-webpage/.
Papers are solicited on all aspects of the architecture, software, and applications of high-performance computing systems of all scales (from chips to supercomputing systems), including but not limited to:
- Processor, accelerator, memory, storage, interconnect and system architectures, including architectures based on future and emerging hardware (e.g. quantum, superconducting, photonic, neuromorphic).
- Programming languages, paradigms and execution models, including domain-specific languages and scientific problem-solving software environments.
- Compilers, runtime systems and system software, including optimization and support for hardware resources and energy management.
- High-performance algorithms and applications including machine learning and large-scale data analytics, as well as the implementation and deployment of algorithms and applications on large-scale systems.
- Tools for measurement, modeling, analysis and visualization of performance, energy, or other quantitative properties of high-performance computing systems.
Submission site: https://ics25.hotcrp.com/
Important dates
Abstract submission: January 13th, 2025
Paper submission: January 16th, 2025
Rebuttal period: February 19th to February 21st, 2025
Author notification: March 14th, 2025
Camera-ready: April 14th, 2025
Call for Papers: LAD 2025 – International Conference on LLM-Aided Design
https://iclad.ai/
Submitted by Jeff Goeders
1st IEEE International Conference on LLM-Aided Design – LAD 2025
June 26-27 2025
Stanford, CA
https://iclad.ai/
This new international conference will focus on how to use Large Language Models (LLMs) to help design circuits, software, and computing systems with improved quality, productivity, robustness, and cost. Building on the success of last year’s LAD workshop, we’re excited to announce the first-ever international LAD conference! The conference will be a timely venue that will host leading researchers and thought leaders in this fast-growing area, providing a forum for researchers and practitioners to present their latest results, contribute open-source models, datasets, and tool flows, and offer benchmarking, testing, and validation methods and solutions.
The main theme of LAD this year will revolve around agentic optimization and scaling inference-time methods, but we welcome a broad range of topics on new methodologies, tools, datasets, and benchmarks pertaining to:
- Agentic workflows for design automation and optimization
- Inference-time techniques for design
- LLM-aided HW/SW design, code generation, and test plan generation
- System-level design methodology development with LLMs
- Finetuning of large foundation models for specialization in design automation
- New datasets and benchmarks of relevance to LLM-aided design
- Evaluation and verification of LLM-aided designs
- LLM-aided design for software development, IT automation, site reliability, and regulatory compliance.
- LLMs for EDA, including RTL, HLS, physical design, and EDA scripting
- LLMs for reasoning and logic used in design process
- Computational efficiency of LLM-aided design tools
- Data science and data analytics for LLM-aided design
- Security of LLM-generated designs
- Privacy, copyright, and other regulatory concerns around LLM-aided design
- LLM-aided bug-fixing
- LLM-aided design for various application domains, such as 3D manufacturing, material discovery, sustainability, etc.
SUBMISSION INSTRUCTION
The conference invites up to 6-page regular papers in the IEEE Conference format (https://www.ieee.org/conferences/publishing/templates.html). Page limits do not include references. Papers should be anonymized for double-blind peer review. We encourage papers with a commitment to open and reproducible research, including datasets and methods. Papers with open-source implementations will be highlighted at the conference. All papers will be published on IEEEXplore. Papers can be submitted via OpenReview (https://openreview.net/group?id=IEEE.org/LAD/2025) by Friday, Feb. 28th, 2025 AoE.
See the conference website (https://iclad.ai/) for more details.
DATASETS AND BENCHMARKS PAPERS
LAD’25 welcomes papers describing new Datasets and Benchmarks of relevance to the LLM-Aided Design community. Papers describing new datasets and benchmarks must follow the exact same rules and procedures as regular (up to) 6-page papers; they will be peer reviewed; and accepted papers will be published in the proceedings. Datasets and Benchmarks papers must include an explicit commitment to releasing all artifacts publicly if accepted. The commitment should be added to the Conclusion section of the paper.
IMPORTANT DATES
Full paper submission: Feb 28th, 2025, AoE
Notification of acceptance: May 8th, 2025, AoE
Camera ready paper due: May 22nd, 2025, AoE
ORGANIZING COMMITTEE
General Chairs: Siddharth Garg (NYU), Haoxing (Mark) Ren (NVidia)
Program Chairs: Azalia Mirhosseini (Stanford), Yong Liu (Cadence), JV Rajendran (TAMU)
Finance Chair: Callie Hao (GaTech)
Publicity Chair: Jeff Goeders (BYU)
Local Chair: Ehsan Degan (IBM)
Webmaster: Kaiwen Cao (UIUC)
Call for Papers: ISPASS 2025
https://ispass.org
Submitted by Stijn Eyerman
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2025)
May 11-13, 2025
Ghent, Belgium
ISPASS provides a forum for sharing advanced academic and industrial research focused on performance analysis in the design of computer systems and software.
Authors are invited to submit previously unpublished work for possible presentation at the conference.
Important Dates
- Abstract submission deadline: December 9 2024, 11:59:59 PM, Anywhere on Earth
- Full submission deadline December 16 2024, 11:59:59 PM, Anywhere on Earth
- Rebuttal: February 10-14, 2025
- Paper notification: March, 3 2025
More information at https://ispass.org.
Call for Papers: ARCS 2025: Mastering novel HPC chip architectures
https://arcs-conference.org/home
Submitted by Mathias Pacher
The ARCS conferences series has over 37 years of tradition reporting
leading edge research in computer architecture and operating systems.
New chips for high-performance computing (HPC) are being developed in and outside Europe
(e.g. ARM processors for HPC, RISC-V chips, special purpose ASIC designs, etc.) and even
disruptive technologies such as QPU accelerators are being connected to HPC systems.
New chips are designed either as general purpose devices with a wide user portfolio in mind,
or target the needs of specific applications (e.g. machine learning pipelines or deep learning
workloads, mobile or embedded systems). Accordingly, they might rely on well established
architectural approaches (CPU-like, vector-extensions), or bring completely new disruptive
ideas, always with the aim of limiting energy consumption. When these are integrated in HPC systems,
the overall system design becomes more and more heterogeneous.
These increasingly complex architectures require optimizations in application code to
exploit the full performance potential. There are standard optimization strategies
that can be implemented specifically for certain architectures, and there may also
be optimization rules that are totally specific to an accelerator or a hybrid
processor-accelerator architecture. Porting HPC code to new architectures is
an important challenge: it is desirable to achieve performance without having
to redesign the whole code, or at least to be able to follow standard optimization rules.
The ARCS’25 conference welcomes all contributions on hardware architectures, as well as
their programming models, software stacks (operating systems, compilers…), their insertion
into computing systems, and the challenges to port optimized code.
In addition to the main conference, ARCS will host:
-A special track on Organic Computing.
-A special track on Dependability and Fault Tolerance.
-A PhD forum to present the work of young doctoral students (10 page papers).
-A Group forum for new professors, individual researchers, and consortia to present their research group’s project (5 page papers).
The proceedings of ARCS 2025 will be published in the Springer Lecture Notes on Computer Science
(LNCS) series. A best paper will be elected by the Program Committee, and
a publicum’s favourite presentation award will be chosen by the audience.
Both awards will be given at the conference.
Call for Papers: ISFPGA 2025
https://www.isfpga.org/
Submitted by Aman Arora
33rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Feb 27 – Mar 1, 2025
https://isfpga.org
The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2025, the 33rd edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.
Paper Submissions (with and without Artifacts)
We solicit research papers related to the following areas:
- FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
- FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory or nano-scale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability.
- CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
- High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
- FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
- Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.
- AI/ML for and on FPGAs: Architectures and implementations of FPGA-based processors for AI/ML algorithms, such as Small Language Models and Large Language Models. Novel uses of AI models to aid in the design and programming of FPGAs.
Research submissions can be in either of two categories:
- Regular — at most 10 pages (excluding references), for a regular presentation at the conference.
- Short — at most 6 pages (excluding references), for a brief presentation.
A paper submitted as either regular or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).
Submission Process
Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/. LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LaTeX link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract and paper submissions in PDF must be received by 11:59 PM AoE (Anywhere-on-Earth time zone).
Submissions will be considered for acceptance as regular or short papers. A paper submitted to the regular or short category will only be considered in that category. Regular or short submissions will also be considered for acceptance as a poster. Once a paper has been submitted, its authorship list is considered to be fixed and final.
Important Dates
Abstracts Due: October 1, 2024 (All papers)
Submissions Due: October 8, 2024 (All papers)
Rebuttals Period: November 11 – November 18, 2024
Notification of Acceptance: November 30, 2024
Camera-Ready Submission Due: December 31, 2024
All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12)
Organizing Committee
General Chair: Andrew (Putnam Microsoft)
Program Chair: Jing Li (University of Pennsylvania)
Call for Papers: ISFPGA 2023
https://www.isfpga.org/call-for-papers/
Submitted by Aman Arora
Call for Papers – FPGA 2024
32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
March 3 – 5, 2024
Website: https://isfpga.org
Submission site: https://fpga24.hotcrp.com
Abstracts Due: October 6, 2023
Submissions Due: October 13, 2023
The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2024, the 32nd edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.
Paper Submissions (with and without Artifacts)
We solicit research papers related to the following areas:
- FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
- FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory or nano-scale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability.
- CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
- High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
- FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
- Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.
Research submissions can be in either of two categories:
- Regular — at most 10 pages (excluding references), for a regular presentation at the conference.
- Short — at most 6 pages (excluding references), for a brief presentation.
A paper submitted as either regular or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).
Submission Process
Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/. LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LaTeX link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract and paper submissions in PDF must be received by 11:59 PM AoE (Anywhere-on-Earth time zone).
Submissions will be considered for acceptance as regular or short papers. A paper submitted to the regular or short category will only be considered in that category. Regular or short submissions will also be considered for acceptance as a poster. Once a paper has been submitted, its authorship list is considered to be fixed and final.
By submitting articles to an ACM Publication, authors are hereby acknowledging that they and their co-authors are subject to all ACM Publications Policies (https://www.acm.org/publications/policies), including ACM’s new Publications Policy on Research Involving Human Participants and Subjects (https://www.acm.org/publications/policies/research-involving-human-participants-and-subjects). Alleged violations of this policy or any ACM Publications Policy will be investigated by ACM and may result in a full retraction of their paper, in addition to other potential penalties, as per ACM Publications Policy.
Authors should ensure that they and their co-authors obtain an ORCID ID (https://orcid.org/register), so that they can complete the publishing process for accepted papers. ACM has been involved in ORCID from the start and ACM has recently made a commitment to collect ORCID IDs from all of their published authors (https://authors.acm.org/author-resources/orcid-faqs). The collection process has started and will roll out as a requirement throughout 2023. ACM is committed to improve author discoverability, ensure proper attribution, and contribute to ongoing community efforts around name normalization; authors’ ORCID ID will help in these efforts.
Double Blind Policy
The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. References to the authors’ prior work should be made in the third person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as “Removed for blind review,” but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission. When necessary, authors should cite widely-available Open Source software website(s) without claiming ownership. Grant numbers and other government markings should also be blinded during the review process. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged. Similarly, if a paper can be unblinded by active search, this is not considered to undermine the spirit of the double-blind review. However, there are resources to blind open-source repositories for review, including: https://github.com/tdurieux/anonymous_github.
If you have questions about how to meet these guidelines, please contact the program chair before the submission deadline.
Reviewer Conflict Policy
During paper submission, all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is left undeclared or a nonexistent conflict is declared in an attempt to manipulate the review process, the submission may be rejected.
For more information about the ACM Conflict of Interest Policy, see: https://www.acm.org/publications/policies/conflict-of-interest
Originality of Submissions
Papers submitted are guaranteed by the authors to be unique manuscripts and not previously published, currently accepted or under consideration for acceptance at another venue. They cannot be substantially similar to any other current/future conference, journal, or workshop submission(s) unless the content appeared at a venue that does not have archived proceedings.
Rebuttal Process
The conference review process includes a rebuttal phase for authors to provide an optional response to reviewers’ questions and comments. This information is considered during the final deliberation process.
Author participation
For inclusion in the ACM digital library, at least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel (more instruction will be available after the camera-ready submission).
Best Paper Award
Authors of this year’s best manuscripts will be eligible for the conference’s best paper awards. They will also be invited to extend their work for consideration in a special issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS).
Artifact Evaluation
The conference will allow authors to submit accompanying artifacts for their paper submissions for evaluation. This process will allow ACM recognized badges to be associated with the final publication. The inclusion of artifacts with a submission is not required for a paper submission nor will any preference be given to submissions with artifacts over those without. Papers and artifacts will be subjected to separate and independent review processes. Artifact evaluation must NOT interfere with the double blind reviewing process of their accompanying papers, so all accompanying links in the paper to the artifacts should be blinded. All authors will be required at the time of paper submission to indicate if there will also be associated artifacts for evaluation. If artifacts will be included, a descriptor of their nature will be required.
For more information, see: https://isfpga.org/artifact-evaluation/
Diversity and Inclusion
The open exchange of ideas and the freedom of thought and expression are central to the aims and goals of the conference. The organizers aim and commit to providing a harassment-free accessible and pleasant conference experience with equity in rights for all. We want every participant to feel welcome, included and safe at the conference.
For more information, see: https://isfpga.org/statement-on-diversity-and-inclusion/
Important Dates
All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12)
| Abstracts Due (All Papers) |
October 6, 2023
(No Extensions) |
| Submissions Due (All Papers) |
October 13, 2023
(No Extensions) |
| Rebuttals Period |
November 18 – November 26, 2023 |
| Notification of Acceptance (All Papers) |
December 13, 2023 |
| Camera-Ready Submission Due |
Mid-January, 2024 |
| Conference |
March 4 – 5, 2024 |
Visa Application
Prospective authors and participants requiring a B-2 visa to enter the US should check the visa appointment wait time using this link: https://travel.state.gov/content/travel/en/us-visas.html and consider applying IMMEDIATELY for a visa, scheduling an appointment in December 2023. By then, notification of acceptance will have been sent out (if applicable), registrations will have been opened, and ACM will be able to deliver letters of support. To the best of our knowledge, the letter of support will never be required before the interview.
Organizing Committee
Call for Papers: FPGA 2025
https://www.isfpga.org/
Submitted by Aman Arora
33rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Late February, 2025
Monterey, California
https://isfpga.org
Submission site: https://fpga25.hotcrp.com
The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2025, the 33rd edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.
Paper Submissions (with and without Artifacts)
We solicit research papers related to the following areas:
- FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
- FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory or nano-scale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability.
- CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
- High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
- FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
- Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.
- AI/ML for and on FPGAs: Architectures and implementations of FPGA-based processors for AI/ML algorithms, such as Small Language Models and Large Language Models. Novel uses of AI models to aid in the design and programming of FPGAs.
Research submissions can be in either of two categories:
- Regular — at most 10 pages (excluding references), for a regular presentation at the conference.
- Short — at most 6 pages (excluding references), for a brief presentation.
A paper submitted as either regular or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).
Submission Process
Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/. LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LaTeX link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract and paper submissions in PDF must be received by 11:59 PM AoE (Anywhere-on-Earth time zone).
Submissions will be considered for acceptance as regular or short papers. A paper submitted to the regular or short category will only be considered in that category. Regular or short submissions will also be considered for acceptance as a poster. Once a paper has been submitted, its authorship list is considered to be fixed and final.
For further details and submission instructions please visit https://www.isfpga.org/call-for-papers/
Important Dates
All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12)
| Abstracts Due (All Papers) |
October 1, 2024 (No Extensions) |
| Submissions Due (All Papers) |
October 8, 2024 (No Extensions) |
| Rebuttals Period |
November 11 – November 18, 2024 |
| Notification of Acceptance (All Papers) |
November 30, 2024 |
| Camera-Ready Submission Due |
December 31, 2024 |
| Conference |
Late February |
Call for Papers: ICCD 2024
https://www.iccd-conf.com/
Submitted by Christina Giannoula
ICCD encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology. We especially encourage submissions that look forward to future systems and technologies. Authors are asked to submit technical papers in accordance with the submission guidelines (https://www.iccd-conf.com/Submission_guide.html)
in one of the following tracks:
Track 1: Computing Systems
System architectures; System support for multi/many cores, co-processors, and accelerators; System support for security, reliability, and energy efficiency and proportionality; Virtual memory; System support for emerging technologies, including NVM, quantum, neuromorphic, bio-inspired computing, machine learning, and artificial intelligence applications; Storage systems for data center and cloud/edge computing, high-performance computing (HPC), exascale systems, and serverless computing.
Track 2: Software Architectures, Compilers, and Tool Chains
Software architectures, compilers, programming language/model, firmware, OS, hypervisor, runtime design, and co-design for embedded/real-time systems; middleware for embedded systems, including resource awareness, reconfiguration, and energy/power management; compiler support for enhanced debugging, profiling, and traceability.
Track 3: Hardware Architectures
Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining, caches, branch prediction, multithreading, and networks-on-chip; Techniques for low-power, secure, and reliable processor architectures; Hardware acceleration for emerging applications including NVM, quantum, neuromorphic, bio-inspired; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, retrospectives.
Track 4: Test, Verification, and Security
Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods; Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs;
Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation; Hardware security primitives and methodologies; Side-channel analysis, attacks and mitigations for processors and accelerators; Interaction between test,
security and trust.
Track 5: Electronic Design Automation
System-level design and synthesis; High-level, logic, and physical synthesis; Analysis and optimization of timing, power, variability/yield, temperature, and noise; Physical design, including partitioning, floorplanning, placement, and routing; Clock tree synthesis; Verification methods at different levels of the EDA flow; Tools for multiple-clock domains, asynchronous, and mixed-timing methodologies; CAD support for accelerators, FPGAs, SoCs, ASICs, NoC, and general-purpose processors; CAD for manufacturing, test, verification, and security; Tools and design methods for emerging technologies (photonics, MEMS, spintronics, nano, quantum); interaction of EDA and AI/ML.
Track 6: Logic and Circuit Design
Circuit design techniques for digital, memory, analog, and mixed-signal systems; Circuit design techniques for high performance and low power; Circuit design techniques for robustness under process variability, electromigration, and radiation; Design techniques for emerging and maturing
technologies (MEMS, nano-spintronics, quantum, flexible electronics, multi-gate devices, in-memory computing); Asynchronous circuit design; Signal-processing, graphic-processor, and datapath circuits. A complete version of the paper should be submitted as a PDF file following the submission guidelines.
IMPORTANT DATES:
May 5 Abstract submission
May 12 Full paper submission
Aug 1 Notification of acceptance
Any questions about submission should be directed tothe Program Chairs, Benjamin Carrion Schaefer and Sara Vinco.
Please consult the ICCD 2024 website for additional information about the conference and submission details.
Call for Papers: CGO 2025
https://conf.researchr.org/home/cgo-2025
Submitted by Luisa Cicolini
IEEE/ACM International Symposium on Code Generation and Optimization (CGO) 2025
Co-located with PPoPP, HPCA and CC
Las Vegas, USA
CGO is the premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.
CGO now uses two submissions per year.
Papers submitted to the first round can either be directly accepted, rejected, or invited to submit a revised version of the paper to the second round. For papers invited to submit a revised version, authors will be given a list of revisions that should be acted on to improve the paper. We will make every effort to ensure that the revised paper is reviewed by the same referees, who will assess whether the revisions are satisfactory. If so, the paper will be accepted. If a paper is rejected, the authors may still submit a revised version in a subsequent round, which will be treated as a new submission.
First Submission Deadline
- Paper Submission: May 30, 2024
- Author Rebuttal Period: July 9-11, 2024
- Paper Notification: July 22, 2024
Second Submission Deadline
- Paper Submission: September 12, 2024
- Author Rebuttal Period: October 22 – 24, 2024
- Paper Notification: November 4, 2024
For submission instructions please visit – https://2025.cgo.org/track/cgo-2025-papers#Submission-Information
CGO has a second category of papers called “Tools and Practical Experience”. Papers in this category must either give a clear account of a tool’s functionality or summarize a practical experience with realistic case studies.
The successful evaluation of an artifact is mandatory for a Tool Paper.
Therefore, authors of work conditionally accepted as Tool Papers must submit an artifact to the Artifact Evaluation Committee. The successful evaluation of the artifact is a requirement for final acceptance.
Practical experience papers are encouraged, but not required, to submit an artifact to the Artifact Evaluation process.
For further information please visit https://2025.cgo.org/track/cgo-2025-papers#Call-for-PapersThe successful evaluation of an artifact is mandatory for a Tool Paper.
Call for Papers: HiPC 2024
https://www.hipc.org/papers/
Submitted by HiPC 2024 Publicity Chairs
31st IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC 2024)
18–21 December 2024 in Bangalore, India
HiPC serves as a forum to present current work by researchers from around the world as well as highlight activities in Asia in the areas of high performance computing and data science. The meeting focuses on all aspects of high performance computing systems, and data science and analytics, and their scientific, engineering, and commercial applications.
Authors are invited to submit original unpublished research manuscripts that demonstrate current research in all areas of high performance computing, and data science and analytics, covering all traditional areas and emerging topics including from machine learning, big data analytics. Each submission should be submitted to one of the six tracks listed under the two broad themes of High Performance Computing and Data Science. Please see https://www.hipc.org/papers/ for more details.
Up to two best paper awards will be given to outstanding contributed papers. Authors of selected high quality papers in HiPC 2024 will be invited to submit extended versions of their papers for possible publication in a special issue of the Journal of Parallel and Distributed Computing (JPDC).
Important Deadlines:
Abstract Submission: June 19, 2024 (Wednesday)
Paper Submission (double-blind): June 26, 2024 (Wednesday)
Reviews to Authors: August 22, 2024 (Thursday)
Rebuttal Period: August 22-27, 2024 (Thursday to Tuesday)
Author Notification: September 13, 2024 (Friday)
Shepherded Paper Submission: September 27, 2024 (Friday)
Final Author Notification: October 5, 2024 (Friday)
GENERAL CO-CHAIRS:
Sanmukh Rao Kuppannagari, Case Western Reserve University, USA
Arnab K. Paul, Birla Institute of Technology and Science Pilani, Goa Campus, India
PROGRAM CO-CHAIRS:
HPC: Devesh Tiwari, North Eastern University, USA
Data Science: Preeti Malakar, Indian Institute of Technology Kanpur, India
STEERING COMMITTEE CHAIR:
Viktor K. Prasanna, University of Southern California, USA
Call for Papers: HPCA 2025
https://hpca-conf.org/2025/call-for-papers/
Submitted by Hung-Wei Tseng
31st IEEE International Symposium on High-Performance Computer Architecture (HPCA 2025)
Las Vegas, NV
HPCA is a high-impact premier venue for presenting research results on a wide range of computer architecture topics. Some topics of interest are listed below,
- Processor, memory, and storage systems architecture
- Instruction-, thread-, and data-level parallelism
- Interconnection networks and network interface architecture
- Domain-specific architectures and Accelerators
- FPGA, CGRA, and Reconfigurable systems
- Near/In-Memory computing
- Cloud, Datacenters, cluster/distributed systems
- Approximate computing
- Compilers/Languages/Runtimes for novel architectures
- IoT, Mobile, Edge, and Embedded architectures
- Effects of circuits or technology on architecture (3D/chiplets/interposer/wafer-scale)
- Architecture modeling and simulation methodologies
- Neuromorphic computing
- Quantum, Superconducting and Emerging technologies impacting computer architectures
- Reliability/Fault Tolerance, Energy Efficiency and Sustainability of Computer Systems
- Security/Privacy
- Evaluation and measurement of real computing systems
HPCA 2025 features a separate Industry Track with a separate call for papers. The goal of the HPCA Industry Track is to publish papers that are written by industry authors and their content relates to industrial products/processes.
Important Dates
Paper Registration and Abstract Submission: 26 July 2024
Paper Submission: 2 August 2024
Revision/Rebuttal Period: 6-18 October, 2024
Notification: 5 November, 2024
For more information please visit https://hpca-conf.org/2025/call-for-papers/ or contact the PC chairs.
Call for Papers: ASPLOS 2025
https://www.asplos-conference.org/asplos-2025-call-for-papers/
Submitted by Zhibin Yu
Scope and Expectations
The scope of ASPLOS 2025 covers all practical aspects related to the three main ASPLOS disciplines: computer architecture, programming languages, and operating systems, as well as closely-related associated areas. We seek original, high-quality research submissions that improve and further the knowledge of applied computer systems, with emphasis on the intersection between the main ASPLOS disciplines. Research submission may be applicable to computer systems of any scale, ranging from small, ultra-low power wearable devices to large scale parallel computers and data centers. We embrace research that directly targets new problems in innovative ways. The research may target diverse goals, such as throughput, latency, energy, and security. Non-traditional topics are encouraged, and the review process will be sensitive to the challenges of multidisciplinary work in emerging areas. We welcome submission of “experience papers” that have a novel component and that clearly articulate the lessons learned. We likewise welcome submissions whereby novelty lies in furthering our understandings of existing systems, e.g., by uncovering previously unknown, valuable insights or by convincingly refuting prior published results and common wisdom. We value submissions more highly if they are accompanied by clearly defined artifacts not previously available, including traces, original data, source code, or tools developed as part of the submitted work. We particularly encourage new ideas and approaches.
Alphabetically sorted areas of interest related to practical aspects of computer architecture, programming languages, and operating systems include but are not limited to:
- Existing, emerging, and nontraditional compute platforms at all scales
- Heterogeneous architectures and accelerators
- Internet services, cloud computing, and datacenters
- Memory, storage, networking, and I/O
- Power, energy, and thermal management
- Profiling, debugging, and testing
- Security, reliability, and availability
- Systems for enabling parallelism and computation on big data
- Virtualization and virtualized systems
A good submission will typically: motivate a significant problem; propose a practical solution or approach that makes sense; demonstrate not just the pros but also the cons of the proposal using sound experimental methods; explicitly disclose what has and has not been implemented; articulate the new contributions beyond previous work; and refrain from overclaiming, focusing the abstract and introduction sections primarily on the difference between the new proposal and what is already available. The latter statement should be interpreted broadly to also encompass studies that broaden our understanding of existing systems (rather than suggest new ones), which may constitute a significant problem in its own right. Submissions will be judged on relevance, novelty, technical merit, and clarity. Submissions are expected to adhere to SIGPLAN’s Empirical Evaluation Guidelines and all the policies specified below.
Resubmissions
Authors of resubmitted work must describe in a separate note – to be uploaded to the submission site at submission time – the changes since the previous submission(s). This description helps reviewers who may have reviewed a previous draft of the work to appreciate any improvements to the currently submitted work. Please try to limit this document to one page.
Submissions rejected from ASPLOS must not be submitted to the next two subsequent review cycles. The corresponding restrictions on ASPLOS ‘25 submissions are thus:
- Papers rejected in 2024 Spring, or earlier, are now eligible for resubmission to ASPLOS.
- Papers rejected in 2024 Summer may not resubmit until ASPLOS 2025 Summer (or later).
- Papers rejected in 2024 Fall may not resubmit until ASPLOS 2025 Fall (or later).
These resubmission rules are strict and hold even if a submission has undergone extensive revision.
Major Revisions
In addition to Accept and Reject outcomes, ASPLOS 2025 will offer some submissions a “Major Revision” decision. The authors of such submissions will be given the opportunity to apply a major revision to their work and resubmit it at the camera ready deadline (6 weeks from notification). These submissions will be provided with clear and actionable reviewer feedback for their revision, and they will be typically reviewed by the same reviewers as the original submission. If the revision requirements are satisfactorily met, the revised submission will be accepted.
Anonymization
ASPLOS employs a double-blind review process, keeping author identities concealed from reviewers and vice versa. You must therefore make a good faith attempt to anonymize your submission by avoiding identifying yourself or your institution/affiliation in any of the submitted documents (except in specific fields on the HotCRP submission form designated for this purpose), either explicitly or by implication, e.g., through references, acknowledgments, online repositories that are referenced by the submission, or interaction with committee members.
Do not include a “reference removed for blind review” text or similar in your submission. When it is necessary to cite your own studies, cite them as written by a third party. Only if that is not possible, they can be uploaded and cited as anonymized supplemental material (see below). This applies to workshop papers that are being extended by your current ASPLOS submission, and related submissions of your own that are simultaneously under review or awaiting publication at other venues. Publication as a technical report or in an online repository does not constitute a violation of this policy, and some other exceptions apply; see the “originality and concurrent submissions” section below for details.
Please make sure not to reveal author and/or affiliation information through side channels and other less obvious means. For example, the metadata included in the PDF should not give away such information. If you’d like to point to a repository of, e.g., the working code of your system (which is great and much appreciated), this repository should, of course, be anonymized. It is okay and often makes sense to create anonymized repositories merely for the sake of an anonymous submission. If your system is already released to the public, rename it in your submission. You should likewise avoid inadvertently revealing affiliation in your submission by identifying your company’s name in situations where, e.g., it is clear that the authors of the submission most probably work for the company that manufactures the device or provides the service that constitutes the topic of your work; instead, please use a generic name, like “a computer server vendor X,” “a cloud service provider Y,” and such like.
If concealing system name or affiliation would make your paper difficult to understand, contact the program chairs to discuss exceptions to this policy. Submissions that are not properly anonymized will likely be rejected without review.
For more details about submission instructions, response period, artifact evaluation, please visit https://www.asplos-conference.org/asplos-2025-call-for-papers/
Questions?
Please direct any questions to the program co-chairs at asplos2025pcchairs@gmail.com.
Call for Papers: ESWEEK 2024
https://esweek.org/
Submitted by Lars Bauer
EMBEDDED SYSTEMS WEEK
Call for Papers: CASES, CODES+ISSS, EMSOFT, MEMOCODE
About Embedded Systems Week (ESWEEK)
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent and connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), one symposium (MEMOCODE), and several workshops and tutorials, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development.
Registered attendees can attend sessions in any of the ESWEEK conferences (CASES, CODES+ISSS, EMSOFT). Tutorials, symposium
(MEMOCODE), and workshops require can be registered individually or in addition with the ESWEEK registration.
Important Dates
Journal Track:
– Abstract Submission: March 24, 2024 (AoE)
– Full Paper Submission: March 31, 2024 (AoE, firm)
– Notification of Acceptance: July 14, 2024
Work-in-Progress and Late Breaking Tracks:
– Paper Submission: June 02, 2024 (AoE, firm)
– Notification of Acceptance: June 30, 2024
Workshops, Tutorials, Education Classes, and Special Sessions:
– Submission: March 24, 2024
Review Process
ESWEEK has three publication venues:
1. Journal Track: Full-length papers describe mature work and are limited to 12 pages in IEEE double column format. Accepted papers will
be published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) after two stages of
review. Articles not accepted after the second stage will still have the possibility of continuing as regular journal papers in TCAD (pending a decision from the TPC chairs).
2. Late Breaking (LB) Result Track: LB papers disseminate complete and mature works written in a condensed form and are limited to 4 pages in IEEE double column format. Accepted papers will be published in IEEE Embedded Systems Letters (ESL) after one stage of review. Articles not accepted after this stage will still have the possibility of continuing as regular journal papers in ESL (pending a decision from the TPC chairs).
3. Work-in-Progress (WiP) Track: WiP papers present not-yet-mature but promising research work, and are limited to extended abstracts of 1
page in IEEE double column format. Accepted WiP papers will be published in the ESWEEK Proceedings of CASES, CODES+ISSS, or EMSOFT, depending on where they have been submitted.
These three venues are mutually exclusive, i.e., a work can only be in submission to one of the three categories. Authors of WiP papers have the opportunity to publish the extended final form of their work when it has matured in any conference or journal they prefer. Special
Session papers, Keynote/Tutorial abstracts, etc. are also published in the ESWEEK Proceedings of the respective conferences. All these
publications will be listed as regular publications within the ACM and/or IEEE digital libraries. For more information on the publishing process, refer to:
CASES: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
CASES is a premier forum where researchers, developers and practitioners
exchange information on the latest advances in compilers and
architectures for high-performance, low-power embedded systems. The
conference has a long tradition of showcasing leading edge research
in embedded processor, memory, interconnect, storage architectures
and related compiler techniques targeting performance, power,
predictability, security, reliability issues for both traditional
and emerging application domains. In addition, we invite innovative
papers that address design, synthesis, and optimization challenges
in heterogeneous and accelerator-rich architectures.
CASES Program Chairs:
Jana Doppa, Washington State University, US
Jeronimo Castrillon, TU Dresden, DE
CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis
The International Conference on Hardware/Software Codesign and System Synthesis is the premier event in system-level design, modeling,
analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hard-ware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design.
CODES+ISSS Program Chairs:
Muhammad Shafique, New York University, US
Prabhat Mishra, University of Florida, US
EMSOFT: International Conference on Embedded Software
The ACM SIGBED International Conference on Embedded Software (EMSOFT) brings together researchers and developers from academia, industry, and government to advance the science, engineering, and technology of embedded software development. Since 2001, EMSOFT has been the premier venue for cutting-edge research in the design and analysis of software that interacts with physical processes, with a long-standing tradition for results on cyber-physical systems, which compose computation, networking, and physical dynamics.
EMSOFT Program Chairs:
Alessandro Biondi, Scuola Superiore Sant’Anna, IT
Martina Maggio, Lund University, SW & Saarland University, DE
MEMOCODE: International Symposium on Formal Methods and Models for System Design
MEMOCODE focuses on formal methods and models for developing computer systems and their components. MEMOCODE’s objective is to emphasize the importance of models and methodologies in correct system design and development.
MEMOCODE Program Chairs:
Qi Zhu, Northwestern University, US
Srinivas Pinisetty, IIT Bhubaneswar, IN
Call for Workshop Proposals
ESWEEK 2024 will host several workshops on Thursday October 3rd and Friday October 4th and is soliciting proposals for new and recurring workshops. Workshops can be half-day to two-day long. We invite you to submit workshop proposals on any topic related to the broad set of research and education.
Workshop Chair:
Heiko Falk, TU Hamburg, DE
Call for Tutorial Proposals
ESWEEK 2024 is looking for high-quality tutorials that will take place on Sunday, September 29th, 2024. Tutorials on all topics related to embedded system design, analysis, and development are welcome. Tutorials can be either half/full-day, lecture style or hands-on.
Tutorials Chair:
Christian Pilato, Politecnico di Milano, IT
Call for Education Proposals
ESWEEK 2024 will host several education lectures virtually on Thursday September 26th and Friday September 27th, and is soliciting proposals for such lectures. We invite you to submit education proposals on any topic related to ESWEEK.
Education Chairs:
Anup Das, Drexel University, US
Qingfeng (Karen) Zhege, East China Normal University, CN
Call for Special Session Proposals
We invite you to submit special session proposals on any topic relevant to the broad areas of interest of ESWEEK. The special session should cover a topic that is contemporary, hot, and complementary to the regular sessions. The special session should be able to generate enthusiasm among the ESWEEK participants.
Special Sessions Chair:
Pi-Cheng Hsiu, Academia Sinica, TW
Software Competition
Following their first introduction in 2023, we will host several software competitions. More details will be available soon.
Software competition chairs
Ganapati Bhat, Washington State University, US
Biresh Kumar Joardar, University of Houston, US
Wanli Chang, Hunan University, CN
Panels: Celebrating the 20th ESWEEK conference
The ESWEEK series started in 2005 in Jersey City, so ESWEEK 2024 will be the 20th edition! This will be the occasion of celebrating the best moments with a chosen panel of people who contributed to the past editions. Two panels will be organized in 2024, one devoted to this
celebration, and another one devoted to the complex interrelations between embedded systems and the environmental crisis (which encompasses the climate change, the biodiversity collapse, the mineral resource depletion), where we will bring some answers to the complex issues of whether embedded systems shall be part of the solution to the environmental crisis, or whether they are part of the problem.
Panel chair
Marilyn Wolf, University of Nebraska-Lincoln, US
Organization
ESWEEK 2024 General Chairs:
Alain Girault, Inria & Univ. Grenoble Alpes, FR (General Chair)
Tei-Wei Kuo, National Taiwan University, TW (Vice General Chair)
Conference and Local Arrangement Chair:
Frank Mueller, North Carolina State University, US
Call for Papers: ASAP 2024
http://www.asap2024.org/
Submitted by Suhaib Fahmy
The 35th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2024
Important dates:
Abstracts Due: 21 Mar 2024
Papers Due: 28 Mar 2024
Notification: 2 May 2024
Camera Ready: 29 May 2024
Topics:
- Accelerator design including for AI, big data, bioinformatics, finance, network processing, compression, image and signal processing, cryptography and security, etc.
- Application-specific instruction-set processors and architectures
- Approximate computing
- Computer arithmetic
- Emerging architectures: neuromorphic and quantum
- Cloud computing accelerator
- Edge computing, wireless, mobile, IoT
- Cyber-physical, embedded, and autonomous systems
- Heterogeneous computing: from embedded to HPC systems and data centers
- Reconfigurable and custom computing (FPGAs, CGRAs, etc.)
- Design methods, tools, and compilers, domain-specific languages, simulation and prototyping
- System quality attributes, e.g., energy efficiency, fault tolerance, security, etc.
- Emerging technologies, e.g., optical computing and communication, 3D devices and interconnects, memristors for storage and logic, in-memory computing
Organizing Committee
General Chair: Prof Ray Cheung, CityU, Hong Kong
General Co-Chair: Prof Wei Zhang, HKUST, Hong Kong
TPC Co Chairs: Prof Florent de Dinechin, INSA, Lyon, France
Prof Martin Herbordt, Boston University, USA
Finance Chair: Prof Shiqi Wang, CityU, Hong Kong
Registration Chair: Prof Donglong Chen, BNU-HKBU United International College, Zhuhai, China
Tutorial Chair: Prof Xin Yao, Guangzhou University, China
Publicity Chair: Prof Suhaib A. Fahmy, KAUST, Saudi Arabia
Local Arrangement Chair: Prof Yao Liu, SYSU, China
Publication Chair: Prof Haoliang Li, CityU, Hong Kong
Sponsorship Chair: Dr Patrick Hung, IEEE HK Computer Chapter, Hong Kong
Webchair: Prof Matthew Tang, Queen Mary University of London, UK
Student Volunteer Chair: Dr Sanka Abdurrashid Ibrahim, CityU, Hong Kong
Please find more information on the conference website: http://www.asap2024.org/
Call for Papers: MICRO 2024
https://microarch.org/micro57/
Submitted by George Tzimpragos
57th IEEE/ACM International Symposium on Microarchitecture – MICRO 2024
November 2 – 6, 2024
Austin, Texas, USA
The IEEE/ACM International Symposium on Microarchitecture® (MICRO) is the premier forum for for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and we aim to continue this tradition at MICRO-57. In 2024, MICRO goes to Austin, Texas, USA.
Important Dates:
Abstract Submission Deadline: April 11, 2024
Full Paper Deadline: April 18, 2024
Notification: July 19, 2024
Papers are solicited on a broad range of topics, including (but not limited to):
- Microarchitectural, architectural, compiler, and hybrid techniques for improving system performance, power, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, or sustainability
- Processor, memory, and storage architectures
- Multicore and multiprocessor systems
- Instruction-, thread-, and data-level parallelism
- Prediction and Speculation
- Memory Hierarchy
- Cloud and datacenter-scale computing
- IoT, mobile, and embedded architecture
- Interconnection network, router, and network interface architecture
- Accelerator-based, application-specific, and reconfigurable architectures
- Architectural support for programming languages, compilation, software development, security and privacy, virtualization
- Architectures for emerging technologies and applications
- Architectural support for non-volatile/persistent memory
- Quantum computing
- In-/near-memory or in-/near-storage processing
- Approximate computing and architectural support for approximation
- Effects of circuits and technology on architecture
- Architecture modeling and simulation methodologies
- Evaluation and measurement of real computing systems
More information on solicited topics is available at https://microarch.org/micro57/submit/papers.php.
Call for Papers: ISMM @ PLDI 2024
https://conf.researchr.org/home/ismm-2024
Submitted by Jae W. Lee
ACM International Symposium on Memory Management (ISMM) 2024 –
co-located with PLDI 2024
Important changes in ISMM 2024. We are excited to announce an expanded scope of ISMM this year to encourage submissions and participation from related fields such as computer architecture and systems in addition to the PL community!
Call for Papers
The 2024 ACM SIGPLAN International Symposium on Memory Management (ISMM 2024) is soliciting full-length submissions on all memory management related topics in both software and hardware, as well as papers presenting confirmations or refutations of important prior results. In addition to regular papers, traditionally submitted to ISMM, we also invite submissions of the following kinds:
- Surveys and comparative analyses that shed new light on previously published techniques.
- Practitioner reports, describing experience with memory management in production. Such papers are not expected to provide novel research contributions, but they should not have been previously published.
- Intellectual abstracts, where researchers share designs, algorithms, or theory that may be interesting to the memory management community, but not yet evaluated.
Please indicate whether the paper is a regular paper, a survey, a practitioner report, or an intellectual abstract, by using a subtitle. For example, for a regular paper, include on of the following on the line below the title line: subtitle{This submission is a regular paper}, subtitle{This submission is a survey}, subtitle{This submission is a practitioner report}, or subtitle{This submission is an intellectual abstract}.
Important Dates
Paper Submission: March 22, 2024
Author Response Period: April 29-30, 2024
Author Notification: May 10, 2024
Camera-Ready Deadline: May 20, 2024
Areas of Interest
Areas of interest include but are not limited to (with this year’s changes highlighted) :
- Caches
- Cache coherence and memory consistency
- Processing in memory and near memory processing
- Memory device architectures (SRAM, DRAM, flash, NVM)
- Security and privacy of memory systems
- Reliability of memory systems
- Garbage collection algorithms and implementations
- Memory allocation and de-allocation
- Memory system design and analysis
- Hardware support for memory management
- Memory management for large-scale data-intensive systems
- Memory management at datacenter and cloud scales
- Formal analysis and verification of memory management algorithms
- Compiler analyses to aid memory management
- Tools to analyze memory usage of programs
- Empirical analysis of memory intensive programs
- Formal analysis and verification of memory intensive programs
- Memory management for machine learning systems
- Programming and management of emerging or persistent memories
The symposium welcomes industry practitioners presenting their recent practice and findings in memory management related to real-world deployments.
Submission guidelines can be found at https://conf.researchr.org/home/ismm-2024#Call-for-Papers
Contact Information
PC Co-chairs of ISMM 2024
Jae W. Lee, Seoul National University – jaewlee@snu.ac.kr
Hannes Payer, Google – hpayer@google.com
Call for Papers: IISWC 2024
https://iiswc.org/iiswc2024/cfp.html
Submitted by Dmitrii Ustiugov
IEEE International Symposium on Workload Characterization
IISWC invites manuscripts that present original unpublished research in all areas related to the characterization and analysis of computing system workloads, including translational research related to production-oriented commercial systems. Work focusing on emerging technologies and interdisciplinary work are especially welcome. Topics of interest include (but are not limited to) characterization of applications in traditional and emerging domains, characterization of system software and middleware, implications of workloads in system design, benchmarking methodologies and suites, and tools for computer systems. A detailed list of the topics can be found at https://iiswc.org/iiswc2024/cfp.html#topics-of-interest
Important dates:
- Submission Deadline: June 3, 2024
- Decision Notification: July 16, 2024
- Camera-ready Deadline: August 9, 2024
Submission Guidelines
https://iiswc.org/iiswc2024/cfp.html#submission-guidelines
Submissions to IISWC can be made in one of the following two categories: (1) regular papers and (2) tool and benchmark papers. The primary focus of regular papers (submission length: 10 pages, excluding references) should be to describe new research ideas supported by experimental implementation and evaluation of the proposed research ideas. The primary focus of tool and benchmark papers should be to describe the design, development, and evaluation of new open-source tools and benchmarks suites. Submissions in the regular papers category are also encouraged to open-source their software or hardware artifacts.
The authors are required to indicate the category of the paper as a part of the submitted manuscript’s title. On the submission system entry, we ask the authors to add a prefix to the title indicating the type of the submission as follows: 1. regular papers: “Regular-TITLE” and 2. tool and benchmark papers: “Tools-TITLE”.
Papers in the tool and benchmark category with relatively shorter length (6 pages) are welcome if the contributions can be well articulated and substantiated. However, all submissions in the tool and benchmark category have the flexibility of using all 10 pages (excluding references). The submissions in both categories will be evaluated to the same standards in terms of novelty, scientific value, demonstrated usefulness, and potential impact to the field. The nature of the contribution differs between the two categories (new research idea vs. new open-source benchmark-suite / tool) and papers will be evaluated based on the intended nature of the contribution, as declared by the chosen paper category at the time of the submission. The chosen category at the time of the submission cannot be changed after the submission deadline.
Double-blind submission guidelines apply to the submissions in both categories. Open-source benchmarks and tools that have not been previously published (but may have been open-sourced) are eligible for submission in the tool and benchmark papers category.
When including source code links in their submission, we require the authors to use new or anonymized code repositories to preserve the integrity of double-blind review process. All submitted papers should have obtained legal permission (if applicable) to open-source the benchmark-suite / tool at the time of submission.
Call for Papers: PACT 2024
https://pact2024.github.io/index
Submitted by Rajiv Gupta
The International Conference on Parallel Architectures and Compilation Techniques (PACT) is a unique technical conference sitting at the intersection of hardware and software, with a special emphasis on parallelism. The PACT conference series brings together researchers from computer architectures, compilers, execution environments, programming languages, and applications, to present and discuss their latest research results.
PACT 2024 will be held as an in-person event in Long Beach, California, USA. At least one of the authors of accepted papers will be required to attend the conference, and we encourage all the authors to participate.
Specific topics of interest include (but are not limited to):
- Parallel architectures, including accelerator architectures for AI or other domains
- Compilers and tools for parallel architectures (as above)
- Applications and experimental systems studies of parallel processing
- Computational models for concurrent execution
- Multicore, multithreaded, superscalar, and VLIW architectures
- Compiler and hardware support for hiding memory latencies
- Support for correctness in hardware and software
- Reconfigurable parallel computing
- Dynamic translation and optimization
- I/O issues in parallel computing and their relation to applications
- Parallel programming languages, algorithms, and applications
- Middleware and run time system support for parallel computing
- Application-specific parallel systems
- Distributed computing architectures and systems
- Heterogeneous systems using various types of accelerators
- In-core and in-chip accelerators and their exploitation
- Applications of machine learning to parallel computing
- Large scale data processing, including computing in memory accelerators
- Insights for the design of parallel architectures and compilers from modern parallel applications
PACT for Quantum and Neurmorphic
- Neuromorphic computing both as an application for and a tool applied to architectures and compilers
- Quantum computing architectures and compilers.
In addition to the regular research papers, PACT 2024 has a special category of papers called “tools and practical experience” (TPE). Such papers are subject to the same page length guidelines and will be reviewed by the same Program Committee. TPE papers focus on applicability (such as traditional methods employed in emerging fields), exposing challenges and experiences the industry is facing as an opportunity to steer the research. A TPE paper must clearly explain its functionality, provide a summary about the practice experience with realistic case studies, and describe all the supporting artifacts available (if relevant). The selection criteria are:
- Originality: Papers should present PACT-related technologies applied to real-world problems with scope or characteristics that set them apart from previous solutions.
- Usability: The presented Tools or compilers should have broad usage or applicability. They are expected to assist in PACT-related research, or could be extended to investigate or demonstrate new technologies. If significant components are not yet implemented, the paper will not be considered.
- Documentation: The tool or compiler should be presented on a web-site giving documentation and further information about the tool.
- Benchmark Repository: A suite of benchmarks for testing should be provided.
- Availability: Preferences will be given to tools or compilers that are freely available (at either the source or binary level). Exceptions may be made for industry and commercial tools that cannot be made publicly available for business reasons.
- Foundations: Papers should incorporate the principles underpinning Parallel Architectures and Compilation Techniques (PACT). However, a thorough discussion of theoretical foundations is not required; a summary of such should suffice.
Submitting your work
Paper submissions are due March 27, 2024 by posting on the conference submission site. Please make sure that your paper satisfies all the following requirements before being submitted. Submissions not adhering to these submission guidelines will be rejected by the submission system and/or subject to an administrative rejection.
- Mark TPE papers clearly by preceding their title with “TPE: ” both in the submission site and in the submitted pdf
- The paper must have an abstract under 300 words.
- The paper must be original material that has not been previously published in another conference or journal, nor is currently under review by another conference or journal. You may submit material presented previously at a workshop without copyrighted proceedings.
- The submission is limited to ten (10) pages in the ACM 8.5” x 11” format (US letter size paper) using 9pt font, with no more than 7 lines per inch. This page limit applies to all content NOT INCLUDING references, and there is no page limit for references. Your paper must print satisfactorily on both Letter paper (8.5”x11”) and A4 paper (8.27”x11.69”). The box containing the text should be no larger than 7.15”x9” (18.2cm x 22.9cm). Templates are available on the ACM Author Gateway.
- Paper submission is double-blind to reduce reviewer bias against authors or institutions. Thus, the submissions cannot include author names, institutions or hints based on references to prior work. If authors are extending their own work, they need to reference and discuss the past work in third person, as if they were extending someone else’s research. We realize that for some papers it will still reveal authorship, but as long as an effort was made to follow these guidelines, the submission will not be penalized.
- Anonymized supplementary material may be provided in a single PDF file uploaded at paper submission time, containing material that supports the content of the paper, such as proofs, additional experimental results, data sets, etc. Reviewers are not required to read the supplementary material but may choose to do so.
- Please make sure that the labels on your graphs are readable without the aid of a magnifying glass.
- The paper must be submitted in PDF. We cannot accept any other format, and we must be able to print the document just as we receive it. We suggest that you use only the four widely used printer fonts: Times, Helvetica, Courier and Symbol.
Poster submissions must conform to the same format restrictions, but may not exceed 2 pages in length. Paper submissions that are not accepted for regular presentations will automatically be considered for posters; authors who do not want their paper considered for the poster session should indicate this in their abstract submission. Two-page summaries of accepted posters will be included in the conference proceedings.
Call for Papers: SYSTOR 2024
https://www.systor.org/2024/cfp/
Submitted by Oleg Kolosov
The ACM International Systems and Storage Conference (SYSTOR) is an international forum for interaction across the systems research community. The program includes innovative, peer-reviewed research papers in the broad area of systems, as well as distinguished keynote lecturers, a poster session, and social events. ACM SYSTOR is designed to engage academic and industrial researchers and practitioners, welcoming both students and seasoned professionals.
Topics:
SYSTOR welcomes academic and industrial papers in systems including storage, cloud and distributed systems, networking, and systems security, broadly construed. SYSTOR encourages submissions that describe results from experimental system prototypes, as well as experience papers describing practical deployments, and valuable lessons learned from them.
This year, we are broadening the scope to also include research on systems issues in AI and/or sustainability, including those that involve workload optimization, data processing, lifecycle of systems, carbon footprint transparency, and system re-designs.
Topics of interest include, but are not limited to:
- Systems and workload optimization for AI/ML systems
- Sustainability/carbon footprint of computer and network systems
- System security and trust
- Big Data infrastructure
- Cloud, edge, data center, and distributed systems
- Embedded and real-time systems
- Fault tolerance, reliability, and availability
- File and storage systems
- Networked, mobile, wireless, peer-to-peer, and sensor systems
- Operating systems, computer architecture, and their interactions
- Performance evaluation and workload characterization
- Runtime systems and compiler/programming-language support
- System deployment, usage, and experience
- System design or adaptation for emerging storage technologies
- Virtualization and containers
- Storage 3.0
Attendance:
The conference this year will be physical.
By submitting a research paper you agree to make the maximal effort that at least the presenting author will attend in person. However, in case of justifiable circumstances, we may allow a video-recorded presentation with online availability for Q&A.
Highlight papers must be presented in person, therefore by submitting a highlight paper you agree that at least the presenting author will attend in person.
Tracks and Submission Dates:
Full Papers Track – original research, at most 12 pages, excluding references: March 13, 2024
Short Papers Track – original research, at most 5 pages, excluding references: March 13, 2024
Highlight Papers Track – papers accepted at top-tier conferences in 2023: April 3, 2024
Posters with Extended Abstract Track – original work presented as a poster, accompanied by an extended abstract in the conference proceedings: April 11, 2024
Program Chairs:
Sam Noh (Virginia Tech, USA)
Aviad Zuck (Technion, Israel)
General Chair:
Dalit Naor (The Academic College of Tel Aviv-Yaffo, Israel)
Ofer Biran (IBM Research – Haifa, Israel)
Call for Papers: ARCS 2024: HPC – Challenges for Sustainable Computing
https://arcs-conference.org
Submitted by Lars Bauer
ARCS 2024
37th GI/ITG International Conference on Architecture of Computing Systems
May 14-16, 2024, Potsdam, Germany
https://arcs-conference.org
THIS YEAR’S FOCUS: *HPC – Challenges for Sustainable Computing*
The ARCS conferences series has over 36 years of tradition reporting leading edge research in computer architecture and operating systems.
High performance computing represents an important tool for tackling climate change. In many other HPC application fields, the need for more high computing power has increased enormously in recent years, especially due to the high demand of AI-specific workloads. The
operation of correspondingly powerful computing systems therefore represents an increasing problem in terms of energy requirements and
the associated CO2 emissions. HPC is therefore not only part of the solution to tackling climate change, but also part of the overall problem.
Heterogeneous computer architectures promise a significant increase in the energy efficiency of HPC systems. The selection of different
accelerator architectures can contribute significantly to increasing efficiency, but there is currently a lack of appropriate concepts for their seamless and scalable integration, as well as the support through appropriate programming models.
The focus of the ARCS’24 conference will be on novel accelerator architectures, which are suited for the integration into HPC systems. This includes fine and coarse grain reconfigurable architectures as well as new ideas for their integration to achieve higher energy efficiency as typical homogeneous architectures. In addition, the topics cover HPC-specific research at the level of computer architectures, runtime and operating systems, design tools and HPC programming models and algorithms.
In addition to the main conference, ARCS will host special tracks on Organic Computing and Dependability and Fault Tolerance.
The proceedings of ARCS 2024 will be published in the Springer Lecture Notes on Computer Science (LNCS) series. A best paper and best presentation award will be presented at the conference.
Important Dates
* Paper submission deadline: February 29, 2024
* Notification of acceptance: March 28, 2024
* Camera-ready papers: May 2, 2024
* Conference (in Potsdam, Germany): May 14 – 16, 2024
Topics of Interest
Paper submission: Authors are invited to submit original, unpublished research papers on one or more of the following topics:
**Hardware Architectures**
* HPC-workload specific accelerator architectures
* Reconfigurable architectures
* Advanced computing architectures
* System-on-chip
* Distributed systems
* High performance systems
* Heterogeneous multi- and many-core architectures
* Architectures for real-time and mixed-criticality systems
* Coarse- and fine-grained reconfigurable architectures
* Flexible I/O support
* Advanced computing architectures
* Using new non-volatile memory for energy-efficient architectures
* New smart network technologies (e.g. SmartNICs, SmartSwitches)
**Programming Models and Runtime Environments**
* HPC programming models for heterogeneous computing
* Tools to monitor and to optimize the power consumption of HPC architecture
* Operating systems, programming models, algorithms, and data structures for heterogeneous HPC architectures
* Operating systems, hypervisors and middleware for homogeneous and heterogeneous multi-/many-core computing platforms
* System management including but not limited to scheduling, memory management, power/thermal management, and RTOS
* Domain-specific languages and programming models
* Architecture specific code generation and optimization
* Architectural simulation
**Cross-sectional Topics**
* Near-memory and in-memory computing
* Memory and network compression technologies
* Organic computing
* Pervasive systems
* Autonomous systems
* Approximate Computing
* Mixed-criticality systems
* Support for safety and security
* Hardware in the loop simulations
Submission guidelines
Submissions should be done through the link that is provided on the conference website https://easychair.org/conferences/?conf=arcs2024.
Papers must be submitted in PDF format.
They should be formatted according to Springer LNCS style (see: https://www.springer.com/gp/computer-science/lncs/conference-proceedings-guidelines) and must not exceed 15 pages, including references and figures.
Organizers
General Chairs
Dietmar Fey, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
Benno Stabernack, Universität Potsdam / Fraunhofer Heinrich Hertz Institut
Program Chairs
Stefan Lankes, RWTH Aachen University, Aachen, Germany
Mathias Pacher, Goethe-University Frankfurt, Frankfurt am Main, Germany
Proceedings Chair
Thilo Pionteck, Magdeburg University, Germany
Publicity and Web Chair
Lars Bauer, Karlsruhe Institute of Technology (KIT), Germany
https://arcs-conference.org
Call for Papers: SEED 2024 Wild and Emerging Ideas (WEI)
Submitted by Dongrui Zeng
2024 IEEE International Symposium on Secure and Private Execution Environment Design (SEED)
https://seed-symposium.org/2024/
Wild and Emerging Ideas (WEI) papers are intended for breaking contributions and do not limit the authors from publishing a full paper on the topic in the future. They will appear in the conference proceedings. A submission should include the title and a brief abstract (2 pages total, including references).
Deadlines
WEI submission deadline: Jan 10th, 2024, 11:59pm AOE
Submission
The submission website is: https://seed24.hotcrp.com/
Manuscripts must be submitted in printable PDF format and must use the two-column IEEE Proceedings format. References must include all authors to facilitate the reviewing process (no et al.). Text must be in minimum 10pt Times font. Please number the pages of your submission. Double-blind submission guidelines apply to the submissions in all categories.
General co-chairs
Fan Yao, University of Central Florida
Omer Khan, University of Connecticut
Program co-chairs
Nael Abu-Ghazaleh, UC Riverside
Gary Tan, Penn State University
Publicity Chairs
Khaled N. Khasawneh, George Mason University
Dongrui Zeng, Palo Alto Networks
Call for Papers: ICS 2024
https://ics2024.github.io/
Submitted by Murali Annavaram
Papers are solicited on all aspects of the architecture, software, and applications of high-performance computing systems of all scales (from chips to supercomputing systems), including but not limited to:
- Processor, accelerator, memory, storage, interconnect and system architectures, including architectures based on future and emerging hardware (e.g. quantum, superconducting, photonic, neuromorphic).
- Programming languages, paradigms and execution models, including domain-specific languages and scientific problem-solving software environments.
- Compilers, runtime systems and system software, including optimization and support for hardware resources and energy management.
- High-performance algorithms and applications including machine learning and large-scale data analytics, as well as the implementation and deployment of algorithms and applications on large-scale systems.
- Tools for measurement, modeling, analysis and visualization of performance, energy, or other quantitative properties of high-performance computing systems.
Abstract submission: January 11th, 2024
Paper submission: January 18th, 2024
Call for Papers: ISCA 2024 Industry Track
https://www.iscaconf.org/isca2024/submit/industry.php
Submitted by Xiaochen Guo
The 51st International Symposium of Computer Architecture includes a separate industry session in the main program following the success of the industry track inaugurated inISCA 2020. The ISCA Industry Track was established under a different vision and motive to bringing the values, trends, and perspectives of real hardware product and system design from the industries. It also serves as a venue to encourage more participation from industries to interact with academia for forward-looking research challenges and solutions. In light of the very specific purpose of the industry track, the submission guidelines are also very specific.
Submission Guidelines
- The papers ideally include (1) retrospective evaluations of real working products, (2) upcoming industry products on their roadmaps, and/or (3) planned products that were canceled but present interesting insights or lessons learned.
- The following types of submissions will not be considered: (1) students’ short-term internship projects in industries, or (2) speculation about hardware that might be built.
- The first and most of the authors of such papers must work in industry.
- The submissions are required to disclose the affiliations of all authors. Reviewers want to know which product is being evaluated and which company is writing the paper. Review assignments will still follow common practice to avoid conflicts of interest.
- All formatting guidelines for the general submission (including page limits) must also be followed by any paper submitted to the industry track. The accepted paper will be labelled as an “Industry Product” in the conference proceedings.
Submissions that fail to abide by the guidelines will be rejected without review.
Important Dates
The program committee recognizes that industry papers need to be approved by management (often involving multiple rounds of redaction) before they can be submitted, and there can be restrictions about filing patents before submitting a paper. Therefore, a later deadline schedule is adopted to increase the chances of receiving such papers.
- Abstract Deadline: January 5, 2024 at 11:59 PM EST
- Full Paper Deadline: January 12, 2024 at 11:59 PM EST
Topics of Interest
Paper topics are not limited to hardware tapeouts. In particular, papers that are software-centric papers relevant to the ISCA audience are welcome in this track (e.g. datacenter software work, compiler work, accelerator software stack work), but they should adhere to the tenet that they must be industry papers about production-level work – whether retrospective, planned and on the roadmap, or planned but canceled.
- Processors, SoCs, GPUs, and domain-specific accelerators
- Systems and interconnect technologies for HPC, cloud, or data centers
- Embedded, mobile, and IoT processors
- FPGA or reconfigurable architectures
- Storage and emerging memory systems
- Architectures using emerging technology
- Architectures for emerging applications including generative AI and bioinformatics
- Architectures for commercialization of quantum computing