This is the 1st April 2025 digest of SIGARCH Messages.
Call for Papers: PAW-ATM 2025: Parallel Applications Workshop, Alternatives To MPI+X
Call for Papers: CogArch @ ISCA 2025
Call for Papers: ARC-LG’ @ ISCA 2025
Call for Papers: DRAMSec @ ISCA 2025
Call for Papers: Championship Branch Prediction (CBP2025) @ ISCA 2025
Call for Participation: ISCA 2025
https://www.iscaconf.org/isca2025/
Submitted by Akihiro Hayashi
52st International Symposium on Computer Architecture (ISCA 2025)
June 21–25, 2025
Tokyo, Japan, at Waseda University
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture.
ISCA is being held in Japan for the first time in 39 years, since it was last hosted in Tokyo in 1986. The program promises to be truly exciting, featuring not only forward-looking and novel technical paper presentations, but also a panel session with ISCA legends and a total of 33 tutorials and workshops.
We warmly invite you to join us!
Registration for the conference is now open at: https://www.iscaconf.org/isca2025/attend/register.php
(Early Registration Deadline: 11:59pm AoE, May 22, 2025)
For those of you requiring a Visa we strongly encourage to start the process as soon as possible.
Visa information is now available at: https://www.iscaconf.org/isca2025/attend/visa.php
For more details on ISCA 2025, please visit the main conference website at:
https://iscaconf.org/isca2025/
Call for Participation: The ASPLOS 2025 / EuroSys 2025 Contest Track
http://asplos-contest.org
Submitted by Michael D. Moffitt
The ASPLOS 2025 and EuroSys 2025 organizers are pleased to announce the ASPLOS 2025 / EuroSys 2025 Contest Track: a challenging, multi-month competition focused on advancing the state-of-the-art in multidisciplinary computer systems research. The high-level goals of this track are threefold:
For this inaugural event, the following two contest topics will run concurrently until March 1st, 2025:
If you have questions, please reach out to the contest organizers at asplos.contest@gmail.com.
Call for Participation: ISPASS 2025
https://ispass.org
Submitted by Stijn Eyerman
The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2025
May 11-13, 2025
Ghent, Belgium
ISPASS provides a forum for sharing advanced academic and industrial research focused on performance analysis in the design of computer systems and software.
We invite you to participate in the conference and tutorials. An overview of the accepted papers and tutorials can be found on https://ispass.org.
The website also contains information on the venue and travel, as well as the registration form. The early registration deadline with discounted fees is on April 11.
Call for Papers: MEMOCODE 2025
https://memocode2025.github.io/
Submitted by Geovani Benita
MEMCODE 2025 – 23rd ACM/IEEE International Symposium on Formal Methods and Models for System Design (FMCPS)
Part of ESWEEK 2025
October 02-03, 2025, TAIPEI, TAIWAN
MEMOCODE, originally a forum on methods and models for hardware-software codesign, has become a privileged forum to discuss on formal methods and models for the design of cyber-physical system and the verification of its safety and security requirements (FMCPS).
MEMOCODE’25 is a part of ESWEEK 2025, which will take place in Taipei, Taiwan. Registered attendees can attend sessions in any of the online events, including the conferences (CASES, CODES+ISSS, EMSOFT), symposia, tutorials, workshops, and education classes.
https://memocode2025.github.io/
https://esweek.org/memocode/
Selected accepted papers will be invited to extend their accepted papers for a special edition in a journal such as the ACM Transactions on Embedded Computing Systems (ACM TECS). See more on this at the end of this CFP.
Topics of interest
MEMOCODE solicits research papers on formal methods in system design that address the foundations, engineering methods, tools, or experimental case studies. Research areas of interest include, but are not limited to, the following:
Important Dates
Abstract submission deadline: April 28, 2025
Paper submission deadline: May 5, 2025
Notification of acceptance: Jul 8, 2025
Final version of papers: August 11, 2025
Submissions
MEMOCODE’25 calls for three kinds of submissions: regular papers, late-breaking results, and tool presentations. All papers must be written in English and formatted according to the ACM Sigconf style conference template. A double-blind review process will be enforced. Authors must not reveal their identity directly or indirectly. Submission of papers is handled via HotCRP.
For questions regarding technical submissions, feel free to contact one of the program committee co-chairs. All accepted papers (regular papers, late-breaking results, and tool papers) will be submitted for inclusion in ACM Digital Library. Publication in the proceedings is contingent on one author registering for and presenting the paper at the conference.
Outstanding Paper Award
A selection of papers will be recognized as outstanding papers and will be highlighted on the symposium website.
Special Edition for Journal
Selected accepted papers will be invited to extend their accepted papers (at least 30% extension over the accepted version) for a special edition in a journal such as the ACM Transactions on Embedded Computing Systems (ACM TECS) or Leibniz Transactions on Embedded Systems (LITES). Kindly follow the call for submissions for the special edition to check the relevant deadlines and timeline of the review process. Note that the extended version of the paper will go through a separate review process in the journal.
Organizing committee
General Chairs:
Claire Pagetti, ONERA, France
Nan Guan, City University of Hong Kong
Program Chairs:
Srinivas Pinisetty, Indian Institute of Technology Bhubaneswar, India
Sudipta Chattopadhyay, Singapore University of Technology and Design
Keynote Speakers:
Sanjay Lall, Stanford University
Naijun Zhan, Peking University
Call for Papers: IISWC 2025
https://iiswc.org/iiswc2025/cfp.html
Submitted by Dmitrii Ustiugov
IEEE International Symposium on Workload Characterization (IISWC) 2025
Overview:
IISWC invites manuscripts that present original, unpublished research in all areas related to the characterization and analysis of computing system workloads, including translational research related to production-oriented commercial systems. Work focusing on emerging technologies and interdisciplinary work are especially welcome.
Important Deadlines:
Paper Submission: June 21, 2025
Rebuttal Period: July 24, 2025 – July 31, 2025
Author Notification: August 12, 2025
Camera-ready Deadline: September 1, 2025
Submission Guidelines:
Topics:
For full details, submission guidelines, and artifact evaluation information, please visit the conference website.
Call for Papers: PACT 2025
http://wikicfp.com/cfp/servlet/event.showcfp?eventid=185980
Submitted by Rio Yokota
The International Conference on Parallel Architectures and Compilation Techniques (PACT) 2025
Irvine, California, USA
November 3-6, 2025.
Submission Site: https://pact25.hotcrp.com
Scope
The International Conference on Parallel Architectures and Compilation Techniques (PACT) is a unique technical conference at the intersection of hardware and software, with a special emphasis on parallelism. PACT brings together researchers from computer architectures, compilers, execution environments, programming languages, and applications to present and discuss their latest research results, tools, and practical experiences.
PACT seeks submissions in two categories:
– Research Papers
– Tools and Practical Experience (TPE) Papers
Research Papers
Research papers will be evaluated by the PACT Program Committee based on:
– Relevance: The paper should align with PACT’s topics of interest.
– Novelty/Originality: The work should present new ideas or offer fresh perspectives.
– Significance: The research should address an important problem and have the potential to influence future work.
– Results: The claims should be well-supported by clear and validated results.
– Comparison to Prior Work: The paper should properly discuss existing literature, highlighting similarities, differences, and improvements.
Tools and Practical Experience (TPE) Papers
TPE papers focus on practical applications, industry challenges, and experience reports. A TPE paper must clearly explain its functionality, summarize practical experience with realistic case studies, and describe any supporting artifacts. The title of a TPE paper must include the prefix “TPE:”. TPE papers follow the same submission guidelines and are reviewed by the same Program Committee as research papers.
TPE papers will be evaluated based on:
– Originality: They should present PACT-related technologies applied to real-world problems.
– Usability: The tool or software should have broad applicability and aid PACT-related research.
– Documentation: The tool/software should be well-documented on a public website.
– Benchmark Repository: A benchmark suite should be provided for testing.
– Availability: Preference is given to tools/software that are freely available, though industry/commercial tools may be considered with justification.
– Foundations: The paper should relate to PACT’s principles, though extensive theoretical discussion is not required.
Topics of Interest
PACT welcomes submissions on topics including, but not limited to:
– Parallel architectures, including accelerators for AI and other domains
– Compilers and tools for parallel architectures
– Applications and experimental studies of parallel processing
– Computational models for concurrent execution
– Multicore, multithreaded, superscalar, and VLIW architectures
– Compiler and hardware support for reducing memory latencies
– Support for correctness in hardware and software
– Reconfigurable parallel computing
– Dynamic translation and optimization
– I/O issues in parallel computing and their application impact
– Parallel programming languages, algorithms, and applications
– Middleware and runtime system support for parallel computing
– Application-specific parallel systems
– Distributed computing architectures and systems
– Heterogeneous systems leveraging various accelerators
– In-core and in-chip accelerators and their optimization
– Applications of machine learning to parallel computing
– Large-scale data processing, including in-memory computing accelerators
– Insights from modern parallel applications for architecture and compiler design
– Neuromorphic computing as both an application and a tool for architectures and compilers
– Quantum computing architectures and compilers
Submission Guidelines
Ensure that your submission meets the following requirements:
– Format: Papers are limited to 10 pages (excluding references) in ACM 8.5” x 11” format, double-column, 9pt font (e.g., using the `sigconf` LaTeX template). The text box must not exceed 7.15” x 9” (18.2cm x 22.9cm). Templates are available on the ACM Author Gateway (https://authors.acm.org/proceedings/production-information/taps-production-workflow).
– Abstract: Papers must include an abstract of under 300 words.
– Originality: Submissions must contain original material not previously published or under review elsewhere. Material presented at workshops without copyrighted proceedings may be submitted.
– TPE Papers: Must be prefixed with “TPE:” in the title.
– Double-Blind Review: The review process is double-blind to prevent bias. Submissions must not include author names, affiliations, or self-references that reveal authorship. Prior work by the authors must be cited in the third person.
– Legibility: Figures and graphs must be readable without magnification.
– Submission Format: Papers must be submitted in PDF format.
– Supplementary Material: A single anonymized PDF may be uploaded with additional proofs, results, or datasets. Reviewers are not required to consult supplementary material.
Posters:
– Poster submissions must follow the same formatting guidelines but are limited to 2 pages.
– Papers not accepted for full presentation will automatically be considered for posters unless authors opt out in their abstract submission.
– Two-page poster summaries will be included in the conference proceedings.
Artifact Evaluation
Authors of accepted papers are encouraged to submit their artifacts for evaluation. The Artifact Evaluation Committee assesses availability, functionality, and reproducibility. Successful artifacts will receive a seal of approval in the published paper. Authors can include a 2-page Artifact Appendix in the final paper.
We encourage authors to use open-source frameworks such as Docker, OCCAM, reprozip, CodeOcean, and Collective Knowledge to improve artifact portability and reproducibility.
Camera-Ready Instructions
– Page Limit: The final version must not exceed 11 pages, with an optional 2-page Artifact Appendix.
– Extra Pages: Up to 2 additional pages may be purchased for $200 per page.
Important Dates
– Abstract Submission Deadline: April 11, 2025 April 18, 2025 (Deadline extended)
– Paper Submission Deadline: April 18, 2025 April 25, 2025 (Deadline extended)
– Rebuttal Period: June 24-27, 2025
– Author Notification: July 28, 2025
– Artifact Submission: August 8, 2025
– Camera-Ready Deadline: September 15, 2025
All deadlines are firm at midnight anywhere on Earth (AoE).
We look forward to your submissions!
Call for Papers: ACM SYSTOR 2025
https://www.systor.org/2025
Submitted by Diana Cohen (publicity chair)
The 18th ACM International Systems and Storage Conference (SYSTOR 2025)
September 8 – 9, 2025
Virtual Event
In collaboration with the 2nd Israeli Systems & AI Workshop (ISW)
September 10, 2025,
IBM Haifa, Israel
The ACM International Systems and Storage Conference (SYSTOR) is an international forum for interaction across the systems research community. The program includes innovative, peer-reviewed research papers in the broad area of systems, as well as distinguished keynote lecturers, and a poster session.
ACM SYSTOR is designed to engage academic and industrial researchers and practitioners, welcoming both students and seasoned professionals.
SYSTOR has traditionally welcomed academic and industrial papers in systems, including storage, cloud and distributed systems, networking, AI systems and systems security. SYSTOR encourages submissions that describe results from experimental system prototypes, as well as experience papers describing practical deployments and valuable lessons learned from them.
Topics of interest include, but are not limited to:
SYSTOR Tracks
The Israeli Systems & AI Workshop:
Important Dates (AoE)
Organizing Committee
Program Chairs:
Pramod Bhatotia (TU Munich, Germany)
Binoy Ravindran (Virginia Tech, USA)
General Chairs:
Amit Golander (Tel Aviv University, Israel)
Joel Nider (UnifabriX, Israel)
Call for Papers: LCTES 2025
https://pldi25.sigplan.org/home/LCTES-2025
Submitted by Seonyeong Heo
26th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2025).
co-located with PLDI 2025
16 – 20 June 2025
Seoul, South Korea
LCTES provides a link between the programming languages and embedded systems engineering communities. Researchers and developers in these areas are addressing many similar problems but with different backgrounds and approaches. LCTES is intended to expose researchers and developers from either area to relevant work and interesting problems in the other area and provide a forum where they can interact. Research papers on innovative techniques are welcome, as well as experience papers on insights obtained by experimenting with real-world systems and applications.
We enthusiastically look forward to your submissions on programming languages, compilers, tools, theory, and architectures that help in overcoming technical challenges in embedded systems and their emerging applications.
Important Dates:
(All times are UTC-12, or “anywhere on earth”)
Paper Categories:
Links:
Call for Papers: ASPLOS 2026
https://asplos26-spring.hotcrp.com/
Submitted by Benjamin Lee
ASPLOS, the ACM International Conference on Architectural Support for Programming Languages and Operating Systems, is the premier academic forum for multidisciplinary applied computer systems research spanning hardware, software, and their interaction. It focuses on practical aspects of computer architecture, programming languages, operating systems, and associated areas such as networking and storage.
Submission Information
Two submission deadlines – spring and summer. As in recent years, ASPLOS 2026 will allow the authors of some submissions to choose to apply a major revision to their submission in order to fix a well-defined list of problems.
More information is available at https://www.asplos-conference.org/asplos2026/cfp/
Important Dates
Submission website: https://asplos26-spring.hotcrp.com/
Call for Papers: FPL 2025
https://2025.fpl.org/
Submitted by Christian Pilato
The 35th International Symposium on Field-Programmable Logic and Applications (FPL 2025)
September 1 – 5, 2025,
Leiden, The Netherlands
The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference dedicated to the rapidly growing field of field-programmable logic and reconfigurable computing. Over the past 34 years, many key advances in reconfigurable system architectures, applications, embedded processors, design automation methods, and tools have been first published in the FPL conference proceedings. The conference brings together researchers and practitioners from academia and industry worldwide.
Submission Information
Prospective authors are invited to submit original, unpublished papers in IEEE double-column format.
– Long papers may include up to eight pages plus up to two pages for references.
– Short papers are limited to four pages plus, at most, one additional page for references.
These limits are strict; submissions exceeding them will be automatically rejected. Conference proceedings will be published in IEEE Xplore.
Submission link: https://easychair.org/conferences?conf=fpl2025.
More detailed submission information: https://2025.fpl.org/calls/call-for-papers/.
Authors of selected papers will be invited to submit extended versions for a Special Issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS) dedicated to FPL 2025.
Important Dates
Topics of Interest
We welcome contributions on (but not limited to) the following topics related to FPL:
– Architectures and Technology
– Application Acceleration
– Programming Models and Languages
– System Software and Environment Support
– Design Methods and Tools
– Safety-Critical Applications
– High-Performance Computing
– Security of Reconfigurable Systems
– Surveys
Organizing Committee
General Chairs:
Nele Mentens (Leiden University, The Netherlands)
Todor Stefanov (Leiden University, The Netherlands)
Program Chairs:
Mirjana Stojilovic (EPFL, Switzerland)
Dirk Stroobandt (Ghent University, Belgium)
Nusa Zidaric (Leiden University, The Netherlands)
Call for Papers: EuroSys 2026
https://2026.eurosys.org/index.html
Submitted by Jingjie Li
EuroSys is a premier international forum for presenting computer systems research, bringing together professionals from academia and industry. EuroSys 2026 seeks papers in all areas of computer systems research, including the list of topics below, that address significant problems with compelling and practical solutions.
https://2026.eurosys.org/index.html
Topics of Interest
Important Dates:
Spring deadline
Fall deadline
Call for Papers: ICS 2025 (Cycle 2)
Submitted by Wenqian Dong
ICS serves as the premier international forum for presenting research results in high-performance computing systems.
Topics of interest
Papers are solicited on all aspects of the architecture, software, and applications of high-performance computing systems of all scales (from chips to supercomputing systems), including but not limited to:
Call for Papers: PAW-ATM 2025: Parallel Applications Workshop, Alternatives To MPI+X
https://sourceryinstitute.github.io/PAW/
Submitted by Karla Vanessa Morris Wright
PAW-ATM 2025: Parallel Applications Workshop, Alternatives To MPI+X
Held in conjunction with SC25, St. Louis, MO
https://sourceryinstitute.github.io/PAW/
Summary
As supercomputers become more and more powerful, the number and diversity of applications that can be tackled with these machines grow. Unfortunately, the architectural complexity of these supercomputers grows as well, with heterogeneous processors, multiple levels of memory hierarchy, and many ways to move data and synchronize between processors. The MPI+X programming model, use of which is considered by many to be standard practice, demands that a programmer be expert in both the application domain and the low-level details of the architecture(s) on which that application will be deployed, and the availability of such superhuman programmers is a critical bottleneck. Things become more complicated when evolution and change in the underlying architecture translates into significant re-engineering of the MPI+X code to maintain performance. Numerous alternatives to the MPI+X model exist, and by raising the level of abstraction on the application domain and/or the target architecture, they offer the ability for “mere mortal” programmers to take advantage of the supercomputing resources that are available to advance science and tackle urgent real-world problems.
However, compared to the MPI+X approach, these alternatives generally lack two things. First, they aren’t as well known as MPI+X and a domain scientist may simply not be aware of models that are a good fit to their domain. Second, they are less mature than MPI+X and likely have more functionality or performance “potholes” that need only be identified to be addressed. PAW-ATM is a forum for discussing HPC applications written in alternatives to MPI+X. Its goal is to bring together application experts and proponents of high-level languages to present concrete example uses of such alternatives, describing their benefits and challenges.
Topics of interest include, but are not limited to:
Submissions
Submissions are solicited in two categories:
Important Dates
Committee
Workshop Chair: Karla Vanessa Morris Wright – Sandia National Laboratories
Organizing committee
Program committee co-chairs
Call for Papers: CogArch @ ISCA 2025
https://cogarchworkshop.org
Submitted by Karthik Swaminathan
CogArch 2025 (organized by IBM Research)
Co-located with ISCA 2025
Sunday, June 22, 2025
Tokyo, Japan
The CogArch workshop emphasizes the challenges associated with the implementation of generative AI and the integration of chiplets as a means to fully realize its potential. As generative AI models continue to expand in size and complexity, the resulting computational demands impact the entire software-hardware ecosystem. This creates a variety of new challenges that necessitate unconventional strategies to maintain scalability in both upward and outward directions. With Large Language Model (LLM) parameter sizes approaching several billions, chiplet-based architectures represent a promising technological advancement that could enable a cost-effective and energy-efficient solution for processing such models, thus potentially transforming the future landscape of cognitive systems.
The CogArch workshop solicits formative ideas and new product offerings in the general space of AI systems that covers all the design aspects of cognitive systems, with particular focus this year on the adoption of chiplets as a promising way to support large-scale generative AI.
Topics of interest include (but are not limited to):
→ Accepted works will have the chance to be published in one of the leading journals in computer architecture.
Important dates:
Organizers:
Call for Papers: ARC-LG’ @ ISCA 2025
https://llm-gnn.org/
Submitted by Pavana Prakash
Workshop on New Approaches for Addressing the Computing Requirements of LLMs and GNNs (ARC-LG’) 2025
Co-located with ISCA 2025
Overview:
Training and deploying huge machine learning models, such as GPT, Llama, or large GNNs, require a vast amount of compute resources, power, storage, memory. The size of such models is growing exponentially, as is the training time and the resources required. The cost to train large foundation models has become prohibitive for everyone but very few large players. While the challenges are most visible in training, similar considerations apply to deploying and serving large foundation models for a large user base.
The proposed workshop aims to bring together AI/ML researchers, computer architects, and engineers working on a range of topics focused on training and serving large ML models. The workshop will provide a forum for presenting and exchanging new ideas and experiences in this area and to discuss and explore hardware/software techniques and tools to lower the significant barrier of entry in the computation requirements of AI foundation models.
Submissions:
Authors can submit either 8-page full papers or up to 4-page short papers. In the short paper format, out-of-the box ideas and position papers are especially encouraged.
See the website for submission details.
Topics:
The workshop will present original works in areas such as (but not inclusive to): workload characterization, inference serving at scale, distributed training, novel networking and interconnect approaches for large AI/ML workloads, addressing resilience of large training runs, data reduction techniques, better model partitioning, data formats and precision, efficient hardware and competitive accelerators.
Call for Papers: DRAMSec @ ISCA 2025
https://dramsec.ethz.ch
Submitted by Tracy Ewen
The Fifth Workshop on DRAM Security (DRAMSec 2025)
co-located with ISCA 2025
Tokyo, Japan
June 21, 2025.
We’re soliciting papers on attacks and defenses on current and future DRAM technologies. We also welcome experimental papers describing tools and methodologies for testing DRAM security. We’ll favor papers that bring new insights, debunk previously held beliefs, re-visit assumptions, present new attacks and defenses, replicate prior art, or put forward controversial points of view. We will also consider position papers, especially from the industry, that outline design and process challenges affecting DRAM security or describe state-of-the-art DRAM defenses.
https://dramsec.ethz.ch/cfp.html
Submission deadline: May 1, 2025
Submission site: https://dramsec25.hotcrp.com/
Workshop chairs: Onur Mutlu (ETH Zürich), Kuljit Bains (NVIDIA)
Submissions and Web Chairs: Nisa Bostancı (ETH Zürich), Abdullah Giray Yağlıkçı (ETH Zürich)
Call for Papers: Championship Branch Prediction (CBP2025) @ ISCA 2025
https://ericrotenberg.wordpress.ncsu.edu/cbp2025
Submitted by Eric Rotenberg
CBP2025 Committee
Organizing Committee: Rami Sheikh (ARM), Saransh Jain (ARM)
Program Chair: Eric Rotenberg (NCSU)
Call for Papers: CogArch @ ISCA 2025
https://cogarchworkshop.org
Submitted by Augusto Vega
9th workshop on Cognitive Architectures (CogArch 2025)
co-located with ISCA 2025
Tokyo, Japan
CogArch solicits formative ideas and new product offerings in the general space of AI systems that covers all the design aspects of cognitive systems, with particular focus this year on the adoption of chiplets as a promising way to support large-scale generative AI.
Topics of interest include (but are not limited to):
Important Dates
Program Committee
Call for Papers: IWLS 2025
https://www.iwls.org/iwls2025/
Submitted by Petr Fišer
The 34th International Workshop on Logic & Synthesis (IWLS 2025)
University of Verona, Verona, Italy
June 12–13, 2025,
Website: www.iwls.org
The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.
Topics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.
The workshop format includes paper presentations, invited talks, social lunch and dinner gatherings, and recreational activities.
Important Dates
Paper abstract submission deadline: March 21, 2025 (AoE)
Full paper submission deadline: March 28, 2025 (AoE)
Notification of acceptance: May 3, 2025
Final version due: May 30, 2025
Submission Instructions
Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages (reference excluded), double column, 10-point font (we recommend using the ACM template or the IEEE template, but not necessarily). Accepted papers are distributed only to IWLS participants.
Double-blind policy: IWLS uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered.
Submission site: EasyChair
IWLS 2025 Programming Contest
The competition this year is a continuation of the IWLS competitions held in the last three years. The decision to continue the competition is based on the observation that the quality of the results has not saturated. Indeed, the competition started in 2022, and the results produced by the participants in 2023 were on average 15% better than those in 2022. Similarly, the results in 2024 were on average 8% better than those in 2023. It will be interesting to see how much progress will be achieved this year.
For details, please check out the call for submissions for the programming contest below.
IWLS 2025 Programming Contest Call for Submissions and the IWLS webpage: www.iwls.org
Submission deadline: June 5, 2025 (AoE)
Organizing Committee
General Chair: Valentina Ciriani, University of Milan
Program Committee Chairs: Walter Lau Neto, Synopsys Weikang Qian, Shanghai Jiao Tong University
Programming Contest Chairs: Alan Mishchenko, UC Berkeley Alessandro Tempia Calvino, Synopsys
Special Session Chair: Tiziano Villa, University of Verona
Finance Chair: Lana Josipović, ETH Zurich
Proceedings Chair: Anna Bernasconi, University of Pisa
Publicity Chairs: Petr Fišer, CTU in Prague Jiahui Xu, ETH Zurich
Local Arrangements Chairs: Tiziano Villa, University of Verona Davide Quaglia, University of Verona Asma Taheri Monfared, University of Bergamo
Technical Program Committee
Luca Amarù, Synopsys
Anna Bernasconi, University of Pisa
Lei Chen, Huawei Noah’s Ark Lab
Zhufei Chu, Ningbo University
Valentina Ciriani, University of Milan
Fabrizio Ferrandi, Politecnico di Milano
Petr Fišer, CTU in Prague
Aman Gayasen, AMD
Winston Haaswijk, Cadence Design Systems
Jie-Hong Roland Jiang, National Taiwan University
Attila Jurecska, Siemens EDA
Victor Kravets, IBM
Chang Meng, EPFL
Giulia Meuli, Synopsys
Shin-ichi Minato, Kyoto UniversityAlan Mishchenko, UC Berkeley
Walter Lau Neto, Synopsys
Augusto Neutzling, Real Intent
Stefan Nikolić, University of Novi Sad
Weikang Qian, Shanghai Jiao Tong University
Stefano Quer, Politecnico di Torino
Andre Reis, UFRGS
Tsutomu Sasao, Meiji University
Herman Schmit, Google
Eleonora Testa, Synopsys
Gabriella Trucco, University of Milan
Tiziano Villa, University of Verona
Robert Wille, TU Munich & SCCH GmbH
Cunxi Yu, University of Maryland
Mingfei Yu, EPFL
Call for Papers: LATTE 2025
https://capra.cs.cornell.edu/latte25/
Submitted by Adrian Sampson
Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE) 2025
co-located with ASPLOS 2025
Rotterdam, Amsterdam
https://capra.cs.cornell.edu/latte25/
LATTE is a venue for discussion, debate, and brainstorming at the intersection of hardware acceleration and programming languages research. The core mission is to bring ideas we love from software programming
languages and tools to the world of hardware design
Important Dates
Paper submission: January 31, 2025
Author Notification: February 14, 2025
Workshop: March 30, 2025
Submit your 2-page position paper. Further details on the website.
Call for Presentations: ModSim 2025
https://www.bnl.gov/modsim/
Submitted by Jason Lowe-Power
Workshop on Modeling & Simulation of Systems and Applications (ModSim) 2025
August 13-15, 2025,
University of Washington Botanic Gardens Center for Urban Horticulture, Seattle
Workshop URL: https://www.bnl.gov/modsim/
Submission URL: https://easychair.org/conferences/?conf=modsimworkshop2025
Important Dates
EasyChair Submission Deadline: Monday, May 26, 2025 (11:59 pm PDT; 6:59 am UTC)
Notification of Acceptance: Monday, June 9, 2025 (via e-mail)
To promote advancements in modeling and simulation (ModSim) research, we are soliciting input in the form of abstracts. If accepted, author(s) will be invited to host a short presentation and/or poster at the annual gathering of our community, the Workshop on Modeling & Simulation of Systems and Applications (ModSim 2025). This year’s workshop theme is Modeling and Simulation for Extreme Computing in the AI Era. The emphasis will be on emerging and revolutionary new technologies and architectures for computing of AI workloads. ModSim for processors and system architectures design and optimization that scale and perform at the pace of AI, including novel AI-driven methodologies for ModSim, as well as tools, best practices, and new directions will be showcased and discussed throughout the workshop. As always, projects and initiatives that address computing challenges in the AI Era and aim to advance the state-of-the-art in modeling performance, power, and reliability of extreme computing will be represented. Specific areas of interest are further defined in the Topic Areas subsection of this call. Submissions related to this year’s workshop theme, imparting lessons learned from specific projects, methods, tools, and use cases, are highly encouraged. Domestic travel to ModSim 2025 may be available for full-time students at U.S.-based academic institutions, supported by a National Science Foundation travel grant.
Topic Areas:
Abstract contributions should relate to the workshop theme Modeling and Simulation for Extreme Computing in the AI Era. Within the overall theme, subcategories of interest include:
Call for Presentations: OSCAR @ ISCA 2025
https://oscar-workshop.github.io/
Submitted by Luca Carloni
Fourth Workshop on Open-Source Computer Architecture Research (OSCAR) 2025
Co-located with ISCA 2025 in Tokyo, Japan
https://oscar-workshop.github.io/
OSCAR 2025 marks the fourth edition of a workshop dedicated to fostering a community of researchers interested in developing and sharing open-source hardware and software for designing next-generation computer architectures.
Recent years have seen significant progress in this direction, with the contributions of hardware components, software tools, and integration platforms to simplify the realization of system prototypes with FPGA or ASIC technologies. The number of developers and users of these open-source artifacts has increased substantially. OSCAR provides a venue that promotes the growth of this community and fosters its effort.
Scope: Topics of interest of the OSCAR workshop include, but are not limited to:
Workshop Format: OSCAR will feature a mix of invited talks and presentations selected from submissions to this call for participation. Abstracts should be submitted in PDF format (max 2 pages) and must include a title, author names and affiliations, and the contact author’s e-mail address. Including the URL of the release website for the open-source contribution described in the abstract is recommended. Submissions of early work and position papers are encouraged. Workshop submissions do not preclude future publications. While no formal proceedings are planned, the OSCAR organizers may explore the possibility a journal special issue featuring a subset of the contributions, after the workshop.
Important Dates:
Organizers:
Call for Workshops/Tutorials: MLArchSys @ ISCA 2025
https://sites.google.com/view/mlarchsys
Submitted by Amir Yazdanbakhsh
Workshop on Machine Learning for Computer Architecture and Systems (MLArchSys 2025)
co-located with ISCA 2025
Tokyo, Japan
Foundation models have become the foundation of a new wave of machine learning models. The application of such models spans from natural language understanding into image processing, protein folding, and many more. The main objective of this workshop is to bring the attention of machine learning and system communities to the upcoming architectural and system challenges for the foundational models and drive the productive usage of these models in chip design process and system design.
Topics of interest include (but are not limited to):
Areas: Computer Architecture, Systems, Compilers, Model Scaling, Security, Self-Attention, Foundational Models, EDA, Foundational Model Compression.
Important Dates:
Full Paper Submission Deadline: April 25nd, 2025, 11:59 AoE (OpenReview)
Author Notification: May 16th, 2025, 11:59 AoE.
Workshop: June 21, 2025 (Tokyo, Japan).
Call for Workshops/Tutorials: ICS 2025
Submitted by Wenqian Dong
The 39th ACM International Conference on Supercomputing (ICS) 2025 : Call for Proposals of Workshop and Tutorials
Salt Lake City, Utah, USA
June 9th-11th, 2025
https://hpcrl.github.io/ICS2025-webpage/
We are soliciting proposals for workshops and tutorials to be held in conjunction with ICS’25, which will be held from 9th to 11th June, 2025, at Salt Lake City, Utah, U.S.A. The scope of workshops and tutorials includes, but is not limited to, supercomputing related topics listed in ICS’25 call for papers, as well as other topics such as education and emerging technologies and their trends.
Schedule:
Deadline for proposals: January 31, 2025
Acceptance notification: February 21, 2025
Workshops and tutorials: June 8, 2025
ICS’25 conference: June 9-11, 2025
Details for workshops and tutorials:
Submission Details:
To submit a workshop proposal, please prepare a PDF file (2 pages max, excluding biographies and references), including the following information:
Episode 19 of the Computer Architecture Podcast Released! Featuring Guest Dr. Arkaprava Basu, IISC
https://www.podbean.com/eas/pb-2exda-1846e61
Submitted by Lisa Hsu
Computer Architecture Podcast: a series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.
Announcing the release of Episode 19: Memory Management and Software Reliability with Dr. Arkaprava Basu, who is an Associate Professor at the Indian Institute of Science, where he mentors students in the Computer Systems Lab. Arka’s research focuses on pushing the boundaries of memory management and software reliability for both CPUs and GPUs. His work spans diverse areas, from optimizing memory systems for chiplet-based GPUs to developing innovative techniques to eliminate synchronization bottlenecks in GPU programs. He is also a recipient of the Intel Rising Star Faculty Award, ACM India Early Career Award, and multiple other accolades, recognizing his innovative approaches to enhancing GPU performance, programmability, and reliability.
Listen to the episode at https://comparchpodcast.podbean.com. Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.
Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.
- Akanksha Jain
SIGARCH Content Editor