Call for Papers: Bench 2023
https://www.benchcouncil.org/bench2023/index.html
Submitted by Biwei Xie

The 15th BenchCouncil International Symposium on Benchmarking, Measuring and Optimizing (Bench 2023)
In conjunction with Federated Intelligent Computing and Chip Conference (FICC 2023)
https://www.benchcouncil.org/bench2023/index.html

Full Papers: July 31, 2023, at 11:59 PM AoE
Notification: September 30, 2023, at 11:59 PM AoE
Final Papers Due: October 31, 2023, at 11:59 PM AoE
Conference Date: December 3-5, 2023
Venue: Sanya, China.

Please note that citizens from up to 59 nations can visit Sanya without a Visa from the Chinese Government. Sanya is a beautiful seaside city, well known as Hawaii in China.

Submission website: https://bench2023.hotcrp.com/

Introduction

Evolving from nine BPOE/SDBA workshops in conjunction with ASPLOS, VLDB, and ICS, Bench is an international multidisciplinary conference on benchmarks, standards, data sets, evaluation, and optimization. Bench 2023 is the fifteenth edition. The Bench conference encompasses a wide range of topics in benchmarks, datasets, metrics, indexes, measurement, evaluation, optimization, supporting methods and tools, and industry best practices in computer science, AI, medicine, finance, education, management, etc. Bench’s multidisciplinary and interdisciplinary emphasis provides an ideal environment for developers and researchers from different areas and communities to discuss practical and theoretical work.

Bench 2023 invites manuscripts describing original work in the above areas and topics (Call for Papers). All accepted papers will be presented at the Bench 2023 conference and published by Springer LNCS (Pending, Indexed by EI). At least one of the authors of the TBench articles published last year is requested to present their work at the Bench conference.

Regularly, the Bench conference will present the BenchCouncil Achievement Award ($3000), the BenchCouncil Rising Star Award ($1000), the BenchCouncil Best Paper Award ($1000), and the BenchCouncil Distinguished Doctoral Dissertation Awards in Computer Architecture ($1000) and in other areas ($1000). This year, the BenchCouncil Distinguished Doctoral Dissertation Award includes two tracks: computer architecture and other areas. Among the submissions of each track, four candidates will be selected as finalists. They will be invited to give a 30-minute presentation at the Bench 2023 Conference and contribute research articles to BenchCouncil Transactions on Benchmarks, Standards and Evaluation. Finally, for each track, one among the four will receive the award for each track, which carries a $1,000 honorarium.

With generous support from BenchCouncil, Bench 2023 will offer travel grants for students to defray a portion of their travel cost. The size and number of these grants will vary depending on funding availability, the number of student applicants, and their respective priority. Grant awards will be made before the early registration deadline; expenses will be reimbursed after the conference; grant recipients will be asked to submit original receipts to verify their expenditures as well as a 1-page summary of their involvement during the conference. While we encourage all in need of a travel grant to apply, the selection process will give higher priority to students who would otherwise not be able to attend the conference. We strongly encourage applications from students that belong to under-represented groups.

Organization

General Co-Chairs
Rakesh Agrawal, Data Insights Laboratories, San Jose, CA, USA
Aoying Zhou, East China Normal University

Program Co-Chairs
Weining Qian, East China Normal University
Sascha Hunold, TU Wien, Austria

Program Vice-Chairs
Biwei Xie, Institute of Computing Technology, CAS
Kai Shu, Illinois Institute of Technology

Web Chair
Jiahui Dai, BenchCouncil

Technical Program Committee(continuously updated):
Bin Ren, William & Mary
Guangli Li, Institute of Computing Technology, Chinese Academy of Sciences
Gwangsun Kim, POSTECH
Khaled Ibrahim, Lawrence Berkeley National Laboratory
Mario Marino, Leeds Beckett University
Miaoqing Huang, University of Arkansas
Murali Emani, Argonne National Laboratory
Vladimir Getov, University of Westminster
Woongki Baek, UNIST
Xiaoyi Lu, University of California, Merced
Zhen Jia, Amazon
Steven Farrell, Lawrence Berkeley National Laboratory

Award Committees

2023 BenchCouncil Achievement Award Committee:
Prof. D. K. Panda, the Ohio State University
Prof. Lizy Kurian John, the University of Texas at Austin
Prof. Geoffrey Fox, Indiana University
Prof. Jianfeng Zhan, University of Chinese Academy of Sciences
Prof. Tony Hey, Rutherford Appleton Laboratory STFC (Since 2020)
Prof. David J. Lilja, University of Minnesota, Minneapolis (Since 2021)
Prof. Jack J. Dongarra, University of Tennessee (Since 2022)
John L. Henning, Oracle (Since 2023)

2023 BenchCouncil Rising Star Award Committees:
Prof. D. K. Panda, the Ohio State University
Prof. Lizy Kurian John, the University of Texas at Austin
Prof. Geoffrey Fox, Indiana University
Prof. Jianfeng Zhan, University of Chinese Academy of Sciences
Prof. Torsten Hoefler, ETH Zürich (Since 2021)
Prof. Vijay Janapa Reddi, Harvard University (Since 2022)
Dr. Peter Mattson, Google, USA (Since 2022)
Dr. Wanling Gao , ICT, Chinese Academy of Sciences (pending)
Dr. Douwe Kiela, Stanford University (Since 2023)

BenchCouncil Distinguished Doctoral Dissertation Award Committee in Other Areas:
Prof. Jack Dongarra, University of Tennessee
Dr. Xiaoyi Lu, The University of California, Merced
Dr. Jeyan Thiyagalingam, STFC-RAL
Dr. Lei Wang, ICT, Chinese Academy of Sciences
Dr. Spyros Blanas, The Ohio State University

BenchCouncil Distinguished Doctoral Dissertation Award Committee in Computer Architecture:
Prof. Resit Sendag, University of Rhode Island, USA
Dr. Peter Mattson, Google
Dr. Vijay Janapa Reddi, Harvard University
Dr. Wanling Gao, Chinese Academy of Sciences

Bench Steering Committees

Prof. Dr. Jack Dongarra, University of Tennessee
Prof. Dr. Geoffrey Fox, Indiana University
Prof. Dr. D. K. Panda, The Ohio State University
Prof. Dr. Felix, Wolf, TU Darmstadt.
JProf. Dr. Xiaoyi Lu, University of California, Merced
Prof. Dr. Resit Sendag, University of Rhode Island, USA
Dr. Wanling Gao, ICT, Chinese Academy of Sciences & UCAS
Prof. Dr. Jianfeng Zhan, BenchCouncil

Call for papers

The Bench conference encompasses a wide range of topics in benchmarks, datasets, metrics, indexes, measurement, evaluation, optimization, supporting methods and tools, and other best practices in computer science, medicine, finance, education, management, etc. Bench’s multidisciplinary and interdisciplinary emphasis provides an ideal environment for developers and researchers from different areas and communities to discuss practical and theoretical work. The topics of interest include, but are not limited to the following:

— Benchmark science and engineering across multi-disciplines: The formulation of problems or challenges in emerging and future computing; The benchmarks, datasets, and indexes in multidisciplinary applications, e.g., medical, finance, education, management, psychology, etc; Benchmark-based quantitative approaches to tackle multidisciplinary and interdisciplinary challenges; Industry best practices.

— Benchmark and standard specifications, implementations, and validations: Big Data, Artificial intelligence (AI), High performance computing (HPC), Machine learning, Big scientific data, Datacenter, Cloud, Warehouse-scale computing, Mobile robotics, Edge and fog computing, Internet of Things (IoT), Blockchain, Data management and storage, Financial, Education, Medical or other application domains.

— Dataset: Detailed descriptions of research or industry datasets, including the methods used to collect the data and technical analyses supporting the quality of the measurements; Analyses or meta-analyses of existing data and original articles on systems, technologies, and techniques that advance data sharing and reuse to support reproducible research; Evaluating the rigor and quality of the experiments used to generate the data and the completeness of the data description; Tools that can generate large-scale data while preserving their original characteristics.

— Workload characterization, quantitative measurement, design, and evaluation studies: Computer and communication networks, protocols and algorithms; Wireless, mobile, ad-hoc and sensor networks, IoT applications; Computer architectures, hardware accelerators, multi-core processors, memory systems and storage networks; HPC systems; Operating systems, file systems and databases; Virtualization, data centers, distributed and cloud computing, fog and edge computing; Mobile and personal computing systems; Energy-efficient computing systems; Real-time and fault-tolerant systems; Security and privacy of computing and networked systems; Software systems and services, and enterprise applications; Social networks, multimedia systems, web services; Cyber-physical systems, including the smart grid.

— Methodologies, metrics, abstractions, algorithms, and tools: Analytical modeling techniques and model validation; Workload characterization and benchmarking; Performance, scalability, power and reliability analysis; Sustainability analysis and power management; System measurement, performance monitoring and forecasting; Anomaly detection, problem diagnosis and troubleshooting; Capacity planning, resource allocation, run time management and scheduling; Experimental design, statistical analysis, and simulation.

— Measurement and evaluation: Measurement standards; Evaluation methodologies and metrics; Testbed methodologies and systems; Instrumentation, sampling, tracing and profiling of large-scale, real-world applications and systems; Collection and analysis of measurement data that yield new insights; Measurement-based modeling (e.g., workloads, scaling behavior, assessment of performance bottlenecks); Methods and tools to monitor and visualize measurement and evaluation data; Systems and algorithms that build on measurement-based findings; Advances in data collection, analysis and storage (e.g., anonymization, querying, sharing); Reappraisal of previous empirical measurements and measurement-based conclusions; Descriptions of challenges and future directions that the measurement and evaluation community should pursue.

Paper Submission

Papers must be submitted in PDF. For a full paper, the page limit is 15 pages in the LNCS format, not including references. For a short paper, the page limit is 8 pages in the LNCS format, not including references. The review process follows a strict double-blind policy per the established Bench conference norms. The submissions will be judged based on the merit of the ideas rather than the length. After the conference, the proceedings will be published by Springer LNCS (Pending, Indexed by EI). Please note that the LNCS format is the final one for publishing.

At least one author must pre-register for the symposium, and at least one author must attend the symposium to present the paper. Papers for which no author is pre-registered will be removed from the proceedings.

Formatting Instructions

Please make sure your submission satisfies ALL of the following requirements:
· All authors and affiliation information must be anonymized.
· Paper must be submitted in printable PDF format.
· Please number the pages of your submission.
· The submission must be formatted for black-and-white printers. Please make sure your figures are readable when printed in black and white.
· The submission must describe unpublished work that is not currently under review of any other conference or journal venues.

Submission site: https://bench2023.hotcrp.com/
LNCS latex template: https://www.benchcouncil.org/file/llncs2e.zip

Awards

BenchCouncil Achievement Award ($3,000)
– This award recognizes a senior member who has made long-term contributions to benchmarking, measuring, and optimizing. The winner is eligible for the status of a BenchCouncil Fellow.

BenchCouncil Rising Star Award ($1,000)
– This award recognizes a junior member who demonstrates outstanding potential for research and practice in benchmarking, measuring, and optimizing.

BenchCouncil Best Paper Award ($1,000)
– This award recognizes a paper presented at the Bench conferences, which demonstrates potential impact on research and practice in benchmarking, measuring, and optimizing.

BenchCouncil Distinguished Doctoral Dissertation Award ($2000)
– This award recognizes and encourages superior research and writing by doctoral candidates in the broad field of benchmarks, data, standards, evaluations, and optimizations community. This year, the award includes two tracks, including the BenchCouncil Distinguished Doctoral Dissertation Award in Computer Architecture ($1000) and BenchCouncil Distinguished Doctoral Dissertation Award in other areas ($1000).

Call for Papers: The 14th International Green and Sustainable Computing (IGSC) 2023
https://www.igscc.org/
Submitted by Dakai Zhu

CALL FOR PAPERS

The International Green and Sustainable Computing (IGSC) Conference provides a forum for presenting and discussing innovative research on a broad range of topics in the fields of sustainable and energy-efficient computing and computing for a more sustainable planet. This year’s conference will be held in Toronto, Canada, October 28-29, co-located with MICRO 2023. IGSC’23 consists of technical papers, panels, workshops, and a PhD Forum on these topics. Topics of interest include, but are not limited to:

Design and Implementation of HW/SW Platforms

• Self-sustaining sensing and edge computing
• Power-aware middleware solutions
• Efficient circuit design and domain-specific architectures for energy harvesting
• Low-power/thermal-aware systems, circuits, and architectures (e.g., embedded and CPS systems, ASICs, reconfigurable computing, on-chip networks)
• Power-aware neuromorphic systems
• Integrated operation of heterogeneous computing cores
• Low-power memory systems

Energy-Aware and Thermal-Aware Resource Management Algorithms

• Smart control for reduced energy and power
• Advanced and predictive models for energy, power and temperature
• Power-aware scheduling for real-time systems
• Software-defined networking for energy-efficient distributed systems
• Data analytics for energy efficiency

Application Design and Methodologies

• Sensor networks for climate and ecosystem monitoring
• Self-organized multiagent systems
• Smart grids, smart cities, smart manufacturing
• Intelligent transportation systems
• Autonomous and mobile systems
• Renewable energy systems
• Data center optimization and management
• Management of cloud computing systems

Paper submission guidelines:

IGSC 23 welcomes submissions that have not been published and that are not under review by other conferences or journals. All submissions will be rigorously evaluated on their originality, technical soundness, significance, presentation, and interest to the conference attendees.

The conference provides 2 tracks for technical papers: a regular paper track and a concept/position/WiP paper track. The page limit for the regular track submissions is 6 pages. The page limit for the concept/position/WiP track is 2 pages. Please refer to the IGSC website (https://www.igscc.org/) for specific instructions related to paper submission. IGSC bestows a best paper award as selected by a technical committee.

• IEEE template: https://www.ieee.org/conferences/publishing/templates.html
• The HotCRP system will be used to handle papers for this conference. Please follow these steps:

1. Set up an IGSC HotCRP account if you don’t already have one, at https://igsc23.hotcrp.com
2. Log into the conference website for IGSC23: https://igsc23.hotcrp.com and follow the instructions on that page.

Paper publication:

We will publish papers in IEEE Xplore.

Trending Topics and Special Sessions 2023:

IGSC seeks proposals for Trending Topics and/or Special Sessions. Proposals for Special Sessions should include biosketches of the proposers, a brief description of the proposed topic and its importance, and a list of potential speakers/authors in the Special Session. Please submit Special Session proposals to one of the TPC Co-Chairs.

Workshops:

Meetings formerly held as workshops will be held in conjunction with the conference, possibly as a special track. Proposals should be submitted to one of the Workshops Co-Chairs.

Student Research Forum:

The forum solicits extended abstract submissions from MS and doctoral students engaged in research on sustainable and energy-efficient computing as well as poster and project demos from all researchers, faculty, and students. Please refer to the IGSC website for submission instructions.

Industrial Partners:

The conference seeks industry partners and sponsors with opportunities for them to showcase their technologies. Please contact one of the General Co-Chairs.

Important dates:

Conference paper submission: June 18, 2023

(To help us plan ahead, prior abstract submission by June 11 is encouraged but certainly NOT mandatory. All papers submitted by June 18 will be fully considered.)

Reviewer deadline: July 16, 2023

Deadline for submitting Workshop and Special Session proposals: June 21, 2023

Deadline for submitting to Student Research Forum: See Research Forum Page

Notifications to authors: August 15, 2023

Conference Website: https://www.igscc.org/

Call for Papers: ICCD 2023
https://www.iccd-conf.com/Home.html
Submitted by Md Hafizul Islam Chowdhuryy

ICCD encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology. We especially encourage submissions that look forward to future systems and technologies. Authors are asked to submit technical papers in accordance to the  submission guidelines  in one of the following tracks:

Track 1. Computer Systems: System architecture and software (compiler, programming language/model, firmware, OS, hypervisor, runtime) design and co-design for embedded/real-time systems; System support and compilers for multi/many cores, co-processors, and accelerators; System support for security, reliability, and energy efficiency and proportionality; Virtual memory; System support for emerging technologies, including NVM, quantum, neuromorphic, bio-inspired computing, machine learning and artificial intelligence applications; Specialized OS, runtime, and storage systems for data center and cloud/edge computing, high-performance computing (HPC), exascale system, and serverless computing.

Track 2. Processor Architecture: Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining, caches, branch prediction, multithreading, and networks-on-chip; Techniques for low-power, secure, and reliable processor architectures; Hardware acceleration for emerging applications including NVM, quantum, neuromorphic, bio-inspired; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, retrospectives.

Track 3. Test, Verification, and Security: Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods; Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation; Hardware security primitives and methodologies; Side-channel analysis, attacks and mitigations for processors and accelerators; Interaction between test, security and trust.

Track 4. Electronic Design Automation: System-level design and synthesis; High-level, logic and physical synthesis; Analysis and optimization of timing, power, variability/yield, temperature, and noise; Physical design, including partitioning, floorplanning, placement, and routing; Clocktree synthesis; Verification methods at different levels of the EDA flow; Tools for multiple-clock domains, asynchronous, and mixed-timing methodologies; CAD support for accelerators, FPGAs, SoCs, ASICs, NoC, and general-purpose processors; CAD for manufacturing, test, verification, and security; Tools and design methods for emerging technologies (photonics, MEMS, spintronics, nano, quantum); interaction of EDA and AI/ML.

Track 5. Logic and Circuit Design: Circuit design techniques for digital, memory, analog and mixed-signal systems; Circuit design techniques for high performance and low power; Circuit design techniques for robustness under process variability, electromigration, and radiation; Design techniques for emerging and maturing technologies (MEMS, nano-spintronics, quantum, flexible electronics, multi-gate devices, in-memory computing); Asynchronous circuit design; Signal-processing, graphic-processor, and datapath circuits.

IMPORTANT DATES:
June 9th, 2023 (11:59pm AOE) (11:59pm AOE)                     Abstract submission
June 16th, 2023 (11:59pm AOE) (11:59pm AOE)                   Full paper submission
August 25th, 2023                                                                 Notification of Acceptance

Call for Papers: HPCA 2024
https://www.hpca-conf.org/2024/
Submitted by Christina Giannoula

REGULAR TRACK CALL FOR PAPERS
30th IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Edinburgh, UK
March 2 – March 6, 2024
https://www.hpca-conf.org/2024/

The International Symposium on High-Performance Computer Architecture (HPCA) is the premier forum for new ideas and research results in computer architecture. In 2024, the 30th edition of HPCA will be held in Edinburgh, Scotland, UK.

Important Dates
Abstract: July 28, 2023 at 11:59 PM PDT
Full Paper: August 4, 2023 at 11:59 PM PDT
Rebuttal/Revision:October 2 – 13, 2023
Author Notification:October 24, 2023

Regular Track Call For Papers
Some topics of interest are listed below, but we encourage authors to contact the PC chair, if they have a question regarding the topic fit.

• Processor, memory, and storage systems architecture
• Instruction-, thread-, and data-level parallelism
• Interconnection network, router, and network interface architecture
• Domain-Specific architectures, including FPGA, CGRA, and reconfigurable systems
• Near/In-Memory computing
• Cloud, datacenter, cluster/distributed systems and applications
• Approximate computing
• Compilers/PL for novel architectures
• IoT, mobile, Edge, and embedded architecture
• Effects of circuits or technology on architecture (3D/chiplets/interposer/wafer-scale)
• Architecture modeling and simulation methodologies
• Neuromorphic computing
• Quantum/ Superconducting computing
• Reliability/Fault Tolerance
• Security/Privacy
• Evaluation and measurement of real computing systems

Call for Papers: NOCS 2023
https://nocs2023.github.io/
Submitted by Peipei Zhou

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation.

Besides regular papers (https://nocs2023.github.io/cfp.html), NOCS welcomes Special Session (https://nocs2023.github.io/cfss.html) proposals to complement and strengthen the technical program.

NOCS’23 — Journal-Integrated Publication Model: All accepted papers will be published in an IEEE Design & Test Special Issue.

Please take a look at the NOCS webpage (https://nocs2023.github.io/) for more information. We look forward to receiving your submissions and seeing you at the symposium!

Submission Information

All papers must represent mature and original work, and not be published or submitted for publication in other conferences and journals. A double-blind review process will be enforced. Authors must not reveal their identity directly or indirectly. Papers must be in PDF format and should strictly follow IEEE Design & Test style and formatting (https://ieee-ceda.org/publication/ieee-design-test-dt/author-info), with an exemption of a 6,500 word limit and a maximum of 18 references.

Below is a summary of requirements from IEEE Design & Test:

• A 100-word abstract.
• Article title should not exceed 9 words.
• No more than 6,500 words, including references and illustrations.
• No more than 18 references.
• Each figure and table is counted, on average, as 200 words.

All papers must be submitted to NOCS 2023 through softconf: https://softconf.com/esweek23/nocs2023/

Call for Papers: HiPC 2023
https://hipc.org/
Submitted by Anand Panangadan

30th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC)
December 18-21, 2023
Goa, India
https://hipc.org/

HiPC 2023 will be the 30th edition of the IEEE International Conference on High Performance Computing, Data, Analytics, and Data Science. HiPC serves as a forum to present current work by researchers from around the world as well as highlight activities in Asia in the areas of high performance computing and data science. The meeting focuses on all aspects of high performance computing systems, and data science and analytics, and their scientific, engineering, and commercial applications.

Authors are invited to submit original unpublished research manuscripts that demonstrate current research in all areas of high performance computing, and data science and analytics, covering all traditional areas and emerging topics including from machine learning, big data analytics. Each submission should be submitted to one of the six tracks listed under the two broad themes of High Performance Computing and Data Science.

High Performance Computing Tracks

Algorithms. This track invites papers that describe original research on developing new parallel and distributed computing algorithms, and related advances. Examples of topics that are of interest include (but not limited to):

• New parallel and distributed algorithms and design techniques;
• Advances in enhancing algorithmic properties or providing guarantees;
• Algorithmic techniques for resource allocation and optimization;
• Provably efficient parallel and distributed algorithms for advanced scientific computing and irregular applications;
• Classical and emerging computation models.

Architecture. This track invites papers that describe original research on the design and evaluation of high performance computing architectures, and related advances. Examples of topics of interest include (but not limited to):

• High performance processing architectures;
• Networks for high performance computing platforms;
• Memory, cache and storage architectures;
• Approaches to improve architectural properties;
• Emerging computational architectures.

Applications. This track invites papers that describe original research on the design and implementation of scalable and high performance applications for execution on parallel, distributed and accelerated platforms, and related advances. Examples of topics of interest include (but not limited to):

• Shared and distributed memory parallel applications;
• Methods, algorithms, and optimizations for scaling applications on peta- and exa-scale platforms;
• Hardware acceleration of parallel applications;
• Application benchmarks and workloads for parallel and distributed platforms.

Systems Software. This track invites papers that describe original research on the design, implementation, and evaluation of systems software for high performance computing platforms, and related advances. Examples of topics of interest include (but not limited to):

• Scalable systems and software architectures for high-performance computing;
• Techniques to enhance parallel performance;
• Techniques to enhance parallel application development and productivity;
• Techniques to deal with uncertainties, hardware/software resilience, and fault tolerance;
• Software for cloud, data center, and exascale platforms;
• Software and programming paradigms for heterogeneous platforms.

Scalable Data Science Tracks

Scalable Algorithms and Analytics. This track invites papers that describe original research on developing scalable algorithms for data analysis at scale, and related advances. Examples of topics of interest include (but not limited to):

• New scalable algorithms for fundamental data analysis tasks (supervised, unsupervised learning, data (pre-)processing and pattern discovery);
• Scalable algorithms that are designed to address the characteristics of different data sources and settings;
• Scalable algorithms and techniques to reduce the complexity of large-scale data;
• Scalable algorithms that are designed to address requirements in different data-driven application domains;
• Scalable algorithms that ensure the transparency and fairness of the analysis;
• Case studies, experimental studies, and benchmarks for scalable algorithms and analytics;
• Scaling and accelerating machine learning, deep learning, and computer vision applications.

Scalable Systems and Software. This track invites papers that describe original research on developing scalable systems and software for handling data at scale and related advances. Examples of topics of interest include (but not limited to):

• New parallel and distributed algorithms and design techniques;
• Design of scalable system software to support various applications;
• Scalable system software for various architectures;
• Architectures and systems software to support various operations in large data frameworks;
• Systems software for distributed data frameworks;
• Standards and protocols for enhancing various aspects of data analytics.

Important dates
Abstract Submission: 30 June, 2023
Paper Submission: 7 July, 2023
Reviews to Authors: 25 August, 2023
Rebuttal Period: 26 August-1 September, 2023
1st Round Author Notification: 22 September, 2023
Revised Paper Submission: 14 October, 2023
Final Author Notification: 28 October, 2023

General Co-Chairs
Chiranjib Sur, Shell, India
Neelima Bayyapu, Manipal Institute of Technology, India

Vice General Co-Chairs
Sanmukh Rao Kuppannagari, Case Western Reserve University, USA
Vivek Yadav, International Institute of Information Technology, Bangalore, India

Program Co-Chairs
High Performance Computing: Yogish Sabharwal, IBM Research, India
Scalable Data Science: Gerald F Lofstead II, Sandia National Laboratories, USA

Program Vice-Chairs
HPC Tracks
– Algorithms: Jee Choi, University of Oregon, USA
– Applications: Preeti Malakar, IIT Kanpur, India
– Architecture: Saurabh Gupta, AMD, India
– System Software: Daniele De Sensi, Sapienza University of Rome, Italy

Scalable Data Science Tracks
– Scalable Algorithms and Analytics: Venkat Chakaravarthy, IBM Research, India
– Scalable Systems and Software: Lena Oden, Argonne National Laboratory, USA

Steering Committee Chair
– Viktor K. Prasanna, University of Southern California, USA

Please see the following site for details: https://hipc.org/

Call for Papers: IISWC 2023
http://iiswc.org
Submitted by Lieven Eeckhout

IISWC invites manuscripts that present original unpublished research in all areas related to characterization and analysis of computing system workloads, including translational research related to production-oriented commercial systems. Work focusing on emerging technologies and interdisciplinary work are especially welcome. Topics of interest include (but are not limited to): characterization of applications in traditional and emerging domains, characterization of system software and middleware, implications of workloads in system design, benchmarking methodologies and suites, and tools for computer systems.

Call for Papers: MICRO 2023
https://www.microarch.org/micro56/
Submitted by Christina Giannoula

56th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
MICRO 2023
Toronto, Canada
October 27 – November 1, 2023
https://www.microarch.org/micro56

The International Symposium on Microarchitecture (MICRO) is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and we aim to continue this tradition at MICRO-56. In 2023, MICRO goes to Toronto, Canada.

• Papers must be submitted in printable PDF format.
• Text must be in a minimum 10pt font.
• Papers must be at most 11 pages, not including references.
• Line spacing (leading) must be no less than 11pt.
• No page limit for references.
• References must include all authors (i.e., do not use et al.). Submissions should follow the guidelines and formatting rules
  specified on the conference website

Call for Papers: ESWEEK 2023
https://esweek.org/cfp_esweek/
Submitted by Lars Bauer

EMBEDDED SYSTEMS WEEK
Call for Papers: CASES, CODES+ISSS, EMSOFT, MEMOCODE, NOCS
Call for Proposals: Workshops, Tutorials, Educations, Special Sessions
Hamburg, Germany, September 17-22, 2023
www.esweek.org

About Embedded Systems Week (ESWEEK)
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent and connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), two symposia (MEMOCODE, NOCS), and several workshops and tutorials, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development.

https://esweek.org/cfp_esweek/

Registered attendees can attend sessions in any of the ESWEEK conferences (CASES, CODES+ISSS, EMSOFT). Please note that tutorials, symposia (MEMOCODE, NOCS), and workshops may use separate registration.

Timeline
Journal Track:

• Abstract Submission: March 16, 2023 (AoE)
• Full Paper Submission: March 23, 2023 (AoE, firm)
• Notification of Acceptance: June 30, 2023

Work-in-Progress Track:

• Paper Submission: May 22, 2023 (AoE, firm)
• Notification of Acceptance: June 19, 2023

Proposals of Workshops, Tutorials, Education
Classes, and Special Sessions: March 20, 2023

Covid-19 planning
ESWEEK 2023 will be an in-person event, taking place in Hamburg, Germany. We will continue to monitor specific travel advisories through official channels, which include the World Health Organization (WHO) and the local Ministry of Health. Please refer to the conference web-site and social media channels for updates.

Review Process
ESWEEK 2023 continues a dual publication model comprising the Journal track and the Work-in-Progress (WiP) track. Journal track papers, which are full-length papers describing mature work, will be published in the ACM Transactions on Embedded Computing Systems (TECS). The WiP track papers, which are short (2-page) papers representing not-yet-mature but promising research, will be published in the ESWEEK proceedings and will be listed as regular publications within the IEEE and/or ACM digital libraries. Authors of WiP papers have the opportunity to publish the extended form of their work in any conference or journal they prefer. Journal and WiP papers are mutually exclusive, i.e., a work can only be in submission in one of the two tracks. For more information on the publishing process, refer to: https://esweek.org/author-information/

CASES: International Conference on Compilers, Architectures,
and Synthesis for Embedded Systems
https://esweek.org/cases/
CASES is a premier forum where researchers, developers and practitioners exchange information on the latest advances in compilers and architectures for high-performance, low-power embedded systems. The conference has a long tradition of showcasing leading edge research in embedded processor, memory, interconnect, storage architectures and related compiler techniques targeting performance, power, predictability, security, reliability issues for both traditional and emerging application domains. In addition, we invite innovative papers that address design, synthesis, and optimization challenges in heterogeneous and accelerator-rich architectures.

CASES Program Chairs:
Swarup Bhunia, University of Florida, US
Jana Doppa, Washington State University, US

CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis
https://esweek.org/codes-isss/
The International Conference on Hardware/Software Co-design and System Synthesis is the premier event in system-level design, modeling, analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hard-ware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design.

CODES+ISSS Program Chairs:
Mohammad Abdullah Al Faruque, UC Irvine, US
Muhammad Shafique, New York University, US

EMSOFT: International Conference on Embedded Software
https://esweek.org/emsoft/
The ACM SIGBED International Conference on Embedded Software (EMSOFT) brings together researchers and developers from academia, industry, and government to advance the science, engineering, and technology of embedded software development. Since 2001, EMSOFT has been the premier venue for cutting-edge research in the design and analysis of software that interacts with physical processes, with a long-standing traditio for results on cyber-physical systems, which compose computation, networking, and physical dynamics.

EMSOFT Program Chairs:
Clarie Pagetti, Onera/ENSEEIHT, FR
Alessandro Biondi, Scuola Superiore Sant’Anna, IT

MEMOCODE: International Symposium on Formal Methods and Models for System Design
https://esweek.org/memocode/
MEMOCODE focuses on formal methods and models for developing computer systems and their components. MEMOCODE’s objective is to emphasize the importance of models and methodologies in correct system design and development.

NOCS: International Symposium on Networks-on-Chip
https://esweek.org/nocs/
NOCS is the premier event dedicated to interdisciplinary research on
on-chip, package-scale, chip-to-chip, and datacenter rack-scale
communication technology, architecture, design methods, applications,
and systems.

————————————————————————-
Call for Workshop Proposals
————————————————————————-
ESWEEK 2023 is soliciting proposals for new and recurring workshops to
be held on September 21/22. Proposals for half-day to two-day workshops
on a broad range of topics relevant to research, education, and design
are welcome. Details can be found at:

https://esweek.org/wp-content/uploads/2023/01/CFW-ESWEEK2023.pdf

Workshop Chair:
Robert Dick, University of Michigan, US

————————————————————————-
Call for Tutorial Proposals
————————————————————————-
ESWEEK 2023 is looking for high-quality tutorials that will take place on
Sunday, September 17, 2023. Tutorials on all topics related to embedded
system design, analysis, and development are welcome. Tutorials can be
either half/full-day, lecture style or hands-on.

Tutorials Chair:
Akash Kumar, Technische Universität Dresden, DE

————————————————————————-
Call for Education Proposals
————————————————————————-
ESWEEK 2023 will host several education lectures virtually on September
14 and 15, and is soliciting proposals for such lectures. The theme of
this year’s Education lectures is “Domain-Specific Hardware and
Software”. We invite you to submit education proposals on a topic related
to this theme.

https://esweek.org/wp-content/uploads/2023/01/CFE-ESWeek2023.pdf

Education Chairs:
Anup Das, Drexel University, US
Qingfeng (Karen) Zhege, East China Normal University, CN

————————————————————————-
Call for Special Session Proposals
————————————————————————-
We invite you to submit special session proposals on any topic relevant
to the broad areas of interest of ESWEEK. The special session should
cover a topic that is contemporary, hot, and complementary to the regular
sessions. The special session should be able to generate enthusiasm among
the ESWEEK participants.

Special Sessions Chair:
Sri Parameswaran, University of New South Wales, AU

————————————————————————-
Special Day Topic: Global Semiconductor Renaissance
————————————————————————-
The semiconductor industry and research are garnering tremendous interest
worldwide. Embedded computing plays a key role in modern digital systems
and that role will grow with the semiconductor renaissance. ESWEEK 2023
welcomes proposals on special sessions, panels, workshops, tutorials,
and education classes that explore the embedded computing’s role in the
future of semiconductors and electronics.

Panel and Special Day Chair:
Marilyn Wolf, University of Nebraska-Lincoln, US

————————————————————————-
Organization
————————————————————————-
ESWEEK 2023 General Chairs:
Xiaobo Sharon Hu, University of Notre Dame, US (General Chair)
Alain Girault, INRIA, FR (Vice General Chair)

Conference and Local Arrangement Chair:
Heiko Falk, Hamburg University of Technology, DE

www.esweek.org

Call for Papers: PACT 2023
https://pact2023.github.io/submit/
Submitted by Juan M. Cebrian

Call for Papers
PACT 2023 will be held in Vienna, Austria, during October 21–25, 2023.

Important Dates and Deadlines
Abstract submission deadline: Mar 25, 2023
Paper submission deadline: Apr 1, 2023
Round 1 rebuttal period: Jun 6-9, 2023
Round 2 rebuttal period: Jul 5-7, 2023
Author notification: Aug 1, 2023
Artifact submission: Aug 4, 2023
Camera ready papers: Sep 1, 2023

All deadlines are firm at midnight anywhere on earth (AoE).
Conference site: https://pact2023.github.io/submit/

Scope
The International Conference on Parallel Architectures and Compilation Techniques (PACT) is a unique technical conference sitting at the intersection of hardware and software, with a special emphasis on parallelism. The PACT conference series brings together researchers from computer architectures, compilers, execution environments, programming languages, and applications, to present and discuss their latest research results.

PACT 2023 will be held as an in-person event in the beautiful city of Vienna. At least one of the authors of accepted papers will be required to attend the conference, and we encourage all the authors to participate.

Specific topics of interest include (but are not limited to):
Parallel architectures
Compilers and tools for parallel computer systems
Applications and experimental systems studies of parallel processing
Computational models for concurrent execution
Multicore, multithreaded, superscalar, and VLIW architectures
Compiler and hardware support for hiding memory latencies
Support for correctness in hardware and software
Reconfigurable parallel computing
Dynamic translation and optimization
I/O issues in parallel computing and their relation to applications
Parallel programming languages, algorithms, and applications
Middleware and run time system support for parallel computing
Application-specific parallel systems
Distributed computing architectures and systems
Heterogeneous systems using various types of accelerators
In-core and in-chip accelerators and their exploitation
Applications of machine learning to parallel computing
Large scale data processing, including computing in memory accelerators
Insights for the design of parallel architectures and compilers from modern parallel applications
Neuromorphic computing both as an application for and a tool applied to architectures and compilers.

Submitting your work
Paper submissions are due April 1, 2023 by posting on the conference submission site. Please make sure that your paper satisfies all the following requirements before being submitted. Submissions not adhering to these submission guidelines will be rejected by the submission system and/or subject to an administrative rejection.

The paper must have an abstract under 300 words.
The paper must be original material that has not been previously published in another conference or journal, nor is currently under review by another conference or journal. You may submit material presented previously at a workshop without copyrighted proceedings.
The submission is limited to ten (10) pages in the ACM 8.5” x 11” format (US letter size paper) using 9pt font, with no more than 7 lines per inch. This page limit applies to all content NOT INCLUDING references, and there is no page limit for references. Your paper must print satisfactorily on both Letter paper (8.5”x11”) and A4 paper (8.27”x11.69”). The box containing the text should be no larger than 7.15”x9” (18.2cm x 22.9cm). Templates are available on the ACM Author Gateway.
Paper submission is double-blind to reduce reviewer bias against authors or institutions. Thus, the submissions cannot include author names, institutions or hints based on references to prior work. If authors are extending their own work, they need to reference and discuss the past work in third person, as if they were extending someone else’s research. We realize that for some papers it will still reveal authorship, but as long as an effort was made to follow these guidelines, the submission will not be penalized.
Anonymized supplementary material may be provided in a single PDF file uploaded at paper submission time, containing material that supports the content of the paper, such as proofs, additional experimental results, data sets, etc. Reviewers are not required to read the supplementary material but may choose to do so.
Please make sure that the labels on your graphs are readable without the aid of a magnifying glass.
The paper must be submitted in PDF. We cannot accept any other format, and we must be able to print the document just as we receive it. We suggest that you use only the four widely used printer fonts: Times, Helvetica, Courier and Symbol.

Poster submissions must conform to the same format restrictions, but may not exceed 2 pages in length. Paper submissions that are not accepted for regular presentations will automatically be considered for posters; authors who do not want their paper considered for the poster session should indicate this in their abstract submission. Two-page summaries of accepted posters will be included in the conference proceedings.

Please submit your work via the conference submission site.

Conflicts of interest
Authors must identify any conflicts-of-interest with PC members and external members of the community. We ask all authors of a submitted paper to register their conflicts at the submission site. If a paper is found to have an undeclared conflict that causes a problem OR if a paper is found to declare false conflicts in order to abuse or game the review system, the paper may be rejected. Conflicts of interests are defined according to ACM’s conflict of interest policy.

Artifact evaluation
Authors of accepted PACT 2023 papers are encouraged to formally submit their supporting materials for Artifact Evaluation. The Artifact Evaluation process is run by a separate committee whose task is to assess the availability, functionality, and reproducibility of the work and experimental results described in the paper. Submission is voluntary. We strongly encourage authors to consider submitting artifacts for their work, including simulators for new architectural designs and extensions.

We encourage authors to prepare their artifacts for submission and make them more portable, reusable and customizable using open-source frameworks including Docker, OCCAM, reprozip, CodeOcean and CK.

Papers that successfully go through the Artifact Evaluation process will receive a seal of approval printed on the papers themselves. Authors of such papers will have an option to include their Artifact Appendix to the final paper (up to 2 pages). Authors are also encouraged to make their artifacts publicly available.

Code of Conduct
All individuals participating in PACT or involved with its organization are expected to follow the

ACM Code of Ethics and Professional Conduct;
The IEEE Code of Ethics and Code of Conduct; and the
Policy Against Harassment at ACM activities.

Publication policies
PACT is supported by both ACM and IEEE and articles accepted for publication are available on both the ACM digital library and IEEE Xplore. By submitting your article to an PACT, you are hereby acknowledging that you and your co-authors are subject to all ACM Publications Policies, including ACM’s new Publications Policy on Research Involving Human Participants and Subjects, and the IEEE Publication Policies. Alleged violations of these policies will be investigated by officers of ACM or IEEE and may result in a full retraction of your paper, in addition to other potential penalties, as per their policies.

Please ensure that you and your co-authors obtain an ORCID ID, so you can complete the publishing process for your accepted paper. ACM has been involved in ORCID from the start and we have recently made a commitment to collect ORCID IDs from all of our published authors. The collection process has started and will roll out as a requirement throughout 2022. We are committed to improve author discoverability, ensure proper attribution and contribute to ongoing community efforts around name normalization; your ORCID ID will help in these efforts.

Call for Papers: LCTES 2023
https://pldi23.sigplan.org/home/LCTES-2023
Submitted by Younghyun Cho

LCTES 2023 Call for Papers

Co-located with PLDI and FCRC 2023
Orlando, Florida
June 18, 2023
https://pldi23.sigplan.org/home/LCTES-2023

Programming languages, compilers, and tools are important interfaces between embedded systems and emerging applications in the real world. Embedded systems are aggressively adapted for deep neural network applications, autonomous vehicles, robots, healthcare applications, etc. However, these emerging applications impose challenges that conflict with conventional design requirements and increase the complexity of embedded system designs. Furthermore, they exploit new hardware paradigms to scale up multicores (including GPUs and FPGAs) and distributed systems built from many cores. Therefore, programming languages, compilers, and tools are becoming more important to address these issues, such as productivity, validation, verification, maintainability, safety, and reliability for meeting both performance goals and resource constraints.

The 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory of Embedded Systems (LCTES 2023) solicits papers presenting original work on programming languages, compilers, tools, theory, and architectures that help in overcoming these challenges. Research papers on innovative techniques are welcome, as well as experience papers on insights obtained by experimenting with real-world systems and applications. Papers can be submitted to https://lctes23.hotcrp.com/.

Important Dates

• Paper submission deadline: March 16, 2023 (firm deadline)
• Paper notification: April 21, 2023
• Artifact submission deadline: May 1, 2023
• Artifact decision: May 12, 2023
• Camera-ready deadline: May 15, 2023
• Conference: June 18, 2023
  

Paper Categories

• Full paper: 10 pages presenting original work.
• Work-in-progress paper: 4 pages papers presenting original ideas that are likely to trigger interesting discussions.

Accepted papers in both categories will appear in the proceedings published by ACM. In addition, this year’s LCTES introduces two journal modes.

• All accepted full papers will be invited to be published in a special issue of the ACM Transactions on Embedded Computing Systems (TECS). A TECS publication will require substantial additional material over the conference publication and will undergo a separate review process.
• Rejected full papers may have the option to submit their work to the IEEE Embedded Systems Letters (ESL; 4 pages). IEEE ESL submissions will undergo a separate review process. 

Original contributions are solicited on the topics of interest including, but not limited to:

Programming language challenges

• Domain-specific languages
• Features to exploit multicore, reconfigurable, and other emerging architectures
• Features for distributed, adaptive, and real-time control embedded systems
• Capabilities for specification, composition, and construction of embedded systems
• Language features and techniques to enhance reliability, verifiability, and security
• Virtual machines, concurrency, inter-processor synchronization, and memory management

Compiler challenges

• Interaction between embedded architectures, operating systems, and compilers
• Interpreters, binary translation, just-in-time compilation, and split compilation
• Support for enhanced programmer productivity
• Support for enhanced debugging, profiling, and exception/interrupt handling
• Optimization for low power/energy, code/data size, and real-time performance
• Parameterized and structural compiler design space exploration and auto-tuning

Tools for analysis, specification, design, and implementation

• Hardware, system software, application software, and their interfaces
• Distributed real-time control, media players, and reconfigurable architectures
• System integration and testing
• Performance estimation, monitoring, and tuning
• Run-time system support for embedded systems
• Design space exploration tools
• Support for system security and system-level reliability
• Approaches for cross-layer system optimization

Theory and foundations of embedded systems

• Predictability of resource behavior: energy, space, time
• Validation and verification, in particular of concurrent and distributed systems
• Formal foundations of model-based design as the basis for code generation, analysis, and verification
• Mathematical foundations for embedded systems
• Models of computations for embedded applications

Novel embedded architectures

• Design and implementation of novel architectures
• Workload analysis and performance evaluation
• Architecture support for new language features, virtualization, compiler techniques, debugging tools
• Architectural features to improve power/energy, code/data size, and predictability

Mobile systems and IoT

• Operating systems for mobile and IoT devices
• Compiler and software tools for mobile and IoT systems
• Energy management for mobile and IoT devices
• Memory and IO techniques for mobile and IoT devices

For additional information and the ACM Publications Policies refer to the LCTES’23 website at https://pldi23.sigplan.org/home/LCTES-2023.

Call for Papers: ICS 2023
https://nschiele.github.io/ICS2023/cfp.html
Submitted by Kristian Rietveld

The ACM International Conference on Supercomputing (ICS) is the premier international forum for the presentation of research results in high-performance computing systems. The 37th edition of ICS will be part of ACM FCRC in Orlando June 21-23, 2023. Papers are solicited on all aspects of the architecture, software, and applications of high-performance computing systems of all scales (from chips to supercomputing systems), including but not limited to:

• Processor, accelerator, memory, storage, interconnect and system architectures, including architectures based on future and emerging hardware (e.g. quantum, photonic, neuromorphic).
• Programming languages, paradigms and execution models, including domain-specific languages and scientific problem-solving software environments.
• Compilers, runtime systems and system software, including optimization and support for hardware resources and energy management.
• High-performance algorithms and applications including machine learning and large-scale data analytics, as well as the implementation and deployment of algorithms and applications on large-scale systems.
• Tools for measurement, modeling, analysis and visualization of performance, energy, or other quantitative properties of high-performance computing systems.

The review process will include a rebuttal period, and the papers will be evaluated based on novelty, technical soundness, and potential impact on the field.

General Chairs
Kyle Gallivan, Florida State University, USA
Efstratios Gallopoulos, University of Patras, Greece

Program Chairs
Ramon Beivide, University of Cantabria, Spain
Moh Haghighat, Intel

Important dates;
Abstract submission: January 27th, 2023
Paper submission: February 3th, 2023
Rebuttal period: April 3-4, 2023
Author notification: April 14th, 2023
Camera-ready paper submission: May 4th, 2023
Dates of the conference: June 21-23, 2023
All submission dates above are AOE (Anywhere on Earth). Consult the conference website, https://ics-conference.org/, for the most up-to-date information.

Call for Papers: ASAP 2023
http://www.asap2023.org
Submitted by Joao MP Cardoso

ASAP 2023
34th IEEE International Conference on Application-specific Systems, Architectures and Processors
Porto, Portugal – July 19-21, 2023
http://www.asap2023.org

The 34th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2023) is organized by the Faculty of Engineering of the University of Porto in Porto, Portugal, July 19 – July 21, 2023. The history of the ASAP conference traces back to the International Workshop on Systolic Arrays, organized in 1986 in Oxford, UK. It later developed into the International Conference on Application-Specific Array Processors. With its current title, it was organized for the first time in Chicago, USA, in 1996. Since then, it has alternated between Europe and North America.

Topics
The conference covers the theory and practice of application-specific systems, architectures, and processors. Further, the conference will build upon traditional strengths in areas such as:

• Accelerator design for complex workloads, e.g., AI, big data, computational genomics, finance, and network processing
• Application-specific instruction-set processors and architectures
• Approximate computing
• Autonomous computing systems
• Cloud computing accelerators
• Compression
• Computer arithmetic
• Cryptography and security
• Design methods, tools, and compilers
• Edge computing, wireless, mobile, IoT, and Cyber-Physical Systems
• Embedded systems and domain-specific solutions
• Heterogeneous computing, ranging from embedded to HPC systems and data centers
• Reconfigurable and custom computing (FPGAs, CGRAs, etc.)
• Signal and image processing
• Simulation and prototyping (e.g., validation, performance analysis)
• System quality attributes (energy efficiency, fault tolerance, security, etc.)
• Systems using emerging technologies (e.g., optical computing or communication, 3D devices and interconnects, memristors for storage and logic, in-memory computing)

Authors are invited to submit original, unpublished research manuscripts on the above topics.

Important Dates

• Abstract submission deadline: Feb 20, 2023
• Paper submission deadline: Feb 27, 2023
• Notification of acceptance: May 2, 2023
• Camera-ready papers: May 29, 2023

Guidelines for Submissions

All papers will be reviewed by at least three members of the program committee, with a double-blind review process.

Manuscripts for full papers should not exceed 8 single-spaced, double-column pages using 10-point size font on 8.5×11 inch pages (IEEE conference style), including references, figures, and tables. Manuscripts for short papers should not exceed 4 single-spaced, double-column pages. Manuscripts for posters should not exceed 2 single-spaced, double-column pages.

All papers must be submitted electronically in PDF format.

Submission link: https://easychair.org/conferences/?conf=asap2023

All accepted papers must be presented by one of the authors in order to be included in the proceedings and published in the IEEE Xplore Digital Library.

Organizing Committee

General Chair:
João MP Cardoso, University of Porto, Faculty of Engineering / INESC TEC, Portugal

Program Co-Chairs:
Alexandra Jimborean, University of Murcia, Spain
Nele Mentens, Leiden University, The Netherlands, and KU Leuven, Belgium

Local Chair:
Pedro C. Diniz, University of Porto, Faculty of Engineering / INESC TEC, Portugal

Publicity Co-Chairs:
Seda Ogrenci, Northwestern University, USA
Vanderlei Bonato, University of São Paulo, ICMC, Brazil
Gianluca Palermo. Politecnico di Milano, Italy

Proceedings Chair:
José G. F. Coutinho, Imperial College London, UK

Finance Chair:
João Canas Ferreira, University of Porto, Faculty Of Engineering / INESC TEC, Portugal

Web and Registration Co-Chairs:
Nuno Paulino, University of Porto, Faculty Of Engineering / INESC TEC, Portugal

Student Volunteers Chair:
João Bispo, University of Porto, Faculty Of Engineering / INESC TEC, Portugal

Sponsorship Chair:
José T. Sousa, University of Lisbon / INESC-ID, Portugal

Steering Committee
José A.B. Fortes, University of Florida, USA
Sun-YuanKung, Princeton University, USA
Wayne Luk, Imperial College London, UK
Michael J. Schulte, AMD Research, USA
Earl Swartzlander, The University of Texas at Austin, USA

Call for Papers: DSN 2023
https://dsn2023.dei.uc.pt/calls_cfp-research.html
Submitted by Onur Mutlu

DSN 2023
The 53rd IEEE/IFIP International Conference on Dependable Systems and Networks
Porto, Portugal
June 27 – 30, 2023
http://dsn.org

Important dates:
All dates refer to AoE time (Anywhere on Earth)
Dec. 1, 2022: Abstract submission deadline
Dec. 7, 2022: Paper submission deadline
Jan. 28, 2023: Early reject notification
Feb. 15 – 28, 2023: Author rebuttal period & revision period
Mar. 17, 2023: Notification to authors

The society today is increasingly dependent on the correct functioning of computer systems, edge devices and networks for systems and services we use every day, such as aviation, energy production & power grids, intelligent/autonomous vehicles, medical devices & electronic health records, and many others.

The Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) is devoted to the mission of ensuring that the computing systems and networks on which society relies are dependable and secure.

DSN, one of the longest running IEEE conferences organizing its 53rd edition in 2023, has pioneered the fusion between dependability and security research under a common body of knowledge, understanding the need to simultaneously fight against accidental faults, intentional cyber-attacks, design errors, and unexpected operating conditions. Its distinctive approach to both accidental faults and malicious attacks made DSN the most prestigious international forum for presenting research furthering robustness and resilience of today’s wide spectrum of computing systems and networks.

All aspects of the research and practice of dependability and applied security are within the scope of DSN. Relevant topics include innovative architectures, protocols, and algorithms, for preventing, detecting, recovering, diagnosing or eliminating accidental and malicious threats as well as experimentation with and assessment of dependable and secure systems and networks.

Authors are invited to submit original papers on the current thematic areas of DSN:

• Hardware (e.g., microprocessors, memory systems, systems on chip, I/O devices, storage systems,Trusted Execution Environments (TEEs), edge and mobile devices, data center infrastructure, hardware accelerators)
• Software (e.g., applications, middleware, distributed algorithms, operating systems, software security, dependable software design)
• Networked systems and clouds (e.g., wireless networks, mobility, software-defined networking, edge computing, cloud computing/storage, networks on chip, network security)
• Autonomous systems (e.g., self-driving vehicles, autonomous robots, assured autonomy, explainable decision making, acceptability, privacy issues)
• Cyber-physical systems (e.g., embedded systems, real-time control of critical systems, internet of things, smart grid, automotive, aerospace, railway, medical systems)
• Distributed ledgers/Blockchain (e.g., BFT/consensus algorithms, cryptocurrencies, decentralized storage, zero knowledge proofs)
• AI/Machine Learning for resilient systems (e.g., robust, resilient, secure, and explainable AI/Machine Learning techniques; applications of AI/ML techniques for dependability and security, robustness issues in ML/AI systems)
• Models and methodologies for programming, evaluating, verifying, and assessing robust (dependable and secure) systems (e.g., performance and dependability evaluation, analytical and numerical methods, simulation, experimentation, benchmarking, verification, field data analysis)
• Emerging technologies and computing paradigms (e.g., robustness, security, dependability issues of emerging memory and storage systems, emerging computing paradigms like quantum computing, processing in memory/sensors/storage/network, 3-dimensional architectures, new hardware/software cooperative paradigms, emerging programming and system paradigms)

Information to authors
Innovative papers in all areas of robust (dependable and secure) systems and networks will be considered. Papers will be assessed with criteria appropriate to each category. The conference broadly and inclusively favors innovative and insightful research that explores new territory, continues a significant research dialogue, or reflects on experience with (or measurements of) state-of-the-art systems. Submissions will be judged on insight, originality, significance, correctness and potential impact.

Research Papers, Practical Experience Reports, and Tool Descriptions will be refereed and included in the Proceedings of the DSN 2023, if accepted.

All contributions must be written in English. IEEE Computer Society will publish accepted contributions.

At least one author of every accepted paper is expected to register (as a regular registration) for the conference and present the work.

Paper Categories
Submissions can be made in one of the following categories (authors are required to indicate the category as part of the paper’s title).

Regular papers (11 pages): full paper describing research contribution, including experimental work focused on implementation and evaluation of existing techniques in the DSN thematic areas. Papers should clearly describe a novel scientific contribution and a significant advancement of the state of knowledge in DSN relevant topics. The paper should address a significant problem with a compelling solution whose validity and practical applicability are clearly discussed.

Practical experience reports (7 pages): a shorter paper describing practitioner experiences or lessons learned applying tools and techniques to real-world problems and systems, or based on the empirical analysis of field data using a rigorous scientific approach. A paper in this category is expected to show new insights and experiences informing the research and practice of robust computing system design. Contributions reporting on industry practical experiences and lessons learned are highly encouraged, including studies reporting negative results or challenges about the practical applicability or scalability of research results in industry

Tool descriptions/demonstrations (7 pages): descriptions of the architecture, implementation and usage of substantive tools to aid the research and practice of dependability. A tool paper is expected to describe and demonstrate the value that the tool brings to the dependability community. Making the tool publicly available, whenever possible, is strongly encouraged.

The number of pages indicated above includes everything except the references: title page, text, figures, appendices, etc. Papers that exceed the number of pages for that submission category will be rejected without review.

Independently of the paper category, we expect all papers to provide enough detail to enable reproducibility of their experimental results and encourage authors, whenever possible, to make both the artifacts and datasets related to the paper publicly available.

Awards
DSN awards a Distinguished Paper Award to one of the accepted scientific papers and Best Paper Awards to multiple (e.g., 3) of the accepted papers. Both the Distinguished Paper Award and Best Paper Award winning papers should be presented in a special Best Paper Session at the conference.

The selection of the candidate papers for the awards is carried out as a three-step process. First, the Program Committee picks 6-7 of the accepted papers based on the review and revision process & committee discussion. Second, the Steering Committee (in consultation with the Program Chairs) chooses among these papers the 3 Best Papers that are to be presented in the Best Paper Session at the conference (all these papers receive the Best Paper Award). Third, and finally, the audience at the conference votes among these Best Papers to select the one that should receive the Distinguished Paper Award. Attendees are strongly encouraged to read the Best Papers as well as carefully listen to their presentations, and make their Distinguished Paper Award choice based on all information they have about the finalized Best Papers and their presentations at the conference.

DSN also attributes a group of awards based on nominations. These awards are the William C. Carter Ph.D. Dissertation Award in Dependability, the Rising Star in Dependability Award, the Test-of-Time Award, and the Jean-Claude Laprie Award. Please check the relevant page on the DSN website for additional details.

For more information, please visit the DSN web site
(http://dsn.org) or contact pc_chairs@dsn.org

Program Committee Co-Chairs

Xavier Défago, Tokyo Institute of Technology, Japan
Onur Mutlu, ETH Zurich, Switzerland

Call for Papers: SYSTOR 2023
https://www.systor.org/2023/
Submitted by Oleg Kolosov

The ACM International Systems and Storage Conference (SYSTOR) is an international forum for interaction across the systems research community. The program includes innovative, peer-reviewed research papers in the broad area of systems and storage, as well as distinguished keynote lecturers, a poster session, and social events. ACM SYSTOR is designed to appeal to academic and industrial researchers and practitioners, welcoming both students and seasoned professionals.

Topics:
SYSTOR welcomes academic and industrial papers in systems and storage, broadly construed. SYSTOR encourages submissions that describe results from experimental system prototypes, as well as experience papers describing practical deployments, and valuable lessons learned from them. Topics of interest include, but are not limited to:

• Big Data infrastructure
• Cloud, edge, data center, and distributed systems
• Embedded and real-time systems
• Fault tolerance, reliability, and availability
• File and storage systems
• Networked, mobile, wireless, peer-to-peer, and sensor systems
• Operating systems, computer architecture, and their interactions
• Performance evaluation and workload characterization
• Runtime systems and compiler/programming-language support
• System deployment, usage, and experience
• System design or adaptation for emerging storage technologies
• System security and trust
• Systems for machine learning/machine learning for systems
• Virtualization and containers

Tracks:

• Full Papers Track – original research, at most 10 pages, excluding references
• Short Papers Track – original research, at most 5 pages, excluding references
• Highlight Papers Track – papers accepted at top-tier conferences
• Posters with Extended Abstract Track – original work presented as a poster, accompanied by an extended abstract in the conference proceedings

Important Dates:

Full and Short Papers Track
Paper Submission              Thursday, March 2, 2023
Acceptance Notification      Thursday, April 13, 2023
Camera-ready                     Monday, May 8, 202

Highlight Papers Track
Extended Abstract Submission  Monday, April 3, 2023
Acceptance Notification             Monday, May 1, 2023

Posters with Extended Abstract Track
Poster & Abstract Submission     Wednesday, March 15, 2023
Acceptance Notification               Monday, April 17, 2023
Camera-ready                             Monday, May 8, 2023 

Conference                    June 5-7, 2023 

Program Chairs:
Yossi Gilad (Hebrew University of Jerusalem, Israel)
Dejan Kostic (KTH Royal Institute of Technology, Sweden) 

Program Committee:
Abutalib Aghayev (Pennsylvania State University)
Aishwarya Ganesan (University of Illinois Urbana-Champaign)
Amit Klein (Hebrew University)
Andromachi Chatzieleftheriou (Microsoft Research)
Animesh Trivedi (VU Amsterdam)
Ashvin Goel (University of Toronto)
Avani Wildani (University of California, Santa Cruz)
Aviad Zuck (Technion-Israel Institute of Technology)
Charlie Hu (Purdue University)
Cristina Abad (Escuela Superior Politecnica del Litoral)
Huaicheng Li (Virginia Tech)
Lluís Vilanova (Imperial College London)
Marco Chiesa (KTH Royal Institute of Technology)
Ming Liu (University of Wisconsin at Madison/ VMware Research)
Orna Agmon Ben-Yehuda (Haifa University)
Patrick P. C. Lee (The Chinese University of Hong Kong)
Ramnatthan Alagappan (University of Illinois Urbana-Champaign)
Rob Johnson (VMWare Research)
Rodrigo Fonseca (Microsoft Research)
Sam H. Noh  Ulsan (National Institute of Science and Technology)
Shir Landau Feibish (Open University Israel)
Thanumalayan Sankaranarayana Pillai (Google)
Thomas Shull (Oracle Labs)
Vasily Tarasov (IBM Research – Almaden)
Waleed Reda (KTH Royal Institute of Technology)
Youjip Won (Korea Advanced Institute of Science and Technology (KAIST))
Youngjin Kwon (Korea Advanced Institute of Science and Technology (KAIST))
Youyou Lu (Tsinghua University)

General Chair:
Ofer Biran (IBM Research – Haifa, Israel)
Yosef Moatti (IBM Research – Haifa, Israel)

Poster Chair:
Dean Lorenz (IBM Research – Haifa, Israel) 

Publicity Chair:
Oleg Kolosov (Technion, Israel)

Steering Committee Head:
Dalit Naor (The Academic College of Tel Aviv-Yaffo, Israel)

Steering Committee:
Michael Factor (IBM Research – Haifa, Israel)
Ethan Miller (University of California Santa Cruz, USA)
Liuba Shrira (Brandeis University, USA)
Dan Tsafrir (Technion, Israel & VMware Research Group, USA)
Gala Yadgar (Technion, Israel)
Erez Zadok (Stony Brook University, USA)

Call for Papers: ISCA 2023: Industry Track
https://www.iscaconf.org/isca2023/submit/industry.php
Submitted by Viji Srinivasan

The 50th International Symposium of Computer Architecture includes a separate industry session in the main program following the success of the industry track inaugurated in ISCA 2020. The ISCA Industry Track was established under a different vision and motive to bringing the values, trends, and perspectives of real hardware product and system design from the industries. It also serves as a venue to encourage more participation from industries to interact with academia for forward-looking research challenges and solutions. In light of the very specific purpose of the industry track, the submission guidelines are also very specific.

• First author, and most authors, must be from industry
• Not for student internship projects
• Submissions must include all author names and affiliations for review (authors may remain blinded)
• All ISCA formatting guidelines apply (11 pages without references, 10pt font)
• Abstract Deadline: January 6, 2023 at 11:59 PM EST
• Full Paper Deadline: January 13, 2023 at 11:59 PM EST

Upload Abstracts and Papers to Industry Track HotCRP

Call for Papers: ISPASS 2023
https://ispass.org/ispass2023/
Submitted by Elaheh Sadredini

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research focused on performance analysis in the design of computer systems and software. ISPASS 2023 will be held on April 23-25, 2023 in Raleigh, North Carolina. Authors are invited to submit previously unpublished work for possible presentation at the conference.

Papers are solicited in fields that include the following:

• Performance and efficiency (power, area, etc.) evaluation methodologies
  • Analytical modeling
  • Statistical approaches
  • Tracing and profiling tools
  • Simulation techniques
  • Hardware (e.g., FPGA) accelerated simulation
  • Hardware performance counter architectures
  • Power, temperature, variability and/or reliability models for computer systems
  • Microbenchmark-based hardware analysis techniques
• Foundations of performance and efficiency analysis
  • Metrics
  • Bottleneck identification and analysis
  • Visualization
• Efficiency and performance analysis of commercial and experimental hardware
  • Multi-threaded, multicore and many-core architectures
  • Accelerators and graphics processing units
  • Memory systems, including storage-class memory
  • Embedded and mobile systems
  • Enterprise systems and data centers
  • HPC and Supercomputers
  • Computer networks
  • Quantum computing
  • Emerging technologies
• Efficiency and performance analysis of emerging workloads and software
  • Software written in managed languages
  • Virtualization and consolidation workloads
  • Datacenter, internet-sector workloads
  • Embedded, multimedia, games, telepresence
  • Deep learning and convolutional neural networks
• Application and system code tuning and optimization
• Confirmations or refutations of important prior results

In addition to research papers, ISPASS welcomes tool and benchmark paper submissions. The conference is an ideal forum to introduce new tools and benchmarks to the community. These papers, which can detail tools and benchmarks in the above fields of interest, will be judged primarily on their potential to enable and amplify future research.

Important Dates

• Paper abstract submission deadline: November 29, 2022, 11:59:59 PM, Eastern Time
• Full submission deadline: December 6, 2022, 11:59:59 PM, Eastern Time
• Rebuttal: February 7-9, 2023
• Paper notification: February 28, 2023

More information here: https://ispass.org/ispass2023/

Call for Papers: DATE 2023
https://www.date-conference.com/call-for-papers
Submitted by Anja Zeun

Call for Papers
Design, Automation, and Test in Europe 2023
https://www.date-conference.com/call-for-papers

Kindly note that all deadline days apply to anywhere on earth (AoE). Deadlines are strict and no extensions will be given.

For its 2023 edition, DATE presents itself in a renewed format: After three years of online editions due to COVID-19, DATE 2023 focusses on interaction as well as reinforcing and rebuilding links in the community. Accordingly, we employ some substantial changes to the established format intending for significant added value for in-person participation: Rather than spreading the attendance throughout an entire week, we condense DATE to three days – and make them count! Furthermore, the vast majority of regular papers will be presented in a renewed format of technical sessions focussing on live interactions (in addition to the common full-length presentations available before, during and after the conference by video). By this, we make sure that the community can actually do what conferences are for: meeting, discussing and exchanging.

In case of any questions, please contact:

DATE Conference Organisation
c/o K.I.T. Group GmbH Dresden
Bautzner Str. 117–119
01099 Dresden, Germany

Phone: +49 351 65573 137
E-mail: date@kitdresden.de
www.date-conference.com

Call for Papers: HOST 2023
http://www.hostsymposium.org/
Submitted by Hadi Mardani Kamali

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) – the premier event aiming to facilitate the rapid growth of hardware security research and development – has opened the call for contributions. The 16th annual HOST will be held May 1-4, 2023 in San Jose, California. HOST 2023 invites original contributions in all areas of overlap between hardware and security, including but not limited to the following:

• Hardware Trojans
• TRNGs and PUFs
• Side-Channel Attacks and Countermeasures
• Hardware Obfuscation
• Architecture-level Security
• System/Board-level hardware security
• Cryptography-PQC
• Fault Injection Attacks and Countermeasures