This is the 1st August 2019 digest of SIGARCH Messages.

In This Issue

Call for Papers: FPGA 2020 - (Note: The Call for Paper type has not been set for this item!)

Call for Papers: Conference on Systems and Machine Learning
Submitted by Vivienne Sze

Conference on Systems and Machine Learning
Austin, TX, USA
March 2 – 4, 2020

Paper submission deadline: Sep 9, 2019 @ 4:59pm PDT

The Conference on Systems and Machine Learning targets research at the intersection of systems and machine learning. The conference aims to elicit new connections amongst these fields, including identifying best practices and design principles for learning systems, as well as developing novel learning methods and theory tailored to practical machine learning workflows. To learn more, see whitepaper at
Videos of previous iterations (SysML18, SysML19) can be found at

Topics of interest include, but are not limited to:
– Efficient model training, inference, and serving
– Distributed and parallel learning algorithms
– Privacy and security for ML applications
– Testing, debugging, and monitoring of ML applications
– Fairness and interpretability for ML applications
– Data preparation, feature selection, and feature extraction
– ML programming models and abstractions
– Programming languages for machine learning
– Visualization of data, models, and predictions
– Customized hardware for machine learning
– Hardware-efficient ML methods
– Machine Learning for Systems

Papers should be up to 10 pages and are due September 9, 2019. Reviewing will be double-blind and papers will be published in conference proceedings. The conference will also include an optional artifact evaluation process to highlight research with reproducible experiments, data, and software artifacts.

For more details, see

Call for Papers: Workshop on Network on Chip Architectures
Submitted by Maurizio Palesi

12th International Workshop on Network on Chip Architectures (NoCArc)
in conjunction with MICRO 2019
Columbus, Ohio, USA
October 12-13, 2019

With the advancement in both computing architectures and process technology, many-core architectures can have thousands of cores into a single chip. This integration opens up a plethora of challenges, e.g., in terms of specialization and energy-focused implementations, and supports the spread of various applications and computational paradigms, ranging from multiprocessing to reconfigurable computing, from quantum computing to the emerging area of neuromorphic computing. Such wild increase in the number of processing elements (PE) per chip, together with the growing architectural and workload heterogeneity, calls for efficient, versatile, scalable and reliable communication infrastructures. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, the integration of a large number of PEs on a chip, or heterogeneous workloads. Novel techniques and architectures are needed to efficiently design and optimize the NoC and evaluate it at the network or system level.

The goal of NoCArc is to provide a forum for researchers to present and discuss innovative ideas and solutions related to the design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis, testing, and application of on-chip networks.

The workshop will focus on issues related to design, analysis, and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation
– Topologies, routing, flow control
– Managing QoS
– Reliability issues
– Security issues
– Design methodologies and tools

NoC Analysis, Optimization, and Verification
– Power, energy and thermal issues
– Benchmarking with NoC-based systems
– Modeling, simulation, and synthesis
– Verification, debug and test of
– Metrics and benchmarks

NoC Applications
– Mapping of applications onto NoCs
– Real and industrial NoC case studies
– NoCs for FPGAs, ASICs, CMPs, and MPSoCs
– NoC designs for heterogeneous systems

NoC at System-level
– Design of memory subsystem
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing, or new models
– Large-scale systems (datacenters, supercomputers) with NoC-based Systems as building blocks

Emerging NoC Technologies
– Wireless, Optical, and RF
– NoCs for 3D and 2.5D packages
– Approximate computing for NoC and NoC-based systems

Machine Learning (ML) and NoC-based Systems
– Interconnects for ML systems/accelerators
– Memory access for the NoC-based ML systems
– NoC-based ML algorithm design

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Submissions must be limited to 6 pages. Please, visit the workshop webpage ( for additional information about the submission process.

Abstract submission deadline: July 25, 2019
Paper submission deadline: August 1, 2019
Acceptance notification: September 1, 2019
Camera-ready version due: September 8, 2019
NoCArc workshop: October 12-13, 2019

General Chair:
Kun-Chih (Jimmy) Chen, National Sun Yat-sen University, Taiwan

TPC Co-Chairs:
Sergi Abadal, Universitat Polit├Ęcnica de Catalunya, Spain
Salvatore Monteleone, University of Catania, Italy

Steering Committee:
Maurizio Palesi, Univ. of Catania, Italy
Davide Patti, Univ. of Catania, Italy
Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden
Masoud Daneshtalab, MDH and KTH, Sweden
Xiaohang Wang, South China University of Technology, China

Call for Papers: Workshop on Heterogeneous High-performance Reconfigurable Computing
Submitted by Jason D. Bakos

Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H^2RC 2019)
in conjunction with Supercomputing 2019
in cooperation with the IEEE Technical Consortium on High Performance Computing (TCHPC)
Denver, Colorado, USA
November 17, 2019

Submission Deadline: August 15, 2019 (4- and 8- page papers)

Accepted 8-page manuscripts published/archived by IEEE (See below for descriptions of submission tracks.)

As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier-to-use high-level programming models for FPGAs, and much of the work in FPGA-based deep learning is built on these frameworks.

Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its fifth year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on how newly-available high-level programming models, including OpenCL, are already empowering HPC software developers to directly leverage FPGAs, and to identify future opportunities and needs for research in this

Submissions are solicited for two tracks:
Track 1: Full-length papers (8 pages) for 25-minute oral presentation and publication in proceedings archived by IEEE.
Track 2: Extended abstracts (4 pages) for 15-minute oral presentation without publication.

Track 1 is targeted for technical papers containing a high level of implementation detail and analysis discussion of experimental results. Track 1 is suited for members of the academic and national lab community who prefer to have their work peer-reviewed, indexed and archived by IEEE.

Track 2 is targeted for industrial contributions that describe new capabilities and opportunities offered by emerging technologies and products or work in progress presentations by the academic and national lab community. The emphasis of this track is to initiate a discussion with the audience.

All submissions are reviewed and evaluated by at least three members of our technical program committee. From the TPC evaluation of each submission, the organizing committee will select papers for presentation based on a criteria that is equally weighted between scientific merit and level of interest and relevance to the HPC community.

1. Improvement of performance or efficiency of HPC or data center
applications with FPGAs
2. System integration of FPGAs in clouds and HPC systems
3. Leveraging reconfigurability
4. Benchmarks
6. Programming languages, tools, and frameworks
7. Future-gazing

Submission Deadline: August 15, 2019
Acceptance Notification: September 15, 2019
Camera-ready Manuscripts Due: October 11, 2019
Workshop Date: November 17, 2019

Jason D. Bakos, University of South Carolina
Michaela Blott, Xilinx
Franck Cappello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Christian Plessl, Paderborn University, Germany

Technical Program Committee:
David Andrews, University of Arkansas
Rizwan Ashraf , Oak Ridge National Laboratory
Paul Chow, University of Toronto
Hans Eberle, Nvidia
Ken Eguro, Microsoft Research
Xin Fang, Northeastern University
Alan George, University of Pittsburgh
Christoph Hagleitner, IBM
Martin Herbordt, Boston University
Zheming Jin, Argonne National Laboratory
Andreas Koch, TU Darmstadt
Miriam Leeser, Northeastern University
Tiffany Mintz, Oak Ridge National Laboratory
Viktor Prasanna, University of Southern California
Yaman Umuroglu, Xilinx Research

Note: The Call for Paper type has not been set for this item!

Call for Papers: FPGA 2020
Submitted by Jing (Jane) Li

Twenty-Eighth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)
February 24-26, 2020
Seaside, California, USA

Submissions due: September 9, 2019

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020) is the premier conference for presentation of advances in FPGA technology. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library.

Types of Submissions Sought:

1. Research Papers (with and without Artifacts)

As usual, we solicit research papers related to the following areas:
– FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
– FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory memory or nano-scale devices. Methods for analyzing and improving static and dynamic power, power and clock distribution, yield, manufacturability, security, reliability, and testability.
– CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
– High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
– FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
– Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.

Research submissions may be either:
– Full: at most 10 pages (excluding references), for a full presentation at the conference; or
– Short: at most 6 pages (excluding references), for a brief presentation.

A paper submitted as either full or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).

2. Tutorial Papers on Emerging Applications / Methodologies

The conference will include a Sunday workshop oriented toward users of FPGAs: be it deep learning implementations, computer security or other emerging topics of interest. For this category, we solicit tutorial papers describing effective design techniques and design flows. The ideal submission will enable beginning researchers to enter the area, current researchers to broaden their scope, and practitioners to gain new insights and applicable skills. Tutorial submissions need not present novel research results, but should integrate expert practical and/or research knowledge related to FPGAs for a broader audience. This may include:
– Technical descriptions of new commercial or academic design tools of general interest;
– Insightful summaries of the state-of-the-art that suggest open research problems; and
– In-depth design tutorials and design experiences.

Tutorial submissions are at least 4 and at most 10 pages. Accepted submissions are published in the proceedings and allocated a presentation time of up to one hour, appropriate to the content.

3. Panel Discussion Proposals

We also solicit proposals for the panel discussion at the conference banquet. The submission should outline the topic, questions to be addressed, and suggested speakers.

Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at Submissions will be considered for acceptance as full or short regular papers, workshop papers, or posters. Regular submissions related to the workshop topic may be scheduled for presentation during the workshop. Regular or workshop submissions will also be considered for acceptance as a poster. A paper submitted to the short or full paper category will only be considered in that category. Once a paper has been submitted, its authorship list is considered to be fixed and finalized. As the inclusion and evaluation of artifacts is new for FPGA 2020, additional information will be provided at by August 2019.

Abstract Submissions due: September 9, 2019
Full Paper Submissions due: September 9, 2019
Final Artifacts for Evaluation due: September 9, 2019
Author Paper Rebuttals due: October 18, 2019
Notification of acceptance: Mid-November, 2019
Camera-ready copy of accepted papers due: Early December, 2019

General Chair: Stephen Neuendorffer, Xilinx
Program Chair: Lesley Shannon, Simon Fraser University
Finance Chair: Kia Bazargan, University of Minnesota,
Artifact Evaluation Co-Chairs: Miriam Leeser, Northeastern University, and Suhaib Fahmy, University of Warwick
Publicity Chair: Jing Li, University of Wisconsin-Madison

Call for Posters: ACM Student Research Competition at MICRO 2019
Submitted by Adwait Jog

ACM Student Research Competition (SRC)
in conjunction with 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Columbus, Ohio, USA
October 12-16, 2019

Abstract Submission: July 31, 2019 (4:59pm PDT)
Acceptance Notification: August 21, 2019

MICRO invites participation in the ACM Student Research Competition (SRC). Sponsored by ACM and Microsoft Research, the SRC is a forum for undergraduates and graduate students to share their research results, exchange ideas and improve their communication skills while competing for prizes. Students accepted to participate in the SRC are entitled to a travel grant (up to $500) to help cover travel expenses. The top 3 undergraduate and graduate winners will receive the following prizes:
1. Monetary prizes of $500, $300 and $200, respectively.
2. A framed Grand Finalist certificate.
3. The names of the winners will be posted on the website.
4. In addition, the first-place winner in each category (undergraduate, graduate) will receive an invitation to participate in the SRC Grand Finals, an online round of competitions among the first-place winners of individual conference-hosted SRCs. Three undergraduates and three graduates will be chosen among them as the SRC Grand Finals winners. They are invited, along with their advisors, to the annual ACM Awards Banquet, where they receive formal recognition.

The SRC consists of two rounds: a poster session and a presentation session. Submissions recommended for acceptance by the selection committee will be invited to a first-round poster session to be held during MICRO-52. A panel of judges will select a number of finalists from the poster session held at the symposium, who will be invited to a second-round SRC presentation session at MICRO-52 and compete for the prizes. The evaluation will be concentrated on the quality of both visual and oral presentation, the research methods and the significance of contribution. You can find more info on the ACM Student Research Competition website:

Details on eligibility requirements can be found on the MICRO website:

Extended abstracts of up to 800 words should be submitted through the following EasyChair link:

ACM and Microsoft Research

Questions? Contact Joshua San Miguel (

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- Boris Grot
SIGARCH Content Editor