This is the 1st October 2019 digest of SIGARCH Messages.

In This Issue

Call for Papers: ISCA 2020
Submitted by Jishen Zhao

The International Symposium on Computer Architecture
May 30 – June 3, 2020
Valencia, Spain

Submissions Due: November 26, 2019

The International Symposium on Computer Architecture is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions.

In 2020, the 47th edition of ISCA will be held in Valencia, Spain.

Important Dates

  • Abstract Deadline: November 19, 2019
  • Full Paper Deadline: November 26, 2019
  • Rebuttal/Revision Period: February 3–14, 2020
  • Author Notification: March 4, 2020

Papers are solicited on a broad range of topics, including (but not limited to):

  • Processor, memory, and storage systems architecture
  • Multiprocessor systems
  • Datacenter-scale computing
  • IoT, mobile and embedded architecture
  • Interconnection network, router and network interface architecture
  • Accelerator-based, application-specific and reconfigurable architecture
  • Architectural support for programming languages or software development
  • Architectural support for security or virtualization
  • Instruction, thread and data-level parallelism
  • Dependable processor and system architecture
  • Architecture for emerging technologies and applications, including quantum computing, novel memory technologies, etc.
  • Effects of circuits or technology on architecture
  • Architecture modeling and simulation methodologies
  • Evaluation and measurement of real computing systems


  • General Chairs: José Martínez (Cornell) and José Duato (UPV)
  • Program Chair: Lieven Eeckhout (Ghent University)

Call for Papers: HiPEAC Workshop on Accelerated Machine Learning (AccML’20)
Submitted by Jose Cano

HiPEAC – 2020
Workshop on Accelerated Machine Learning (AccML)

Co-located with the HiPEAC 2020 Conference

January 20, 2020
Bologna, Italy

Submissions Due: November 8, 2019

In the last 5 years, the remarkable performance achieved in a variety of application areas (natural language processing, computer vision, games, etc.) has led to the emergence of heterogeneous architectures to accelerate machine learning workloads. In parallel, production deployment, model complexity and diversity pushed for higher productivity systems, more powerful programming abstractions, software and system architectures, dedicated runtime systems and numerical libraries, deployment and analysis tools. Deep learning models are generally memory and computationally intensive, for both training and inference. Accelerating these operations has obvious advantages, first by reducing the energy consumption (e.g. in data centers), and secondly, making these models usable on smaller devices at the edge of the Internet. In addition, while convolutional neural networks have motivated much of this effort, numerous applications and models involve a wider variety of operations, network architectures, and data processing. These applications and models permanently challenge computer architecture, the system stack, and programming abstractions. The high level of interest in these areas calls for a dedicated forum to discuss emerging acceleration techniques and computation paradigms for machine learning algorithms, as well as the applications of machine learning to the construction of such systems.

Links to the Workshop pages


Keynote: Luca Benini (ETH Zurich and U. di Bologna)
Title: Extreme Edge AI on Open Hardware

Edge Artificial Intelligence (AI) is the new mega-trend, as privacy concerns and network bandwidth/latency bottlenecks prevent cloud offloading of AI functions in many application domains, from autonomous driving to advanced prosthetics. Hence we need to push AI toward sensors and actuators. I will give an overview of recent efforts in developing systems of-on-chips based on open source hardware and  capable of significant analytics and AI functions “at the extreme edge”, i.e. within the limited power budget of traditional microcontrollers that can be co-located and integrated with the sensors/actuators themselves.  These open, extreme edge AI platforms create an exciting playground for research and innovation.

Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. In 2009-2012 he served as chief architect in STmicroelectronics France.  Dr. Benini’s research interests are in energy-efficient computing systems design, from embedded to high-performance. He is also active in the design of ultra-low power VLSI Circuits and smart sensing micro-systems. He has published more than 1000 peer-reviewed papers and five books. He is an ERC-advanced grant winner, a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award and of the  2019 IEEE TCAD Donald O. Pederson Best Paper Award.

Other invited speakers
Carole-Jean Wu (Facebook).
Two additional speakers from industry (Arm, Google) will be announced before the paper submission deadline.

Presentations will include ample time for interaction.

Topics of interest include (but are not limited to):

– Novel ML systems?: heterogeneous multi/many-core systems, GPUs, FPGAs;
– Software ML acceleration: languages, primitives, libraries, compilers and frameworks;
– Novel ML hardware accelerators and associated software;
– Emerging semiconductor technologies with applications to ML hardware acceleration;
– ML for the construction and tuning of systems;
– Cloud and edge ML computing: hardware and software to accelerate training and inference;
– Computing systems research addressing the privacy and security of ML-dominated systems.

Papers will be reviewed by the workshop’s technical program committee according to criteria regarding a submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions in the context of accelerating machine learning. Research papers, case studies, and position papers are all welcome.
In particular, we encourage authors to submit works-In-Progress papers: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and generally spark discussion.

The workshop does not have formal proceedings.

Important Dates
Submission deadline: November 8, 2019
Notification of decision: December 6, 2019

José Cano (University of Glasgow)
Valentin Radu (University of Edinburgh)
Marco Cornero (DeepMind)
Albert Cohen (Google)
Olivier Temam (DeepMind)
Alex Ramirez (Google)

Call for Papers: IEEE TC Special Issue on Domain-Specific Architectures for Emerging Applications
Submitted by Lisa Wu Wills

IEEE TC Special Issue on Domain-Specific Architectures for Emerging Applications

Submissions Due: December 15, 2019

IEEE Transactions on Computers seeks original manuscripts for a Special Issue on Domain-Specific Architectures for Emerging Applications scheduled to appear in May 2020.

Domain-specific architectures have gained prominence in the effort to overcome the stagnation in transistor feature-size scaling. The push towards greater performance and energy efficiency gains have necessitated in dedicated hardware focused on accelerating key application kernels. Such accelerators have proliferated, particularly in the machine learning and deep learning space, and are increasingly becoming essential components of mainstream commercial processors across a multitude of other domains as well. The rapid rate at which application and system software are evolving has also been reflected in processor design methodologies with most general-purpose computers being augmented with custom accelerators, both on and off-chip, making hardware-software co-development an essential component of the design and manufacturing flow. This IEEE Transactions on Computers Special Issue on Domain Specific Architectures for Emerging Applications seeks to expand our understanding of novel accelerator designs across emerging application domains, from circuit and microarchitecture aspects, to solutions at the compiler and system-software level.

Topics of interest to this special issue include, but not limited to:

  • Novel accelerator designs catering to biomedical, healthcare, geospatial, industrial and manufacturing sectors, big data analytics, autonomous driving systems and other emerging domains
  • Prototype demonstrations of field deployment-ready accelerators.
  • Novel cloud-backed edge accelerator designs and architecture/system-software support thereof
  • Special optimizations targeted towards maximizing energy efficiency and reliability of the accelerator
  • Design of novel memory architectures for accelerators
  • Leveraging emerging logic and memory technologies in accelerator designs
  • Novel interconnect designs for heterogeneous accelerator-rich systems
  • New agile design automation techniques for design and manufacturing of accelerator-rich systems
  • Scalable distributed algorithms and architectures for homogeneous/heterogeneous accelerator swarms

Submitted articles must not have been previously published or currently submitted for journal publication elsewhere. As an author, you are responsible for understanding and adhering to the Transactions submission guidelines. Those guidelines are available on the IEEE Computer Society web site, Please thoroughly read these before submitting your manuscript. Please submit your paper to Manuscript Central at

Please note the following important dates.

  • Submission Deadline: December 15, 2019
  • Reviews Completed: February 1, 2020
  • Major Revisions Due: March 1, 2020
  • Reviews of Revisions Completed: March 15, 2020
  • Notification of Final Acceptance: March 15, 2020
  • Publication Materials for Final Manuscripts Due: April 1, 2020
  • Publication date: May 2020

Please address all other correspondence regarding this special session to Guest Editors Karthik Swaminathan ( and Lisa Wu Wills (

Call for Papers: IEEE Micro Special Issue on Machine Learning for Systems
Submitted by Heiner Litz

IEEE Micro Special Issue on Machine Learning for Systems

Submissions due: 2/24/20

The proliferation of hardware accelerators has enabled the pervasive use of machine-learning algorithms in a range of diverse real-world applications, from computer vision to natural language processing. In addition to building the systems and accelerators that have enabled this current momentum in artificial intelligence, the computer architecture community has also explored these new models to improve and optimize the computing systems that we build.

This is a less-explored but promising research direction, with important implications across the full computing stack: from software performance and profiling to operating systems, compilers, architecture, microarchitecture, and circuit design. Potential improvements involve increasing hardware performance and efficiency, performing design space explorations, improving design automation, and reducing the efforts of architecting and designing hardware.

This special issue of IEEE Micro will explore broadly the use of machine learning including supervised, unsupervised, and reinforcement learning-based techniques to improve computer architecture and computer systems. Papers on the following topics are solicited:

Use of machine learning to improve:

  • Computer Architecture, Microarchitecture, and Accelerators
  • Circuit Design and Layout
  • Interconnects and Networking
  • Memory and Storage Systems
  • Runtime Systems
  • Datacenter Management
  • Computing at the Edge
  • Algorithm Optimization of Hardware and Software Systems
  • Hardware/Software Co-Design
  • Source Code Optimization
  • Compilers
  • Modeling and Simulation Techniques
  • Workload Characterization
  • Profiling and Performance Optimization

Important Dates

Submissions due: 2/24/20
Reviews due: 4/6/20
Revisions due: 6/8/20
Final reviews due: 6/29/20
Final notifications: 7/13/20
Publication: Sept/Oct 2020

Submission guidelines

Please see the Author Information page and the Magazine Peer Review page for more information. Please submit electronically through ScholarOne Manuscripts (, selecting this special-issue option.


Contact guest editors Heiner Litz and Milad Hashemi at or editor-in-chief Lizy John at

Call for Papers: IEEE Micro Special Issue on Agile and Open-Source Hardware
Submitted by Trevor E. Carlson

IEEE Micro Special Issue on Agile and Open-Source Hardware

Submissions Due: January 3, 2020

As the benefits of traditional technology scaling, like Dennard Scaling and Moore’s Law, slow significantly, computer architecture is poised to enter a golden age of innovation. Domain-specific architectures (DSA) are a promising solution to continue improving computing performance, while maintaining the level of energy efficiency previously found in technology scaling. Unfortunately, traditional methodologies of chip design and hardware development have created significant barriers, requiring extremely high non-recurring engineering (NRE) costs in tools, labor, IPs, etc., ultimately prohibiting the wide adoption of DSA.

In contrast, the significant engineering costs and extremely long design cycles of software have shrunk significantly over the past decades due to the proliferation of open-source software and the use of agile software development techniques. Small teams of software developers can now realize their innovative ideas quickly. Inspired by these results from the software community, agile and open hardware design is considered to be one of the most promising ways to lower the design cost of chip design, although there are still many challenges in abstraction, methodologies, and tools. This special issue of IEEE Micro will explore academic and industrial research on topics that relate to agile chip design and open-source hardware. Such topics include, but are not limited to:

  • Agile DSA accelerator design approaches, targeting ASICs or reconfigurable fabrics (e.g. FPGAs)
  • Open-source EDA tools and methodologies to enable agile hardware development
  • High-level hardware abstraction and representation
  • New hardware description languages
  • Domain-specific languages (DSLs)
  • Agile hardware development for formally verified designs
  • Agile domain-specific ISA/extension design
  • Hardware generator methodologies
  • Verification and simulation approaches
  • Fast chip design-space exploration
  • Agile hardware and software co-design approaches
  • Comparison studies of different hardware design and development approaches
  • Survey and tutorial studies of agile and open-source hardware

Important Dates

  • Submissions due: January 3, 2020
  • Initial notifications: March 6, 2020
  • Revised papers due: April 10, 2020
  • Final notifications: May 15, 2020
  • Final versions due: June 1, 2020
  • Publication: July/August 2020

Submission guidelines

Please see the Author Information page and the Magazine Peer Review page for more information. Please submit electronically through ScholarOne Manuscripts (, selecting this special-issue option.


Contact guest editors Yungang Bao and Trevor E. Carlson at or the editor-in-chief Lizy John at

Call for Workshops/Tutorials: ISPASS 2020: CALL for WORKSHOP and TUTORIAL PROPOSALS
Submitted by I-Ting Angelina Lee

2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
April 5-7, 2020 in Boston, MA, USA

Proposals Due: November 1, 2019

ISPASS 2020 will be hosting both workshops and tutorials at the conference venue. The purpose of these gatherings is to provide a forum for exchanging ideas and preliminary results of topics that are related to ISPASS in an interactive environment. We invite proposals from both academia and industry with the intent to draw upon the collective experience, interests, and opinions of our conference attendees.

Submission information:

All proposals must provide the following information:

• Workshop or tutorial name and a 150- to 200-word abstract describing the event, suitable for the conference web site.
• In case of a tutorial proposal, detailed outline of the tutorial, rationale for co-locating with ISPASS, presenter(s), duration (full/half day), any requirements to run the tutorial.
• In case of a workshop proposal, rationale for the workshop and for co-locating with ISPASS, draft Call For Papers (CFP), workshop deadlines, main organizers and tentative composition of the committees, duration (full/half day), format (expected number of presentations, invited talks, keynote, panel, etc.), expected number of submissions and participants.
• If applicable, provide a description of past versions of the activity, including dates, organizers, submission and acceptance counts (for workshops), attendance, and information with which conference the workshop/tutorial was co-located.

Proposals should be emailed to

Important dates:
Proposals due: November 1, 2019
Acceptance notification: November 8, 2019
Date of Tutorial/Workshop: April 5, 2020

For any questions, please contact the ISPASS 2020 workshop/tutorial chair Lieven Eeckhout at Ghent University by sending an email to

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Samira Khan
SIGARCH Content Editor