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Call for Papers: FCCM 2027
https://www.fccm.org
Submitted by Nan Wu

The 35th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2027)
May 9 – 12, 2027, Provo, Utah, USA
Conference Site: https://www.fccm.org
Submission Site: https://fccm27.hotcrp.com/

The IEEE Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past three decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems.

Topics of Interest

• Custom Computing and Reconfigurable Architectures:
  Heterogeneous and mixed signal digital/analog field customizable accelerators
  Neuromorphic emulation and accelerators
  Memory centric computing architectures
  Overlays, coarse-grained reconfigurable architectures
  Clusters, data centers, and large systems
  IoT and Embedded SoC, MPSoC architectures with reconfigurable devices
  Security enhancements for reconfigurable computing
  Customizable soft processor systems
  
• Abstractions, Programming Models, and Tools:
  Use of Large Language Models (LLMs) for FPGA design
  Domain-specific languages, frameworks, and open-source HW/SW synthesis/compilation tools
  Design tools, instrumentation, debug for designer productivity
  High-level synthesis
  Software-defined-systems (e.g. radio, networks, frameworks for new domains)
  CAD tools, abstractions, and languages for mixed analog/digital fabrics
• Run-Time Reconfiguration:
  Run-time management and scheduling of reconfigurable hardware
  System resilience/fault tolerance for reconfigurable hardware
  Evolvable, adaptable, approximate, or autonomous reconfigurable computing systems
  Security assessment and enhancement of run-time reconfiguration
• Applications:
  Evaluations and analysis on custom computing architectures with GPUs, NPUs, or DSPs
  Post Quantum Cryptography, quantum control and emulation
  Safety critical, reliable and high assurance
  Security detection and prevention, and side channel analysis and attack
  Digital twin, modeling, and acceleration

Submission Guidelines

Research submissions can be in either of two categories:

• Long — at most 8 pages (excluding references), for a regular presentation at the conference.
• Short — at most 4 pages (excluding references), for a brief presentation at the conference. This category is intended for new projects, early results, late breaking, and work that can be presented concisely in the 4-page budget.

FCCM uses a double-blind review system. Manuscripts must not identify authors or their affiliations. In addition, papers must not be simultaneously under review or waiting to appear at another conference or in a journal and must not be essentially the same as any paper that has been previously published.

AI policy: Per IEEE policy, the use of content generated by AI in an article (including but not limited to text, figures, images, and code), except editing and grammar enhancement, shall be disclosed in the acknowledgments section of any article submitted to an IEEE publication. Failure of proper disclosure may result in a desk reject.
For more detailed submission guidelines, please refer to https://www.fccm.org/call-for-papers-2027/.

Important Dates

All deadlines are in the Anywhere on Earth (UTC– 12) time zone

• Abstract Submission Due: January 10th, 2027 (No Extensions)
• Full Paper Submission Due: January 17th, 2027 (No Extensions)
• Rebuttal Period: February 23 – 27th, 2027
• Notification of Acceptance: March 14th, 2027
• Camera-Ready Submission Due: April 4th, 2027

Organizing Committee
General Chair: Jeff Goeders, BYU
Program Chair: Zhenman Fang, University of Minnesota

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Call for Papers: Workshop on Accelerated Machine Learning (AccML) @ HiPEAC 2027
https://accml.dcs.gla.ac.uk/
Submitted by José L. Abellán

9th Workshop on Accelerated Machine Learning (AccML)
Co-located with the HiPEAC 2027 Conference
January 19, 2027
Glasgow, United Kingdom

Topics of interest include (but are not limited to):

• Novel ML/AI systems: heterogeneous multi-/many-core systems, GPUs, NPUs/TPUs, ASICs, FPGAs, and chiplet-based accelerators;
• Software ML/AI acceleration: programming models, languages, primitives, libraries, compilers, runtimes, and frameworks;
• Novel ML/AI hardware accelerators and associated system software;
• Emerging semiconductor, near-/in-memory, analog, photonic, and neuromorphic technologies for ML/AI hardware acceleration;
• ML/AI for the design, optimization, autotuning, and management of hardware, compilers, runtimes, and systems;
• Cloud, data-center, edge, embedded, and on-device ML/AI computing: hardware and software to accelerate training and inference;
• Hardware/software co-design techniques for efficient model training and inference, including quantization, sparsity, pruning, compression, efficient attention, and distillation;
• Training, fine-tuning, serving, and deployment of foundation models, LLMs, multimodal models, large GNNs, recommender systems, agentic AI, and retrieval-augmented generation;

Invited Speakers
Anton Lokhmotov (KRAI): “KRAI’s vision on Accelerated Accelerator Programming”.
Miquel Moreto (BSC): “Designing HPC Architectures to Accelerate AI at BSC”

Submission
Papers will be reviewed by the workshop’s technical program committee according to criteria regarding the submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions in the context of accelerating machine learning. Research papers, case studies, and position papers are all welcome.

In particular, we encourage authors to submit work-in-progress papers: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and spark productive discussions.
The workshop does not have formal proceedings.

Important Dates
Submission deadline: November 13, 2026
Notification of decision: November 27, 2026

Links to the Workshop page
Organizers: https://accml.dcs.gla.ac.uk/workshop-2027-hipeac.html
HiPEAC: https://www.hipeac.net/2027/glasgow/#/program/8325/

Organizers
José L. Abellán (University of Murcia)
Valentin Radu (University of Sheffield)
Ulysse Beaugnon (Google DeepMind)
José Cano (University of Glasgow)

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Call for Papers: Submit Agentic Hardware Research to and Attend the A3 Workshop
https://agentic-arch.org/call-for-papers.html
Submitted by Jack Toubes

A3: Workshop on Agentic Approaches to Architecture
Co-located with MICRO 2026
November 1, 2026
Athens, Greece
https://agentic-arch.org

The A3 workshop explores the paradigm shift toward reasoning-capable AI agents in computer architecture. A3 centers on agentic methodologies which leverage AI reasoning and planning, combined with agentic tool use, perception, and iterative refinement/memory, to make impactful contributions to computer architecture and surrounding fields.

The primary goal of A3 is to foster a collaborative community focused on agentic methodologies in computer architecture. By bringing together researchers in this emerging area, the workshop aims to establish an open forum for sharing preliminary research and establishing core best practices through expert presentations and panel sessions. We welcome 2-4 page submissions that advance the frontier of agentic methodologies throughout the hardware/software co-design ecosystem.

Topics of Interest: https://agentic-arch.org/call-for-papers.html

Agentic discovery for architecture
Agentic cross-stack HW/SW co-design
Dynamically adapting agentic systems for hardware
Infrastructure for agents for hardware
Engineering and analysis of agents for hardware
Making hardware design tools better for Agents
Topics may span architecture and all related fields
e.g. EDA, VLSI, HW/SW co-design, compilers, systems, and more.

Submission Guidelines:

Paper length: 2-4 pages with IEEE or ACM format, excluding references
Other requirements will broadly follow those of conferences like ASPLOS, ISCA, and MICRO. Use of AI-assistance in paper writing is welcomed, but must be acknowledged at the end of the paper. Human authors are responsible for the entire contents, tone, and quality of their paper.

Important Dates:
Abstract Registration Deadline: September 14 AoE
Paper Submission Deadline: September 21, AoE
Decisions Released: September 26, AoE (two days before MICRO early-registration deadline)
Workshop Day: November 1, 1-5pm

Contact: a3-workshop@lists.berkeley.edu