SIGARCH

This is the 1st June 2026 digest of SIGARCH Messages.

In This Issue

Call for Papers: PDSW 2026 @ SC26 - (Note: The Call for Paper type has not been set for this item!)

Call for Nominations: Call for Nominations: IEEE CS TCuArch Graduate Student Industry Impact Award
https://ieee.secure-platform.com/a/solicitations/1477/home
Submitted by Onur Kayiran

IEEE Computer Society TCuArch Graduate Student Industry Impact Award

Call for Nominations
The IEEE Computer Society TCuArch Graduate Student Industry Impact Award recognizes a graduate student for exceptional technical contributions made during an industry internship in the field of computer architecture. The award honors students whose work demonstrates high technical quality, innovation, and clear relevance to industry needs. The award highlights the role graduate students play in strengthening ties between academia and industry, fostering collaboration, and advancing research that informs both scientific progress and industrial practice.

Official Citation: “For exceptional technical contributions during an industry internship, advancing both industrial impact and academic-industry collaboration in computer architecture.”

Administration: The award is administered by IEEE Computer Society Technical Committee on Microarchitecture (TCuArch).

Eligibility: The nominee must be a current graduate student enrolled in a master’s or doctoral program and an active member of IEEE Computer Society TCuArch at the time of nomination. The nominee must be currently engaged in, or have completed, an industry internship within one year prior to the nomination deadline. The internship contribution must be technical in nature and directly relevant to the company’s products, services, technical capability, or strategic direction. Nominations must be submitted by the student’s academic advisor; self-nominations are not accepted.

A complete nomination package must include the following:

1. A letter from the industry mentor, up to 2 pages, who directly supervised the student during the internship. The letter should describe the technical quality and innovation of the student’s contributions, the expected or demonstrated impact on the company’s product, service, technical capability, or strategic direction, and how the student demonstrated initiative, problem-solving skills, and collaboration.
2. Up to two optional supporting letters from other industry co-advisors or collaborators involved in the internship, providing additional perspective on the student’s technical contributions and impact.
3. The nominee’s CV, up to 3 pages, highlighting relevant research, technical contributions, and achievements.

Prize: Up to two recipients may be selected annually. Each recipient receives a commemorative plaque and recognition on the TCuArch website and communications. No honorarium or travel allowance is provided.

Multiple Nominations: In case of multiple nominations of the same individual, only one nomination package will be considered, and the nominators may be asked to coordinate a single complete package. Withdrawal of a nomination may be requested by the corresponding nominator or by the nominee before the nomination deadline.

Nominations should comply with IEEE Policies and restrictions on awards. Incidents of misconduct including, but not limited to, violations of IEEE’s publication policies, will be strongly considered by the awards committee and may be grounds for denial of an award or leadership position.

Nomination Deadline: July 8, 2026

Submission: Via the IEEE online nominations portal: https://ieee.secure-platform.com/a/solicitations/1477/home. The nomination portal is expected to open during the week of June 15, 2026.

Call for Nominations: IEEE Computer Society TCuArch Mid-Career Faculty Mentoring Award
https://ieee.secure-platform.com/a/solicitations/1476/home
Submitted by Guru Venkataramani

IEEE Computer Society TCuArch Mid-Career Faculty Mentoring Award

Description: The IEEE Computer Society TCuArch Mid-Career Faculty Mentoring Award recognizes a mid-career faculty member who has demonstrated exceptional dedication to mentoring and role modeling within the TCuArch community. The award honors individuals who guide students and junior colleagues in their technical and career development and whose mentoring impact extends beyond their own research group to benefit the broader computer architecture community. By fostering professional growth, promoting collaboration, and serving as examples of leadership and integrity, the awardee strengthens the pipeline of future leaders and advances excellence and inclusivity in the field.

Administration: The award is administered by IEEE Computer Society TCuArch.

Eligibility: The nominee must be a mid-career faculty member with a minimum of 6 years and a maximum of 15 years in a faculty position at the time of nomination and an active member of IEEE TCuArch at the time of submission. The nominee should be an active and respected member of the computer architecture research community, with evidence of leadership and service. Mentoring contributions must extend beyond the nominee’s immediate research group and demonstrate engagement with the broader TCuArch community.

A complete nomination package must include the following:
1. The nomination letter, up to 2 pages shall describe the nominee’s mentoring philosophy, sustained contributions, and evidence of impact on mentees’ technical and career growth. The letter should highlight how the nominee’s mentoring and role modeling extend beyond their immediate research group, influencing the broader academic and professional community.
2. Up to three but no less than 2 supporting letters from current or former mentees or colleagues, ideally including individuals outside the nominee’s own group, that highlight specific examples of the nominee’s mentorship and role modeling.
3. Evidence of Impact (optional appendix, up to 2 pages) such as mentee achievements, testimonials, community initiatives, or examples of mentorship contributions beyond the nominee’s lab.
4. The nominee’s CV (up to 4 pages) that highlights academic achievements, mentoring activities, and community engagement.

In case of multiple nominations of the same individual, only one nomination package will be considered, and the nominators may be asked to coordinate a single complete package. Withdrawal of a nomination may be requested by the corresponding nominator or by the nominee before the nomination deadline of July 8, 2026.

Nominations should comply with IEEE Policies and restrictions on awards. Incidents of misconduct including, but not limited to, violations of IEEE’s publication policies, will be strongly considered by the awards committee and may be grounds for denial of an award or leadership position.

Award submissions and related information can be found at https://ieee.secure-platform.com/a/solicitations/1476/home

Call for Nominations: Call for Nominations: MICRO Test of Time Award 2026
https://www.sigmicro.org/awards/tot/cfn.php
Submitted by Saugata Ghose

The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the thirteenth MICRO ToT Award. This award recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field.

The award will recognize an influential MICRO paper whose influence is still felt 18-22 years after its initial publication. In other words, the award will be given to one or more papers published at MICRO conferences in any of the years N-22, N-21, N-20, N-19, or N-18. This year, N = 2026, so only papers published at MICRO conferences held in 2004, 2005, 2006, 2007, or 2008 are eligible. An eligible paper that has received at least 100 citations (according to Google Scholar) is automatically nominated, but explicit nominations of such papers are still encouraged.

Nominating a Paper
To nominate a paper, send an email to micro-tot-award-nominations@googlegroups.com by July 10, 2026, with the following:

  1. The title, the author list, and publication year of the nominated paper
  2. A 100-word (maximum) nomination statement, describing why the paper deserves the Test of Time Award
  3. The name, title, affiliation of the nominator, and if appropriate, the relationship of the nominator to the authors

Only one paper can be nominated in a single email. There is a maximum of five nominations per person. You cannot nominate a paper that you are a co-author on. One paper will be selected as the award winner from the pool of nominees by the award committee.

For more information on the nomination and selection process, a list of all eligible papers, this year’s committee members, prior award winners, and other information, please visit https://www.sigmicro.org/awards/tot/

Call for Nominations: SIGMICRO Distinguished Service Award Nominations
https://www.sigmicro.org/awards/dsa.php
Submitted by Erik Altman

SIGMICRO Distinguished Service Award – Call for Nominations

We seek nominations by July 13 for the 2026 SIGMICRO Distinguished Service Award.  This annual award is presented to an individual who has contributed important service to the processor microarchitecture and microsystems community while also serving as an active member of SIGMICRO who has contributed (or is contributing) significantly to SIGMICRO organization and/or SIGMICRO-sponsored conference committees.

Nominations
Nomination packages should be emailed to the selection committee chair, Erik Altman:  ealtman@us.ibm.com
A nomination for the Distinguished Service Award that is not awarded may remain valid for consideration in future years.

Each nomination should consist of the following:

  • Name, email address, and phone number of the person making the nomination (the nominator).
  • Name, address, phone number, and email address of the candidate for whom an award is recommended (the nominee).
  • A short statement (200-500 words) explaining why the nominee deserves the award in question.
  • A one-sentence citation to be used if the nominee receives the award.
  • Names and email address of 3-4 people to who will send 200-500 word endorsements of the nomination to the same email address above and by the same July 13 deadline.

Self-nominations are not allowed.

Recognition
The award recipient will receive a memento engraved with their name along with a $1000 honorarium.  The award is presented by the SIGMICRO Chair at MICRO during MICRO’s award presentation session.  The award recipient may receive up to $2000 towards MICRO conference registration, and when attendance is not virtual, support for travel costs such as airfare and hotel.  Additional travel support may be provided at the discretion of the SIGMICRO Executive Committee.

The recipient will be listed with the citation for their award on the SIGMICRO Distinguished Service Award website:  https://www.sigmicro.org/awards/dsa.php

Committee
Erik Altman (Chair)
Mattan Erez
Ulya R. Karpuzcu
Thomas Wenisch

Call for Participation: GCASR 2026
https://gcasr.org/2026
Submitted by Peter Dinda

13th Greater Chicago Area Systems Research Workshop (GCASR 2026)
May 11, 2026
Northwestern University, Evanston, Illinois
https://gcasr.org/2026

The GCASR Workshop, now in its 13th iteration, is a premier venue that promotes awareness, collaboration, and synergy among academic and industry systems researchers in Chicagoland and the greater Midwest region. Its participants span a variety of systems sub-disciplines—including (but not limited to) operating systems, distributed and decentralized computing, machine learning systems, high performance computing, computer architecture, networks, databases, programming languages and compilers, quantum computing, and security.

GCASR 2026 will consist of a keynote, a range of invited talks, and a robust poster session, all highlighting systems research in Chicagoland and the greater Midwest region.
Faculty members, researchers, postdocs, students, industry professionals, and others with an interest in the workshop topics are invited to submit a poster for presentation at GCASR 2026. We welcome posters that highlight theoretical and experimental work in computing systems—including benchmarking, theoretical results, applications, software design, and algorithm/protocol design.

Important Dates

  • Friday, April 10th, 2026 — Abstract Deadline
  • Friday, April 17th, 2026 — Poster Notification
  • Monday, May 11, 2026 — Workshop (Northwestern University, Evanston, Illinois)

Submission Requirements

Topics of Interest

  • Operating Systems
  • Computer Architecture
  • Networking
  • Distributed Systems
  • Grids/Clouds/Supercomputing (including HPC/MTC/HTC)
  • Edge Computing
  • Internet-of-Things
  • Energy Efficient Computing
  • Reconfigurable, Real-time, Cyber-Physical, and Embedded Systems
  • Programming Languages, Runtime Systems, and Compilers
  • File and Storage Systems
  • Parallelism and Multi/Many-core Systems
  • Secure and Reliable Systems
  • Databases
  • Artificial Intelligence and Machine Learning
  • Quantum Computing

Call for Participation: ISCA 2026
https://iscaconf.org/isca2026
Submitted by Adarsh Patil

53st International Symposium on Computer Architecture (ISCA 2026)
June 27– July 1, 2026
Raleigh, USA

The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture.
ISCA is being held in Raleigh at the Raleigh Convention Center. The program promises to be truly exciting, featuring forward-looking and novel technical paper presentations.
We warmly invite you to join us!

Registration for the conference is now open at: https://iscaconf.org/isca2026/attend/register.php
(Early Registration Deadline: 11:59pm AoE, May 22, 2026)

For those of you requiring a Visa we strongly encourage to start the process as soon as possible.
Visa information is now available at: https://www.iscaconf.org/isca2026/attend/visa.php

For more details on ISCA 2026, please visit the main conference website at:
https://iscaconf.org/isca2026/

Call for Participation: UR2PhD Tutorial: Strategies for Productively Engaging Undergraduate Students in Research
https://cra.org/events/ur2phd-isca-tutorial/
Submitted by Kelly Shaw

UR2PhD Tutorial: Strategies for Productively Engaging Undergraduate Students in Research
Co-located with ISCA 2026
Raleigh, NC, USA
Sunday, June 28, 2026

Overview:

Do you want to engage undergraduate students to work on your research, but you don’t know how to do so productively? Do you worry about the time commitment of doing so? 

Working with undergraduate students can help move your research forward productively and can be an enjoyable experience for both you and the students with appropriate planning.  This tutorial will offer concrete strategies for recruiting and mentoring undergraduate researchers. 

Participants will be guided through how to design a well-scoped initial project that is appropriate for undergraduate students and that will advance the participants’ research.  Additionally, the tutorial will include a hands-on session in which the participants will develop onboarding materials that they can use repeatedly for new undergraduate students joining their research group over the course of a project’s duration. 

This tutorial can benefit everyone who works with undergraduate students on research or any long running technical project – graduate students, post-docs, faculty members, and industry professionals.  

Tentative Schedule:

  • 8:00 –  8:30:  Why work with undergraduate researchers? How is working with undergraduate students different from working with graduate students?
  • 8:30 – 10:00:  Hands-on Activity: Designing well-scoped research projects for undergraduates
  • 10:00 – 10:15: Break
  • 10:15 – 11:00: Hands-on Activity: Designing reusable, research onboarding materials
  • 11:00 -12:00: Strategies for mentoring/advising undergraduate researchers, including lots of Q&A

Organizers:

  • Kelly Shaw (Williams College)
  • Susan Rodger (Duke University)

Call for Papers: CCMCC 2026: IEEE Cross-Disciplinary Conference on Memory-Centric Computing
https://ccmcc.eclectx.org/cfp.html
Submitted by Saugata Ghose

2nd IEEE Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC 2026)
October 28–30, 2026
Lyon, France

CCMCC is a cross-disciplinary conference that brings experts from diverse fields together, all working on advancing memory-centric computing, including in-memory computing and processing-near-memory. It is a platform for sharing new ideas, exchanging insights, and fostering collaboration. CCMCC’s mission is to accelerate innovation in memory-centric computing and its integration into real-world applications.

We are soliciting papers across the entire memory-centric computing stack, from software to architecture to circuits and devices. Authors can choose to submit either a long paper (10–12 pages) or a short paper (4–6 pages). More details on topics of interest, formatting requirements, and submission procedures can be found at https://ccmcc.eclectx.org/cfp.html

Important Dates
Abstracts due June 15;
Full papers due June 22

Call for Papers: Composable Heterogeneous Architecture for Scalable Machine Learning (CHASM) Workshop @ MICRO’26
https://sites.google.com/view/chasm-micro26/home
Submitted by Tom St. John

Composable Heterogeneous Architecture for Scalable Machine Learning (CHASM) Workshop
Co-located with MICRO 2026
https://sites.google.com/view/chasm-micro26/home
November 1, 2026


The scale and complexity of modern artificial intelligence workloads, particularly the rise of agentic AI and multi-modal foundational models, have outpaced the capabilities of monolithic compute nodes.  As the industry scales, the future of AI infrastructure relies on the effective disaggregation of workloads across heterogeneous hardware.

The CHASM workshop aims to bring together researchers and practitioners from computer architecture, systems software, and machine learning to address the critical bottlenecks in disaggregated AI.  We seek to explore the full stack of challenges from hardware-level interconnects and memory pooling to the systems software required to compile, orchestrate, and verify highly dynamic execution graphs across heterogeneous accelerators.

Topics of Interest
  • Systems Software and Compilation
    Compilation frameworks and intermediate representations for disaggregated, heterogeneous environments
    Compilation, scheduling, and runtime orchestration of agentic AI workloads as dynamic execution graphs
    Formal verification, debugging, and equivalence checking for distributed tensor algebra and parallel execution
    Online adaptation, test-time training, and adaptive inference compute in deployed agentic AI systems on disaggregated infrastructure
  • Architecture and Hardware
    Architectures for scalable memory disaggregation and pooling in AI clusters
    High-performance interconnects and networking protocols tailored for heterogeneous accelerator communication
    Hardware-software co-design for composable AI systems
  • Characterization and Evaluation
    Characterization of agentic, multi-modal, and tool-augmented Ai workloads on heterogeneous systems
    Marginal cost-efficiency analysis and performance benchmarking of contemporary AI accelerators in distributed topologies
    Novel simulation and evaluation methodologies for disaggregated datacenter architectures
    Telemetry, profiling, and bottleneck analysis in large-scale heterogeneous AI deployments

 

Submission Guidelines
We solicit both full papers (8-10 pages) and short/position papers (4-6 pages). Submissions are double-blinded. The page limit includes figures, tables, and appendices, but excludes references. Please use standard LaTeX or Word ACM templates. All submissions will need to be made via EasyChair (link) . Each submission will be reviewed by at least three reviewers from the program committee. Papers will be reviewed for novelty, quality, technical strength, and relevance to the workshop.

Call for Papers: HotStorage @ SOSP 2026
https://www.hotstorage.org/2026/index.html
Submitted by Zeren Yang

8th ACM Workshop on Hot Topics in Storage and File Systems (HotStorage ’26)
September 28th and 29th, 2026
Prague, Czechia,
co-located with SOSP 2026

The workshop is sponsored by ACM in cooperation with USENIX, and its proceedings will appear in the ACM Digital Library.

The HotStorage workshop provides a forum for cutting-edge storage research, a place where academic researchers and industry practitioners can discuss new opportunities and challenges in storage technology. Submissions should propose new research directions, explore non-traditional approaches, or report on noteworthy or counterintuitive learnings and experience in emerging areas. Submissions will be judged on their originality, technical merit, topical relevance, and the likelihood of leading to insightful discussions that will influence future storage systems design and applications.

In keeping with the goals of the HotStorage workshop, the review process will favor submissions that are forward-looking and open-ended. If you are only a couple of months away from submitting to FAST, NSDI, EuroSys, VLDB, OSDI, SOSP, ASPLOS, SoCC, etc. you are probably already past the sweet spot for HotStorage. If you have a forward-looking or unorthodox idea or new research, and some evidence or early working system to support your view, but still have open questions, please consider bringing your work to HotStorage. The program committee will also welcome position papers that solicit discussion on controversial topics, introduce emerging methods and paradigms, or call out for new research directions.

Call for Papers: Ramulator & DRAM Bender Tutorial @ ICS 2026
https://events.safari.ethz.ch/ics26-ramulator-drambender/
Submitted by Tracy Ewen

Third Workshop+Tutorial on Ramulator & DRAM Bender: Cutting-Edge Infrastructures for Real and Future Memory System Evaluation (R&DB),
Co-located with the ACM International Conference on Supercomputing 2026 (ICS 2026)
Belfast, Northern Ireland, United Kingdom,
Monday, July 6th.

A limited number of slots are available for invited presentations alongside our invited talks on DRAM characterization and memory system simulation. We welcome extended abstract submissions to be included in the ICS’26 proceedings on a broad range of topics related to memory system evaluation using Ramulator or DRAM Bender, including extensions and enhancements to either infrastructure, studies on performance, reliability, security, or emerging memory technologies, cross-layer research combining simulation with real-chip characterization, demonstrating new research insights.

We especially encourage early-stage research, work-in-progress results, experimental methodologies, and community contributions that will benefit the broader memory systems community.

To submit, send a brief proposal with an extended abstract of your work.
Submission deadline: May 21, 2026 (AoE)
Submission website: forms.gle/Hfa2pfGD7BS7jXJi6

Workshop website & submission details: https://events.safari.ethz.ch/ics26-ramulator-drambender/

Don’t miss this opportunity to showcase your research and connect with the memory systems community!
Organizers: Nisa Bostanci, Ataberk Olgun, Ismail Emir Yuksel, Haocong Luo, Onur Mutlu

Call for Papers: IEEE Micro Special Issue: GenAI in the Age of Chiplets
https://www.computer.org/digital-library/magazines/mi/cfp-gen-ai-age-chiplets
Submitted by Augusto Vega

  • Submission deadline: Aug 2, 2026
  • Publication: Jan/Feb 2027
  • Guest Editors: Augusto Vega & Pradip Bose (IBM Research)

We invite submissions to an IEEE Micro Special Issue on “GenAI in the Age of Chiplets”.

The issue focuses on system and architectural challenges at the intersection of generative AI and chiplet-based design, including scalability, efficiency, and full-stack co-design.

Topics include chiplet architectures (2.5D/3D), interconnects/memory, AI accelerators, HW/SW    co-design, reliability/security, and deployment experience.

More information: https://www.computer.org/digital-library/magazines/mi/cfp-gen-ai-age-chiplets

Note: The Call for Paper type has not been set for this item!

Call for Papers: PDSW 2026 @ SC26
https://www.pdsw.org/
Submitted by Sarah Neuwirth

The 11th International Parallel Data Systems Workshop (PDSW 2026)
https://www.pdsw.org/

We are excited to announce the 11th International Parallel Data Systems Workshop (PDSW’26), to be held in conjunction with SC26: The International Conference for High Performance Computing, Networking, Storage, and Analysis, in Chicago, IL. PDSW’26 builds upon the rich legacy of its predecessor workshops, the Petascale Data Storage Workshop (PDSW, 2006–2015) and the Data Intensive Scalable Computing Systems (DISCS, 2012–2015) workshop.
The increasing importance of efficient data storage and management continues to drive scientific productivity across traditional simulation-based HPC environments and emerging Cloud, AI/ML, and Big Data analysis frameworks. Challenges are compounded by the rapidly expanding volumes of experimental and observational data, the growing disparity between computational and storage hardware performance, and the rise of novel data-driven algorithms in machine learning. This workshop aims to advance research and development by addressing the most pressing challenges in large-scale data storage and processing.
We invite the community to contribute original research manuscripts that introduce and evaluate novel algorithms or architectures, share significant scientific case studies or workloads, or assess the reproducibility of previously published work. We emphasize the importance of community collaboration for problem identification, workload capture, solution interoperability, standardization, and shared tools. Authors are encouraged to provide comprehensive experimental environment details (software versions, benchmark configurations, etc.) to promote transparency and facilitate collaborative progress.

Important Dates
Paper Submissions due: July 31st, 2026, 11:59 PM AoE
AD due: August 7th, 2026, 11:59 PM AoE
Paper Notification: Sep 4th, 2026, 11:59 PM AoE
Camera ready due: Sep 25th, 2026, 11:59 PM AoE
Final AD/AE due: Sep 25th, 2026, 11:59 PM AoE
Workshop day: Monday, Nov 16th, 2026 (all day)

Submissions website: https://submissions.supercomputing.org/

Topics of Interest

  • Scalable Architectures: Distributed data storage, archival, and virtualization.
  • New Data Processing Models and Algorithms: Application of innovative data processing models and algorithms for parallel computing and analysis.
  • Performance Analysis: Benchmarking, resource management, and workload studies.
  • Cloud and Container-Based Models: Enabling cloud and container-based frameworks for large-scale data analysis.
  • Storage Technologies: Adaptation to emerging hardware and computing models.
  • Data Integrity: Techniques to ensure data integrity, availability, reliability, and fault tolerance.
  • Programming Models and Frameworks: Big data solutions for data-intensive computing.
  • Hybrid Cloud Data Processing: Integration of hybrid cloud and on-premise data processing.
  • Cloud-Specific Opportunities: Data storage and transit opportunities specific to cloud computing.
  • Storage System Programmability: Enhancing programmability in storage systems.
  • Data Reduction Techniques: Filtering, compression, and reduction techniques for large-scale data.
  • File and Metadata Management: Parallel file systems, metadata management at scale.
  • In-Situ and In-Transit Processing: Integrating computation into the memory and storage hierarchy for in-situ and in-transit data processing.
  • Alternative Storage Models: Object stores, key-value stores, and other data storage models.
  • Productivity Tools: Tools for data-intensive computing, data mining, and knowledge discovery.
  • Data Movement: Managing data movement between compute and data-intensive components.
  • Cross-Cloud Data Management: Efficient data management across different cloud environments.
  • AI-enhanced Systems: Storage system optimization and data analytics using machine learning.
  • New Memory and Storage Systems: Innovative techniques and performance evaluation for new memory and storage systems.
  • AI and Agentic related data management: tools and techniques necessary to support AI workloads and Agentic AI data analytics for online decision making.

Template and Submission
– A full paper up to 6 pages in length, excluding references, acknowledgements, and AD/AE appendices. Once anonymization is removed for camera ready submission, these limits must still be met. Please make sure that author names fit within the 6-page limit as well even though the submission should be double-anonymized.
– Artifact Description (AD) Appendix is mandatory and Artifact Evaluation (AE) Appendix is optional.
– Papers must adhere to the IEEE conference proceeding template available at: https://www.ieee.org/conferences/publishing/templates
– Papers will be reviewed double-blind. Author names and affiliations should NOT be included in the submitted paper.
– Submit your papers by July 31st, 2026, 11:59 PM AoE at https://submissions.supercomputing.org/

Reproducibility Initiative
Aligned with the SC26 Reproducibility Initiative (https://sc26.supercomputing.org/program/papers/reproducibility-initiative/), we require detailed and structured artifact descriptions (AD) using the SC26 format (https://github.com/jennfshr/sc26-repro). The AD should include a field for one or more links to data (Zenodo, figshare, etc.) and code (Github, GitLab, Bitbucket, etc.) repositories. For the artifacts that will be placed in the code repository, we encourage authors to follow the PDSW 2026 Reproducibility Addendum (https://www.pdsw.org/pdsw26/PDSW2026ReproducibilityInitiativeAddendum.pdf) on how to structure the artifact, as it will make it easier for the reviewing committee and readers of the paper in the future.

Submissions website: https://submissions.supercomputing.org/

Organization Team
General Chair:
Jay Lofstead, Sandia National Laboratories, USA

Program Co-Chairs:
Sarah Neuwirth, Johannes Gutenberg University Mainz, Germany
Lipeng Wan, Georgia State University, USA

Call for Presentations: Workshop+Tutorial on Ramulator & DRAM Bender @ISCA’26
https://events.safari.ethz.ch/isca26-ramulator-drambender/
Submitted by Tracy Ewen

2nd Workshop+Tutorial on Ramulator & DRAM Bender: Cutting-Edge Infrastructures for Real and Future Memory System Evaluation (R&DB),
co-located with ISCA 2026
Raleigh, North Carolina
Saturday, June 27th

A limited number of slots are available for invited presentations alongside our invited talks on DRAM characterization and memory system simulation. If you’re working with Ramulator or DRAM Bender, we’d love to hear from you!
We welcome submissions on a broad range of topics related to memory system evaluation using Ramulator or DRAM Bender, including extensions and enhancements to either infrastructure, studies on performance, reliability, security, or emerging memory technologies, cross-layer research combining simulation with real-chip characterization, and community contributions such as benchmarks, methodologies, open-source tools, or case studies demonstrating new research insights.

We especially encourage early-stage research, work-in-progress results, experimental methodologies, and community contributions that will benefit the broader memory systems community!
To submit, send a brief proposal with an extended abstract of your work.

Important Dates
Submission deadline: June 14, 2026 (AoE)

Submission Website: https://forms.gle/mR1UvGueyetKyy8EA
Workshop website & submission details: https://events.safari.ethz.ch/isca26-ramulator-drambender/

Organizers:
Nisa Bostanci, Ataberk Olgun, İsmail Emir Yüksel, Haocong Luo, Onur Mutlu

Call for Presentations: ModSim 2026: Workshop on Modeling & Simulation of Systems and Applications
https://www.bnl.gov/modsim/
Submitted by Jason Lowe-Power

ModSim 2026: Workshop on Modeling & Simulation of Systems and Applications
August 12-14, 2026,
University of Washington Botanic Gardens
Center for Urban Horticulture, Seattle

Workshop URL: https://www.bnl.gov/modsim/
Submission URL: https://easychair.org/conferences/?conf=modsim26

Important Dates
EasyChair Submission Deadline: Friday, June 05, 2026 (11:59 pm PDT; 6:59 am UTC)
Notification of Acceptance: Monday, June 15, 2026 (via e-mail)

To promote advancements in modeling and simulation (ModSim) research, we are soliciting input in the form of abstracts. If accepted, author(s) will be invited to host a short presentation and poster at the annual gathering of our community, the Workshop on Modeling & Simulation of Systems and Applications (ModSim 2026).

The overarching theme this year, “ModSim-integrated AI and HPC,” will emphasize the central role of modeling and simulation in the design, implementation, optimization, operation, and scaling of the exponentially growing artificial intelligence (AI) ecosystem. We will discuss AI-driven ModSim methodologies, tools, best practices, projects, and initiatives; explore new computing and storage technologies for AI; and investigate best-in-class models enabling widely encompassing, quantitative, and accurate ModSim. Moreover, ModSim 2026 will aim to project future advances for technologies, workflows, and use case scenarios at all scales of computing for AI.

Submissions related to this year’s workshop theme, imparting lessons learned from specific projects, methods, tools, and use cases, are highly encouraged.

All abstracts must be submitted through EasyChair (https://easychair.org/conferences/?conf=modsim26) no later than Friday, June 05, 2026 (11:59 pm PDT; 6:59 am UTC). Those with accepted abstracts will be notified via e-mail on Monday, June 15, 2026. Domestic travel to ModSim 2026 may be available for full-time students at U.S.-based academic institutions, supported by a National Science Foundation travel grant.

Topic of Interest

Abstract contributions should relate to the workshop theme “ModSim-integrated AI and HPC.” Within the overall theme, subcategories of interest include:

Artificial Intelligence and Machine Learning: Workloads, Workflows, and Systems. AI, in general, and Machine Learning (ML), in particular, are important drivers to all forms of computing, including large-scale data- and numerically intensive high-performance computing (HPC). Consequently, systems designed for AI/ML workloads are critically important. Abstracts in this category should offer novel approaches for AI and ML workloads, ModSim for AI/ML architectures, and other approaches (e.g., intelligent computational steering driven by dynamic and offline learning).

Methodologies and Tools. AI and ML are not only revolutionizing applications, but these techniques also have the potential to revolutionize the way that HPC systems are designed. This abstract category solicits submissions that adopt AI/ML techniques in system design, such as predictive models of performance, power, or cost; approaches that intelligently explore and recommend designs; and techniques that optimize individual subsystems, across system layers, or the whole system with AI/ML. Abstracts should highlight how to advance the state of the art, as well as expectations for impacting future directions in this area.

Recent Advances in ModSim Implementation. The rapidly increasing complexity of systems and application workloads – along with the blending of compute, memory devices, storage, and interconnect then further combined with application software – translates into unprecedented challenges within the ModSim field. Submissions in this category, showcasing AI and non-AI approaches, are expected to highlight recent developments that can help overcome these significant challenges. Possible topics include, but are not limited to, novel ModSim methodologies, emerging areas of R&D, new projects or advances in existing projects, and new applications of ModSim tools to real-life problems.

Submission Guidelines

Suggested format: IEEE paper format – a two-column, single-spaced layout using Times New Roman 10-point font (letter or A4 size).

For Rapid Fire Consideration Only:
There is no set word limit for abstract submissions. However, please limit the submission to one page (letter or A4 size) with no smaller than 10-point font type. The abstract should provide an overview that adequately summarizes the topic(s) presented and any proposed impact on ModSim research or techniques, especially those relevant to the workshop theme.

*For Sudhakar Yalamanchili Award Applicants:
There is no set word limit for submissions. However, please limit the submission to no more than two pages (letter or A4 size) with no smaller than 10-point font type. The submission should formally address the topic(s) presented and proposed impacts on ModSim research or techniques, especially any details relevant toward meeting Sudha Award eligibility criteria.

The following details a proposed abstract layout and points to consider, all within the workshop’s theme:

Abstract Title
Primary research area:
– Artificial Intelligence and Machine Learning: Workloads, Workflows, and Systems
– Methodologies and Tools
– Recent Advances in ModSim Implementation

The abstract should include specific aspects of the work and answer questions, such as:

What is being modeled (e.g., performance, reliability, power, other)?
What is the target application?
What modeling techniques are being used?
What is novel about the approach versus current state of the art?
Are preliminary results or any notable lessons learned available?

*The Dr. Sudhakar Yalamanchili Award will be presented to the researcher who demonstrates an “outstanding contribution to ModSim” as derived from a pre-submitted Formal Abstract and Presentation/Poster Session hosted during the ModSim 2026 Workshop. ModSim 2026 Workshop Organizing Committee members will evaluate the abstracts/presentations/posters and make the final selection. To qualify, a person must be a graduate student or recent graduate within two years of her/his/their highest awarded degree at the time of the ModSim Workshop. Those holding “Assistant Professor” roles (e.g., tenure-track, early-career position [U.S.]; lecturer or junior professor [EU]) are not eligible. All submissions that satisfy these criteria are eligible for the award.

Call for Workshops/Tutorials: IISWC 2026 Call for Tutorial & Workshop Proposals
https://iiswc.org/iiswc2026/cftw.html
Submitted by Select Name...

We are actively seeking proposals for engaging and insightful tutorials and workshops to precede the main conference.
This year, all sessions will be conducted in person, with proposed formats ranging from lightweight 2-hour introductions to comprehensive full-day immersions.
This is an opportunity to share your valuable insights with both the hardware and software communities.

IISWC Workshops and Tutorials will be held on Sunday, September 27th, 2026 in Boulder, CO.
Workshop and Tutorial proposals must be submitted by June 26th, 2026
Submitters will be notified on July 3rd, 2026.

Submission Guidelines
Please direct your tutorial and workshop proposals to samuel.thomas@pomona.edu, including the following information:
• Session Type: Tutorial or Workshop
• Session Title
• List of Organizers
• Abstract: A brief summary of the session content
• Duration: 2 hours, half day, or full day
• Planning Requirements: Any specific planning needs for your session

We encourage you to take this opportunity to lead a session that advances understanding and innovation in key areas of computer science and technology.

Call for Posters: International Conference on Parallel Processing (ICPP) 2026
https://icpp2026.github.io/call-for-posters/
Submitted by Qinbin Li

ICPP 2026 invites poster submissions presenting early-stage research, novel ideas, work-in-progress results, and late-breaking developments in parallel processing and related areas. The poster session provides an interactive forum to exchange ideas, receive feedback, and connect with the ICPP community.

Important Dates

  • Poster submission deadline: June 15, 2026
  • Poster author notification: July 15, 2026

Poster Submission Guidelines

  • Submission type: 1) an Extended Abstract and 2) a Poster Draft. The extended abstract will be included in the Workshop proceedings if accepted.
  • Requirement: The poster abstract should not exceed 2 pages (including references) and all submissions must be made electronically through the conference submission portal (https://ssl.linklings.net/conferences/icpp) in PDF format printable on US letter size (8.5″ x 11″) paper. Please use the ACM format located at: https://www.acm.org/publications/proceedings-template. configuration for submissions prepared in LaTeX. Changes to the template (e.g., margin, font size) could lead to automatic rejection. Submissions should represent original research results and cannot already be under review or accepted for publication/presentation in another venue.} We recommend using documentclass[sigconf,review]{acmart}

Topics of Interest
Posters are welcome on (but not limited to) the following areas:

  • System Architecture & Hardware Components
  • Programming Environments & System Software
  • Innovation combining multiple disciplines, Converged HPC Cloud Edge computing, Complex Workflows, Methodologies for Performance Portability and/or Productivity across Architectures.
  • Parallel and Distributed Algorithms,
  • Performance Modeling of Parallel or Distributed Computing, Performance Evaluation of Parallel or Distributed Systems
  • Parallel, Distributed and Accelerated Applications, Scalable Data Analytics & Applied Machine Learning.
  • AI for Application & Use Case, AI for System Architecture & Hardware Components, AI for Multidisciplinary, AI for Performance and AI for Programming Environments & Systems Software
  • Parallel simulators of quantum computers, use of parallel computing for quantum compilation and optimization,

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Adarsh Patil
SIGARCH Content Editor

Top