SIGARCH

This is the 1st July 2026 digest of SIGARCH Messages.

In This Issue


Call for Nominations: SIGMICRO Dissertation Award
https://www.sigmicro.org/awards/dissertation.php
Submitted by Erik Altman

We invite nominations for the SIGMICRO Dissertation Award

Please email nominations to committee Chair Pradip Bose:  pbose@us.ibm.com

Nomination Deadline:  August 8, 2026

The SIGMICRO Dissertation Award is a new annual award that recognizes excellent thesis research by doctoral candidates in the field of computer microarchitecture. Dissertations will be reviewed for technical depth and significance of the research contribution, potential impact, and quality of presentation.

Eligibility

Eligible dissertations must have been successfully defended and deposited in the previous calendar year. Each nominated dissertation must be on a topic relevant to computer microarchitecture. The determination of whether a thesis is within scope for the award will be made by the SIGMICRO Dissertation Award Committee.
A dissertation can be nominated for both the SIGMICRO Dissertation Award and the ACM Doctoral Dissertation Award. However, a dissertation that has received the SIGARCH Dissertation Award is ineligible for nomination.

Application Requirements

Nominations should be made in the form of an email addressed to the Chair of the Dissertation Award Committee (Pradip Bose; pbose@us.ibm.com) with the subject 2024 SIGMICRO Dissertation Award Nomination. Self nominations are not allowed. The following materials are required for the nomination:

  • English language copy of the thesis.
  • A statement from the nominator, limited to two pages, addressing why the nominee’s dissertation should receive this award. This should address the significance of the dissertation, and not simply repeat information in the thesis abstract.
  • Three letters of support, limited to two pages each. Supporting letters should be included from experts in the field who can provide additional insights or evidence of the dissertation’s impact. The nominator/advisor may not write a letter of support. The letter should also contain the qualification of the endorser and his/her role with respect to the nominee. If a letter writer is supporting more than one nomination, they may be asked to rank those nominations.
  • A list of publications contributing to thesis.
  • Suggested citation if the candidate is selected. This should be a concise statement (maximum of 25 words) describing the key technical contribution for which the candidate merits this award. Note that the final wording for awardees will be at the discretion of the Dissertation Award Committee.

The nominator is responsible for ensuring that all nomination materials reach the Dissertation Award Committee Chair, by email, by the submission deadline.


Committee
Pradip Bose (Chair)
Erik Altman
Reetuparna Das
Lieven Eeckhout
Radu Teodorescu


Call for Nominations: SIGMICRO Early Career Award
https://www.sigmicro.org/awards/earlycareer.php
Submitted by Erik Altman

We invite nominations for the SIGMICRO Early Career Award

Submit nominations to: stefanos.kaxiras@it.uu.se

Deadline:  Aug 18, 2026

Committee
Stefanos Kaxiras (Chair)
Lizy John
Aamer Jaleel
Jae W. Lee
Tamara Lehman


Call for Nominations: MICRO Test of Time Award 2026
https://www.sigmicro.org/awards/tot/cfn.php
Submitted by Saugata Ghose

The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the thirteenth MICRO ToT Award. This award recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field.

The award will recognize an influential MICRO paper whose influence is still felt 18-22 years after its initial publication. In other words, the award will be given to one or more papers published at MICRO conferences in any of the years N-22, N-21, N-20, N-19, or N-18. This year, N = 2026, so only papers published at MICRO conferences held in 2004, 2005, 2006, 2007, or 2008 are eligible. An eligible paper that has received at least 100 citations (according to Google Scholar) is automatically nominated, but explicit nominations of such papers are still encouraged.

Nominating a Paper
To nominate a paper, send an email to micro-tot-award-nominations@googlegroups.com by July 10, 2026, with the following:

  1. The title, the author list, and publication year of the nominated paper
  2. A 100-word (maximum) nomination statement, describing why the paper deserves the Test of Time Award
  3. The name, title, affiliation of the nominator, and if appropriate, the relationship of the nominator to the authors

Only one paper can be nominated in a single email. There is a maximum of five nominations per person. You cannot nominate a paper that you are a co-author on. One paper will be selected as the award winner from the pool of nominees by the award committee.

For more information on the nomination and selection process, a list of all eligible papers, this year’s committee members, prior award winners, and other information, please visit https://www.sigmicro.org/awards/tot/


Call for Nominations: IEEE CS TCuArch Graduate Student Industry Impact Award
https://ieee.secure-platform.com/a/solicitations/1477/home
Submitted by Onur Kayiran

IEEE Computer Society TCuArch Graduate Student Industry Impact Award

Call for Nominations
The IEEE Computer Society TCuArch Graduate Student Industry Impact Award recognizes a graduate student for exceptional technical contributions made during an industry internship in the field of computer architecture. The award honors students whose work demonstrates high technical quality, innovation, and clear relevance to industry needs. The award highlights the role graduate students play in strengthening ties between academia and industry, fostering collaboration, and advancing research that informs both scientific progress and industrial practice.

Official Citation: “For exceptional technical contributions during an industry internship, advancing both industrial impact and academic-industry collaboration in computer architecture.”

Administration: The award is administered by IEEE Computer Society Technical Committee on Microarchitecture (TCuArch).

Eligibility: The nominee must be a current graduate student enrolled in a master’s or doctoral program and an active member of IEEE Computer Society TCuArch at the time of nomination. The nominee must be currently engaged in, or have completed, an industry internship within one year prior to the nomination deadline. The internship contribution must be technical in nature and directly relevant to the company’s products, services, technical capability, or strategic direction. Nominations must be submitted by the student’s academic advisor; self-nominations are not accepted.

A complete nomination package must include the following:

1. A letter from the industry mentor, up to 2 pages, who directly supervised the student during the internship. The letter should describe the technical quality and innovation of the student’s contributions, the expected or demonstrated impact on the company’s product, service, technical capability, or strategic direction, and how the student demonstrated initiative, problem-solving skills, and collaboration.
2. Up to two optional supporting letters from other industry co-advisors or collaborators involved in the internship, providing additional perspective on the student’s technical contributions and impact.
3. The nominee’s CV, up to 3 pages, highlighting relevant research, technical contributions, and achievements.

Prize: Up to two recipients may be selected annually. Each recipient receives a commemorative plaque and recognition on the TCuArch website and communications. No honorarium or travel allowance is provided.

Multiple Nominations: In case of multiple nominations of the same individual, only one nomination package will be considered, and the nominators may be asked to coordinate a single complete package. Withdrawal of a nomination may be requested by the corresponding nominator or by the nominee before the nomination deadline.

Nominations should comply with IEEE Policies and restrictions on awards. Incidents of misconduct including, but not limited to, violations of IEEE’s publication policies, will be strongly considered by the awards committee and may be grounds for denial of an award or leadership position.

Nomination Deadline: July 8, 2026

Submission: Via the IEEE online nominations portal: https://ieee.secure-platform.com/a/solicitations/1477/home. The nomination portal is expected to open during the week of June 15, 2026.


Call for Nominations: IEEE Computer Society TCuArch Mid-Career Faculty Mentoring Award
https://ieee.secure-platform.com/a/solicitations/1476/home
Submitted by Guru Venkataramani

IEEE Computer Society TCuArch Mid-Career Faculty Mentoring Award

Description: The IEEE Computer Society TCuArch Mid-Career Faculty Mentoring Award recognizes a mid-career faculty member who has demonstrated exceptional dedication to mentoring and role modeling within the TCuArch community. The award honors individuals who guide students and junior colleagues in their technical and career development and whose mentoring impact extends beyond their own research group to benefit the broader computer architecture community. By fostering professional growth, promoting collaboration, and serving as examples of leadership and integrity, the awardee strengthens the pipeline of future leaders and advances excellence and inclusivity in the field.

Administration: The award is administered by IEEE Computer Society TCuArch.

Eligibility: The nominee must be a mid-career faculty member with a minimum of 6 years and a maximum of 15 years in a faculty position at the time of nomination and an active member of IEEE TCuArch at the time of submission. The nominee should be an active and respected member of the computer architecture research community, with evidence of leadership and service. Mentoring contributions must extend beyond the nominee’s immediate research group and demonstrate engagement with the broader TCuArch community.

A complete nomination package must include the following:
1. The nomination letter, up to 2 pages shall describe the nominee’s mentoring philosophy, sustained contributions, and evidence of impact on mentees’ technical and career growth. The letter should highlight how the nominee’s mentoring and role modeling extend beyond their immediate research group, influencing the broader academic and professional community.
2. Up to three but no less than 2 supporting letters from current or former mentees or colleagues, ideally including individuals outside the nominee’s own group, that highlight specific examples of the nominee’s mentorship and role modeling.
3. Evidence of Impact (optional appendix, up to 2 pages) such as mentee achievements, testimonials, community initiatives, or examples of mentorship contributions beyond the nominee’s lab.
4. The nominee’s CV (up to 4 pages) that highlights academic achievements, mentoring activities, and community engagement.

In case of multiple nominations of the same individual, only one nomination package will be considered, and the nominators may be asked to coordinate a single complete package. Withdrawal of a nomination may be requested by the corresponding nominator or by the nominee before the nomination deadline of July 8, 2026.

Nominations should comply with IEEE Policies and restrictions on awards. Incidents of misconduct including, but not limited to, violations of IEEE’s publication policies, will be strongly considered by the awards committee and may be grounds for denial of an award or leadership position.

Award submissions and related information can be found at https://ieee.secure-platform.com/a/solicitations/1476/home


Call for Nominations: SIGMICRO Distinguished Service Award Nominations
https://www.sigmicro.org/awards/dsa.php
Submitted by Erik Altman

SIGMICRO Distinguished Service Award – Call for Nominations

We seek nominations by July 13 for the 2026 SIGMICRO Distinguished Service Award.  This annual award is presented to an individual who has contributed important service to the processor microarchitecture and microsystems community while also serving as an active member of SIGMICRO who has contributed (or is contributing) significantly to SIGMICRO organization and/or SIGMICRO-sponsored conference committees.

Nominations
Nomination packages should be emailed to the selection committee chair, Erik Altman:  ealtman@us.ibm.com
A nomination for the Distinguished Service Award that is not awarded may remain valid for consideration in future years.

Each nomination should consist of the following:

  • Name, email address, and phone number of the person making the nomination (the nominator).
  • Name, address, phone number, and email address of the candidate for whom an award is recommended (the nominee).
  • A short statement (200-500 words) explaining why the nominee deserves the award in question.
  • A one-sentence citation to be used if the nominee receives the award.
  • Names and email address of 3-4 people to who will send 200-500 word endorsements of the nomination to the same email address above and by the same July 13 deadline.

Self-nominations are not allowed.

Recognition
The award recipient will receive a memento engraved with their name along with a $1000 honorarium.  The award is presented by the SIGMICRO Chair at MICRO during MICRO’s award presentation session.  The award recipient may receive up to $2000 towards MICRO conference registration, and when attendance is not virtual, support for travel costs such as airfare and hotel.  Additional travel support may be provided at the discretion of the SIGMICRO Executive Committee.

The recipient will be listed with the citation for their award on the SIGMICRO Distinguished Service Award website:  https://www.sigmicro.org/awards/dsa.php

Committee
Erik Altman (Chair)
Mattan Erez
Ulya R. Karpuzcu
Thomas Wenisch


Call for Participation: GCASR 2026
https://gcasr.org/2026
Submitted by Peter Dinda

13th Greater Chicago Area Systems Research Workshop (GCASR 2026)
May 11, 2026
Northwestern University, Evanston, Illinois
https://gcasr.org/2026

The GCASR Workshop, now in its 13th iteration, is a premier venue that promotes awareness, collaboration, and synergy among academic and industry systems researchers in Chicagoland and the greater Midwest region. Its participants span a variety of systems sub-disciplines—including (but not limited to) operating systems, distributed and decentralized computing, machine learning systems, high performance computing, computer architecture, networks, databases, programming languages and compilers, quantum computing, and security.

GCASR 2026 will consist of a keynote, a range of invited talks, and a robust poster session, all highlighting systems research in Chicagoland and the greater Midwest region.
Faculty members, researchers, postdocs, students, industry professionals, and others with an interest in the workshop topics are invited to submit a poster for presentation at GCASR 2026. We welcome posters that highlight theoretical and experimental work in computing systems—including benchmarking, theoretical results, applications, software design, and algorithm/protocol design.

Important Dates

  • Friday, April 10th, 2026 — Abstract Deadline
  • Friday, April 17th, 2026 — Poster Notification
  • Monday, May 11, 2026 — Workshop (Northwestern University, Evanston, Illinois)

Submission Requirements

Topics of Interest

  • Operating Systems
  • Computer Architecture
  • Networking
  • Distributed Systems
  • Grids/Clouds/Supercomputing (including HPC/MTC/HTC)
  • Edge Computing
  • Internet-of-Things
  • Energy Efficient Computing
  • Reconfigurable, Real-time, Cyber-Physical, and Embedded Systems
  • Programming Languages, Runtime Systems, and Compilers
  • File and Storage Systems
  • Parallelism and Multi/Many-core Systems
  • Secure and Reliable Systems
  • Databases
  • Artificial Intelligence and Machine Learning
  • Quantum Computing

Call for Papers: CCMCC 2026: IEEE Cross-Disciplinary Conference on Memory-Centric Computing
https://ccmcc.eclectx.org/cfp.html
Submitted by Saugata Ghose

2nd IEEE Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC 2026)
October 28–30, 2026
Lyon, France

CCMCC is a cross-disciplinary conference that brings experts from diverse fields together, all working on advancing memory-centric computing, including in-memory computing and processing-near-memory. It is a platform for sharing new ideas, exchanging insights, and fostering collaboration. CCMCC’s mission is to accelerate innovation in memory-centric computing and its integration into real-world applications.

We are soliciting papers across the entire memory-centric computing stack, from software to architecture to circuits and devices. Authors can choose to submit either a long paper (10–12 pages) or a short paper (4–6 pages). More details on topics of interest, formatting requirements, and submission procedures can be found at https://ccmcc.eclectx.org/cfp.html

Important Dates
Abstracts due June 15;
Full papers due June 22


Call for Papers: PDSW @ SC 2026
https://www.pdsw.org/
Submitted by Sarah Neuwirth

The 11th International Parallel Data Systems Workshop (PDSW 2026)
https://www.pdsw.org/

We are excited to announce the 11th International Parallel Data Systems Workshop (PDSW’26), to be held in conjunction with SC26: The International Conference for High Performance Computing, Networking, Storage, and Analysis, in Chicago, IL. PDSW’26 builds upon the rich legacy of its predecessor workshops, the Petascale Data Storage Workshop (PDSW, 2006–2015) and the Data Intensive Scalable Computing Systems (DISCS, 2012–2015) workshop.
The increasing importance of efficient data storage and management continues to drive scientific productivity across traditional simulation-based HPC environments and emerging Cloud, AI/ML, and Big Data analysis frameworks. Challenges are compounded by the rapidly expanding volumes of experimental and observational data, the growing disparity between computational and storage hardware performance, and the rise of novel data-driven algorithms in machine learning. This workshop aims to advance research and development by addressing the most pressing challenges in large-scale data storage and processing.
We invite the community to contribute original research manuscripts that introduce and evaluate novel algorithms or architectures, share significant scientific case studies or workloads, or assess the reproducibility of previously published work. We emphasize the importance of community collaboration for problem identification, workload capture, solution interoperability, standardization, and shared tools. Authors are encouraged to provide comprehensive experimental environment details (software versions, benchmark configurations, etc.) to promote transparency and facilitate collaborative progress.

Important Dates
Paper Submissions due: July 31st, 2026, 11:59 PM AoE
AD due: August 7th, 2026, 11:59 PM AoE
Paper Notification: Sep 4th, 2026, 11:59 PM AoE
Camera ready due: Sep 25th, 2026, 11:59 PM AoE
Final AD/AE due: Sep 25th, 2026, 11:59 PM AoE
Workshop day: Monday, Nov 16th, 2026 (all day)

Submissions website: https://submissions.supercomputing.org/

Topics of Interest

  • Scalable Architectures: Distributed data storage, archival, and virtualization.
  • New Data Processing Models and Algorithms: Application of innovative data processing models and algorithms for parallel computing and analysis.
  • Performance Analysis: Benchmarking, resource management, and workload studies.
  • Cloud and Container-Based Models: Enabling cloud and container-based frameworks for large-scale data analysis.
  • Storage Technologies: Adaptation to emerging hardware and computing models.
  • Data Integrity: Techniques to ensure data integrity, availability, reliability, and fault tolerance.
  • Programming Models and Frameworks: Big data solutions for data-intensive computing.
  • Hybrid Cloud Data Processing: Integration of hybrid cloud and on-premise data processing.
  • Cloud-Specific Opportunities: Data storage and transit opportunities specific to cloud computing.
  • Storage System Programmability: Enhancing programmability in storage systems.
  • Data Reduction Techniques: Filtering, compression, and reduction techniques for large-scale data.
  • File and Metadata Management: Parallel file systems, metadata management at scale.
  • In-Situ and In-Transit Processing: Integrating computation into the memory and storage hierarchy for in-situ and in-transit data processing.
  • Alternative Storage Models: Object stores, key-value stores, and other data storage models.
  • Productivity Tools: Tools for data-intensive computing, data mining, and knowledge discovery.
  • Data Movement: Managing data movement between compute and data-intensive components.
  • Cross-Cloud Data Management: Efficient data management across different cloud environments.
  • AI-enhanced Systems: Storage system optimization and data analytics using machine learning.
  • New Memory and Storage Systems: Innovative techniques and performance evaluation for new memory and storage systems.
  • AI and Agentic related data management: tools and techniques necessary to support AI workloads and Agentic AI data analytics for online decision making.

Template and Submission
– A full paper up to 6 pages in length, excluding references, acknowledgements, and AD/AE appendices. Once anonymization is removed for camera ready submission, these limits must still be met. Please make sure that author names fit within the 6-page limit as well even though the submission should be double-anonymized.
– Artifact Description (AD) Appendix is mandatory and Artifact Evaluation (AE) Appendix is optional.
– Papers must adhere to the IEEE conference proceeding template available at: https://www.ieee.org/conferences/publishing/templates
– Papers will be reviewed double-blind. Author names and affiliations should NOT be included in the submitted paper.
– Submit your papers by July 31st, 2026, 11:59 PM AoE at https://submissions.supercomputing.org/

Reproducibility Initiative
Aligned with the SC26 Reproducibility Initiative (https://sc26.supercomputing.org/program/papers/reproducibility-initiative/), we require detailed and structured artifact descriptions (AD) using the SC26 format (https://github.com/jennfshr/sc26-repro). The AD should include a field for one or more links to data (Zenodo, figshare, etc.) and code (Github, GitLab, Bitbucket, etc.) repositories. For the artifacts that will be placed in the code repository, we encourage authors to follow the PDSW 2026 Reproducibility Addendum (https://www.pdsw.org/pdsw26/PDSW2026ReproducibilityInitiativeAddendum.pdf) on how to structure the artifact, as it will make it easier for the reviewing committee and readers of the paper in the future.

Submissions website: https://submissions.supercomputing.org/

Organization Team
General Chair:
Jay Lofstead, Sandia National Laboratories, USA

Program Co-Chairs:
Sarah Neuwirth, Johannes Gutenberg University Mainz, Germany
Lipeng Wan, Georgia State University, USA


Call for Papers: HASP @ MICRO 2026
https://www.haspworkshop.org/2026/index.html
Submitted by Theodoros Trochatos; Wenjie Xiong; Yanan Guo

Hardware and Architectural Support for Security and Privacy (HASP) 2026
In conjunction with MICRO 2026,
Athens, Greece
Oct. 31, 2026
https://www.haspworkshop.org/2026/index.html

Call for Papers
Security and privacy research focusing on hardware and architecture aspects has become increasingly important. In the era of cloud computing, smart devices, and novel nano-scale devices, practitioners and researchers have to address new challenges and requirements in order to meet the ever-changing landscape of security research and new demands from consumers, enterprises, governments, defense, and other industries.

Topics of Interest
• Secure hardware processor architectures and implementations
• Side-channel attacks, evaluations, and defenses
• Fault injection attacks (e.g., Rowhammer, electromagnetic), evaluations, and defenses
• Hardware support for software security protection (e.g., memory safety)
• Hardware Trojan threat evaluation, detection, and prevention
• Cryptographic hardware design, implementation, and evaluation
• Security simulation, testing, validation, and verification
• Hardware fingerprinting and physically unclonable functions (PUFs)
• Hardware and architectural support for trust management
• Fault-resilient architecture designs
• Hardware-enhanced cloud security
• Commercial trusted execution environment (TEE) systems and security solutions
• Hardware support for secure Internet of Things (IoT) and mobile devices
• Quantum computer security
• Security of emerging architectures, such as analog computing, etc.

Submission Types:

  • Regular Paper (7 pages, excluding the bibliography and appendices)
    • Research Paper
    • SoK Paper: Systemization-of-Knowledge papers should concisely, but exhaustively, systematize and conceptualize existing knowledge (similar to SoK papers in S&P conferences, but focusing on hardware and architecture). Titles must use the prefix “SoK Paper:”.
    • Position Paper: Papers should define new problems in hardware or architecture security and privacy topics, supported by facts, evidence, and logical reasoning. Titles must use the prefix “Position Paper:”.
  • Short Paper (4 pages, excluding the bibliography and appendices)
    • Short Research Paper: Titles must use the prefix “Short Paper:”.
    • Work-in-Progress (WIP): Titles must use the prefix “WiP:”. WiP papers will not appear in the proceedings, but the title and authors will be listed on the HASP web page as a public record of the presentation.

Submission Information
All submissions must use the double-column ACM ICPS template (LaTeX preferred); please use the ACM Standard template in the usual two-column format. The template can be found at https://www.acm.org/publications/proceedings-template. Submissions must be anonymized for double-blind review. Regular paper and short paper submissions must be at most 7 or 4 pages respectively, excluding the bibliography and appendices. All accepted research papers, SoK papers, and position papers will be included in the ACM Digital Library; WiP papers are not included. The proceedings will be published through ACM ICPS following the open access model. Submission site: https://hasp26.cs.rochester.edu/

Keynote Speakers & Mentoring Program
Keynote speakers will be announced on the workshop website. HASP 2026 will also organize a mentoring program, which provides student attendees opportunities to get connected with senior researchers individually and have conversations about their research and career. Students will be paired with faculty/postdoc mentors for meetings during the workshop/conference, and any follow-ups afterward.

Important Dates
• Submission Deadline: Aug. 10, 2026 (AoE)
• Notification of Acceptance: Sep. 16, 2026
• Camera-Ready Version: Oct. 1, 2026
• Physical Workshop: With MICRO 2026, Athens

Program Chairs
• Wenjie Xiong, Virginia Tech, USA
• Yanan Guo, University of Rochester, USA
• Theodoros Trochatos, Yale University, USA


Call for Papers: Composable Heterogeneous Architecture for Scalable Machine Learning (CHASM) Workshop @ MICRO’26
https://sites.google.com/view/chasm-micro26/home
Submitted by Tom St. John

Composable Heterogeneous Architecture for Scalable Machine Learning (CHASM) Workshop
Co-located with MICRO 2026
https://sites.google.com/view/chasm-micro26/home
November 1, 2026


The scale and complexity of modern artificial intelligence workloads, particularly the rise of agentic AI and multi-modal foundational models, have outpaced the capabilities of monolithic compute nodes.  As the industry scales, the future of AI infrastructure relies on the effective disaggregation of workloads across heterogeneous hardware.

The CHASM workshop aims to bring together researchers and practitioners from computer architecture, systems software, and machine learning to address the critical bottlenecks in disaggregated AI.  We seek to explore the full stack of challenges from hardware-level interconnects and memory pooling to the systems software required to compile, orchestrate, and verify highly dynamic execution graphs across heterogeneous accelerators.

Topics of Interest
  • Systems Software and Compilation
    Compilation frameworks and intermediate representations for disaggregated, heterogeneous environments
    Compilation, scheduling, and runtime orchestration of agentic AI workloads as dynamic execution graphs
    Formal verification, debugging, and equivalence checking for distributed tensor algebra and parallel execution
    Online adaptation, test-time training, and adaptive inference compute in deployed agentic AI systems on disaggregated infrastructure
  • Architecture and Hardware
    Architectures for scalable memory disaggregation and pooling in AI clusters
    High-performance interconnects and networking protocols tailored for heterogeneous accelerator communication
    Hardware-software co-design for composable AI systems
  • Characterization and Evaluation
    Characterization of agentic, multi-modal, and tool-augmented Ai workloads on heterogeneous systems
    Marginal cost-efficiency analysis and performance benchmarking of contemporary AI accelerators in distributed topologies
    Novel simulation and evaluation methodologies for disaggregated datacenter architectures
    Telemetry, profiling, and bottleneck analysis in large-scale heterogeneous AI deployments

 

Submission Guidelines
We solicit both full papers (8-10 pages) and short/position papers (4-6 pages). Submissions are double-blinded. The page limit includes figures, tables, and appendices, but excludes references. Please use standard LaTeX or Word ACM templates. All submissions will need to be made via EasyChair (link. Each submission will be reviewed by at least three reviewers from the program committee. Papers will be reviewed for novelty, quality, technical strength, and relevance to the workshop.


Call for Papers: HotStorage @ SOSP 2026
https://www.hotstorage.org/2026/index.html
Submitted by Zeren Yang

8th ACM Workshop on Hot Topics in Storage and File Systems (HotStorage ’26)
September 28th and 29th, 2026
Prague, Czechia,
co-located with SOSP 2026

The workshop is sponsored by ACM in cooperation with USENIX, and its proceedings will appear in the ACM Digital Library.

The HotStorage workshop provides a forum for cutting-edge storage research, a place where academic researchers and industry practitioners can discuss new opportunities and challenges in storage technology. Submissions should propose new research directions, explore non-traditional approaches, or report on noteworthy or counterintuitive learnings and experience in emerging areas. Submissions will be judged on their originality, technical merit, topical relevance, and the likelihood of leading to insightful discussions that will influence future storage systems design and applications.

In keeping with the goals of the HotStorage workshop, the review process will favor submissions that are forward-looking and open-ended. If you are only a couple of months away from submitting to FAST, NSDI, EuroSys, VLDB, OSDI, SOSP, ASPLOS, SoCC, etc. you are probably already past the sweet spot for HotStorage. If you have a forward-looking or unorthodox idea or new research, and some evidence or early working system to support your view, but still have open questions, please consider bringing your work to HotStorage. The program committee will also welcome position papers that solicit discussion on controversial topics, introduce emerging methods and paradigms, or call out for new research directions.


Call for Workshops/Tutorials: IISWC 2026 Call for Tutorial & Workshop Proposals
https://iiswc.org/iiswc2026/cftw.html
Submitted by Select Name...

We are actively seeking proposals for engaging and insightful tutorials and workshops to precede the main conference.
This year, all sessions will be conducted in person, with proposed formats ranging from lightweight 2-hour introductions to comprehensive full-day immersions.
This is an opportunity to share your valuable insights with both the hardware and software communities.

IISWC Workshops and Tutorials will be held on Sunday, September 27th, 2026 in Boulder, CO.
Workshop and Tutorial proposals must be submitted by June 26th, 2026
Submitters will be notified on July 3rd, 2026.

Submission Guidelines
Please direct your tutorial and workshop proposals to samuel.thomas@pomona.edu, including the following information:
• Session Type: Tutorial or Workshop
• Session Title
• List of Organizers
• Abstract: A brief summary of the session content
• Duration: 2 hours, half day, or full day
• Planning Requirements: Any specific planning needs for your session

We encourage you to take this opportunity to lead a session that advances understanding and innovation in key areas of computer science and technology.


Episode 24 of the Computer Architecture Podcast Released! Featuring Guest Dr. Partha Ranganathan, Google
https://comparchpodcast.podbean.com/
Submitted by Suvinay Subramanian

Computer Architecture Podcast: A series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.

Announcing the release of Episode 24: From Unicorns to Centaurs: Codesigning Computer Systems for the AI Era with Dr. Partha Ranganathan who is a VP and Technical Fellow at Google, where he serves as the area technical lead for hardware and datacenters. Partha is currently driving next-generation computing systems for the AI era, tackling the challenges of building, scaling and managing warehouse-scale computers, and the bleeding edge of hardware-software codesign. He has pioneered numerous impactful innovations touching billions of users–spanning power-efficient servers, specialized accelerators, and disaggregated datacenters. A leading voice in the field, Partha has published 100+ papers, is a co-inventor on 125+ patents, and co-authored the seminal textbook, “The Datacenter as a Computer.” He is an IEEE and ACM Fellow, a member of the ISCA, ASPLOS, HPCA halls of fame, a recipient of the ACM SIGARCH Maurice Wilkes Award, MIT Tech Review’s top-35 young innovators, distinguished alumni awards from Rice University and IIT Madras, and uniquely for a computer scientist, an Emmy Award.

Listen to the episode at https://comparchpodcast.podbean.com. Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.


Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Adarsh Patil
SIGARCH Content Editor

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