This is the 1st October 2022 digest of SIGARCH Messages.

In This Issue

Call for Nominations: SIGARCH Elections

Submitted by Babak Falsafi

The SIGARCH elections nominating committee invites nominations (including self-nominations) for candidates to serve on the SIGARCH Executive Committee (EC). The nominating committee will select the final slate of candidates for elections to be held according to ACM rules. The initial term for the EC is for two years, beginning July 1st, 2023, with a possible extension for another two years.

The EC positions are:
Board of Directors (4 members) 

The SIGARCH EC is a working committee where each member is responsible for at least one substantive project in the service of the architecture community. Besides overseeing a  rich portfolio of conferences and awards, the EC has launched a number of initiatives in recent years including (but not limited to) the Computer Architecture Today blog and Computer Architecture Podcast, student mentoring (now in collaboration with CASA), the CARES committee (with SIGMICRO) and best practices guidelines (with IEEE CS TCCA) and more – see the last SIGARCH annual report for the portfolio of current activities. Joining the SIGARCH EC therefore requires a significant time commitment in exchange for an opportunity to make an impact on our community and enjoy a rewarding service experience.

The nominating committee will select the final slate of candidates based on enthusiasm, vision, past record of service (commensurate with seniority), and multiple dimensions of diversity.

Please submit a nomination with the following information to by 5pm (Anywhere on Earth) November 7th, 2022.

  • Name, affiliation, and email address of the nominee.
  • Position sought (chair/vice-chair/treasurer/director).
  • Previous significant service to SIGARCH and ACM.
  • Other significant service and relevant experience.
  • A brief biography or curriculum vitae.
  • Recent institutional affiliations.
  • Areas of research expertise within computer architecture.
  • A brief statement from the nominee (e.g., 150 words) in support of the nomination (e.g., a description of their ideas and commitment if elected).

All final candidates must be professional ACM members and SIGARCH members by the time of final selection. The nominating committee consists of current and past SIGARCH chairs: Babak Falsafi (chair), Sarita Adve, David Wood.

Call for Nominations: MICRO Test of Time Award 2022
Submitted by Saugata Ghose

The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the ninth MICRO ToT Award. This award recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field.

The award will recognize an influential MICRO paper whose influence is still felt 18-22 years after its initial publication. In other words, the award will be given to at most one paper that was published at MICRO conferences in any of the years N-22, N-21, N-20, N-19, or N-18. This year, N = 2022, so only papers published at MICRO conferences held in 2000, 2001, 2002, 2003, or 2004 are eligible. An eligible paper that has received at least 100 citations (according to Google Scholar) is automatically nominated, but explicit nominations of such papers are still encouraged.

Nominating A Paper

To nominate a paper, send an email to by September 9, 2022, with the following:

  1. The title, the author list, and publication year of the nominated paper
  2. A 100-word (maximum) nomination statement, describing why the paper deserves the Test of Time Award
  3. The name, title, affiliation of the nominator, and if appropriate, the relationship of the nominator to the authors

Only one paper can be nominated in a single email. There is a maximum of five nominations per person. You cannot nominate a paper that you are a co-author on. One paper will be selected as the award winner from the pool of nominees by the award committee.

For more information on the nomination and selection process, a list of all eligible papers, this year’s committee members, prior award winners, and other information, please visit

Call for Participation: ESWEEK 2022
Submitted by Lars Bauer

Call for Participation
Hybrid-Shanghai-Phoenix, October 07-14, 2022


About Embedded Systems Week (ESWEEK)

Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), two symposia (NOCS, MEMOCODE), and several workshops, tutorials, and education classes, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development.

ESWEEK 2022 will be a week-long and truly hybrid event, with in-person and online events in Shanghai and Phoenix as well as online-only events. All sessions, except for offline social events, will be accessible through the ESWEEK Gather space. The program of ESWEEK 2022 will run from Oct 7-14, 2022, around the clock. A short teaser video (1 min) of each talk and a PDF file of each journal-track and work-in-progress (WiP) paper will be made available in the program two weeks before the conference.

Shanghai Program

Phoenix Program

Virtual Program

Registered attendees can attend sessions in any of the online events, including three leading conferences (CASES, CODES+ISSS, EMSOFT), two symposia (NOCS and MEMOCODE), tutorials, workshops, and education classes. Early registration deadline: Sept. 20, 2022, 12:00pm GMT


Plenary Talks


  • Keynote 1: “Blockchain, Big Data, and AI Empower High-Quality Development of Industrial Internet”, by Dr. Jie Li, Shanghai Jiao Tong University
  • Keynote 2: “Outracing Champion Gran Turismo Drivers with Deep Reinforcement Learning”, by Peter Stone, The University of Texas at Austin
  • Keynote 3: “The Computing and Information Science and Engineering Landscape: A Look Forward”, by Margaret Martonosi, National Science Foundation (NSF)
  • Skytalk 1: “AI for EDA”, by Yu Huang, HiSilicon, Huawei
  • Skytalk 2: “Open Source Software Stacks for Heterogeneous SoCs”, by Tomas Evensen, AMD/Xilinx
  • Panel: “Waferscale Computing Systems: Are We There Yet?”,
    Organizers: Puneet Gupta (UCLA), Saptadeep Pal (Auradine Inc.)
    Panelists: Rakesh Kumar (University of Illinois at Urbana Champaign), Gabriel H. Loh (AMD Research), Joel Hestness (Cerebras Systems), Dave Nellans (NVIDIA)


  • CASES: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems


    Program Chairs: Preeti Panda, IIT Delhi, IN
    Swarup Bhunia, University of Florida, US

  • CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis


    Program Chairs: Chengmo Yang, University of Delaware, US
    Mohammad Abdullah Al Faruque, UC Irvine, US

  • EMSOFT: International Conference on Embedded Software


    Program Chairs: David Broman, KTH Royal Institute of Technology, SE
    Claire Pagetti, ONERA, FR


  • MEMOCODE: International Symposium on Formal Methods and Models for System Design
  • NOCS: International Symposium on Networks-on-Chip



  • Workshop on Compilers, Deployment, and Tooling for Edge AI (CODAI)
  • International Workshop on Heterogeneous Edge Computing for Embedded System (HEC)
  • International Workshop on Memory and Storage Computing (MSC)
  • International Workshop on Edge Intelligent Computing (EIC)
  • International Workshop on Rapid System Prototyping (RSP)
  • International Workshop on Secure RISC-V Architecture Design Exploration (SECRISC-V)
  • SIGBED x SIGDA Workshop on Emerging Techniques in System Design and Design Automation for Embedded Systems



  • T1: Tutorials on Quantum Control
  • T2: Taming Delays in Cyber-Physical Systems
  • T3: Tutorial on QuantumFlow+VACSEN: A Visualization System for Quantum Neural Networks on Noisy Quantum Device
  • T4: Integrating Compute Acceleration Into Embedded System Design Using Vitis
  • T5: Embedded Machine Learning: Design, Optimizations, and Applications
  • T6: Manycore processing-in-memory systems for accelerating deep learning applications
  • T7: Hardware Security and Trust Verification

Education Classes


  • EC1: A Hitchhiker’s Guide to Systems Security: The Art and Science of Building and Breaking Secure Computing Systems
  • EC2: A synchronous approach for the design of biomedical cyber-physical systems
  • EC3: FPGA design for cryptography and security
  • EC4: Robustness against Poisoning Attacks in Centralized and Federated Deep Learning Scenarios: A Survey
  • EC5: Confidential Computing – protecting the confidentiality, integrity, and consistency of applications
  • EC6: An Exposition of Fault Based Attacks on Modern Cryptosystems
  • EC7: Fuzzing and automated repair of security vulnerabilities in embedded software
  • EC8: You better act normal! Ubiquitous electronic observation: Threats and Attempted Solutions
  • EC9: ML-Assisted Hardware Trojan Detection
  • EC10: High-Level Approaches to Hardware Security


Student Competitions

  • ACM SIGBED Student Research Competition (SRC)
  • Embedded Human Activity Recognition Student Competition
  • F1-tenth Car Race


ESWEEK | 2022 Organizing Committee

ESWEEK 2022 General Chairs:
Aviral Shrivastava, Arizona State University, US (General Chair)
Xiaobo Sharon Hu, Notre Dame, US (Vice General Chair)

Shanghai Chair:
Edwin Sha, East China Normal University, CN

Call for Participation: Workshop on Artificial Intelligence and Machine Learning for Scientific Applications at SC’22
Submitted by Murali Emani

[AI4S]: The 3rd Workshop on Artificial Intelligence and Machine Learning for Scientific Applications
To be held in conjunction with SC22
Monday, 14 November 2022, 1:30pm – 5pm CST
Kay Bailey Hutchison Convention Center, Dallas, TX, USA

The purpose of this workshop is to bring together computer scientists and domain scientists from academia, government, and industry to share recent advances in the use of AI/ML to various scientific applications, introduce new scientific application problems to the broader community, and stimulate tools and infrastructures to support the application of AI/ML in scientific applications.The workshop will be organized as a series of plenary talks based on peer-reviewed paper submissions accompanied by keynotes from distinguished researchers in the area and a panel discussion. We encourage participation and submissions from universities, industry, and DOE National Laboratories.

Artificial intelligence (AI)/machine learning (ML) is a game-changing technology that has shown tremendous advantages and improvements in algorithms, implementation, and applications. We have seen many successful stories of applying AI/ML to scientific applications, such as predicting extreme weather events, identifying exoplanets in trillions of sky pixels, and accelerating numerical solvers in fluid simulation. However, there are a number of problems remaining to be studied to enhance the usability of AI/ML to scientific applications. For example, how to systematically and automatically apply AI/ML to scientific applications? How to incorporate domain knowledge (e.g., conservation laws, invariants, causality and symmetries) into AI/ML models? How to make the models interpretable and robust for HPC? How to make AI/ML more approachable to the HPC community? Addressing the above problems will bridge the gap between AI/ML and scientific applications and enable wider employment of AI/ML in HPC.

Call for Papers
We solicit research papers in the following topic areas, but not be limited to:

  • Innovative AI/ML models to analyze, accelerate, or improve performance of scientific applications in terms of execution time and simulation accuracy;
  • Innovative methods to incorporate complex constraints imposed by physical principles to scientific applications;
  • Innovative methods to completely or partially replace first-order computation with efficient AI/ML models;
  • Tools and infrastructure to improve the usability of AI/ML to scientific applications;
  • Performance characterization and study on the possibility of using AI/ML to specific scientific applications;
  • Workflow of applying AI/ML to scientific applications;
  • Innovative methods to make AI models interpretable and robust for scientific applications.


Authors are invited to submit manuscripts in English structured as technical papers up to 6 pages, letter size (8.5in x 11in) and including figures, tables, and references. Submissions not conforming to these guidelines may be returned without review. Your paper should be formatted using IEEE conference format which can be found from

All manuscripts will be peer-reviewed and judged on correctness, originality, technical strength, and significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding length limit, or not appropriately structured may also not be considered. At least one author of an accepted paper must register for and attend the workshop. Authors may contact the workshop organizers for more information.

Papers should be submitted electronically at:, SC22 Workshop: AI4S’22: Workshop on Artificial Intelligence and Machine Learning for Scientific Applications”.

The final papers are planned to be published through IEEE. Published proceedings will be included in the IEEE Xplore digital library.

Important Dates:

Submission Deadline: August 2, 2022 (AoE)
Notification of acceptance: September 8, 2022
Camera Ready: September 23, 2022
Workshop: November 14, 2022


Gokcen Kestor, Pacific Northwest National Laboratory
Dong Li, University of California, Merced
Murali Krishna Emani, Argonne National Laboratory

Program Committee

Debbie Bard, Lawrence Berkeley National Laboratory
Kevin Barker, Pacific Northwest National Laboratory
Aparna Chandramowlishwaran, University of California, Irvine
Wenqian Dong, University of California, Merced
Yao Fehlis, AMD Research
Olexandr Isayev, Carnegie Mellon University
Jiawen Liu, Facebook
Brian C Van Essen, Lawrence Livermore National Laboratory
Natalia Vassilieva, Cerebras
Venkatram Vishwanath, Argonne National Laboratory
Laurent White, AMD Research

Call for Participation: IEEE/ACM MICRO-55
Submitted by Georgios Tziantzioulis

55th IEEE/ACM International Symposium on Microarchitecture (MICRO-55)
October 1-5, 2022, Chicago, IL

The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. The symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and this tradition continues at MICRO-55. In 2022, MICRO will be held again in-person in Chicago, IL.

MICRO-55 Technical Program

  • 3 exciting live keynote talks and 83 technical papers
  • 21 weekend workshops/tutorials
  • Social events
    • Sunday evening reception at Westin Chicago River North
    • Monday evening excursion/banquet in one of Chicago’s most exciting museums
    • Conference grounds right next to the Chicago River Boardwalk and the River North neighborhood, a stylish district of art galleries, history-defining buildings, and home to one of the city’s most energetic culinary and nightlife scenes.

MICRO-55 Registration

Registration gives full access to all the symposium live events (all keynotes and all regular paper sessions), all live workshops/tutorials, and all recordings that are made as part of MICRO. Information about the full fee structure, along with details on when materials will be made available to registered attendees, can be found on the registration information

Early registration ends on September 15th, at 9:59 PM PDT.

Call for Papers: DATE 2023
Submitted by Anja Zeun

Call for Papers
Design, Automation, and Test in Europe 2023

Submission                            Deadline
D, A, T and E papers 18 September 2022 (abstract)
25 September 2022 (full paper)
21 November 2022 (notification of acceptance)
27 January 2023 (camera-ready paper)
Late Breaking Results papers 04 December 2022 (abstract)
11 December 2022 (full paper)
20 January 2023 (notification of acceptance)
Paper presentation video 24 February 2023
Embedded Tutorials proposals 02 October 2022
Workshop proposals 02 October 2022
Focus Session proposals 02 October 2022
Multi-Partner Projects 21 November 2022
PhD Forum 21 November 2022
Careers Fair-Industry & Student Group Fair 21 November 2022
Careers Fair-Academia & University Fair 21 November 2022


Kindly note that all deadline days apply to anywhere on earth (AoE). Deadlines are strict and no extensions will be given.

For its 2023 edition, DATE presents itself in a renewed format: After three years of online editions due to COVID-19, DATE 2023 focusses on interaction as well as reinforcing and rebuilding links in the community. Accordingly, we employ some substantial changes to the established format intending for significant added value for in-person participation: Rather than spreading the attendance throughout an entire week, we condense DATE to three days – and make them count! Furthermore, the vast majority of regular papers will be presented in a renewed format of technical sessions focussing on live interactions (in addition to the common full-length presentations available before, during and after the conference by video). By this, we make sure that the community can actually do what conferences are for: meeting, discussing and exchanging.

In case of any questions, please contact:

DATE Conference Organisation
c/o K.I.T. Group GmbH Dresden
Bautzner Str. 117–119
01099 Dresden, Germany

Phone: +49 351 65573 137

Call for Papers: HOST 2023
Submitted by Hadi Mardani Kamali

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) – the premier event aiming to facilitate the rapid growth of hardware security research and development – has opened the call for contributions. The 16th annual HOST will be held May 1-4, 2023 in San Jose, California. HOST 2023 invites original contributions in all areas of overlap between hardware and security, including but not limited to the following:

  • Hardware Trojans
  • TRNGs and PUFs
  • Side-Channel Attacks and Countermeasures
  • Hardware Obfuscation
  • Architecture-level Security
  • System/Board-level hardware security
  • Cryptography-PQC
  • Fault Injection Attacks and Countermeasures
HOST 2023 has two submission windows. The page limit is 10 pages (excluding references), in double column, IEEE format. There is no limit on the length of the bibliography. Only work that has not been previously published at the time of the submission will be considered. Duplicate submissions to concurrent conferences/journals are not permissible, and if encountered will be rejected and reported to IEEE. The paper selection will involve a double-blind review – the identity of authors must not be revealed, directly or indirectly, over the course of the entire process, with all references to the author(s)’ own previous work or affiliations in the bibliographic citations being in the third person. Avoid the use of “omitted for blind review” in the bibliography section and make sure that the PDF metadata does not contain author information.
Fall Submission
October 17, 2022: Submission of Paper
December 15, 2022: Notification of Acceptance
December 30, 2022: Camera-ready Version
Winter Submission
January 16, 2023: Submission of Paper
March 1, 2023: Notification of Acceptance
March 10, 2023: Camera-ready Version
HOST 2023 also accepts proposals for tutorials and demos. More information will be disseminated in future calls. For detailed submission information, please visit the HOST website:
Contact Information:
Program Chairs:
– Farimah Farahmandi (Email:
– Sheng Wei (Email:

Call for Papers: FastPath: Workshop on Performance Analysis of Machine Learning Systems
Submitted by Erik Altman

Call for Papers
FastPath: Workshop on Performance Analysis of Machine Learning Systems
In conjunction with MICRO 2022

FastPath 2022 brings together researchers and practitioners involved in cross-stack hardware/software performance analysis, modeling, and evaluation for efficient machine learning systems. Machine learning demands tremendous amount of computing. Current machine learning systems are diverse, including cellphones, high performance computing systems, database systems, self-driving cars, robotics, and in-home appliances. Many machine-learning systems have customized hardware and/or software. The types and components of such systems vary, but a partial list includes traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators, hybrid systems, converged infrastructure, and IT appliances. Designing efficient machine learning systems poses several challenges.

These include distributed training on big data, hyper-parameter tuning for models, emerging accelerators, fast I/O for random inputs, approximate computing for training and inference, programming models for a diverse machine-learning workloads, high-bandwidth interconnect, efficient mapping of processing logic on hardware, and cross system stack performance optimization. Emerging infrastructure supporting big data analytics, cognitive computing, large-scale machine learning, mobile computing, and internet-of-things, exemplify system designs optimized for machine learning at large.


FastPath seeks to facilitate the exchange of ideas on performance analysis and evaluation of machine learning/AI systems and seeks papers on a wide range of topics including, but not limited to:

  • Workload characterization, performance modeling and profiling of machine learning applications
  • GPUs, FPGAs, ASIC accelerators
  • Memory, I/O, storage, network accelerators
  • Hardware/software co-design
  • Efficient machine learning algorithms
  • Approximate computing in machine learning
  • Power/Energy and learning acceleration
  • Software, library, and runtime for machine learning systems
  • Workload scheduling and orchestration
  • Machine learning in cloud systems
  • Large-scale machine learning systems
  • Emerging intelligent/cognitive systems
  • Converged/integrated infrastructure
  • Machine learning systems for specific domains, e.g., financial, biological, education, commerce, healthcare


Prospective authors must submit a 2-4 page extended abstract electronically on EasyChair

Authors of selected abstracts will be invited to give a 30-min presentation at the workshop.

Key Dates

  • Submission: September 9, 2022
  • Notification: September 19, 2022


  • General Chair: Erik Altman (IBM)
  • Program Chairs: Parijat Dube (IBM), Nandita Vijaykumar (University of Toronto)
  • Web Chair: Gavin Guan (University of Toronto)


Call for Papers: RoboARCH (co-located with MICRO 2022)
Submitted by Sabrina Neuman

Call for Abstracts and Participation: RoboARCH at MICRO 2022
Workshop on Robotics Acceleration with Computing Hardware (RoboARCH)
October 2, 2022 in Chicago, IL
Co-located with the IEEE/ACM International Symposium on Microarchitecture (MICRO)

Robotics is pushing the limits of conventional computing. Autonomous robots must operate untethered in dynamic and unpredictable environments, requiring many robotics software applications to run online in real-time. Conventional CPU systems are proving unable to deliver the high performance needed by essential latency-critical robotics applications. This is a call to action for researchers across academia and industry: we must leverage nontraditional computing hardware (e.g., custom accelerator ASICs, FPGAs, and GPUs) and navigate enormous design spaces spanning across algorithms, hardware, and physical robot parameters in order to design new high performance systems enabling critical tasks in robotics. This workshop aims to gather pioneers and innovators working at the intersection of robotics and computer architecture, and to provide an introduction to this exciting emerging field to the computer architecture community.

We welcome submission of 1-page abstracts on any topic related to accelerating robotics applications (e.g., computer vision, mapping, localization, motion planning, control, and end-to-end learning, for all robotics systems) using nontraditional computing hardware (e.g., ASICs, FPGAs, GPUs), as well as real-time, distributed, cloud, and edge computing systems that might be leveraged by robotics platforms. We especially encourage early work, and work-in-progress.

Accepted authors will be invited to present a 2-minute single-slide lightning talk during the main program and a poster at the poster sessions. Submissions are anonymous, so please remove author names and all identifying information from the submission. See submission instructions on the workshop website:

Important Dates:

Abstract Submission Deadline: September 19, 2022 (extended)
Author Notification: September 23, 2022
Workshop Date: October 2, 2022

Call for Papers: DISCC 2022 (Co-located with MICRO)
Submitted by David Trilla

Recent papers from Meta (Facebook) and Google have created a major concern about data integrity in large-scale computing in cloud data centers. The term “mercurial cores” has been coined to refer to errant processor cores that have been clearly diagnosed as being the source of generating silent data errors – and recent panels (as referred to above) have brought together experts from cloud service providers and processor chip designers with the objective of raising awareness of this acute problem, and also encouraging leading-edge research to devise affordable chip and system-level mitigation solutions. In addition to such data integrity concerns, the rise of data security and privacy breaches in cloud computing environments has accelerated research and development of practical solutions that enable computing with encrypted data (e.g., advanced cryptographic methods like Fully Homomorphic Computing or FHE); e.g., recent papers.

This workshop (DISCC-2022) proposes to bring together aspects of data integrity and security in a single, unified forum. The workshop will comprise a keynote speech, several contributed papers and, time permitting, a closing panel session involving leading edge experts in data integrity and security in a hyper-scale cloud computing setting. Potential speakers are encouraged to submit an extended abstract (1-2 pages) highlighting the key contributions in the light of the above-stated technical scope of the problem. Solution approaches at the algorithm, software/firmware and/or hardware level are encouraged for early dissemination and discussion in a workshop setting.

Topics of interest include but are not limited to:

  • Testing (including detection and/or diagnosis) of silent data errors (SDEs) for plaintext and/or HE-mode ciphertext computation.
  • Detection and mitigation of malicious attacks that can lead to SDEs.
  • Privacy-preserving data-secure computation: novel software and/or hardware solutions.
  • Characterization of HE workloads for “discovery” of hardware acceleration primitives.
  • Simulation and/or emulation based modeling methods to evaluate DISCC domain software-hardware solutions.
  • Modeling of cloud-edge solutions for specific safety-, security- and/or privacy-critical applications: e.g., autonomous vehicles, internet banking, credit card fraud detection, etc.

Call for Papers: WDDSA at MICRO 2022
Submitted by Christopher Torng

Domain-specific accelerators (DSAs) require tremendous effort to achieve a working end-to-end system. These systems are often designed independently for different domains, despite sharing common needs across applications and systems programming, compiler and architectural support, as well as rapid prototyping and analysis of design metrics. This workshop aims to bring together experts from academia and industry to share their efforts in democratizing domain-specific accelerators.

We are interested in work that attempts to broaden support for general-purpose computing on recent DSAs. However, we also welcome submissions in general on DSAs and their infrastructure. This workshop is interested in but is not limited to the following topics.

  • Novel use cases of an accelerator where applications are outside accelerators’ original application domains.
  • Systems, programming, and software for democratizing domain-specific accelerators.
  • Architectural support for democratizing domain-specific accelerators.
  • Performance/power/energy evaluation/analysis of democratizing domain-specific accelerators.
  • Implications to future “democratized” accelerator design.

Call for Papers: Special Issue on Real-Time Computing in the IoT-to-Edge-to-Cloud Continuum, ACM TECS
Submitted by Daniel Casini

ACM Transactions on Embedded Computing Systems (ACM TECS)
Special Issue on Real-Time Computing in the IoT-to-Edge-to-Cloud Continuum


Guest Editors:

Daniel Casini, Scuola Superiore Sant’Anna, Italy,
Dakshina Dasari, Robert Bosch GmbH, Germany,
Matthias Becker, KTH Royal Institute of Technology, Sweden,
Giorgio Buttazzo, Scuola Superiore Sant’Anna, Italy,

The edge computing paradigm is becoming increasingly popular as it facilitates real-time computation, reduces energy consumption and carbon footprint, and fosters security and privacy preservation by processing the data closer to its origin, thereby drastically reducing the amount of data sent to the cloud. However, some computations still need to occur in the cloud, thus connecting the IoT, the edge, and the cloud and originating the so-called IoT-to-Edge-to-Cloud Compute Continuum. Many edge applications tightly interact with the surrounding
environment and are required to deliver a result (e.g., perform actuation or send a message through a 5G network) within a well-defined deadline. Therefore, a key requirement in edge computing is the need to ensure predictability when communicating across the IoT-to-Edge-to-Cloud Compute Continuum while also efficiently utilizing the system resources.
However, meeting the above requirements is non-trivial. Modern edge devices can be very diverse, ranging from hand-held devices to large in-premise servers, and can include complex embedded platforms with multiple heterogeneous cores and hardware accelerators such as GPUs, TPUs, and FPGAs. Secondly, the network transmission time (TSN over Ethernet to 5G links) can lead to variability in the end-to-end latencies incurred by edge applications. Timing guarantees must also be provided for the involved middlewares, virtualization technologies, and communication protocols to ensure meeting end-to-end requirements for applications deployed across the compute continuum.
When connected to the cloud, massively distributed applications must be managed by orchestrators capable of allocating workloads on a vast realm of heterogeneous resources, each characterized by a diverse computing capacity and processing capability. Consequently, the IoT-to-Edge-to-Cloud Compute Continuum needs to be empowered with new algorithms to guarantee real-time constraints and monitoring mechanisms and provide dynamic load balancing and adaptation while accounting for the heterogeneous nature of computing platforms
and communication latencies over the network.
This special issue will solicit regular papers from an open call as well as extended versions of best-selected papers from the 1st International Workshop on Real-time And intelliGent Edge computing (RAGE) 2022, see Invited speakers of RAGE 2022 will also be invited to submit a contribution related to their talk. The standard peer-review process of ACM TECS will be followed in all cases.

All submissions must address real-time requirements in the edge computing domain to be in scope in the special issue. Topics of interest include, but are not limited to:

• Temporal isolation in light-weight virtualization mechanisms (Docker, WebAssembly) for serverless edge computing
• Real-time scheduling policies for containers in edge virtualized systems
• End-to-end latency analysis in the IoT-to-Edge-to-Cloud Compute Continuum
• Methods for timing-aware functional decomposition between the edge and cloud
• Timing guarantees for communication protocols and middlewares for edge computing (e.g., DDS, Zenoh, MQTT, ROS 2, and more)
• Timing and resource-aware orchestration for the IoT-to-Edge-to-Cloud Compute Continuum
• Real-time edge computing industrial use cases, best practices, and experience reports

Important Dates
• Submissions deadline: October 10, 2022.
• First-round review decisions: December 10, 2022.
• Deadline for revision submissions: February 4, 2023.
• Notification of final decisions: April 4, 2023.
• Tentative publication: Spring/Summer, 2023.

Submission Information
Prospective authors are invited to submit their manuscripts electronically adhering to the ACM Transactions on Embedded Computing Systems guidelines ( Please submit your papers through the online system ( and be sure to select the “Special Issue on Real-Time Computing in the IoT-to-Edge-to-Cloud Continuum” option for the paper-type. Please indicate that you are submitting to the Special Issue on Real-Time Computing in the IoT-to-Edge-to-Cloud Continuum in the author’s
cover letter. Manuscripts should not be published or currently submitted for publication elsewhere.
Extended versions of conference papers (including RAGE 2022) must include at least 30% new research-based technical content, and be less than 50% verbatim similarity as reported by a tool (such as CrossRef).
The cover letter should clearly state which are the key new contributions with respect to the previous version, and the title of the extended journal version should be different from the title of the published conference version.

For questions and further information, please contact Daniel Casini (

Call for Papers: HaSS Special Issue on Multi-tenant Computing Security Challenges and Solutions
Submitted by Domenic Forte

On-demand availability of computing resources or “cloud computing” offers more scalable, reliable, and cost-effective information technology (IT) infrastructure. One of the main drivers of these benefits is multi-tenancy where multiple customers of a cloud service provider (CSP) share the same computing resources (CPUs, GPUs, and most recently FPGAs), either temporally, spatially, or both. However, it’s been shown time and again that failure to effectively isolate tenants in cloud computing system implementations can compromise availability (e.g., DoS), integrity (e.g., through RowHammer, fault injection, etc.) and confidentiality (e.g., through side- or covert-channels).

For CPUs, Meltdown and Spectre demonstrated that user/kernel isolations could be bypassed in every widely deployed ISA for decades. Even elaborate attempts to provide isolation, such as address space separation and trust execution environments (TEEs), still fail since other tenants may observe an isolated execution’s effect on shared resources through timing channels. Further, communication between isolated components of the same tenant must occur over untrusted communication mediums. Even with encryption, it is possible to ascertain secrets from the size and/or timing of messages, thus necessitating secure communication to also be made oblivious of any secret data.

Meanwhile, FPGA-acceleration in the cloud is still in its infancy. Although current FPGA deployments only support multi-tenancy though temporal multiplexing, closing the resource utilization gap will eventually require efficient spatial allocation of FPGA resources across multiple tenants. Here, the situation is even more challenging. Prior FPGA deployments only required trust in the FPGA vendor. However, in FPGA-as-a-service, additional security risks arise from untrusted tenants, third-party developers of accelerators, and CSPs. FPGA platforms are not yet equipped with a trusted computing base nor mechanisms that only allow only trusted designs on the hardware. FPGAs are also vulnerable to a growing number of remotely exploitable physical attacks such as power leakage and power drop attacks, crosstalk attacks, and thermal leakage attacks.

This HaSS special issue focuses on the security of multi-tenant computing systems. The aim is to provide a spectrum of challenges, approaches, and solutions, and provide an authoritative reference of the state-of-the-art. Its scope includes CPUs, GPUs, and FPGAs. Submissions from academia, industry, and government are encouraged.

Call for Papers: Call for Papers: IEEE Micro Top Picks 2023
Submitted by Jae W. Lee

IEEE Micro Special Issue on Top Picks from the 2022 Computer Architecture Conferences

IEEE Micro will publish its annual “Top Picks from the Computer Architecture Conferences” issue in July/August 2023. This issue collects some of the most significant research papers in computer architecture based on novelty and potential for long-term impact. Any computer architecture paper published in the top conferences of 2022 (including MICRO-55) is eligible. Each Top Picks submission must be based on a single paper, not a combination of multiple papers. The Top Picks Selection Committee will recognize those significant and insightful papers that have the potential to influence the work of computer architects for years to come.

Important Dates

  • Submission website opens: October 3, 2022
  • Submission deadline: October 28, 2022
  • Author notification: January 16, 2023
  • Revised papers due: February 17, 2023
  • Publication: July/August 2023

Submission Guidelines

To simplify reviewing, there is a mandatory format for submissions. Authors will need to upload the following two documents:

1. A three-page (including all references), two-column document using 10-point type. The first two pages should summarize the paper. The third page should argue for the potential of the work to have long-term impact, clearly articulating why and how it will influence other researchers and/or industry.

2. The final version of the original conference paper.

Submissions that do not follow this format will not be reviewed. The first document should contain the names of the authors with a footnote that includes the title of the original conference paper, the full name of the conference, and date of publication.

Please submit here:

Accepted Paper Guidelines

Authors of accepted papers will receive further instructions on how to prepare the final papers to conform to IEEE Micro‘s guidelines. Final papers should not exceed 6,000 words including no more than 15 references and short bios of authors, with each average-size figure counting as 250 words toward this limit. Papers must have at least 30 percent new content. Final papers will be reviewed again before publication and edited for structure, style, clarity, and readability.

Guest Editors (and Selection Committee Co-Chairs)

Christopher Batten, Cornell University
Jae W. Lee, Seoul National University/Google Brain

Contact the guest editors at

Call for Papers: IEEE MICRO Special Issue on Security and Privacy Preserving Execution Environments
Submitted by Guru Venkataramani

Call for Papers
IEEE MICRO Special Issue on Security and Privacy Preserving Execution Environments

Important Dates

  • Submissions Due: 8 October 2022
  • Initial Notifications: 4 December 2022
  • Final Version Due: 23 March 2023
  • Publication: May/June 2023

Security and privacy violations have increased in recent times due to the adversaries exploiting the loopholes in the processor hardware and system designs. The spate of attacks reported in the literature has reinforced a greater need in formulating robust design principles for future generation computer systems. This special issue is to advance the understanding of this critical research topic among the computer architecture, systems and security community researchers.

Contributions are solicited in topics overlapping architecture, operating system and programming models for secure/private execution, but not limited to:

  • Novel designs enhancing security and privacy in GPUs, accelerators, FPGAs
  • Novel cryptographic hardware
  • Designs that enhance security/privacy in post-Moore’s law technologies and quantum computing
  • Metrics for measuring vulnerabilities in hardware and systems
  • Compiler, hardware, and code generation methods to mitigate architecture-induced side/covert channels and other vulnerabilities

Here are the guidelines for this special issue:

  • Contributions must clearly show the overlap between computer architecture/systems and security. The threat model under consideration must be clearly described.
  • Evaluation of proposed designs must include experimental results or theoretical proofs to show how security or privacy is achieved.
  • Research contributions from prior IEEE International Symposium on Secure and Private Execution Environment Design (SEED) conference are encouraged. All previously published papers must have at least one-third new content compared to any overlapping publication(s). Concurrent submissions are not permitted.
  • Papers that do not match guidelines will be rejected without review.

Submission Guidelines

For author information and guidelines on submission criteria, please visit IEEE Micro‘s Author Information page. Please submit papers through the ScholarOne system, and be sure to select the special-issue name. Manuscripts should not be published or currently submitted for publication elsewhere. Please submit only full papers intended for review, not abstracts, to the ScholarOne portal.


Please contact the guest editors at

Guest Editor 

Guru Prasadh Venkataramani

Call for Workshops/Tutorials: HPCA 2023 Call for Workshop and Tutorial
Submitted by Wenjie Xiong

The International Symposium on High-Performance Computer Architecture (HPCA) seeks proposals for workshops and tutorials. Workshops and tutorials will be held on Saturday and Sunday before the main conference, on the 25th and 26th of February 2023. Barring extraordinary circumstances, HPCA will be held in person in Montreal, Canada.

Proposal Format

Proposals should be one to two pages, and must include the following information:

Workshop Proposals:

  • The title of the workshop/tutorial,
  • The organizers, their affiliations, and short bios,
  • The expected duration of the workshop/tutorial (i.e., half day or full day),
  • A sample call for papers, including the main workshop topics, and
  • If the workshop was held previously, the location (which conference), date, number of published papers, and number of attendees.

Tutorial Proposals:

  • The title of the workshop/tutorial,
  • The organizers, their affiliations, and short bios,
  • The expected duration of the workshop/tutorial (i.e., half day or full day),
  • An abstract,
  • A tentative outline of the tutorial program / topics covered, and
  • If the tutorial was held previously, the location (which conference), date, and the attendance count.

Call for Posters: ACM Student Research Competition @ PACT 2022
Submitted by Saugata Ghose

PACT 2022 invites students to participate in the ACM Student Research Competition (SRC). The SRC is a forum for graduate and undergraduate students to share their research results, exchange ideas, and improve their communication skills while competing for prizes. The SRC consists of three rounds: (1) an online abstract submission, (2) a poster session at PACT 2022 for accepted abstracts, and (3) a presentation at PACT 2022 by poster session finalists.

All authors of accepted abstracts will receive free conference registration to PACT (October 10-12, 2022, in Chicago), to help offset costs of attendance. Students must attend PACT 2022 in person to take part in the poster session and finalist presentation.

Student winners receive prizes of $500, $300, and $200 for first/second/third place, respectively, in each of the undergraduate and graduate divisions, along with a framed certificate.

800-word poster abstracts are due September 1, 2022 (AoE), and authors are expected to be notified on September 15.

For more details, please see the ACM SRC @ PACT 2022 website at

Tool Release: Argus – An End-to-End Framework for Accelerating CNNs on FPGAs
Submitted by Michael Ferdman

We are pleased to announce the release of the Argus online Verilog Code Generator tool. Argus is an end-to-end framework for accelerating CNNs on FPGAs. The core of Argus is an accelerator generator that translates high-level CNN descriptions into efficient multi-core accelerator designs. Argus explores an extensive design space, jointly optimizing all design aspects for the target FPGA and generating multi-core accelerator designs that achieve near-perfect dynamic arithmetic unit utilization.

Our online code generator allows anyone to use Argus to produce network-optimized and FPGA-optimized CNN accelerators in Verilog. To minimize user effort, Argus includes a model parser for importing CNN models from popular machine learning frameworks and a software stack for running an FPGA-backed CNN inference microservice.  The tool can be accessed online at

The Argus tool was built by researchers in the COMPAS Lab at Stony Brook University’s departments of Computer Science and Electrical and Computer Engineering. Argus is part of a larger research effort studying efficient hardware acceleration of machine learning.

Episode 9 of Computer Architecture Podcast Released! Featuring guest Prof. Yungang Bao
Submitted by Suvinay Subramanian

Computer Architecture Podcast: a series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.

Announcing the release of Episode 9: Hyperscale Cloud and Agile Hardware Design in China with Dr. Yungang Bao who is a professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT-CAS. Prof. Bao founded the China RISC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include open-source hardware and agile chip design, datacenter architecture and memory systems. Prof. Bao’s contributions include developing the PARSEC 3.0 benchmark suite which has been adopted by leading industry players in China (like Alibaba and Huawei), the labeled von Neumann paradigm to enable a software-defined cloud, Hybrid Memory Trace Tool (HMTT), and Partition-Based DMA Cache. He was awarded the CCF-Intel Young Faculty Award, was the winner of CCF-IEEE CS Young Computer Scientist Award, and received China’s National Honor for Youth under 40.

Listen to the episode at Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Akanksha Jain
SIGARCH Content Editor