Call for Papers: PDP 2021
http://www.pdp2021.org
Submitted by Dora B. Heras

29th Euromicro International Conference on Parallel, Distributed and Network-based Processing (Virtual)
March 10 – 12, 2021

Submissions Due: October 4, 2020

INTRODUCTION:

Parallel, Distributed, and Network-Based Processing has undergone impressive change over recent years. New architectures and applications have rapidly become the central focus of the discipline. These changes are often a result of cross-fertilisation of parallel and distributed technologies with other rapidly evolving technologies. It is of paramount importance to review and assess these new developments in comparison with recent research achievements in the well-established areas of parallel and distributed computing, from industry and the scientific community. PDP 2021 will provide a forum for the presentation of these and other issues through original research presentations and will facilitate the exchange of knowledge and new ideas at the highest technical level.

Topics of interest include, but are not restricted to:

• Parallel Computing: massively parallel machines; embedded parallel and distributed systems; multi- and many-core systems; GPU and FPGA based parallel systems; parallel I/O; memory organisation.
• Distributed and Network-based Computing: Cluster, Grid, Web and Cloud computing; mobile computing; interconnection networks.
• Big Data: large scale data processing; distributed databases and archives; large scale data management; metadata; data intensive applications.
• Programming models and Tools: programming languages and environments; runtime support systems; performance prediction and analysis; simulation of parallel and distributed systems.
• Systems and Architectures: novel system architectures; high data throughput architectures; service-oriented architectures; heterogeneous systems; shared-memory and message-passing systems; middleware and distributed operating systems; dependability and survivability; resource management.
• Advanced Algorithms and Applications: distributed algorithms; multi-disciplinary applications; computations over irregular domains; numerical applications with multi-level parallelism; real-time distributed applications.

IMPORTANT DATES (ALL 23:59 A.O.E)

Deadline for paper submission: October 4, 2020
Acceptance notification: December 18, 2020
Camera ready paper due: January 17, 2021
Registration: *** to be announced
On-line conference: March 10 – 12, 2021

SUBMISSION OF PAPERS:

Prospective authors should submit a full paper not exceeding 8 pages in the Conference proceedings format (double-column, 10pt) to the conference main track or to the Special Sessions through the EasyChair conference submission system indicating thr Main Track or the chosen Special Session.

Double-blind review: the paper should not contain authors names and affiliations; in the reference list, references to the authors’ own work entries should be substituted with the string “omitted for blind review”.

Publication: Proceedings will be published by Conference Publishing Services (CPS). All accepted papers will be included in the same volume, published by the Conference Publishing Services (CPS). The Final Paper Preparation and Submission Instructions will be published after the notification of acceptance. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be submitted to IEEE explore, CDSL, and for indexing among others, to DBLP, Scopus ScienceDirect, and ISI Web of Knowledge.

JOURNAL SPECIAL ISSUES

Selected papers will be invited to submit an extended version to a special issue in a JCR-indexed journal.

ABOUT EUROMICRO

Euromicro is an international scientific organization advancing sciences and applications of Information Technology and Microelectronics. A major focus is on organizing conferences and workshops in Computer Science and Computer Engineering. Euromicro is a non-profit association founded in 1974 and annual conferences have taken place in more than 20 countries all over Europe. Find out more

Call for Papers: DATE 2021: Dependability and System-level Test
http://www.date-conference.com/
Submitted by Karthik Pattabiraman

Topic T3: Dependability and System-level Test
Test and Dependability Track @ DATE 2021
Grenoble, France
February 1-5, 2021

Submissions Due: September 21, 2020

https://www.date-conference.com/tpc#T3

DEADLINES: The deadline to submit papers is 
************************************************
Abstract: Sunday, September 14, 2020 23:59:59 CET.
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For a paper to be considered a valid submission, at least a title, abstract, and the complete list of authors (cannot be modified after Monday, September 14, 2020 23:59:59 CET) should be submitted by this date. The full paper can be submitted at the same time or later, but must be uploaded at the latest by

************************************************
Full Paper: Monday, September 21, 2020 23:59:59 CET.
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Please note that there will not be any additional deadline extensions beyond Monday, September 21, 2020 23:59:59 CET.

DATE 2021
The 24th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems, and embedded software. The conference addresses all aspects of research into technologies for electronic and (embedded) systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecom, wireless communications, multimedia, healthcare and automotive systems.

Persons involved in innovative industrial designs are particularly encouraged to submit papers to foster the feedback from design to research. Panels, hot-topic sessions and embedded tutorials highlight and inform about emerging topics. The Test and Dependability track addresses various quality aspects of electronic and embedded systems. The emphasis is on test technology, design-for-testability, security, reliability and other dimensions of dependability. The track’s focus includes significant improvements on existing methods, algorithms and tools as well as forward-looking approaches related to these topics.

T3 – DEPENDABILITY AND SYSTEM-LEVEL TEST TOPIC
The Dependability and System-level Test topic is one of the six topics foreseen in the Test and Dependability track. It is devoted to the presentation and discussion of state-of-the-art advances in the theory and practice of hardware and software solutions for system’s dependability crossing all layers of the system’s stack. Topics of interest include, but are not limited to:

• microarchitecture-level and system-level error/fault modeling; 
• cross-layer dependability analysis and evaluation; 
• reliable and fail-safe architectures and systems design; 
• system-level on-line test and functional safety; 
• runtime system management for dependability; 
• cross-layer solutions for dependability (microarchitecture-level, software-level, system-level); 
• application resilience; 
• high-level synthesis (HLS) dependability;
• approximate computing for resilient systems;
• computational intelligence methods (AI/ML) for dependability; 
• system-level and microarchitecture-level solutions for safety- and mission-critical systems, IoT and cloud infrastructure

TOPIC TECHNICAL COMMITTEE
Karthik Pattabiraman, University of British Columbia (chair)
Stefano Di Carlo, Politecnico di Torino (cp-chair),
Jyotika Athavale, Intel Corp
Görschwin Fey, Hamburg University of Technology
Dimitris Gizopoulos, University of Athens
Paolo Rech, UFRGS
Juan Carlos Ruiz Garcia, UPV Valencia
Rishad Shafik, Newcastle University

SUBMISSION INSTRUCTIONS
Submission instructions can be found on the conference web page: www.date-conference.com

Call for Papers: IoTSMS 2020
https://emergingtechnet.org/IOTSMS2020/
Submitted by Marco Guazzone

7th International Conference on Internet of Things: Systems, Management and Security (IoTSMS 2020)
Paris, France
December 14-16, 2020

Submissions Due: September 10, 2020

URL: https://emergingtechnet.org/IOTSMS2020/

IMPORTANT DATES
* Submission Date: September 10, 2020 (firm and final extension)
* Notification to Authors: October 10, 2020
* Camera Ready Submission: November 1, 2020

The Internet of Things (IoT) technology offers unprecedented opportunities to interconnect human beings as well as Machine-to-Machine (M2M), whereby sensors and networks allow all ‘things’ to communicate directly with each other to share vital information allowing us to have an instrumented universe where accurate data is readily available to inform optimal decision making. The IoT is about to enable a range of new capabilities and services far beyond today’s offerings. It will fundamentally change how people go about their lives. According to Gartner, the number of objects connected to the Internet is set to reach 20 billion by 2020. Cisco estimates the number will be close to 26 billion objects by 2020. Others believe the actual number will be even higher with the assumption that any object with a simple micro controller and on-off switch will be connected to the Internet in the near feature. The scale of the IoT is set to have a major economic, social and environmental impacts; the intersection of which forms the future sustainable growth.

The international conference on Internet of Things: Systems, Management and Security (IoTSMS) aims at soliciting original ideas on the broad area of IoT including challenges and opportunities, concepts and applications and future trends. The IoTSMS aims to facilitate discussions among academics and IoT practitioners and make positive contributions to the field.

TOPICS OF INTERESTS
* Emerging concepts of IoT Systems
* Architectures of IoT systems
* Machine-to-Machine Communication and IoT
* Modeling of IoT applications
* SDN and NFV support for IoT applications and Systems
* Fog and Edge support for IoT Applications
* 5G support for IoT Applications
* IoT for Smart Cities
* Energy management in IoT
* Design methodologies for IoT
* Novel services and applications of IoT to facilitate environmental responsibility
* Green by Internet of Things
* IoT and Social benefits/impact
* IoT Economics and Business Models
* Emerging Internet of Things business models and process changes
* Communication systems and network architectures for the IoT
* IoT and Data Management
* Security and privacy of IoT
* Reliability of IoT
* Disaster recovery in IoT
* Applications of Internet of things
* Emerging applications and interaction paradigms for everyday citizens
* Big data and IoT
* Self-organizing IoT
* Cloud Computing and IoT
* IoT and sustainable Growth

PUBLICATION
All accepted papers will appear in the conference proceedings and will be published by IEEE and included in the IEEE Xplore digital library.

GENERAL CHAIRS
* Abdelhakim Hafid Senhadji, University of Montreal, Canada.
* Francisco Falcone, Universidad Publica de Navarra, Spain.

PROGRAM CHAIRS
* Attila Kertesz <keratt@inf.u-szeged.hu>
* Marco Guazzone <marco.guazzone@uniupo.it>

Call for Papers: CGO 2021
http://cgo.org/
Submitted by Dongyoon Lee

IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
co-located with PPoPP, CC, and HPCA
February 27 – March 3, 2021, Virtual Conference
http://cgo.org/

UPDATES
With the continued impact of the COVID-19, the joint steering committee of CGO/PPoPP/HPCA/CC has decided to make the conference a virtual event this year. The next conference will be held in Seoul again in 2022. The details on the virtual conference format will be announced later.

Submissions Due: September 1, 2020

CALL FOR PAPERS

The International Symposium on Code Generation and Optimization (CGO) is a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

IMPORTANT DATES
Abstract Submission: August 25, 2020
Paper Submission: September 1, 2020
Author Rebuttal Period: October 11 – 17, 2020
Paper Notification: November 5, 2020

Original contributions are solicited on, but not limited to, the following topics:

– Code Generation, Translation, Transformation, and Optimization for performance, energy, virtualization, portability, security, or reliability concerns, and architectural support
– Efficient execution of dynamically typed and higher-level languages
– Optimization and code generation for emerging programming models, platforms, domain-specific languages
– Dynamic/static, profile-guided, feedback-directed, and machine learning based optimization
– Static, Dynamic, and Hybrid Analysis for performance, energy, memory locality, throughput or latency, security, reliability, or functional debugging
– Program characterization methods
– Efficient profiling and instrumentation techniques; architectural support
– Novel and efficient tools
– Compiler design, practice and experience
– Compiler abstraction and intermediate representations
– Vertical integration of language features, representations, optimizations, and runtime support for parallelism
– Solutions that involve cross-layer (HW/OS/VM/SW) design and integration
– Deployed dynamic/static compiler and runtime systems for general purpose, embedded system and Cloud/HPC platforms
– Parallelism, heterogeneity, and reconfigurable architectures
– Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA
– Compiler support for vectorization, thread extraction, task scheduling, speculation, transaction, memory management, data distribution and synchronization

ARTIFACT EVALUATION

The Artifact Evaluation process is run by a separate committee whose task is to assess how the artifacts support the work described in the papers. This process contributes to improve reproducibility in research that should be a great concern to all of us. There is also some evidence that papers with a supporting artifact receive higher citations than papers without (Artifact Evaluation: Is It a Real Incentive? by B. Childers and P. Chrysanthis).

Authors of accepted papers at CGO have the option of submitting their artifacts for evaluation within two weeks of paper acceptance. To ease the organization of the AE committee, we kindly ask authors to indicate at the time they submit the paper, whether they are interested in submitting an artifact. Papers that go through the Artifact Evaluation process successfully will receive a seal of approval printed on the papers themselves. Additional information is available on the CGO AE web page. Authors of accepted papers are encouraged, but not required, to make these materials publicly available upon publication of the proceedings, by including them as “source materials” in the ACM Digital Library.

CALL FOR TOOLS AND PRACTICAL EXPERIENCE PAPERS

Last year CGO had a special category of papers called “Tools and Practical Experience,” which was very successful. CGO this year will have the same category of papers. Such a paper is subject to the same page length guidelines, except that it must give a clear account of its functionality and a summary about the practice experience with realistic case studies, and describe all the supporting artifacts available.

For papers submitted in this category that present a tool it is mandatory to submit an artifact to the Artifact Evaluation process and to be successfully evaluated. These papers will initially be conditionally accepted based on the condition that an artifact is submitted to the Artifact Evaluation process and that this artifact is successfully evaluated. Authors are not required to make their tool publicly available, but we do require that an artifact is submitted and successfully evaluated.

Papers submitted in this category presenting practical experience are encouraged but not required to submit an artifact to the Artifact Evaluation process.

The selection criteria for papers in this category are:

– Originality: Papers should present CGO-related technologies applied to real-world problems with scope or characteristics that set them apart from previous solutions.
– Usability: The presented Tools or compilers should have broad usage or applicability. They are expected to assist in CGO-related research, or could be extended to investigate or demonstrate new technologies. If significant components are not yet implemented, the paper will not be considered.
– Documentation: The tool or compiler should be presented on a web-site giving documentation and further information about the tool.
– Benchmark Repository: A suite of benchmarks for testing should be provided.
– Availability: Preferences will be given to tools or compilers that are freely available (at either the source or binary level). Exceptions may be made for industry and commercial tools that cannot be made publicly available for business reasons.
– Foundations: Papers should incorporate the principles underpinning Code Generation and Optimization (CGO). However, a thorough discussion of theoretical foundations is not required; a summary of such should suffice.
– Artifact Evaluation: The submitted artifact must be functional and supports the claims made in the paper. Submission of an artifact is mandatory for papers presenting a tool.

Authors should carefully consider the difference in focus with the co-located conferences when deciding where to submit a paper. CGO will make the proceedings freely available via the ACM DL platform during the period from two weeks before to two weeks after the conference. This option will facilitate easy access to the proceedings by conference attendees, and it will also enable the community at large to experience the excitement of learning about the latest developments being presented in the period surrounding the event itself.

ORGANIZERS

General Chair
Jae W. Lee, Seoul National University

Program Chairs
Mary Lou Soffa, University of Virginia
Ayal Zaks, Intel

Call for Papers: tinyML 2021
https://docs.google.com/document/d/165lfe1dmgB4SYuuE4FkWUdyVDUAzsIUledMqJfu5tms/edit
Submitted by Vijay Janapa Reddi

tinyML Research Symposium 2021
New academic & commercial research symposium as part of the 3rd annual tinyML Summit
Monday, March 22, 2021

Submissions Due:  Nov 2, 2020

Tiny machine learning (tinyML) is a fast-growing field of machine learning technologies and applications including algorithms, hardware, and software capable of performing on-device sensor (vision, audio, IMU, biomedical, etc.) data analytics at extremely low power, typically in the mW range and below, and hence enabling a variety of always-on use-cases and targeting battery-operated devices. tinyML systems are becoming “good enough” for (i) many commercial applications and new systems on the horizon; (ii) significant progress is being made on algorithms, networks, and models down to 100 kB and below; and (iii) initial low power applications in vision and audio are becoming mainstream and commercially available. There is growing momentum demonstrated by technical progress and ecosystem development.

The first annual tinyML research symposium serves as a flagship venue for research at the intersection of machine learning applications, algorithms, software, and hardware in deeply embedded machine learning systems. We solicit papers from academia and industry combining cross-layer innovations across topics. Submissions must describe tinyML innovations that intersect and leverage synergy between at least two of the following subject areas:

tinyML Datasets

• Public release of new datasets to tinyML
• Frameworks that automate dataset development
• Survey and analysis of existing tiny datasets that can be used for research

tinyML Applications

• Novel applications across all fields and emerging use cases
• Discussions about real-world use cases
• User behavior and system-user interaction
• Survey on practical experiences

tinyML Algorithms

• Federated learning or stream-based active learning methods
• Deep learning and traditional machine learning algorithms
• Pruning, quantization, optimization methods
• Security and privacy implications

tinyML Systems

• Profiling tools for measuring and characterizing system performance and power
• Solutions that involve hardware and software co-design
• Characterization of tiny real-world embedded systems
• In-sensor processing, design, and implementation

tinyML Software

• Interpreters and code generator frameworks for tiny systems
• Optimizations for efficient execution
• Software memory optimizations
• Neural architecture search methods

tinyML Hardware 

• Power management, reliability, security, performance
• Circuit and architecture design
• Ultra-low-power memory system design
• MCU and accelerator architecture design and evaluation

tinyML Evaluation

• Measurement tools and techniques
• Benchmark creation, assessment and validation
• Evaluation and measurement of real production systems

Accepted papers will be published in the form of peer-reviewed online proceedings. An author of an accepted paper must attend the research symposium to give a presentation.

PROGRAM CHAIRS

Vijay Janapa-Reddi, Harvard Univ.

Boris Murmann, Stanford Univ.

PROGRAM & ORGANIZING COMMITTEE

Please see detailed CFP.

IMPORTANT DATES

• Papers Due:  Nov 2nd, 2020
• Author Notification: Jan 15th, 2021
• Camera Ready: Feb 15th, 2021
  

SUBMISSION WEBSITE

Please visit OpenReview.

Call for Papers: ASPLOS 2021
https://asplos-conference.org/
Submitted by Emery Berger

The 26th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2021)
Detroit, USA
April, 2021

Submissions Due: August 21, 2020

https://asplos-conference.org/
https://asplos21.hotcrp.com/

ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, operating systems and networking. The 26th ASPLOS will be held in Detroit, Michigan (USA), a.k.a. Motor City, the historic heart of America’s automotive industry and the birthplace of Motown Records.

Like its predecessors, ASPLOS 2021 invites papers on ground-breaking research at the intersection of the ASPLOS disciplines: architecture, programming languages, operating systems, and related areas. Non-traditional topics are especially encouraged. The importance of cross-cutting research continues to grow as we grapple with the end of Dennard scaling, the explosion of big data, scales ranging from ultra-low power wearable devices to exascale parallel and cloud computers, the need for sustainability, and increasingly human-centered applications. ASPLOS embraces systems research that directly target new problems in innovative ways. The research may target diverse goals, such as performance, energy and thermal efficiency, resiliency, security, sustainability, applicability to future technologies, applications, and environments. The review process will be sensitive to the challenges of multidisciplinary work in emerging areas.

Areas of interest include, but are not limited to:

• Existing and emerging platforms at all scales (embedded to cloud)
• Internet services, cloud computing, and datacenters
• Multicore architectures and systems
• Heterogeneous architectures and accelerators
• Systems for enabling parallelism at extreme scale
• Programming models, languages, and compilation for all platforms
• Managing, storing, and computing on big data
• Virtualization and virtualized systems
• Memory and storage technologies and architectures
• Power, energy, and thermal management
• Security, reliability, and availability
• Verification and testing, and their impact on design
• Support for approximations and approximate computing
• Non-traditional computing systems, including emerging devices

Deadlines
Paper registration: August 14, 2020
Full paper submission: August 21, 2020
Author response: November 4-6, 2020
Notification: November 19, 2020
Final paper deadline: February 1, 2021

ASPLOS’21 Extended Abstracts

In the past decade, our community has grown considerably both in the number of researchers and the number of institutions involved. While this is a wonderful development for our field, the corresponding growth in conference submissions is stressing our paper review processes. The increasingly larger program committees (PC) and multi-day PC meetings have not been sufficient to address the problems. PC members complain about excessive reviewing workloads and long PC meetings where they rarely talk. Authors routinely complain about low quality of reviews and inconsistent review outcomes.

We believe the key to high quality review outcomes and an overall high quality program is to involve more PC members with the review and decision for each paper. To allow for that in the presence of record submission counts (almost 500 for ASPLOS’20), we will pilot the use of extended abstracts in ASPLOS’21.  Each paper submission must be accompanied by a 2-page extended abstract that summarizes the motivation, key insights, main artifacts, and important contributions (see this template for suggested structure). The extended abstracts are inspired by the familiar submission format for the yearly IEEE Micro Top Picks issue.

Here is how extended abstracts will help in the reviewing process:

• We will use the extended abstracts in the first round of reviewing (R1). We expect each abstract to be reviewed by 4 or more PC members (plus additional external reviewers) and each PC member will review 4x to 5x more abstracts than papers in a traditional R1. We hope that more PC reviews per submission and better calibrated PC members will lead to better R1 decisions. Contrast this to recent ASPLOS conferences, where some papers were rejected in R1 with 1 or 2 PC reviews.
• We will use the extended abstracts to increase the number of informed participants in the PC meeting. Ahead of the PC meeting, we will ask PC members to read a few additional extended abstracts and 1-page review summaries for submissions in their area. This will allow us to quickly bring further expertise into the discussion for challenging submissions. We will also allow any PC member to access extended abstract and review summaries. That way, we hope to avoid what is common in PC meetings, where a disagreement by the 3 PC reviewers is resolved with a vote by uninformed and uncalibrated PC members.

The PC members may suggest other uses for the extended abstracts throughout the review process.

We are excited to measure and understand how extended abstracts can improve our reviewing process. Along with other experiments, such as multiple submission deadlines throughout the year, they can help us achieve high quality paper review and selection as our community grows.

Christos Kozyrakis & Emery Berger
PC Co-chairs, ASPLOS’21

Call for Papers: PPoPP 2021
https://ppopp21.sigplan.org
Submitted by Boris Grot

26th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2021)
Co-located with CGO and HPCA
Seoul, South Korea
February 27 – March 3, 2021

Submissions Due: August 13, 2020

IMPORTANT DATES:
Paper registration and abstract submission: August 6, 2020
Full paper submission: August 13, 2020
Early notification for papers not passing first stage: October 10, 2020
Author response period: October 30–November 2, 2020
Author Notification: November 16, 2020
Artifact submission to AE committee (tentative): November 26, 2020
Artifact notification by AE committee (tentative): December 26, 2020
Final paper due: January 2, 2021
All deadlines are at midnight anywhere on earth (AoE), and are firm.

PPoPP is the premier forum for leading work on all aspects of parallel programming, including theoretical foundations, techniques, languages, compilers, runtime systems, tools, and practical experience. In the context of the symposium, “parallel programming” encompasses work on concurrent and parallel systems (multicore, multi-threaded, heterogeneous, clustered, and distributed systems; grids; data centers; clouds; and large scale machines). Given the rise of parallel architectures in the consumer market (desktops, laptops, and mobile devices) and data centers, PPoPP is particularly interested in work that addresses new parallel workloads and issues that arise out of extreme-scale applications or cloud platforms, as well as techniques and tools that improve the productivity of parallel programming or work towards improved synergy with such emerging architectures.

Conference submission site: https://ppopp21.hotcrp.com.

For further details, including topics of interest, submission guidelines and the artifact evaluation process, please refer to the conference web site.

Call for Papers: EuroSys 2021
https://2021.eurosys.org/cfp.html#cfp
Submitted by Boris Grot

European Conference on Computer Systems (EuroSys)
Edinburgh, Scotland, UK
April 26-29, 2021

Submissions Due: October 9, 2020

The European Conference on Computer Systems (EuroSys) is a premier international forum for presenting computer systems research. EuroSys 2021 seeks papers on all areas of computer systems research, including:

– Operating systems
– Distributed systems
– Cloud computing and datacenter systems
– File and storage systems
– Networked systems
– Language support and runtime systems
– Systems security and privacy
– Dependable systems
– Analysis, testing and verification of systems
– Database systems and data analytics frameworks
– Virtualization and virtualized systems
– Systems for machine learning/machine learning for systems
– Mobile and pervasive systems
– Parallelism, concurrency, and multicore systems
– Real-time, embedded, and cyber-physical systems

We encourage papers that span multiple topics and communities. Papers will be judged on novelty, significance, correctness, and clarity. The program committee seeks papers that address a significant problem with an interesting and compelling solution whose validity and practicality are clearly demonstrated. A good paper will draw appropriate conclusions, honestly present related prior work, acknowledge its own limitations, and clearly articulate the advances it offers over prior work.

There are three new features in this year’s Eurosys reviewing process:
1) Author response
2) Revision stage
3) Artifact Evaluation

Please visit the conference web site for a detailed description of each of these features.

Posters:
In addition to paper presentations, EuroSys 2021 will have a poster session. Submissions for posters will open closer to the conference deadline. Accepted papers will automatically qualify for the poster session, and authors will be strongly encouraged to participate.

Awards:
EuroSys grants awards for the best and best student papers. In addition, EuroSys will also present the best artifact award this year.

Submission guidelines:
Please see the conference web site for detailed submission guidelines.

Important dates
Abstract submission: 1 October 2020
Paper submission: 9 October 2020
Author response: 6-8 January 2021
Notification of conditional accept / revise / reject: 20 January 2021
Revision submission (selected papers): 17 February 2021
Notification of conditional accept/reject for revisions: 3 March 2021
Shepherding decisions: 23 March 2021
Camera-ready submission: 26 March 2021

Contact:
For any further information, please contact the PC chairs: pc-chairs-2021@eurosys.org
Lorenzo Alvisi (Cornell University)
Cristian Cadar (Imperial College London)

Call for Papers: Reconfigurable Systems at DATE 2021
https://www.date-conference.com
Submitted by Suhaib Fahmy

Topic D12 Reconfigurable Systems
Design Methods and Tools Track @ DATE 2021
Grenoble, France
February 1-5, 2021

Submissions Due: September 21, 2020

For a paper to be considered a valid submission, at least a title, abstract, and the complete list of authors (cannot be modified after Monday, September 14, 2020 23:59:59 CET) should be submitted by this date.

The full paper can be submitted at the same time or later, but must be uploaded at the latest by Monday, September 21, 2020 23:59:59 CET. Otherwise the initial submission will be automatically withdrawn. Please note that there will not be any additional deadline extensions beyond Monday, September 21, 2020 23:59:59 CET.

The 24th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems.

DATE puts strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems, and embedded software.

The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days and a track for executives. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software, and (industrial) design experiences from different application domains, e.g. automotive, wireless, telecom and multimedia applications. The organisation of user group meetings, fringe meetings, a university booth, a PhD forum, vendor presentations and social events offers a wide variety of extra opportunities to meet and exchange information on relevant issues for the design and test community. Special space will also be allocated for EU-funded projects to show their results.

The conference addresses all aspects of research into technologies for electronic and (embedded) systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecom, wireless communications, multimedia, healthcare and automotive systems.

Persons involved in innovative industrial designs are particularly encouraged to submit papers to foster the feedback from design to research. Panels, hot-topic sessions and embedded tutorials highlight and inform about emerging topics.

The Design Methods and Tools Track addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

The Reconfigurable Systems topic (D12) is one of fifteen topics in the Design Methods and Tools Track.

TOPIC DESCRIPTION

The Reconfigurable Systems topic (D12) is devoted to all aspects of reconfigurable computing systems. Topics of interest include, but are not limited to:

– Reconfigurable computing platforms and architectures
– Heterogeneous platforms (e.g., including FPGA/GPU/CPU)
– Reconfigurable processors
– Statically and dynamically reconfigurable systems and components
– Reconfigurable computing for machine learning, data center and high-performance computing
– FPGA architecture
– FPGA partial reconfiguration
– Design methods and tools for reconfigurable computing

TOPIC TECHNICAL COMMITTEE

– Christos Bouganis, Imperial College London, GB
– Miriam Leeser, Northeastern University, US
– Bogdan Pasca, Intel, FR
– Marco D. Santambrogio, Politecnico di Milano, IT
– David Sidler, Microsoft Corporation, CH
– Ioannis Sourdis, Chalmers University of Technology, SE
– Stephan Wong, Delft University of Technology, NL
– Daniel Ziener, Technische Universität Ilmenau, DE

SUBMISSION INSTRUCTIONS

Submission instructions can be found on the conference web page: www.date-conference.com

Papers can be submitted either as Scientific Papers for Oral Presentation or as Scientific Papers for Interactive Presentation.

Oral presentations require novel and complete research work supported by experimental results. They will be evaluated with regard to their suitability for the conference, originality, and technical soundness.
Accepted papers will be published in the conference proceedings (max six pages) and will be presented in either 30-minute (“long”) or 15-minute (“short”) slots in the conference program in front of an audience.
The Program Committee reserves the right to reorient Oral-Presentation papers to Interactive-Presentation, to obtain the most suitable presentation format.

Interactive presentations are expected to articulate emerging and future design, verification and test problems including work in progress and identify open problems that merit innovative future research.
Accepted papers will be published in the conference proceedings (max four pages) and will be presented in a face-to-face discussion area.
Presenters are required to prepare a poster (up to A0 format) to help the discussion.

The accepted file format is PDF.
Submissions should be formatted as close as possible to the final format: A4 or letter pages, double column, single spaced, Times or equivalent font of minimum 10pt (templates are available on the DATE Web site for your convenience).
To permit blind review, manuscripts should not include the author names nor affiliations. Manuscripts not in line with the above rules might be discarded.