This is the 1st July 2019 digest of SIGARCH Messages.

In This Issue

Call for Participation: Workshop on AI-assisted Design for Architecture
Submitted by Lizhong Chen

The 2nd International Workshop on AI-assisted Design for Architecture (AIDArc-2)
in conjunction with ISCA 2019
Phoenix, Arizona, USA
June 22, 2019

Recent advancements in machine learning algorithms, fueled by increased data availability and high-performance computing infrastructure, have led to successful applications of machine learning (and AI in general) in numerous disciplines and domains. Although much attention has been drawn in the computer architecture community on accelerating machine learning, limited research has been conducted to utilize the power of AI/ML to help architects design better computer architectures and systems.

The AIDArc Workshop is intended to bring together researchers, scientists and practitioners across academia and industry, to share early discoveries, successful examples, and opinions on opportunities and challenges regarding utilizing AI to assist computer architecture designs. Research along this line may potentially transform the way computers are designed and optimized. It may also lead to interesting “self-evolving architecture”, where AI helps to speed up computers which, in turn, are used to speed up the AI.

This year’s keynote speaker is Dr. Henry Hoffmann from the University of Chicago. A tentative schedule is available at

Workshop Chair:
Lizhong Chen, Oregon State University,

Program Committee:
David Brooks, Harvard University
Bella Bose, Oregon State University
Paul Gratz, Texas A&M University
Crayton Hughes, Sandia National Laboratories
Daniel Jimenez, Texas A&M University
Ben Lee, Oregon State University
Tao Li, University of Florida
Ahmed Louri, George Washinton University
Abdullah Muzahid, Texas A&M Universit
Jun Yang, University of Pittsburgh
Cliff Young, Google

Call for Participation: ASAP 2019
Submitted by Zhenman Fang

The 30th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2019)
New York, USA
July 15-17, 2019

Early Registration Deadline: June 21, 2019

ASAP 2019 will take place in Cornell Tech, New York, United States. The history of the event traces back to the International Workshop on Systolic Arrays, organized in 1986 in Oxford, UK. It later developed into the International Conference on Application Specific Array Processors. With its current title, it was organized for the first time in Chicago, USA in 1996. Since then it has alternated between Europe and North-America. The conference will cover the theory and practice of application-specific systems, architectures, and processors. The 2019 conference will build upon traditional strengths in areas such as computer arithmetic, cryptography, compression, signal and image processing, network processing, reconfigurable computing, application-specific instruction-set processors, and hardware accelerators.

The preliminary program is available at

For a quick preview, in addition to regular paper talks, we will have three exciting keynotes, three invited talk sessions on hot topics such as hardware acceleration and in-memory computing, as well as lots of interesting poster presentations. In addition, we will also arrange reception and social events during the conference.

Keynote 1: DNA Data Storage and Near-Molecule Processing for the Yottabyte Era
Luis Ceze, University of Washington

Keynote 2: From AI1.0, AI2.0, to XAI3.0
Sun-Yuan Kung, Princeton University

Keynote 3: Heterogeneous Systems Research – in the Mood for AI in the age of Cloud and IoT
Jinjun Xiong, IBM T.J. Waston

General Chair: Zhiru Zhang, Cornell University
Program Chair: Yun (Eric) Liang, Peking University
Publicity Chair: Zhenman Fang, Xilinx/Simon Fraser University
Finance Chair: Jieming Yin, AMD Research
Sponsorship Chair: Guojie Luo, Peking University
Local Chair: Bo Yuan, Rutgers University
Web chair: Cunxi Yu, Cornell University

Steering Committee:
José A.B. Fortes, University of Florida, USA
Sun-Yuan, Kung Princeton University, USA
Wayne Luk, Imperial College London, UK
Michael J. Schulte, University of Wisconsin Madison, USA
Earl Swartzlander, The University of Texas at Austin, USA

Call for Papers: CGO 2020
Submitted by Fabian Gruber

IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
in conjunction with PPoPP and HPCA
San Diego, CA, USA
February 22-26, 2020

Abstract Submission: August 30, 2019
Paper Submission: September 6, 2019
Author Rebuttal Period: October 9 – 10, 2018
Paper Notification: October 22, 2019

The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

Original contributions are solicited on, but not limited to, the following topics:
– Code Generation, Translation, Transformation, and Optimization for performance, energy, virtualization, portability, security, or reliability concerns, and architectural support
– Efficient execution of dynamically typed and higher-level languages Optimization and code generation for emerging programming models, platforms, domain-specific languages Dynamic/static, profile-guided, feedback-directed, and machine learning based optimization
– Static, Dynamic, and Hybrid Analysis for performance, energy, memory locality, throughput or latency, security, reliability, or functional debugging
– Program characterization methods
– Efficient profiling and instrumentation techniques; architectural support
– Novel and efficient tools
– Compiler design, practice and experience
– Compiler abstraction and intermediate representations
– Vertical integration of language features, representations, optimizations, and runtime support for parallelism
– Solutions that involve cross-layer (HW/OS/VM/SW) design and integration
– Deployed dynamic/static compiler and runtime systems for general purpose, embedded system and Cloud/HPC platforms
– Parallelism, heterogeneity, and reconfigurable architectures
– Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA
– Compiler support for vectorization, thread extraction, task scheduling, speculation, transaction, memory management, data distribution and synchronization

The Artifact Evaluation process is run by a separate committee whose task is to assess how the artifacts support the work described in the papers. Authors of accepted papers have the option of submitting their artifacts for evaluation within two weeks of paper acceptance. To ease the organization of the AE committee, we kindly ask authors to indicate at the time they submit the paper, whether they are interested in submitting an artifact. Papers that go through the Artifact Evaluation process successfully will receive a seal of approval printed on the papers themselves. Additional information is available on the CGO AE web page. Authors of accepted papers are encouraged, but not required, to make these materials publicly available upon publication of the proceedings, by including them as “source materials” in the ACM Digital Library.

This year, CGO has a special category of papers called “tools and practical experience”. Such a paper is subject to the same page length guidelines, except that it must give a clear account of its functionality and a summary about the practice experience with realistic case studies, and describe all the supporting artifacts available. The selection criteria are:

– Originality: Papers should present CGO-related technologies applied to real-world problems with scope or characteristics that set them apart from previous solutions.
– Usability: The presented Tools or compilers should have broad usage or applicability. They are expected to assist in CGO-related research, or could be extended to investigate or demonstrate new technologies. If significant components are not yet implemented, the paper will not be considered.
– Documentation: The tool or compiler should be presented on a web-site giving documentation and further information about the tool.
– Benchmark Repository: A suite of benchmarks for testing should be provided.
– Availability: Preferences will be given to tools or compilers that are freely available (at either the source or binary level). Exceptions may be made for industry and commercial tools that cannot be made publicly available for business reasons.
– Foundations: Papers should incorporate the principles underpinning Code Generation and Optimization (CGO). However, a thorough discussion of theoretical foundations is not required; a summary of such should suffice.

Authors should carefully consider the difference in focus with the co-located conferences when deciding where to submit a paper. CGO will make the proceedings freely available via the ACM DL platform during the period from two weeks before to two weeks after the conference. This option will facilitate easy access to the proceedings by conference attendees, and it will also enable the community at large to experience the excitement of learning about the latest developments being presented in the period surrounding the event itself.

General Chairs:
Jason Mars, University of Michigan
Lingjia Tang, University of Michigan

Program Chairs:
Jingling Xue, UNSW Sydney
Peng Wu, Futurewei Technologies

Workshop and Tutorials Chairs:
Johann Hauswald, Clinc
Yunqi Zhang, Clinc

Artifact Evaluation Chairs:
Bastian Hagedorn, University of Münster
Michael Laurenzano, University of Michigan/Clinc
Michel Steuwer, University of Glasgow

Student Research Competition Chair:
Changhee Jung, Purdue University

Student Travel Grants Chair:
Animesh Jain, Amazon

Treasurer/Finance Chair:
Christophe Dubach, University of Edinburgh

Publicity Chair:
Fabian Gruber, Inria

Registration Chair:
Dongyoon Lee, Virgina Tech

Web Chair:
Dongjie He, UNSW Sydney

Program Committee:
Aaron Smith, Microsoft/Edinburgh University
Andrew Adams, Facebook
Antonia Zhai, University of Minnesota
Ben Hardekopf, UCSB
Björn Franke, University of Edinburgh
Bruce R. Childers, University of Pittsburgh
Changhee Jung, Purdue University
Christophe Dubach, University of Edinburgh
Damian Dechev, University of Central Florida
Derek Bruening, Google
Erik Altman, IBM
Fabrice Rastello, Inria
Fredrik Kjolstad, MIT
Gennady Pekhimenko, University of Toronto
Guilherme Ottoni, Facebook
Guoyang Chen, Alibaba Group US Inc
Huimin Cui, Chinese Academy of Sciences
Jaejin Lee, Seoul National University
J Nelson Amaral, University of Alberta
Lisa Wu, UC Berkeley
Louis-Noël Pouchet, Colorado State University
Mahmut T. Kandemir, Pennsylvania State University
Maria Garzaran, Intel/UIUC
Michel Steuwer, University of Glasgow
Pen-Chung Yew, University of Minnesota
Raj Barik, Uber
Rajiv Gupta, UC Riverside
Sanjay Rajopadhye, Colorado State University
Simone Campanoni, Northwestern University
Snehasish Kumar, Google
Sreepathi Pai, University of Rochester
Svilen Kanev, Google
Teresa Johnson, Google
Timothy M. Jones, University of Cambridge
Tobias Grosser, ETH Zurich
Vijay Janapa Reddi, Harvard University
Walter Binder, University of Lugano
Xipeng Shen, North Carolina State University
Xu Liu, College of William and Mary
Zheng Wang, Lancaster University

Steering Committee:
Aaron Smith, Microsoft Research
Carol Eidt, Microsoft
Fabrice Rastello, Inria
Jack W. Davidson, University of Virginia
Jason Mars, University of Michigan
Teresa Johnson, Google

Call for Papers: PPoPP 2020
Submitted by Vijay Nagarajan

25th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2020)
in conjunction with HPCA and CGO 2020
San Diego, California, USA
February 22-26, 2020

Paper registration and abstract submission: July 31, 2019
Full paper submission: August 6, 2019
Author response period: October 28–31, 2019
Author Notification: November 19, 2019
Artifact submission to AE committee: November 25, 2019
Artifact notification by AE committee: December 20, 2019
Final paper due: January 2, 2020

All deadlines are at midnight anywhere on earth (AoE), and are firm.

PPoPP is the premier forum for leading work on all aspects of parallel programming, including theoretical foundations, techniques, languages, compilers, runtime systems, tools, and practical experience. In the context of the symposium, “parallel programming” encompasses work on concurrent and parallel systems (multicore, multi-threaded, heterogeneous, clustered, and distributed systems; grids; data centers; clouds; and large scale machines). Given the rise of parallel architectures in the consumer market (desktops, laptops, and mobile devices) and data centers, PPoPP is particularly interested in work that addresses new parallel workloads and issues that arise out of extreme-scale applications or cloud platforms, as well as techniques and tools that improve the productivity of parallel programming or work towards improved synergy with such emerging architectures.

Specific topics of interest include (but are not limited to):
– Compilers and runtime systems for parallel and heterogeneous systems
– Concurrent data structures
– Development, analysis, or management tools
– Fault tolerance for parallel systems
– Formal analysis and verification
– High-performance / scientific computing
– Libraries
– Middleware for parallel systems
– Parallel algorithms
– Parallel applications and frameworks
– Parallel programming for deep memory hierarchies including nonvolatile memory
– Parallel programming languages
– Parallel programming theory and models
– Parallelism in non-scientific workloads: web, search, analytics, cloud, machine learning
– Performance analysis, debugging and optimization
– Programming tools for parallel and heterogeneous systems
– Software engineering for parallel programs
– Software for heterogeneous architectures
– Software productivity for parallel programming
– Synchronization and concurrency control

Paper Submission URL:

For detailed submission requirements, please see the PPoPP’20 website.

Call for Papers: HOST 2020
Submitted by Farimah Farahmandi

IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
San Jose, USA
May 4-8, 2020

HOST 2019 – the premier event aims to facilitate the rapid growth of hardware-based security research and development and highlight new results in the area of hardware security – has opened the call for contributions. Starting this year, HOST has two submission windows (Aug. 15th and Nov. 15th) with no abstract deadlines and no extensions. The 13th annual HOST will be held 4-8 May 2020 in San Jose, California, the capital of Silicon Valley. HOST 2020 invites original contributions in all areas of overlap between hardware and security. This includes but is not limited to the following:

– Security primitives
– Computer-aided design (CAD) tools
– Emerging and nanoscale devices
– Trojans and backdoors
– Side-channel attacks and mitigation
– Fault injection and mitigation
– (Anti-)Reverse engineering and physical attacks
– Anti-tamper
– Anti-counterfeit

– Trusted execution environments
– Cache-side channel attacks and mitigation
– Privacy-preserving computation
– System-on-chip (SoC)/platform security
– FPGA and reconfigurable fabric security
– Cloud computing
– Smart phones and smart devices

– Internet-of-things (IoT) security
– Sensors and sensor network security
– Smart grid security
– Automotive/autonomous vehicle security
– Cyber-physical system security
– (Adversarial) Machine learning and cyber deception

Paper Submission (Two Submission Windows):
* Summer Deadline
Full Paper Submission: Aug. 15, 2019
Rebuttal: Sept. 30 – Oct. 4, 2019
Notification: Oct. 20, 2019
Camera-ready: Nov. 19, 2019
Submission Site:
* Fall Deadline
Full Paper Submission: Nov. 15, 2019
Rebuttal: Jan. 8 – 15, 2020
Notification: Jan. 30, 2020
Camera-ready: Feb. 1, 2020
Submission Site: TBD

Tutorial Proposal Submission (Notification): Oct. 4, 2019 (Nov. 15, 2019)
HW Demo Proposal Submission (Notification): Dec. 15, 2019 (Jan. 16, 2020)

Submit your paper on the symposium submission website ( The page limit is 10 pages, double column, IEEE format, with a minimum font size of 10pt. Submissions must be anonymous and must not identify the authors, directly or indirectly, anywhere in the manuscript. All submission information and topic details can be found at

Call for Papers: Championship Value Prediction
Submitted by Arthur Perais

Championship Value Prediction

The year-round Championship Value Prediction (CVP) is still accepting submissions! After a new entry taking the lead in its Unlimited storage track in June 2019, we continue to encourage contestants to submit their ideas, knowing that outperforming the current leader of a track is not required to submit an entry. Accepted CVP submissions – including the ones that did not make it into the leaderboard – will be considered for inclusion in the next CVP workshop, that is tentatively planned to take place in 2020.

The goal for this competition is to compare different value prediction algorithms in a common framework. Predictors will be evaluated for all instructions producing a general-purpose register. Predictors must be implemented within a fixed storage budget as specified in the competition rules. The simple and transparent evaluation process enables dissemination of results and techniques to the larger computer architecture community and allows independent verification of results.

General Rules:
The championship has three tracks, each designing value predictors with different storage budgets: 8KB, 32KB, and unlimited size (Competitors can choose not to compete in a particular budget category). In each category an additional side buffer of unbounded size is allowed for tracking additional information used by the predictor (e.g., global history). Authors are also required to provide a 4-page write-up describing their contribution and how storage was allocated to the different hardware structures. Note that novelty is not a strict requirement, for example, a contestant may submit his/her previously published design or make incremental enhancements to a previously proposed design, on the implicit condition that the write-up contains new insight regarding why performance has increased.

All source code, write-ups and performance results will be made publicly available through the leaderboard (

We look forward to receiving new submissions, and we encourage you to spread the word about CVP’s format and mission to colleagues and/or students that could potentially be interested.

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Boris Grot
SIGARCH Content Editor