This is the 1st August 2021 digest of SIGARCH Messages.

In This Issue

Commitment to diversity and inclusivity

Submitted by Samira Khan

Dear SIG members,

As an organization, we are committed to creating an environment that welcomes new ideas and perspectives, and where hostility or other harmful behaviors are not tolerated. As an organization, we stand with and honor those who promote diversity and inclusivity.  In addition to being the right thing to do, we believe this is important for the advancement of science.

We appreciate ACM’s reconfirmation of these commitments in response to the recent controversy surrounding Turing Award winner Jeffrey Ullman, contained in the below statement on the ACM website:

We confirm our intention to adopt the ACM policies in our SIG award selection process to the extent that they are not already present.  In addition, to emphasize our commitment to diversity and inclusivity in all our activities, we will ask nominators and endorsers for personal achievement awards to comment on how the nominee(s) exemplifies these core values.

Finally, we would like to reiterate our support for Iranian and Native American students and scholars, as well as all other ethnicities and nationalities. You are welcomed and valued members of our global community.

Thank you,


ISCA’19 Joint Investigative Committee Announcement

Submitted by Samira Khan

The ACM and IEEE Joint Investigative Committee (JIC) has completed its investigation into the allegations of professional and publications-related misconduct in connection with ISCA 2019. The full announcement related to the investigation is available here.

Call for Nominations: MICRO Test of Time Award 2021
Submitted by Saugata Ghose

The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the eighth MICRO ToT Award. This award recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field.

The award will recognize an influential MICRO paper whose influence is still felt 18-22 years after its initial publication. In other words, the award will be given to at most one paper that was published at MICRO conferences in any of the years N-22, N-21, N-20, N-19, or N-18. This year, N = 2020, so only papers published at MICRO conferences held in 1999, 2000, 2001, 2002, or 2003 are eligible. An eligible paper that has received at least 100 citations (according to Google Scholar) is automatically nominated, but explicit nominations of such papers are still encouraged.

Nominating A Paper

To nominate a paper, send an email to by August 21, 2021, with the following:

  1. The title, the author list, and publication year of the nominated paper
  2. A 100-word (maximum) nomination statement, describing why the paper deserves the Test of Time Award
  3. The name, title, affiliation of the nominator, and if appropriate, the relationship of the nominator to the authors

Only one paper can be nominated in a single email. There is a maximum of five nominations per person. You cannot nominate a paper that you are a co-author on. One paper will be selected as the award winner from the pool of nominees by the award committee.

For more information on the nomination and selection process, a list of all eligible papers, this year’s committee members, prior award winners, and other information, please visit

Nominations Due: August 21, 2021

Call for Participation: ASAP 2021
Submitted by Zhenman Fang

The 32nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2021) will be held on July 7-8, 2021. ASAP 2021 will go virtual this year, and features three keynote speakers, four oral paper sessions, two special sessions, two poster sessions, and one panel. The early bird registration deadline is June 19. Registration for all students is free!

The conference has a line-up of excellent high-profile speakers from industry and academia. Please check the program agenda for more details.


Keynote I “21st-Century NanoSystems for Abundant-Data Computing: The N3XT 1,000X” 
Prof. Subhasish MitraStanford University, USA

Keynote II “Scalable ML Architectures for Real-time Energy-efficient Computing” 
Prof. R. Iris BaharBrown University, USA

Keynote III “Amplifying Human Potential with AI” 
Intel Fellow Lama NachmanIntel Corporation, USA

Call for Participation: ISVLSI 2021
Submitted by Hao Zheng

IEEE Computer Society Annual Symposium on VLSI Systems (ISVLSI 2021)
July 7-9, 2021 – Virtual

The IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2021) will be held virtually from July 7-9, 2021. ISVLSI 2021 features four keynote speakers, 8 oral paper sessions, 4 special sessions, 1 poster session, and 1 panel. The early registration deadline is June 23.

Registration for keynote talks is free for students! 
Registration link:

Keynote Speakers

Title: Reimagining Digital Design
Speaker: Mr. Serge Leef, Program Manager, DARPA, USA

Title: Optimal Layout Synthesis for Quantum Computing
Speaker: Dr. Jason Cong, Volgenau Chair for Engineering Excellence Professor, University of California, Los Angeles, USA

Title: The Dual Role of Technology in Addressing Climate Change
Speaker: Dr. Tamar, Eilam, IBM Fellow, Thomas J. Watson Research Center, Yorktown Heights, NY USA

Title: Transforming Chip Design in the Age of Machine Learning
Speaker: Dr. Dan Zhang, Google Brain, USA

Call for Participation: CF 2021
Submitted by Naseef Mansoor

18th ACM International Conference on Computing Frontiers (CF’21)
May 11-13, 2021 – Virtual Conference

Technical Co-Sponsor: ACM, SIGMICRO
Financial Sponsors: ARM, Intel, SambaNova Systems, Tactical Computing Labs

The 18th ACM International Conference on Computing Frontiers (CF) will be held virtually during 11-13 May, 2021.  Computing Frontiers is an eclectic, interdisciplinary, collaborative community of researchers who investigate emerging technologies in the broad field of computing: our common goal is to drive the scientific breakthroughs that support society.

The conference will include a highly selective single track technical program comprised of:

– 2 Keynote Speeches
– 1 Workshop
– 4 Special sessions
– 20 Papers

Full Program and Registration Information:

Recordings of technical paper presentations will be available to all registered participants starting from a week before the beginning of the conference.

Keynote Speakers:

Quantum Computing: A Scalable, Systems Approach
Dr. Anne Matsuura, Intel Labs (Hillsboro)
Director of quantum applications and architecture at Intel Labs

Leveraging ML to Handle the Increasing Complexity of the Cloud
Christina Delimitrou
Cornell University

Call for Participation: uArch Workshop
Submitted by Divya Mahajan

Applications for funding to attend the Third Annual Undergrad Architecture Mentoring (uArch) Workshop and International Symposium on Computer Architecture (ISCA) are now open. The funding will cover the registration fee for attending the workshop and conference.

The workshop will be held virtually as part of ISCA 2021, and is aimed at undergraduate and early master’s students with an interest in computer architecture. We expect the workshop will most benefit students who will receive their undergraduate degree in 2022 or 2023. Women and people from underrepresented groups are particularly encouraged to apply for funding. The workshop:

  • Introduces students to graduate research and career opportunities in the field of computer architecture,

  • Provides sessions and panels with professors and current students on how to apply for and survive graduate school, in addition to covering how to navigate the architecture research landscape effectively,

  • Offers interactive mentoring and networking sessions with professors in the field of computer architecture, and

  • Connects students with established seniors architects in academia and industry and peers in graduate school.

Selected applicants will have the opportunity to participate in the entire program of the workshop and ISCA conference.

Location: Global Online Event

Important Dates:

  • May 14: Application deadline

  • May 28: Notification to accepted applicants

  • June 14 – June 19: ISCA Conference and Workshops

  • June 18: Main uArch Workshop

Website and link to application form:

ISCA Website:

Organizers: Newsha Ardalani, Bobbie Manne, Lena Olson, Joshua San Miguel, Divya Mahajan, Abdulrahman Mahmoud, Tony Nowatzki

Past Workshop Websites with agenda:

For queries and questions:

Call for Papers: Bench 21
Submitted by Chen Liu

The International Symposium on Benchmarking, Measuring and Optimizing encompasses a wide range of topics in benchmarking, measurement, evaluation methods and tools. Bench’s multi-disciplinary emphasis provides an ideal environment for developers and researchers from the architecture, system, algorithm, and application communities to discuss practical and theoretical work covering workload characterization, benchmarks and tools, evaluation, measurement and optimization, and dataset generation.

We solicit papers describing original and previously unpublished work. The topics of interest include, but are not limited to, the following.

Benchmark and standard specifications, implementations, and validations: Big Data, Artificial intelligence (AI), High performance computing (HPC), Machine learning, Warehouse-scale computing, Mobile robotics, Edge and fog computing, Internet of Things (IoT), Blockchain, Data management and storage, Financial, Education, Medical or other application domains.

Dataset Generation and Analysis: Research or industry data sets, including the methods used to collect the data and technical analyses supporting the quality of the measurements; Analyses or meta-analyses of existing data and original articles on systems, technologies and techniques that advance data sharing and reuse to support reproducible research; Evaluations of the rigor and quality of the experiments used to generate data and the completeness of the descriptions of the data; Tools generating large-scale data.

Workload characterization, quantitative measurement, design and evaluation studies: Characterization and evaluation of Computer and communication networks, protocols and algorithms; Wireless, mobile, ad-hoc and sensor networks, IoT applications; Computer architectures, hardware accelerators, multi-core processors, memory systems and storage networks; HPC systems; Operating systems, file systems and databases; Virtualization, data centers, distributed and cloud computing, fog and edge computing; Mobile and personal computing systems; Energy-efficient computing systems; Real-time and fault-tolerant systems; Security and privacy of computing and networked systems; Software systems and services, and enterprise applications; Social networks, multimedia systems, web services; Cyber-physical systems.

Methodologies, abstractions, metrics, algorithms and tools: Analytical modeling techniques and model validation; Workload characterization and benchmarking; Performance, scalability, power and reliability analysis; Sustainability analysis and power management; System measurement, performance monitoring and forecasting; Anomaly detection, problem diagnosis and troubleshooting; Capacity planning, resource allocation, run time management and scheduling; Experimental design, statistical analysis and simulation.

Measurement and evaluation: Evaluation methodologies and metrics; Testbed methodologies and systems; Instrumentation, sampling, tracing and profiling of large-scale, real-world applications and systems; Collection and analysis of measurement data that yield new insights; Measurement-based modeling (e.g., workloads, scaling behavior, assessment of performance bottlenecks); Methods and tools to monitor and visualize measurement and evaluation data; Systems and algorithms that build on measurement-based findings; Advances in data collection, analysis and storage (e.g., anonymization, querying, sharing); Reappraisal of previous empirical measurements and measurement-based conclusions; Descriptions of challenges and future directions that the measurement and evaluation community should pursue.

  • Paper Submission: The full version of the paper should be submitted as a PDF file following the submission guidelines. Submission issues should be directed to the Program Chairs, Lei WangAxel Ngonga and Chen Liu. Please consult the Bench’21 website for additional information about the conference and submission details.
  • Publication: All accepted papers will be presented at the Bench’21 conference and will be published in a special issue of the BenchCouncil Transactions on Benchmarks, Standards and Evaluation (TBench).
  • Awards: Bench’21 conference will present the BenchCouncil Achievement Award ($3000), the BenchCouncil Rising Star Award ($1000), the BenchCouncil Distinguished Doctoral Dissertation Award ($1000),and the BenchCouncil Best Paper Award ($1000). To encourage reliable and reproducible research using the benchmarks from all organizations, the Bench conference presents the BenchCouncil Award for Excellence for Reproducible Research to the papers using publicly available benchmarks. Each article receives a $100 prize, for up to 12 articles.

Important Dates

Abstracts: July 16, 2021
Full Papers: July 30, 2021
Notification: September 15, 2021
Final Papers Due: October 11, 2021

Call for Papers: ICRC 2021
Submitted by Michael P. Frank

The 6th IEEE International Conference on Rebooting Computing (ICRC 2021) will be held from November 30th to December 2nd, 2021 as a virtual conference. ICRC grew out of the IEEE Rebooting Computing Initiative (RCI), which was founded in 2012 to catalyze rethinking of the computer at all levels of the technology stack. The Rebooting Computing community represents multiple IEEE Societies and Councils, and the membership in the technical community is over two thousand. For more information on the RCI please visit the Rebooting Computing Portal (

Now in its 6th year, the IEEE International Conference on Rebooting Computing is the premier venue for forward-looking computing, including algorithms and languages, system software, system and network architectures, new devices and circuits, and applications of new materials and physics. This is an interdisciplinary conference that has participation from a broad technical community, with emphasis on all aspects of the computing stack. Bridging reversible and quantum computing, analog and neural computing, and new architectures, the broad scope of ICRC extends to many areas of interest, including novel device physics and materials for post-Moore, beyond CMOS, and non-von Neumann computing paradigms.

Topics of Interest:

Future computing approaches, including neuromorphic, brain-inspired computing, approximate and probabilistic computing, and analog and physical computing; computing based on novel device physics and materials (e.g., spin-based electronics, nonlinear dynamics and chaos); energy-efficient computing including reversible, adiabatic, and ballistic computing, superconductor and cryogenic computing; quantum computing; optical computing; biological and biochemical computing; non-von Neumann computer architectures (e.g., in-memory processing, memory-based computing, content addressable memory, cellular automata, or  neural networks); graph processing architectures.

Future computing design aspects, including extending Moore’s law and augmenting CMOS; error-tolerant logic and circuits; future of design automation; post-CMOS, 3D, heterogeneous integration and packaging; future impact on performance, power, scalability, reliability, and supportability; modeling and simulation tools for future computing.

Future Software and Applications, including beyond von Neumann system software issues (operating systems, compilers, security, and resource management); future computing programming paradigms and languages; applications suitable for and driving next generation computing (e.g., machine learning, deep learning.); algorithms that are enabled by or optimized for new computing approaches.

Future computing use cases and prototypes, including ethics in design, implementation, and use; new technologies impacting the International Roadmap for Devices and Systems (IRDS); cybersecurity in future computing systems.

Paper Submission:

Important Dates:

  • Abstracts due: Fri. 6 August 2021 (11:00 pm EDT)
  • Paper submissions due: Fri. 20 August 2021 (11:00 pm EDT)
  • Author notification of acceptance: Mon. 11 October 2021 (tentative)
  • Final copies of papers due: Fri. 22 October 2021 (tentative)
  • Session recordings due: Sat. 13 November 2021
  • Conference: Tue.-Thu. 30 November – 2 December 2021

Organizing Committee:

  • General Co-Chairs: Thomas Conte (Georgia Tech), John McAllister (Queen’s University Belfast)
  • Program Co-Chairs: Michael Frank (Sandia National Laboratories), Sapan Agarwal (Sandia National Laboratories)
  • Web chair: Simon Caton (University College Dublin)
  • Full committee list:

Call for Papers: CGO 2022
Submitted by Dongyoon Lee

The International Symposium on Code Generation and Optimization (CGO) is a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

Important Dates

Abstract Submission: August 27, 2021
Paper Submission: September 3, 2021
Author Rebuttal Period: October 18 – October 22, 2021
Paper Notification: November 5, 2021
Artifact Evaluation Deadline: November 19, 2021
Artifact Evaluation Notification: December 17, 2021

Original contributions are solicited on, but not limited to, the following topics:

  • Code Generation, Translation, Transformation, and Optimization for performance, energy, virtualization, portability, security, or reliability concerns, and architectural support
  • Efficient execution of dynamically typed and higher-level languages
  • Optimization and code generation for novel and emerging programming models, hardware platforms, and domain-specific languages
  • Dynamic/static, profile-guided, feedback-directed, and machine learning based optimization
  • Static, Dynamic, and Hybrid Analysis for performance, energy, memory locality, throughput or latency, security, reliability, or functional debugging
  • Program characterization methods
  • Efficient profiling and instrumentation techniques; architectural support
  • Novel and efficient tools
  • Compiler design, practice and experience
  • Compiler abstraction and intermediate representations
  • Vertical integration of language features, representations, optimizations, and runtime support for parallelism
  • Solutions that involve cross-layer (HW/OS/VM/SW) design and integration
  • Deployed dynamic/static compiler and runtime systems for general purpose, embedded system and Cloud/HPC platforms
  • Parallelism, heterogeneity, and reconfigurable architectures
  • Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA
  • Compiler support for vectorization, thread extraction, task scheduling, speculation, transaction, memory management, data distribution and synchronization

Call for Tools and Practical Experience Papers

Last two years CGO had a special category of papers called “Tools and Practical Experience,” which was very successful. CGO this year will have the same category of papers. Such a paper is subject to the same page length guidelines, except that it must give a clear account of its functionality and a summary about the practice experience with realistic case studies, and describe all the supporting artifacts available.

For papers submitted in this category that present a tool it is mandatory to submit an artifact to the Artifact Evaluation process and to be successfully evaluated. These papers will initially be conditionally accepted based on the condition that an artifact is submitted to the Artifact Evaluation process and that this artifact is successfully evaluated. Authors are not required to make their tool publicly available, but we do require that an artifact is submitted and successfully evaluated.

Papers submitted in this category presenting practical experience are encouraged but not required to submit an artifact to the Artifact Evaluation process.

The selection criteria for papers in this category are:

  • Originality: Papers should present CGO-related technologies applied to real-world problems with scope or characteristics that set them apart from previous solutions.
  • Usability: The presented Tools or compilers should have broad usage or applicability. They are expected to assist in CGO-related research, or could be extended to investigate or demonstrate new technologies. If significant components are not yet implemented, the paper will not be considered.
  • Availability: Preferences will be given to tools or compilers that are freely available (at either the source or binary level). Exceptions may be made for industry and commercial tools that cannot be made publicly available for business reasons.
  • Documentation: Publicly available tools should be presented on a web-site giving documentation and further information about the tool.
  • Test or Benchmark Repository: Tool papers must provide a suite of tests or benchmarks. Papers that make performance claims must provide benchmarks.
  • Foundations: Papers should incorporate the principles underpinning Code Generation and Optimization (CGO). However, a thorough discussion of theoretical foundations is not required; a summary of such should suffice.
  • Artifact Evaluation: The submitted artifact must be functional and supports the claims made in the paper. Submission of an artifact is mandatory for papers presenting a tool.

Artifact Evaluation

The Artifact Evaluation process is run by a separate committee whose task is to assess how the artifacts support the work described in the papers. This process contributes to improving reproducibility in research that should be a great concern to all of us. There is also some evidence that papers with a supporting artifact receive higher citations than papers without (Artifact Evaluation: Is It a Real Incentive? by B. Childers and P. Chrysanthis).

Authors of accepted papers at CGO have the option of submitting their artifacts for evaluation within two weeks of paper acceptance. Authors of tools papers submitted in the category of “Tools and Practical Experience Papers” must submit an artifact. To ease the organization of the AE committee, we kindly ask authors to indicate at the time they submit the paper, whether they are interested in submitting an artifact. Papers that go through the Artifact Evaluation process successfully will receive a seal of approval printed on the papers themselves. Additional information is available on the CGO AE web page. Authors of accepted papers are encouraged, but not required, to make these materials publicly available upon publication of the proceedings, by including them as “source materials” in the ACM Digital Library.

Authors should carefully consider the difference in focus with the co-located conferences when deciding where to submit a paper. CGO will make the proceedings freely available via the ACM DL platform during the period from two weeks before to two weeks after the conference. This option will facilitate easy access to the proceedings by conference attendees, and it will also enable the community at large to experience the excitement of learning about the latest developments being presented in the period surrounding the event itself.

Call for Papers: IISWC 2021
Submitted by Moriyoshi Ohara

IISWC invites manuscripts that present original unpublished research in all areas related to characterization and analysis of computing system workloads, including translational research related to production-oriented commercial systems. The detailed CFP can be found here.


  • Submission Deadline : July 9, 2021 (11:59 EDT)
  • Decision Notification : September 3, 2021
  • Camera-ready deadline : October 8, 2021

**New in 2021 — Artifact Evaluation**

This year, IISWC will include an artifact evaluation process to promote the reproducibility of experimental results. We will invite the authors of accepted IISWC papers to submit their supporting materials to the Artifact Evaluation process, which is to assess how the artifacts support the work described in the papers. This submission will be voluntary and will not influence the final decision regarding acceptance of the paper. The description of the artifact will not be included in the page limit. The artifact submission deadline will be shortly after the notification of the paper’s acceptance — authors should prepare in advance to ensure sufficient time for artifact assembly and documentation. More details of artifact evaluation will be made available to the authors of the accepted paper.

Submission Guidelines

Submissions to IISWC can be made in one of the following two categories: (1) regular papers (2) tool and benchmark papers. The primary focus of “regular papers” (submission length: 10 pages, excluding references) should be to describe new research ideas supported by experimental implementation and evaluation of the proposed research ideas. The primary focus of “tool and benchmarks papers” should be to describe the design, development, and evaluation of new open-source tools / benchmarks suites. Submissions in the “regular papers” category are also encouraged to open-source their software or hardware artifacts.

The authors are required to indicate the category of the paper as a part of the submitted manuscript’s title. The last line of the title should indicate the paper type by using one of the two phrases (1) Paper Type: Regular, or (2) Paper Type: Tool / Benchmark.

Papers in the tool and benchmark category with relatively shorter length (6 pages) are welcome, if the contributions can be well articulated and substantiated. However, all submissions in the tool and benchmark category have the flexibility of using all 10 pages (excluding references).

The submissions in both categories will be evaluated to the same standards in terms of novelty, scientific value, demonstrated usefulness, and potential impact on the field. The nature of the contribution differs between the two categories (new research idea vs. new open-source benchmark-suite / tool) and papers will be evaluated based on the intended nature of the contribution, as declared by the chosen paper category at the time of the submission. The chosen category at the time of the submission can not be changed after the submission deadline.

Double-blind submission guidelines apply to the submissions in both categories.

Open-source benchmarks and tools that have not been previously published (but may have been open-sourced) are eligible for submission in the “tool and benchmark papers” category. Even in cases where the benchmarks suite/tool is already being used in the community, the authors should demonstrate a good faith effort to adhere to the double-blind submission guidelines. All submitted papers should have obtained legal permission (if applicable) to open-source the benchmark-suite / tool at the time of submission.

Topics of Interest

Characterization of applications in domains including

  • Life sciences, bioinformatics, scientific computing, finance, forecasting
  • Machine learning, data analytics, data mining
  • Cyber-physical systems, pervasive computation and Internet of Things (IoT)
  • Security and privacy-preserving computing
  • Quantum computing
  • High performance computing
  • Cloud and edge computing
  • Mobile computing
  • User behavior and system-user interaction
  • Search engines, e-commerce, web services, and databases
  • Embedded, multimedia, real-time, 3D-graphics, gaming
  • Blockchain services

Emerging workloads and architectures, such as

  • Quantum computations and communication
  • Serverless computing
  • Near-threshold computing
  • Non-volatile memory
  • Near data processing architectures
  • Neuromorphic and brain-inspired computing
  • Artificial intelligence and transactional memory workloads

Characterization of OS, Virtual Machine, middleware and library behavior, including

  • Virtual machines, .NET, Java VM, databases
  • Graphics libraries, scientific libraries
  • Operating system and hypervisor effects and overheads

Implications of workloads in system design, such as

  • Power management, reliability, security, privacy, performance
  • Processors, memory hierarchy, I/O, and networks
  • Design of accelerators, FPGAs, GPUs, CGRAs, etc.
  • Large-scale computing infrastructures and facilities

Benchmark methodologies and suites, including

  • Representative benchmarks for emerging workloads
  • Benchmark cloning methods
  • Profiling, trace collection, synthetic traces
  • Validation of benchmarks

Measurement tools and techniques, including

  • Instrumentation methodologies for workload verification and characterization
  • Techniques for accurate analysis/measurement of production systems
  • Analytical and abstract modeling of program behavior and systems

Call for Papers: HPCA 2022
Submitted by Wenjie Xiong

The 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA) will be held in Seoul, South Korea, February 12-16, 2022. HPCA is a high-impact venue for presenting research results on a wide range of computer architecture topics.

Some computer architecture topics of interest are listed below, but we encourage authors to contact the PC chair if they have a question regarding the topic fit:

  • Accelerators
  • Approximate Computing
  • Compilers/PL for novel architectures
  • CPU/Microarchitecture
  • Domain-Specific Processing
  • Embedded/IoT/Edge
  • FPGA, CGRA, Reconfigurable Systems
  • GPGPU/GPU Computing
  • Integration (3D/interposer/wafer-scale)
  • Memory/Storage
  • Measurement, Modeling, Simulation
  • Near/In-Memory Computing
  • Networks and Interconnects
  • Neuromorphic Computing
  • Quantum/ Superconducting Computing
  • Reliability/Fault Tolerance
  • Security/Privacy

Please note that HPCA-2022 features a separate Industry Track with a separate CfP. The goal of the HPCA Industry Track is to publish papers that are written by industry authors and their content relates to industrial products/processes.

Important Dates
Abstract submission deadline: July 23rd, 2021 23:59 UTC / 16:59 PDT
Paper submission deadline: July 30th, 2021 23:59 UTC / 16:59 PDT
Revision/rebuttal period: Sept. 28th – Oct 8th, 2021
Notification: Oct. 27th, 2021

Program Chair: Prof. Stefanos Kaxiras (Uppsala University)
General Chairs: Prof. Jung Ho Ahn (Seoul National University), Prof. John Kim (KAIST)
Web Chair: Prof. Youngsok Kim (Yonsei University)
Industry Session Chair: Dr. Daniel Lustig (NVIDIA)

For more information, including submission instructions (when available), please see the HPCA22 website (

Call for Papers: HPCA 2022 Industry Track
Submitted by Wenjie Xiong

The International Symposium on High-Performance Computer Architecture includes an industry track within the main conference program. The objective of this track is to present papers with high industry relevance that describe existing/planned/cancelled products and/or insights on important challenges faced by industry. The discussion in this forum is expected to educate the wider computer architecture community on the challenges facing the industry and to encourage them to investigate solutions. The session will include a small number of papers selected based on depth and relevance to the HPCA audience. Architects, designers, and developers involved in some aspect of industrial computer systems design and development are invited to submit a paper describing existing, planned, or canceled products, as well as new challenges, issues, and opportunities in next-generation computer systems. The paper needs to provide insights, results, etc. that are unique to industry and that make it clearly distinguishable from a regular paper.

Authors should submit an abstract by July 23rd, 2021. They should submit the full version of the paper by July 30th, 2021. No extensions will be granted. The full version should be a PDF file following the submission guidelines that will be made available at the submission website. Papers should be submitted for double-blind review.  The company or product name in question need not be obscured, but no references should be made to individual author identities.

Please take note of the following guidelines for the industry track:

  • The goal of the HPCA industry track is to publish papers written by industry authors with content related to an industrial product/process. This includes both existing products and planned products, even if the product was cancelled, as long as interesting insights/learned lessons are presented in the paper.
  • Examples are papers that describe a product, papers that characterize a product, papers that describe some interesting component of a product, papers that provide some insights on challenges faced by industry, etc.
  • Papers may include co-authors from academia, provided that the content is clearly related to an industrial product/process. On the other hand, research papers whose scope is not clearly related to a product are not appropriate for this track and will be rejected from the industry track.  Such papers should be submitted to the regular track even if authors are from industry.
  • Papers will be evaluated with the same standards of quality as papers submitted to the regular track.

Topics of interest include, but are not limited to:

  • Processor, cache, and memory architectures
  • Parallel/Multi-core architectures
  • GPUs and domain-specific accelerators
  • Power-efficient architectures
  • Dependable/secure architectures
  • Analysis and exploitation of product security vulnerabilities
  • High-performance I/O systems
  • Embedded, IoT, reconfigurable, and heterogeneous architectures
  • Interconnect and network interface architectures
  • Architectures for cloud, HPC, and data centers
  • Innovative hardware/software trade-offs
  • Impact of compilers and system software on architecture
  • Performance/Power modeling and evaluation
  • Architectures for emerging technology and applications

Important Dates

Abstract submission: July 23rd, 2021
Full paper submission: July 30th, 2021
Author rebuttal period: Sep. 28th — Oct. 8th, 2021
Author notification: Oct. 27th, 2021

For more information, including submission instructions (when available), please see the HPCA22 website (

Call for Papers: SEED 2021
Submitted by Jakub Szefer

IEEE International Symposium on Secure and Private Execution Environment Design (SEED)
Worldwide Virtual Event
September 20-21, 2021

Submissions Due: May 21, 2021


The IEEE International Symposium on Secure and Private Execution Environment Design (SEED) is a forum which brings together researchers from the computer architecture and computer security communities into one venue that focuses on the design of architectural and system primitives which provide secure and private execution environments for applications, containers, or virtual machines.

SEED primarily focuses on research topics spanning across the boundaries of computer architecture, systems, and security. Papers are solicited on a range of topics, including (but not limited to):

* Architecture, operating systems, and programming models and language for supporting secure and private execution
* Novel Designs for secure and private execution environments for GPUs, accelerators, and FPGAs
* Architectural support for new security primitives
* Novel cryptographic hardware designs for secure and private execution
* Models and analysis of performance-security trade-offs in the design of a secure execution environment
* Evaluation of security vulnerabilities in post-Moore’s Law technologies, e.g. persistent memory, quantum computing
* Demonstration and mitigation of architectural side channels, covert channels and other security vulnerabilities
* Metrics for measuring architecture-related security vulnerabilities
* Compiler and code generation techniques for mitigating architecture-induced side and covert channels and other vulnerabilities


Abstract Deadline: May 14, 2021 at 11:59 PM AoE
Full Paper Deadline: May 21, 2021 at 11:59 PM AoE
Rebuttal Period: TBD
Author Notification: July 31, 2021
Camera-ready Submission: August 15, 2021
Conference Dates: September 20-21, 2021



General Chairs: Jakub Szefer (Yale Univ.) and Yan Solihin (Univ. of
Central Florida)
Program Chairs: Guru Venkataramani (George Washington Univ.) and Yinqian
Zhang (SUSTech)


Todd Austin (U. of Michigan)
David Kaeli (Northeastern U.)
Ruby Lee (Princeton)
Milos Prvulovic (Ga. Tech)
Deborah Shands (SRI)
Yan Solihin – Chair (U. of Central Florida)
Guru Venkataramani (GWU)

Call for Papers: ICPP 2021
Submitted by Xu Liu

The 50th International Conference on Parallel Processing (ICPP)
August 9-12, 2021

Submissions Due: April 23, 2021

The International Conference on Parallel Processing (ICPP) is one of the oldest continuously running computer science conferences in parallel computing in the world. It is a premier forum for researchers, scientists, and practitioners in academia, industry, and government to present their latest research findings in all aspects of the field. This year will be the 50th year of ICPP. ICPP2021 will be held at the US Argonne National Laboratory in Chicago, USA and special events will be held to celebrate the 50th anniversary at the conference. ICPP2021 is in cooperation with ACM SIGHPC. We invite everyone to participate in the conference and its celebration.

ICPP is a premier venue for presenting the latest research on all aspects of parallel processing. Topics of interest in ICPP 2021 papers include, but not limited to: Algorithms, Applications, Architecture, Performance, Software. More details of paper submission and about the conference can be found at the conference website at

Important Deadlines
● Abstract Submission: April 10, 2021
● Paper Submission: April 23, 2021
● Author Response Period: May 31 – June 2, 2021
● Author Notification: June 11, 2021

For submission, please visit Linklings submission site ( to
make paper submissions.

Call for Papers: ROAD4NN 2021
Submitted by Zhenman Fang

The 2nd ROAD4NN (Research Open Automatic Design for Neural Networks) Workshop Call For Papers
(Co-located with DAC 2021), Dec 5, 2021

In the past decade, machine learning, especially neural network based deep learning, has achieved amazing success. Various types of neural networks, such as CNNs, RNNs, LSTMs, BERT, GNNs, SNNs, and the recent vision transformers, have been deployed for various industrial applications like image classification, speech recognition, natural language understanding, autonomous driving, and automated control. On one hand, there is a very fast algorithm evolvement of neural network models. Almost every week there is a new model from a major academic and/or industry institute. On the other hand, all major industry giants have been developing and/or deploying specialized hardware platforms to accelerate the performance and improve the energy-efficiency of neural networks across the cloud and edge devices. This includes Nvidia GPUs, Google TPUs, ARM and Qualcomm mobile CPUs and GPUs, programmable DSPs and NPUs, Intel Nervana/Habana/Loihi ASICs, Xilinx and Intel FPGAs, Microsoft Brainwave, Amazon Inferentia, to name just a few. However, there is a significant gap between the fast algorithm evolvement and staggering hardware development, hence calling for broader participation in software-hardware co-design from both academia and industry.

In this workshop, we focus on the open research of automated design for neural networks, a holistic open source approach to general-purpose computer systems broadly inspired by neural networks. More specifically, we discuss full stack open source infrastructure support to develop and deploy novel neural networks, including novel algorithms and applications, hardware architectures and emerging digital/analog devices, as well as programming, compiler, system, and tool support. We plan to bring together academic and industry experts to share their experience, discuss challenges they face as well as potential focus areas for the community.

We are soliciting work-in-progress papers from the community. Workshop topics include, but are not limited to:

  • New algorithm advancement of neural networks
  • Bio-plausible neural network models
  • Neural network model compression, quantization, and network architecture search
  • Application of neural networks into new areas
  • Hardware acceleration and architecture for neural networks
  • New analog and mixed-signal circuits and architecture for neural networks
  • Abstraction to bridge the algorithm and hardware gap for neural networks
  • Compilation and design automation support to map neural networks to hardware platforms
  • System support to deploy neural networks in cloud and edge devices
  • Benchmarks for various neural network models and hardware accelerators
  • Other research infrastructures that enable the above studies

Submission guidelines:

Interested authors are encouraged to submit their work-in-progress papers (up to four pages) through EasyChair (link: Authors are encouraged to submit preliminary work for new projects and early results. All papers will be reviewed with a double-blind review process. Manuscripts should not exceed 4 single-spaced, double-column pages using 10-point size font on 8.5×11 inch pages (IEEE conference style), including references, figures, and tables. All papers must be submitted electronically in PDF format. Accepted papers will be invited to give a 25 mins talk with 5 min Q/A for each talk; there will be no proceedings, so that authors can still submit their papers to other conferences/journals. The deadline for submission is Aug 8, 11:59 PM (Pacific Time), 2021.

Student presentation award: We will select the three Best Student Presentations from the workshop and send a mysterious gift to each student awardee.

Important dates:

  • Paper submission: Aug 8, 2021, 11:59 PM (Pacific Time)
  • Author notification: Aug 31, 2021 (Pacific Time)
  • Workshop date: Dec 5, 2021 (Pacific Time)


Past ROAD4NN workshop: 

We have organized the first ROAD4NN workshop co-located with the Design Automation Conference 2020 (DAC 2020) on Jul 19, 2020. It is a huge success with more than 500 registrations from more than 200 academic institutions and industrial companies. The first workshop was invitation only, and we invited a number of renowned researchers to give talks, who come from academia and industry and some of them have successful experience in co-founding machine learning startup companies. For example, we have invited Prof. Deming Chen from UIUC to give a keynote. Other invited researchers include Xilinx Fellow Ashish Sirasao, Microsoft Brainwave project researcher Fanny Nina Paravecino (female), Prof. Song Han from MIT, Prof. Zhiru Zhang from Cornell, Prof. Zhangyang (Atlas) Wang from TAMU, Prof. Yingyan Lin from Rice (female), Prof. Peng Li from UCSB, to name just a few. The full schedule (with talk slides) can be found on our ROAD4NN 2020 workshop website:

Call for Papers: H2RC Workshop
Submitted by Jason D. Bakos

The Seventh International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) will be held on Monday, November 15, 2021. Accepted papers will be indexed and published in the IEEE Digital Library though TCHPC and invited to submit extended manuscript to a special issue of the Elsevier Journal of Parallel and Distributed Computing on H2RC 2021.

Submission link

As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier-to-use high-level programming models for FPGAs, and much of the work in FPGA-based deep learning is built on these frameworks.

Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its sixth year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on how newly-available high-level programming models, including OpenCL, are already empowering HPC software developers to directly leverage FPGAs, and to identify future opportunities and needs for research in this area.

Submission Tracks and Contribution Selection
Submissions are solicited for two tracks:

Track 1: Full-length papers (10 pages excluding references) for 25-minute oral presentation and publication in proceedings archived by IEEE.
Track 2: Extended abstracts / talk proposals (4 pages) for 15-minute oral presentation without publication.

Track 1 is targeted for technical papers containing a high level of implementation detail and analysis and discussion of experimental results. Track 1 is suited for members of the academic and national lab community who prefer to have their work peer-reviewed, indexed and archived by IEEE.

Track 2 is targeted for industrial contributions that describe new capabilities and opportunities offered by emerging technologies and products, or work in progress presentations by the academic and national lab community. The emphasis of this track is to initiate a discussion with the audience.

All submissions are reviewed and evaluated by at least three members of our technical program committee.  From the TPC evaluation of each submission, the organizing committee will select papers for presentation based on a criteria that is equally weighted between scientific merit and level of interest and relevance to the HPC community.

Submission Topics
Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance compute architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers.  Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, or any other area that promises to make a significant contribution to our understanding of heterogeneous high-performance reconfigurable computing and will help to shape future research and implementations in this domain. A non-comprehensive list of potential topics of interest is given below:

  1. Improvement of performance or efficiency of HPC or data center applications with FPGAs
  2. System integration of FPGAs in clouds and HPC systems
  3. Leveraging reconfigurability
  4. Benchmarks
  5. Programming languages, tools, and frameworks
  6. Future-gazing

Submission Guidelines

Full papers (Track 1)Authors should submit original contributions of up to 10 pages (excluding references) in PDF format using the SC21 Linklings portal (, which is also linked from the H2RC website ( Submissions must be formatted as single-spaced, double-column, A4 pages without page numbers following the IEEE conference proceedings format, including figures, tables, and references. H2RC uses a single blind review process. We support the SC reproducibility initiative and highly encourage authors to add an artifact description/artifact evaluation appendix of up to 2 additional pages to their paper. All accepted papers will be published in the IEEE TCHPC Proceedings in the IEEE Xplore digital library.

Talk proposals (Track 2):To apply for a talk authors should submit a 4-page extended abstract. The extended abstract will be peer-reviewed and used for deciding on the acceptance of a presentation assignment of a presentation slot, but will not be published in the proceedings. The papers shall follow the same formatting instructions as the full papers and have also to be submitted using the Linklings system.

Important Dates
Submission Deadline:                                    August 7, 2021
Acceptance Notification:                                October 1, 2021
Camera-ready Manuscripts Due:                   October 15, 2021
Workshop Date:                                             November 15, 2021

Workshop Format
H2RC is a full-day Monday workshop.  It will be comprised of:

  • Keynote and invited talks
  • Talks selected among paper submissions
  • Panel discussion on research opportunities and needs

Workshop Organizers
Jason D. Bakos, University of South Carolina
Franck Capello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Ken O’Brien, Xilinx
Christian Plessl, Paderborn University

Call for Papers: Parallel Applications Workshop, Alternatives To MPI+X
Submitted by Karla Morris

Held in conjunction with SC21, St. Louis, MO

Architectural hierarchy and heterogeneity makes programming supercomputers challenging. In practice, HPC applications tend to be written using a mix of programming models—like C++, MPI, CUDA, and/or OpenMP—each of which is becoming more complex over time. This negatively impacts the costs of developing, maintaining, and porting HPC applications.

Meanwhile, alternative HPC programming models strive to improve things by raising the level of abstraction; incorporating modern features; and/or leveraging the respective strengths of programmers, compilers, and runtimes. These alternatives take the form of new languages (e.g., Chapel, Regent, XcalableMP), frameworks for large-scale data science (e.g., Arkouda, Dask, Spark), or extensions to existing languages (e.g., Charm++, COMPSs, Fortran, Legion, UPC++).

PAW-ATM is a forum for discussing HPC applications written in alternatives to MPI+X. Its goal is to bring together application experts and proponents of high-level languages to present concrete example uses of such alternatives, describing their benefits and challenges.

Scope and Aims

The PAW-ATM workshop aims to serve as a forum for exhibiting parallel applications developed using high-level parallel programming models that serve as alternatives to MPI+X-based programming. We encourage the submission of papers and talks from the community detailing practical distributed-memory applications written using alternatives to MPI+X, including characterizations of scalability and performance, expressiveness and programmability, as well as any downsides or areas for improvement in such models. In doing so, our hope is to create a setting in which application authors, language designers, and architects can present and discuss the state of the art in alternative scalable programming models while also wrestling with how to increase their effectiveness and adoption. Beyond well-established HPC scientific simulations, we also encourage submissions exploring artificial intelligence, big data analytics, machine learning, and other emerging application areas.

Topics of interest include, but are not limited to:

  • Novel application development using high-level parallel programming languages and frameworks.
  • Examples that demonstrate performance, compiler optimization, error checking, and reduced software complexity.
  • Applications from artificial intelligence, data analytics, bioinformatics, and other novel areas.
  • Performance evaluation of applications developed using alternatives to MPI+X and comparisons to standard programming models.
  • Novel algorithms enabled by high-level parallel abstractions.
  • Experience with the use of new compilers and runtime environments.
  • Libraries using or supporting alternatives to MPI+X.
  • Benefits of hardware abstraction and data locality on algorithm implementation.

Papers that include description of applications that demonstrate the use of
alternative programming models will be given higher priority.


Submissions are solicited in two categories:

1) Full-length papers presenting novel research results: Full-length papers will be published in the workshop proceedings (+). Submitted papers must describe original work that has not appeared in, nor is under consideration for, another conference or journal. Papers shall be eight (8) pages minimum and not exceed ten (10) including text, appendices, and figures. Appendix pages related to the reproducibility initiative dependencies, namely the Artifact Description (AD) and Artifact Evaluation (AE), are not included in the page count.

+ The specific publisher of the proceedings is TBA pending acceptance of our proposal to the proceedings publisher.

2) Extended abstracts summarizing preliminary/published results: Extended abstracts will be evaluated separately and will not be included in
the published proceedings; they are intended to propose timely communications of novel work that will be formally submitted elsewhere at a later stage, and/or of already published work that would be of interest to the PAW-ATM audience in terms of topic and timeliness. Extended abstracts shall not exceed four (4) pages.

When deciding between submissions with similar merit, submissions whose focus relates more directly to the key themes of the workshop (application studies, computing at scale, high-level alternatives to MPI+X) will be given priority over those that don’t. In addition, full-length paper submissions will be given preference over extended abstracts.

Submissions shall be submitted through Linklings:

Submissions must use 10pt font in the IEEE format:

PAW-ATM follows the reproducibility initiative of SC21. For more information, please refer to:

Workshop Chair:
Karla Morris – Sandia National Laboratories

Organizing Committee:
Rosa M. Badia – Barcelona Supercomputing Center
Michael Ferguson – Hewlett Packard Enterprise

Program Committee Chairs:
Bill Long – Hewlett Packard Enterprise
Sean Treichler – NVIDIA

Program Committee:
* Vicenç Bertran – Barcelona Supercomputing Center
* Dan Bonachea – Lawrence Berkeley National Laboratory
* Peter Braam – University of Oxford
* Harold Castro – Los Andes University (Colombia)
* Bradford L. Chamberlain – Hewlett Packard Enterprise
* John Feo – Pacific Northwest National Laboratory
* Michael Ferguson – Hewlett Packard Enterprise
* Salvatore Filippone – University of Rome Tor Vergata
* Fernanda Foertter – The BioTeam, Inc.
* Max Grossman – Georgia Institute of Technology
* Hideto Iwashita – HPFPC
* Daniel S. Katz – University of Illinois, Urbana-Champaign
* Wonchan Lee – NVIDIA
* Daniele Lezzi – Barcelona Supercomputing Center
* Bill Long – Hewlett Packard Enterprise
* Karla Morris – Sandia National Laboratories
* Irene Moulitsas – Cranfield University
* Mitsuhisa Sato – RIKEN Advanced Institute for Computational Science
* Sean Treichler – NVIDIA

Advisory Committee:
* Bradford L. Chamberlain – Hewlett Packard Enterprise
* Damian W. I. Rouson – Sourcery Institute
* Katherine A. Yelick – Lawrence Berkeley National Laboratory

Important Dates
* Submissions deadline: July 23, 2021
* Manuscripts review period: August 6-20, 2021
* Rebuttal submission: September 3, 2021
* Building consensus: September 4-10, 2021
* Notification to authors: September 13, 2021
* Final program: September 15, 2021
* Camera-ready papers due from authors: October 1, 2021
* Workshop date: November 14|15|19, 2021


Call for Papers: LCPC 2021
Submitted by Xiaoming Li

Since its inception in 1988, the Workshop on Languages and Compilers for Parallel Computing (LCPC) has been a leading venue for cutting-edge research on all aspects of parallel programming systems — from parallel programming models, languages, compilers, runtimes and tools, to results related to new parallel applications or systems. Its scope is particularly broad: it encompasses foundational results, as well as practical experience reports and bold new ideas for future systems.

In addition to its traditional themes in parallel programming systems, relevant topics include advances in programming systems for heterogeneous and reconfigurable computing, mobile computing, IoT and cloud computing, and papers in data analytics, machine learning and cognitive computing. Along with research in new computing domains such as analog, neuromorphic and quantum computing, LCPC particularly encourages submissions in areas that are enabled or enhanced by parallelism and work that combines scientific computing with data analytics and machine learning.

Specific topics of interest for LCPC 2021 include, but are not limited to:

  • Compilers for parallel computing, including heterogeneous systems
  • Static, dynamic and adaptive optimization of parallel programs
  • Just-in-time compiling, including for scripting languages
  • Parallel programming models and languages for traditional and emerging architectures
  • Languages and tools for programming quantum computing systems
  • Formal methods in analysis, verification, and software engineering of parallel programs
  • Intermediate representations for general-purpose and domain-specific compilation
  • Parallel runtime systems and libraries
  • Performance analysis and debugging tools for parallel programs
  • Parallel algorithms and concurrent data structures
  • Parallel applications for Big Data, Machine Learning, Embedded Systems, Bio, IoT
  • Fault tolerance in parallel systems
  • Parallel communication idioms and libraries (e.g. MPI, OpenSHMEM)

LCPC 2021 invites the following kinds of papers in Springer Verlag LNCS format:

  • Full papers of up to 15 pages on innovative and original research that describe new research contributions
  • Short papers of up to 8 pages on preliminary results, surveys, demonstrations, or visions for future research

Note that presentations for both kinds of papers will be 30 minutes (25 minutes talk + 5 minutes questions)

Papers must be submitted in PDF format. There will be pre-workshop, informal proceedings as well as post-workshop proceedings in Springer Verlag’s LNCS series. Authors of accepted papers will be required to sign the Springer copyright form. Instructions for preparing papers for the formal proceedings will be emailed to authors of accepted papers.

For detailed instructions please see…

LNCS templates can be downloaded from Springer (LaTex2e class, LaTex2e sample and MS Word).

Submission and reviewing timeline:

Submission opens: July 1, 2021
Full paper submission: July 15, 2021, Anywhere on Earth
Decision notification: August 30 2021
Pre-workshop version due: September 30, 2021
Workshop date: October 13-15, 2021

Camera-ready version for publication in Springer LNCS: December 14, 2021

Submission instructions:

Please submit your papers via EasyChair. Reviews will be double-blind.

Call for Papers: ACM SRC @ PACT 2021
Submitted by Changhee Jung

The ACM Student Research Competition (SRC) is a forum for graduate and undergraduate students to share their research results, exchange ideas, and improve their communication skills while competing for prizes. The SRC consists of three rounds: a) online abstract submission authored by the student alone, b) poster session at PACT 2021 by authors for selected abstracts and c) presentation at PACT 2021 by authors of the top posters selected by judges at the conference.

The evaluation of round (1) will focus on the quality of the research contributions, while rounds (2) and (3) will also consider the quality of visual and oral presentation. You can find more information on the ACM Student Research Competition at

Important Dates
Abstract Deadline: Friday, August 20, 2021 (AoE)
Notification: Monday, September 13, 2021
Submission Site:
Conference Dates: Sep 26-29 2021

A participant in the SRC must meet all of the following conditions:

  • The abstract and the poster must be authored solely by the participant.
  • The participant must submit an abstract of up to 800 words outlining the content of a poster that is going to be presented during the competition.
  • The abstract must include the poster title, author name, affiliation, and the name of the academic advisor. It should describe the research problem, motivation and background, techniques and results, and the prospect for clearly and concisely conveying the work in a poster format. It should state the novelty and contributions of the work explicitly.
  • The standard self-plagiarism rules are in effect. If the research results have already appeared in a publication, prior to the SRC submission date, then they are not permitted to be submitted to an SRC for consideration. Furthermore, the same work may not be presented at an SRC and in another session at PACT 2021. Novelty is one of the criteria for selection.
  • The participant can be from anywhere in the world, but must be an ACM student member, and must maintain an undergraduate or graduate student status as of the abstract deadline. Please indicate whether you are an undergraduate or graduate student. You may join ACM prior to entering. Basic student membership is $19 per year or less:
  • The other eligibility requirements are mentioned here:
  • The content of the SRC poster can be included in a future submission to other conferences or journals.

Abstract Submission
Submissions to the PACT 2021 ACM Student Research Competition (SRC) must be submitted electronically at this SRC Submission site

  • The submission should be in pdf format. Blind submissions are fine, but not required.
  • Submissions should not exceed 1 page, and should not exceed 800 words. Figures and References are fine and must fit within the single page.
  • You may use the templates provided here:
  • Please also note that all students whose abstracts are accepted are expected to attend PACT 2021 and present a poster of their work, and present it in a PACT session if selected from the poster session.

All questions about submissions should be emailed to PACT 2021 ACM SRC Chair Changhee Jung (chjung -at-

Call for Presentations: ModSim 2021
Submitted by Jason Lowe-Power

Workshop on Modeling & Simulation of Systems and Applications (ModSim) 2021
August 11-13, 2021, University of Washington Botanic Gardens
Center for Urban Horticulture, Seattle

Submissions Due: May 10, 2021

Workshop URL:
Submission URL:
EasyChair Submission Deadline: Sunday, May 10, 2021 (11:59 PM, Pacific Daylight Time [PDT])
Notification of Acceptance: Friday, June 04, 2021 (via e-mail)

To promote advancements in modeling and simulation (ModSim) research, we are soliciting community input in the form of abstracts. If accepted, author(s) will be invited to offer a poster and short presentation at the annual gathering of our community, the ModSim 2021 Workshop.

The overarching theme for this year’s workshop is “Modeling and Simulation in the Artificial Intelligence Era.” The emphasis will be on AI-driven methodologies, tools, best practices, projects, and initiatives that aim to address the challenges and achieve the goal of modeling performance, power, and reliability of high-performance systems under a realistic application workload.

Abstract Submission Guidelines
There is no set word limit for abstract submissions. However, please limit your submission to one page. The abstract should provide an overview that adequately summarizes the topic(s) presented and any proposed impact on ModSim research or techniques, especially related to modeling and simulation in the era of artificial intelligence. The following details a proposed abstract layout and points to consider:

Abstract Title
Primary research area:

– Artificial Intelligence and Machine Learning Workloads and Systems
– Modeling and Simulation of Subsystems via Artificial Intelligence and Machine Learning
– Advances in ModSim Implementation

What is being modeled? (e.g., performance, reliability, power, other)
What is the target application?
What modeling techniques are being used?
What is novel about the approach versus current state of the art?
Are preliminary results available?

All abstracts must be submitted through EasyChair ( no later than Sunday May 02, 2021 (11:59 PM, PDT). Those with accepted abstracts will be notified via e-mail on Friday, June 04, 2021

Dr. Sudhakar Yalamanchili Award
Submissions will be eligible for the Dr. Sudhakar Yalamanchili Award, which is intended to recognize young researchers for their outstanding contribution to the field of performance modeling and simulation. Presenters, who must be a graduate student or postdoctoral researcher (within six years of highest awarded degree), will be evaluated during the Contributed Presentation/Poster Session at the ModSim 2021 Workshop. Learn more at

Topic Areas

Abstract contributions should focus on the following topical areas of interest:

Artificial Intelligence and Machine Learning Workloads and Systems. AI, in general, and Machine Learning (ML), in particular, are important drivers to all forms of computing, including large-scale data- and numerically intensive high-performance computing (HPC). Consequently, systems designed for AI/ML workloads are critically important. Abstracts in this category should offer novel approaches for AI and ML workloads, ModSim for AI/ML architectures, and other approaches (e.g., intelligent computational steering driven by dynamic and offline learning).

Methodologies and Tools. AI and ML are not only revolutionizing applications, but these techniques also have the potential to revolutionize the way that HPC systems are designed. This abstract category solicits submissions that adopt AI/ML techniques in system design, such as predictive models of performance, power, or cost; approaches that intelligently explore and recommend designs; and techniques that optimize individual subsystems, across system layers, or the whole system with AI/ML. Abstracts should highlight how to advance the state of the art, as well as expectations for impacting future directions in this area.

Recent Advances in ModSim Implementation. The rapidly increasing complexity of systems and application workloads–along with the blending of compute, memory devices, storage, and interconnect then further combined with application software–translates into unprecedented challenges within the ModSim field. Submissions in this category, not necessarily related to AI/ML, are expected to highlight recent developments that can help overcome these significant challenges. Possible topics include, but are not limited to, novel ModSim methodologies, emerging areas of research and development, new projects or advances in existing efforts, and new applications of ModSim tools to real-life problems.

Call for Workshops/Tutorials: MICRO 2021
Submitted by Dimitrios Skarlatos

IEEE/ACM MICRO-54 Call for Workshops & Tutorial
Athens, October 16-17, 2021

Submission Deadline: June 10, 2021

The International Symposium on Microarchitecture® (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers—we aim to continue and strengthen this longstanding tradition at the 54th MICRO in Athens, Greece.


Important dates

Submission Deadline: June 10, 2021

Notification: June 30, 2021

Workshops/Tutorials days: October 16-17, 2021


We invite proposals for workshops and tutorials to be held on Saturday 16 and Sunday 17 October, 2021, before the main symposium days of 18-20 October, 2021.

Proposals should be one to two pages long and must include the following information:

  • Title of the Workshop/Tutorial
  • Organizers and their affiliations (including short bios)
  • Expected duration of the workshop/tutorial, i.e., half day or full day
  • If the workshop/tutorial was previously held, provide the location (i.e., which conference), date, number of published papers (if any), and number of attendees at the last event
  • Provide a sample call for papers and workshop main topics (for a workshop proposal)
  • Provide the abstract of the tutorial (for a tutorial proposal)

Proposals should highlight a plan for ensuring diversity in invited speakers, tutorial presenters, and organizing and selection committees (if applicable).

Submit workshop and tutorial proposals (1 to 2 pages) to: and


Workshop/Tutorials Co-Chairs:

Lisa Wu Wills and Dionisios Pnevmatikatos

New Book: Robotic Computing on FPGAs
Submitted by Brent Beckley

Morgan & Claypool is proud to announce a new book published in our Computer Architecture series (Series Editor: Natalie Enright Jerger, University of Toronto).

Robotic Computing on FPGAs
Shaoshan Liu, PerceptIn
Zishen Wan, Georgia Institute of Technology
Bo Yu, PerceptIn
Yu Wang, Tsinghua University
ISBN: 9781636391656 | PDF ISBN: 9781636391663 | Hardcover ISBN: 9781636391670
Copyright © 2021 | 218 Pages
DOI: 10.2200/S01101ED1V01Y202105CAC056
Retail Bookstore:

This book provides a thorough overview of the state-of-the-art field-programmable gate array (FPGA)-based robotic computing accelerator designs and summarizes their adopted optimized techniques. This book consists of ten chapters, delving into the details of how FPGAs have been utilized in robotic perception, localization, planning, and multi-robot collaboration tasks. In addition to individual robotic tasks, this book provides detailed descriptions of how FPGAs have been used in robotic products, including commercial autonomous vehicles and space exploration robots.

Episode 5 of Computer Architecture Podcast Released! Featuring guest Prof. Christina Delimitrou
Submitted by Suvinay Subramanian

Computer Architecture Podcast: A series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.

Announcing the release of Episode 5: Datacenter Architectures and Cloud Microservices with Dr. Christina Delimitrou, an assistant professor in the Electrical and Computer Engineering Department at Cornell University. Prof. Delimitrou has made significant contributions to improving resource efficiency of large-scale datacenters, QoS-aware scheduling and resource management techniques, performance debugging, and cloud security. She received the 2020 IEEE TCCA Young Architect Award for leading research in ML-driven management and design of cloud systems. She talks to us about datacenter architectures, cloud microservices, and applying machine learning techniques to optimizing and managing these systems.

Listen to the episode at Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Samira Khan
SIGARCH Content Editor