This is the 1st May 2022 digest of SIGARCH Messages.

In This Issue

Call for Participation: ISA to ILA: Tutorial at ISCA 2022
Submitted by Sharad Malik

Generalizing the ISA to the ILA
A Software/Hardware Interface for Accelerator-rich Platforms

The Instruction-Set Architecture (ISA) has long served as the software/hardware interface for programmable processors. The ISA simultaneously serves as a specification for the hardware implementation and as an abstraction of the hardware for software development. Over the years, this interface has enabled independent development of the hardware and software. This has enabled ISA-compliant hardware upgrades and portability of software applications. With the advent of multiprocessors, the memory consistency model (MCM) provided the software/hardware interface for processor interactions through shared memory. As with the ISA, the MCM serves both as the specification for the hardware and its abstraction for software. We are now in an era where accelerator-rich platforms are widely used to deliver the power-performance requirements of emerging applications. Unfortunately, there is no widely accepted software/hardware interface for these platforms – this has implications for both hardware and software development. The accelerator specifications are typically informal, with the possible availability of executable reference models (C/C++/SystemC). The software development largely depends on APIs providing platform-specific hardware functions calls for utilizing the hardware specialization – similar to how peripheral devices are accessed. This results in software that is not portable across platforms or optimizable using standard compiler flows.

The recently developed Instruction-Level Abstraction (ILA) provides a software/hardware interface that generalizes the notion of ISAs to accelerators. The ILA model of an accelerator is a functional model that defines the response of the accelerator to commands at its interface. These commands serve as “instructions” for the accelerator. These commands are generally memory-mapped input-output (MMIO) instructions issued by a host processor – thus, there is a one-to-one mapping of these MMIO instructions and ILA instructions of the accelerator. As with the ISA, the ILA defines the architectural state of the accelerator as the state that is persistent across instructions. Again, as with the ISA, the ILA is a modular specification that defines how this architectural state is updated by each instruction. Further, the ILA-MCM model shows how the operational ILA model can be integrated with an axiomatic memory consistency model for a detailed functional specification that includes accelerator-processor interactions through shared memory.

Tentative Schedule
In this tutorial we will introduce the ILA model and its application to the different use cases for accelerator-rich platform highlighted above.

  • 1:00 – 1:10 PM: Software/Hardware Interfaces
    Review existing software/hardware interfaces used for accelerator-rich platforms and evaluate their strengths and weaknesses.
  • 1:10 – 1:40 PM: ILA Models
    Formally define the ILA model including the instructions, architectural state and per-instruction state update functions – this makes the model amenable to formal analysis tools.
  • 1:45 – 2:10 PM: Simulation and Co-simulation
    Show how the ILA model enables automated generation of executable functional models (C++/SystemC) that can be used in hardware simulation and hardware-software co-simulation.
  • 2:15 – 2:35 PM: Formal Hardware Verification
    Show how the formal ILA model can be used for formal verification of the hardware implementation and hardware-software co-verification.
  • 2:40 – 3:10 PM: Memory Consistency
    Show how the ILA-MCM model can be used to reason about correctness of code executing across processors and accelerators for a given MCM.
  • 3:15 – 4:00 PM: Compilation to Accelerators
    Show how the ILA instructions can be used in a compiler flow targeting specialized accelerators – in particular a compiler flow for deep-learning accelerators using the TVM compiler framework.



  • Sharad Malik (Princeton University)
  • Aarti Gupta (Princeton University)
  • Bo-Yuan Huang (Intel Corporation)

Call for Participation: ISPASS 2022 Tutorials
Submitted by Burin Amornpaisannon

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research focused on performance analysis in the design of computer systems and software. ISPASS 2022 will be held on May 22-24, 2022 as a Hybrid Event in Singapore.

ISPASS 2022 will be hosting tutorials at the conference venue on May 22, 2022. The purpose of these gatherings is to provide a forum for exchanging ideas and preliminary results of topics that are related to ISPASS in an interactive environment. The tutorials consist of two half-day sessions that introduce tools and techniques in computer architecture simulation and hardware security. The topics and abstracts of the tutorials are available in the computer architecture simulation tutorial website and hardware security tutorial website.

Important Dates
– Early registration deadline: May 6, 2022
– Tutorial date: May 22, 2022

Call for Participation: FCCM’22 Call for Participation (Early Registration by May 1)
Submitted by Callie Hao

Call for Participation: The 30th IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM)
May 15–18, 2022 | New York City | Hybrid Event

The IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware.

Conference Information

Keynote, Program, and Workshop & Tutorials

  • Keynote: Intel FPGAs for Programmable, Accelerated Infrastructure and Applications for the Modern Data Center
    • Jim Dworkin, Intel Corporation, Vice President & General Manager, Cloud & Enterprise Acceleration Division, Programmable Solutions Group, Data Center & AI Group, Intel Corporation
  • Technical program: We have two days of long and short paper presentations on tools, machine learning, architectures, and applications. Two poster sessions and a set of demos covering a variety of topics. We also have nine tutorials and workshops covering hot topics such as open-source tools, programming languages, and processors. For more details, see

— May 15 (Sunday) —

  • Tutorial: Introduction to Vitis AI development Tools Flow
  • Tutorial: OpenFPGA: The Open Source Revolution Comes to FPGAs
  • Tutorial: Hands-On Tutorial: Introduction to oneAPI with Intel FPGAs

— May 16 (Monday) —

  • Session 1 – Tools
  • Session 2 – Architecture
  • Session 3 – Applications 1
  • Reception + Demo Night

— May 17 (Tuesday) —

  • Session 4 – Machine Learning
  • Session 5 – Security and Crypto
  • Session 6 – Applications 2

— May 18 (Wednesday) —

  • Workshop: First Workshop on Formal Methods In High-Level Synthesis
  • Tutorial: TAPA: High-Performance Customization-Friendly HLS Framework
  • Workshop: Workshop on Security for Custom Computing
  • Tutorial: Hardware Description Languages: Past, Present, and Future
  • Tutorial: CFU-Playground: Build Your Own Custom TinyML Processor
  • Tutorial: Nios V: RISC-V Based Processors for Intel FPGAs

Demo Night: The Demo Night is an opportunity for people to show off their latest and greatest systems, tools, and technologies in a relaxed atmosphere. See the latest technology from industry, meet with the leading FCCM researchers, demonstrate your latest work, and receive early feedback on their work in progress.

Organization Committee

  • General Chair: Zhiru Zhang (Cornell University)
  • Program Chair: Eriko Nurvitadhi (Intel)
  • Publication Chair: Gabriel Weisz (Microsoft)
  • Finance Chair: Andrew Schmidt (University of Southern California ISI)
  • Hybridization Chairs: Ron Sass (UNCC), Peipei Zhou (University of Pittsburgh)
  • Sponsorship Chair: Lana Josipovic (ETH), Guojie Luo (Peking University)
  • Workshop Chairs: Yun (Eric) Liang (Peking University), Zhenman Fang (SFU)
  • Travel Awards Chair: Zhenman Fang (SFU)
  • Publicity and Website Chair: Cong (Callie) Hao (Georgia Tech)
  • Expo and Demo-Night Chair: Grace Zgheib (Intel)
  • Local Arrangement Chair: Mohamed Abdelfattah (Cornell Tech), Debjit Pal (Cornell)

Call for Participation: ISCA 2022
Submitted by Zehra Sura

The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and research results in computer architecture.

The 49th edition of ISCA has been pushed back a week from its original dates, and will now be held June 18-22 in New York City. This year, the conference is being held in-person, with a provision for  remote attendance for those who cannot make it in-person.

Registration for the conference is now open at:
Early registration deadline is May 20, 2022.

Workshop and tutorial details are available at:

For more details, please visit the main conference website at:

Call for Papers: ARITH 2022
Submitted by Florent de Dinechin

29th IEEE International Symposium on Computer Arithmetic (ARITH 2022)
September 12-14, 2022 (virtual conference)

Call for conference papers — Abstract deadline April 17, 2022

Computer arithmetic has always been at the core of the digital age, and is currently driving innovation in domains such as artificial intelligence, high-performance computing, signal processing, and security.

Since 1969, the ARITH symposia have served as the premier conference for presenting the latest research in computer arithmetic.
Due to the uncertainty of the world health situation and travel restrictions, the 29th edition of the symposium, ARITH 2022, will be a virtual conference with live presentation of research results, keynote talks, and panels.

ARITH 2022 welcomes submissions of conference papers (less than 8 pages in the IEEE CS Conference format) describing recent scientific advances related to computer arithmetic.
Accepted papers will be included in the conference proceedings and in the IEEE Xplore Digital Library.

Topics of interest include, but are not restricted to:

  • Foundations of computer arithmetic: emerging number systems and their applications, novel arithmetic algorithms, their analysis and applications.
  • Efficient, low-power, or high-performance novel implementations of computer arithmetic in software and hardware: integer or floating-point operations, elementary and special functions, multiple-precision computing, interval arithmetic, finite field arithmetic, etc.
  • Novel floating-point algorithms, properties of floating-point arithmetic in emerging domains and applications.
  • Computer arithmetic in emerging standards, high-level languages, and compilers.
  • Test, verification, formal proof, computer aided design (CAD) automation and fault/error-tolerance for computer arithmetic.
  • New arithmetic paradigms, architectures and implementations for emerging technologies, for FPGAs or configurable logic, and for non-conventional computing systems.
  • New arithmetic paradigms and architectures for specific application domains such as cryptography, security, Internet-of-Things, neural networks, deep learning, signal processing, computer graphics, multimedia, computer vision, high-performance computing, finance, etc., and emerging application domains.
  • Inexact and stochastic arithmetic algorithms, architectures and applications.

Important Dates

Abstract submission deadline: April 17, 2022
Paper submission deadline: April 24, 2022
Reviews sent to authors: June 20, 2022
Review rebuttal deadline: June 23, 2022
Authors notified: June 28, 2022
Camera ready and copyright due: July 17, 2022

Detailed submission procedure available at

General chair: Florent de Dinechin, INSA Lyon
Program co-chairs:
Stuart Oberman, Nvidia
Bogdan Pasca, Intel
Leonel Sousa, IST/U Lisbon

Call for Papers: PAW-ATM: Parallel Applications Workshop, Alternatives To MPI+X
Submitted by Karla Morris

Call for Papers
PAW-ATM 2022: Parallel Applications Workshop, Alternatives To MPI+X
Held in conjunction with SC22, Dallas, TX
As supercomputers become more and more powerful, the number and diversity of applications that can be tackled with these machines grows. Unfortunately, the architectural complexity of these supercomputers grows as well, with heterogeneous processors, multiple levels of memory hierarchy, and many ways to move data and synchronize between processors. The MPI+X programming model, use of which is considered by many to be standard practice, demands that a programmer be expert in both the application domain and the low-level details of the architecture(s) on which that application will be deployed, and the availability of such superhuman programmers is a critical bottleneck. Things become more complicated when evolution and change in the underlying architecture translates into significant re-engineering of the MPI+X code to maintain performance.
Numerous alternatives to the MPI+X model exist, and by raising the level of abstraction on the application domain and/or the target architecture, they offer the ability for “mere mortal” programmers to take advantage of the supercomputing resources that are available to advance science and tackle urgent real-world problems. However, compared to the MPI+X approach, these alternatives generally lack two things. First, they aren’t as well known as MPI+X and a domain scientist may simply not be aware of models that are a good fit to their domain. Second, they are less mature than MPI+X and likely have more functionality or performance “potholes” that need only to be identified to be addressed.
PAW-ATM is a forum for discussing HPC applications written in alternatives to MPI+X.  Its goal is to bring together application experts and proponents of high-level languages to present concrete example uses of such alternatives, describing their benefits and challenges.
Scope and Aims
The PAW-ATM workshop is designed to be a forum for discussion of supercomputing-scale parallel applications and their implementation in programming models outside of the dominant MPI+X paradigm. Papers and talks will explore the benefits (or perhaps drawbacks) of implementing specific applications with alternatives to MPI+X, whether those benefits are in performance, scalability, productivity, or some other metric important to that application domain. Presenters are encouraged to generalize the experience with their application to other domains in science and engineering and to bring up specific areas of improvement for the model(s) used in the implementation.
In doing so, our hope is to create a setting in which application authors, language designers, and architects can present and discuss the state of the art in alternative scalable programming models while also wrestling with how to increase their effectiveness and adoption. Beyond well-established HPC scientific simulations, we also encourage submissions exploring artificial intelligence, big data analytics, machine learning, and other emerging application areas.
Topics of interest include, but are not limited to:
  • Novel application development using high-level parallel programming languages and frameworks.
  • Examples that demonstrate performance, compiler optimization, error checking, and reduced software complexity.
  • Applications from artificial intelligence, data analytics, bioinformatics, and other novel areas.
  • Performance evaluation of applications developed using alternatives to MPI+X and comparisons to standard programming models.
  • Novel algorithms enabled by high-level parallel abstractions.
  • Experience with the use of new compilers and runtime environments.
  • Libraries using or supporting alternatives to MPI+X.
  • Benefits of hardware abstraction and data locality on algorithm implementation.
Papers that include description of applications that demonstrate the use of alternative programming models will be given higher priority.
Submissions are solicited in 3 categories:
  1. Full-length papers presenting novel research results: Full-length papers will be published in the workshop proceedings. Submitted papers must describe original work that has not appeared in, nor is under consideration for, another conference or journal. Papers shall be eight (8) pages minimum and not exceed ten (10) including text, appendices, and figures.
  2. Extended abstracts summarizing preliminary/published results: Extended abstracts will be evaluated separately and will not be included in the published proceedings; they are intended to propose timely communications of novel work that will be formally submitted elsewhere at a later stage, and/or of already published work that would be of interest to the PAW-ATM audience in terms of topic and timeliness.  Extended abstracts shall not exceed four (4) pages.
  3. Pictures or videos showcasing results from parallel applications: In addition to the manuscript submissions categories described above, authors have the option to submit pictures or videos of the results obtained with their parallel applications. This submission category should include pictures or video files and 250 words abstract, describing the application. These will be considered for PAW-ATM Best Visual Effects Award.
When deciding between manuscript submissions with similar merit, submissions whose focus relates more directly to the key themes of the workshop (application studies, computing at scale, high-level alternatives to MPI+X) will be given priority over those that don’t.
Submissions shall be submitted through Linklings:
Submissions must use 10pt font in the IEEE format:
PAW-ATM follows the reproducibility initiative of SC22.  Submissions must include Artifact Description (AD) and Artifact Evaluation (AE) appendix. The appendix pages related to the reproducibility initiative dependencies, are not included in the page count. For more information, please refer to:
Workshop Chair
  • Karla Morris – Sandia National Laboratories
Organizing Committee
  • Irene Moulitsas – Cranfield University
  • Elliott Slaughter – SLAC National Accelerator Laboratory
  • Michael Ferguson – Hewlett Packard Enterprise
Program Committee Co-chairs
  • Bill Long – Hewlett Packard Enterprise
  • Daniele Lezzi – Barcelona Supercomputing Center
Program Committee
  • David Bunde – Knox College
  • Barbara Chapman – Hewlett Packard Enterprise and Stony Brook University
  • Lúcia María de Assumpcao Drummond – Universidade Federal Fluminense
  • Sally Ellingson – University of Kentucky
  • Michael Ferguson – Hewlett Packard Enterprise
  • Salvatore Filippone – Università di Roma Tor Vergata
  • Dounia Khaldi – Intel
  • Eric Laurendeau – Polytechnique Montreal
  • Daniele Lezzi – Barcelona Supercomputing Center
  • Laércio Lima Pilla – National Center for Scientific Research and University of Bordeaux
  • Bill Long – Hewlett Packard Enterprise
  • Francesc Lordan – Barcelona Supercomputing Center
  • Esteban Meneses Rojas – National High Technology Center
  • Karla Morris – Sandia National Laboratories
  • Irene Moulitsas – Cranfield University
  • Swaroop S. Pophale – Oak Ridge National Laboratory
  • Mitsuhisa Sato – RIKEN Advanced Institute for Computational Science
  • Christine Sweeney – Los Alamos National Laboratory
  • Elliott Slaughter – SLAC National Accelerator Laboratory
  • Kenjiro Taura – University of Tokyo
  • Sean Treichler – NVIDIA
  • Richard W Vuduc – Georgia Institute of Technology
Advisory Committee
  • Bradford L. Chamberlain – Hewlett Packard Enterprise
  • Damian W. I. Rouson – Sourcery Institute
  • Katherine A. Yelick – Lawrence Berkeley National Laboratory
Important Dates
  • Submissions deadline: July 29, 2022
  • Manuscripts review period: August 8-25, 2022 (including Rebuttal)
  • Rebuttal submission: August 26, 2022
  • Building consensus: August 29 – September 2, 2022
  • Notification to authors: September 9, 2022
  • Final program: September 30, 2022
  • Camera-ready papers due from authors: October 1, 2022
  • PAW-ATM Workshop at SC22: November 13-18, 2022

Call for Papers: HotSpots Strike Back Workshop at ISCA
Submitted by Mark Hempstead

HSSB: HotSpots Strike Back: Call For Papers
June 19th, 2022 New York City
At ISCA 2022: 

On-chip thermal hotspots are becoming one of the primary design concerns for next-generation processors. Industry chip design trends coupled with post-Dennard power density have led to a stark increase in localized and application-dependent hotspots. These “advanced” hotspots cause a variety of adverse effects if untreated, ranging from dramatic performance loss, incorrect circuit operation, and reduced device lifespan. In the past, hotspots could be addressed with physical cooling systems and EDA tools; however, the severity of advanced hotspots is prohibitively high for conventional thermal regulation techniques alone. Cross stack approaches that incorporate device, circuit, packaging, cooling, architecture, and software are needed.

HSSB: HotSpots Strike Back: seeks papers that study next-generation advanced on-chip thermal hotspots. Position papers and work-in-progress papers are encouraged. The organizers are interested in presenting a diversity of fields and approaches to thermal on-chip hotspots. 

List of Potential Topics

  • Packaging and system cooling approaches to hotspot mitigation
  • Data and retrospective studies characterizing hotspot behavior in simulation or silicon
  • Device, circuit, architecture studies that illustrate the challenges of hotspots and their impact on chip’s performance, cost, and reliability 
  • Tools (at the transistor, chip, package, and system abstractions) that characterize or model hotspot behavior
  • Hotspot aware predictions or mitigations at the circuit, architecture, or software level
  • Design automation (EDA) approaches to hotspot prediction and mitigation

Submission and Presentation Format

An abstract of at most 2 pages should be submitted that describes the problem, the study or the design to be presented at the workshop. The presentation format will include a 15-30 minute presentation. In addition, all speakers will be invited to join a panel discussion at the end of their session where questions from the audience and debate among panelists will be encouraged. 

Submit your abstract hereL 

Important Dates

Submission Due Date: May 1, 2022
Author Notification: May 8, 2022
Final Abstract Due Date: May 29, 2022
Workshop: Sunday, June 19th (morning session)

Workshop Organizers

  • Mark Hempstead (Tufts University)
  • Alexander Hankin (Harvard University / Tufts University)
  • Julien Sebot (Intel)
  • Kaushik Vaidyanathan (Google)
  • David Werner (Tufts University)

Call for Papers: Workshop on Accelerated Machine Learning (AccML) at HiPEAC 2022
Submitted by José Cano

4th Workshop on Accelerated Machine Learning (AccML)
Co-located with the HiPEAC 2022 Conference
June 22, 2022
Budapest, Hungary

The remarkable performance achieved in a variety of application areas (natural language processing, computer vision, games, etc.) has led to the emergence of heterogeneous architectures to accelerate machine learning workloads. In parallel, production deployment, model complexity and diversity pushed for higher productivity systems, more powerful programming abstractions, software and system architectures, dedicated runtime systems and numerical libraries, deployment and analysis tools. Deep learning models are generally memory and computationally intensive, for both training and inference. Accelerating these operations has obvious advantages, first by reducing the energy consumption (e.g. in data centers), and secondly, making these models usable on smaller devices at the edge of the Internet. In addition, while convolutional neural networks have motivated much of this effort, numerous applications and models involve a wider variety of operations, network architectures, and data processing. These applications and models permanently challenge computer architecture, the system stack, and programming abstractions. The high level of interest in these areas calls for a dedicated forum to discuss emerging acceleration techniques and computation paradigms for machine learning algorithms, as well as the applications of machine learning to the construction of such systems.


Topics of interest include (but are not limited to):

  • Novel ML systems: heterogeneous multi/many-core systems, GPUs, FPGAs;
  • Software ML acceleration: languages, primitives, libraries, compilers and frameworks;
  • Novel ML hardware accelerators and associated software;
  • Emerging semiconductor technologies with applications to ML hardware acceleration;
  • ML for the construction and tuning of systems;
  • Cloud and edge ML computing: hardware and software to accelerate training and inference;
  • Computing systems research addressing the privacy and security of ML-dominated systems.

Papers will be reviewed by the workshop’s technical program committee according to criteria regarding the submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions in the context of accelerating machine learning. Research papers, case studies, and position papers are all welcome.

In particular, we encourage authors to submit work-in-progress papers: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and spark productive discussions.

Important Dates
Submission deadline: April 15, 2022
Notification of decision: April 30, 202

José Cano (University of Glasgow)
Valentin Radu (University of Sheffield)
José L. Abellán (Catholic University of Murcia)
Marco Cornero (DeepMind)
Albert Cohen (Google)
Dominik Grewe (DeepMind)

Call for Papers: Accelerator Architecture in Computational Biology and Bioinformatics Workshop (AACBB-2022)
Submitted by Leonid Yavits

4th Accelerator Architecture in Computational Biology and Bioinformatics workshop (AACBB-2022)
June 18th 2022
In conjunction with 49th IEEE International Symposium on Computer Architecture
New York City, New York, USA

Workshop website:

Important dates
Submission link:
Submission deadline: April 20, 2022, EoD AoE
Notifications: May 5, 2022

Over the last decade, the advent of high-throughput sequencing techniques brought an exponential growth in sequenced data.At the same time, the single-thread performance continued to improve by only a few percent point annually. The growing gap between the performance demand to performance supply became a significant challenge in the path to scientific discovery. The computational bottleneck of genome analysis pipelines became even more apparent during the ongoing Covid-19 pandemic, where fast and reliable virus detection and classification tools have been critical for the worldwide genomic surveillance system.

The gap between the performance of a conventional computer architecture and the biological data processing requirements is growing. For example, assembling a human genome from 3rd generation sequenced data may require hundreds of CPU hours. Hence, computational biology and bioinformatics will have to rely on hardware accelerators to allow processing to keep up with the exploding amount of sequenced data.

In a typical application, the dominant portion of the runtime is spent in a small number of computational kernels, making it an excellent target for hardware acceleration. The combination of increasingly large datasets and high performance computing requirements make computational biology a prime candidate to benefit from accelerator architecture research. Potential directions include 3D integration, near-data processing, in-data processing and reconfigurable architectures.

This workshop will focus on architecture and design of hardware accelerators for computational biology and bioinformatics problems. We plan to present and discuss a variety of acceleration techniques, accelerator architectures and their implications on the development of computational biology. This year, we plan to extend the industry angle, by providing a keynote and invited talks from leading industry research specialists.

List of Topics
This workshop focuses on architecture and design of hardware and software accelerators for computational biology and bioinformatics problems. Topics of interest include, but are not limited to the following:

Hardware and software algorithms/applications in the fields of computational biology, such as (but not limited to):

  • Bioinformatics
  • Genomics
  • Proteomics
  • Protein structure prediction
  • Covid-19 pandemic

Bioinformatics and computational biology accelerator architecture and design based on (but not limited to):

  • 3D memory-logic stack
  • Near-data (in-memory) processing
  • In-data processing
  • FPGAs
  • Reconfigurable architectures
  • Emerging memory technologies and their impact on bioinformatics and computational biology
  • Impact of bioinformatics and biology applications on computer architecture research
  • Bioinformatics and computational biology-inspired hardware/software trade-offs

Keynote Speakers

  • Tajana Rosing, Prof of Computer Science and Engineering, director of System Energy Efficiency Lab, UCSD
  • Onur Mutlu, Prof of Computer Science, Zurich ETH and CMU


Program Committee

  • Ananth Kalyanaraman, WSU
  • Can Alkan, Bilkent University
  • Engin Ipek, University of Rochester
  • Jason Cong, UCLA
  • Mattan Erez, UT Austin
  • Mircea Stan, UVA
  • Onur Mutlu, ETH/CMU
  • Ran Ginosar, Technion
  • Ronnie Ronen, Technion
  • Yuan Xie, UCSB

Organizing committee

* Department of Engineering, Bar Ilan University
^ Department of Electrical and Computer Engineering, University of California, San Diego

Important Notes
Presenting a paper in the workshop does not preclude publication in other venues

All questions about submissions should be emailed to Leonid Yavits (

Call for Workshops/Tutorials: FPL 2022
Submitted by Zhenman Fang

The 32nd International Conference on Field-Programmable Logic and Applications (FPL)
Aug 29 to Sep 2, 2022 @ Belfast, Northern Ireland, UK

Submissions due: 1st June 2022

The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest covering the rapidly growing area of field-programmable logic and reconfigurable computing. Field-programmable devices promise the flexibility of software with the  performance of hardware and have become an important area of research and development in high-performance computing systems, embedded and low-power control instruments, mobile communications, rapid prototyping and product emulation, among other areas. For the last 31 years, FPL has seen the first unveiling of the latest and most significant works in reconfigurable architectures, applications, embedded processors and design automation. FPL2022 will bring together academic and industrial researchers and practitioners from across the globe. It will offer a hybrid format, with the entire conference accessible both in-person and online.

FPL will be pleased to host in-person, hybrid or fully-virtual workshops and tutorials on Thursday, September 1 and Friday, September 2. We would be delighted to receive proposals for workshops, tutorials and special sessions to be held at FPL 2022.

These events provide excellent opportunities to bring together researchers and practitioners from different communities to share their experiences in an interactive atmosphere, and to foster collaboration for new and innovative projects. Proposals may be for successors of events that have been held in previous years, or for brand new events this year. Proposals should be submitted through the EasyChair submission system.

Suitable topics for event proposals include (but are not limited to):

  • Tools and Design Techniques: placement, routing, synthesis, verification, debugging, runtime support, technology mapping, partitioning, parallelization, timing optimization, design and run-time  environments, high-level synthesis (HLS) compilers, languages and modeling techniques, provably-correct development, intellectual property core-based design, domain-specific development, hardware/software co-design.
  • Architectures for field-programmable technology: field-programmable gate arrays, complex programmable logic devices, coarse-grained reconfigurable arrays, field-programmable interconnect, field-programmable analogue arrays, field-programmable arithmetic arrays, memory architectures, interface technologies, low-power techniques, adaptive devices, reconfigurable computing systems, high-performance reconfigurable systems, evolvable hardware and adaptive computing, fault tolerance and avoidance.
  • Device technology: including programmable memories such as non-volatile, dynamic and static memory cells and arrays, interconnect devices, circuits and switches, and emerging VLSI device technologies.
  • Applications: accelerators for biomedical/scientific/neuro-morphic computing and machine learning, network processors, real-time systems, rapid prototyping, hardware emulation, digital signal processing, interactive multimedia, machine vision, computer graphics, cryptography, robotics, manufacturing systems, embedded applications, evolvable and biologically-inspired hardware.
  • Education: courses, teaching and training experience, experiment equipment, design and applications.

For inspiration, you might like to consult the list of workshops and tutorials that were held at FPL last year:

If you would like to propose an event, please prepare a 2-page proposal that includes:

  1. Title of the proposed event
  2. Preferred date
  3. Preferred mode (face-to-face, fully virtual, or hybrid)
  4. Preferred duration (half-day or full-day) and tentative schedule
  5. Any resources required (e.g. “a room with wifi”, “a computer lab”)
  6. Names, affiliations, and contact information for event organiser(s)
  7. Short biography of the organiser(s)
  8. Scope and topics of the event
  9. Rationale: why is the topic timely and important? Why would it be of interest to FPL attendees?
  10. Names of potential speakers at the event

If you are proposing a hybrid event, please also briefly explain how you plan to ensure that virtual participants are involved. To help with this, workshop organisers will have access to the same web-based hybrid-conference platform as the main conference.

Submissions will be considered on first-come, first-serve basis. To allow sufficient time for organisation we request proposals by June 1st, as a single PDF file through the EasyChair submission system.

You are welcome to contact FPL 2022 Workshop chairs through the below email addresses for informal queries.

FPL Steering Committee
Patrick Lysaght (Xilinx), Chairman
Jürgen Becker (Karlsruhe Institute of Technology)
Koen Bertels (University of Porto)
Eduardo Boemo (Universidad Autónoma de Madrid)
João M. P. Cardoso (Universidade do Porto)
Peter Y. K. Cheung (Imperial College London)
Martin Danek (Daiteq)
Apostolos Dollas (Technical University of Crete)
Fabrizio Ferrandi (Politecnico di Milano)
Manfred Glesner (Technische Universität Darmstadt)
Diana Goehringer  (Technische Universität  Dresden)
Reiner Hartenstein (Technische Universität Kaiserslautern)
Andreas Herkersdorf (Technische Universität München)
Paolo Ienne (EPFL)
Udo Kebschull (Goethe Universität Frankfurt)
Wayne Luk (Imperial College London)
Xavier Martorell(Universitat Politècnica de Catalunya & Barcelona Supercomputing Center)
Jari Nurmi (Tampere University of Technology)
Ioannis Sourdis (Chalmers University of Technology)
Dirk Stroobandt (University of Ghent)
Lionel Torres (Université Montpellier 2)
Jim Tørresen (Universitetet i Oslo)

FPL’22 General Chairs
John McAllister, Queen’s University of Belfast, UK
Roger Woods, Queen’s University of Belfast, UK

FPL’22 Workshops & Tutorials Chairs
Chongyan Gu, Queen’s University of Belfast, UK
John Wickerson, Imperial College London, UK

Call for Posters: FPL 2022
Submitted by Zhenman Fang

FPL 2022 CALL FOR PhD Forum/Demo Night
The 32nd International Conference on Field-Programmable Logic and Applications (FPL)
Aug 29 to Sep 2, 2022 @ Belfast, Northern Ireland, UK

Submission deadline: June 01, 2022
Notification: June 15th 2022
Camera-Ready Deadline: June 27th 2022

The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest covering the rapidly growing area of field-programmable logic and reconfigurable computing. Field-programmable devices promise the flexibility of software with the performance of hardware and have become an important area of research and development in high-performance computing systems, embedded and low-power control instruments, mobile communications, rapid prototyping and product emulation, among other areas. For the last 31 years, FPL has seen the first unveiling of the latest and most significant works in reconfigurable architectures, applications, embedded processors and design automation. FPL2022 will bring together academic and industrial researchers and practitioners from across the globe. It will offer a hybrid format, with the entire conference accessible both in-person and online.

The FPL 2022 PhD Forum is an excellent occasion for PhD students to present their work in progress or preliminary results, and receive early feedback from senior researchers and experts in the domain. Moreover, it is a unique opportunity for PhD students, whether fresh or close to completion, to give a broad overview of their work and draw attention to it from both the academic and industrial worlds.

PhD Forum authors are invited to submit 2-page papers using the same format as FPL 2022 regular papers before the deadline of June 1st, 2022 through the EasyChair submission system:

PhD Forum papers should include clear descriptions of the project’s motivation, objectives, problem definition, addressed solutions, current status, and planned work if applicable. Contributions based on preliminary results or on work in progress are particularly encouraged. Accepted PhD Forum papers require a registration for being included in the conference proceedings and will be presented at a special poster session in conjunction with the FPL Demo Night. Therefore, PhD forum presenters can optionally provide a demo along with the poster presentation. Prior to the forum, presenters will endorse their posters through a short “elevator pitch” (2‐minute presentation).

The FPL 2022 Demo Night is an opportunity to demonstrate and disseminate exciting work at the biggest annual gathering of experts in the field. Bring your demo to FPL and increase your visibility, interact with attendees, impress the FPL community and make a real impact. Demonstrations may include, but are not limited to, academic or commercial experiments, prototypes, tools, platforms, systems, and applications. This year, we are particularly inviting open-source contributions. Academic presenters must register for the conference and presenters from industry, must sign up for one of the on-site sponsor packages. Demo Night presenters are invited to submit a demo description through the EasyChair submission system by June 1st, 2022 providing the following information:

  • Demo Title
  • Names, affiliations, and email addresses (if different from the EasyChair information)
  • Description of the demo, its main objectives and its relevance to the FPL community
  • Short biographies of demo presenters
  • Any logistical requirements the demonstration may have (Internet access, screens, etc.)

Optionally, each submission may include a one-page abstract using the FPL 2022 regular papers format on a separate page. The abstract must state a technical contribution and will appear in the proceedings subject to passing a review process (pure marketing will be rejected). Abstract titles must start with “FPL Demo: …”

You are welcome to use those email addresses of the PhD Forum and Demo Night chairs for informal queries.

FPL Steering Committee
Patrick Lysaght (Xilinx), Chairman
Jürgen Becker (Karlsruhe Institute of Technology)
Koen Bertels (University of Porto)
Eduardo Boemo (Universidad Autónoma de Madrid)
João M. P. Cardoso (Universidade do Porto)
Peter Y. K. Cheung (Imperial College London)
Martin Danek (Daiteq)
Apostolos Dollas (Technical University of Crete)
Fabrizio Ferrandi (Politecnico di Milano)
Manfred Glesner (Technische Universität Darmstadt)
Diana Goehringer  (Technische Universität  Dresden)
Reiner Hartenstein (Technische Universität Kaiserslautern)
Andreas Herkersdorf (Technische Universität München)
Paolo Ienne (EPFL)
Udo Kebschull (Goethe Universität Frankfurt)
Wayne Luk (Imperial College London)
Xavier Martorell(Universitat Politècnica de Catalunya & Barcelona Supercomputing Center)
Jari Nurmi (Tampere University of Technology)
Ioannis Sourdis (Chalmers University of Technology)
Dirk Stroobandt (University of Ghent)
Lionel Torres (Université Montpellier 2)
Jim Tørresen (Universitetet i Oslo)

FPL’22 General Chairs
John McAllister, Queen’s University of Belfast, UK
Roger Woods, Queen’s University of Belfast, UK

FPL’22 PhD Forum & Demo Chairs
Dirk Koch, University of Heidelberg, Germany
Daniel Ziener, Technische Universität Ilmenau, Germany

Episode 8 of Computer Architecture Podcast Released! Featuring guest Prof. Todd Austin
Submitted by Suvinay Subramanian

Computer Architecture Podcast: a series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.

Announcing the release of Episode 8: Durable Security and Privacy-enhanced Computing with Dr. Todd Austin, University of Michigan, who is a Professor of Electrical Engineering and Computer Science at the University of Michigan in Ann Arbor. His research interests include robust and secure system design, hardware and software verification, and performance analysis tools and techniques. Todd has donned multiple hats, being a senior processor architect at Intel’s Microprocessor Research Labs, a professor at the University of Michigan, serving as the director of research centers like C-FAR, and more recently serving as the CEO and co-founder of the startup Agita Labs. He is also an IEEE Fellow and received the ACM Maurice Wilkes Award for his work on SimpleScalar, and the DIVA and Razor architectures.

Listen to the episode at Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Akanksha Jain
SIGARCH Content Editor