This is the 1st March 2021 digest of SIGARCH Messages.

In This Issue

ISCA’19 Joint Investigative Committee Announcement

Submitted by Samira Khan

The ACM and IEEE Joint Investigative Committee (JIC) has completed its investigation into the allegations of professional and publications-related misconduct in connection with ISCA 2019. The full announcement related to the investigation is available here.

Call for Nominations: 2021 ACM-IEEE CS Eckert-Mauchly Award
Submitted by Boris Grot

The ACM/IEEE-CS Eckert-Mauchly Award is given for contributions to computer and digital systems architecture where the field of computer architecture is considered to encompass the combined hardware-software design and analysis of computing and digital systems.  Recent winners of the award have included Luiz A. Barroso, Mark Hill, Susan Eggers and Charles P. Thacker.

Nominations are due March 30, 2021. Further information, including nomination instructions, can be found at the award web site:

Call for Nominations: Berenbaum Distinguished Service Award: Nominations Due Mar 1
Submitted by Boris Grot

Nominations are sought for the ACM SIGARCH Alan D. Berenbaum Distinguished Service Award. This annual award is presented to an individual who has contributed important service to the computer architecture community.

Full details of the award, including the nominations process, can be found here:

Call for Participation: ISPASS 2021
Submitted by I-Ting Angelina Lee

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
March 28-30, 2021


The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software. ISPASS 2021 will be held March 28 through 30, 2021 in a virtual online format. The MLBench 2021 and FastPath 2021 workshops, and a tutorial on ESP: An Open-Source Platform for Agile SoC Development will be held in conjunction with the conference.  The preliminary conference program has been posted, and registration is now open. The detailed program is available on the conference website at

The format of ISPASS will follow a new format and include session panel discussions instead of traditional presentations. We will start each day with a keynote, one from Daniel Lustig, a Senior Research Scientist at Nvidia, and one from Reetuparna Das, an Associate Professor of Electrical Engineering and Computer Science at the University of Michigan. Presentation formats will differ this year, with group panel discussions following each presenter’s lightning talks. We are aiming for an interactive discussion with the community on a variety of topics.

Through the generous support of the IEEE TCCA and our industry sponsors, the conference is pleased to offer student participation grants that will cover the conference registration fee for eligible students. Applications are due March 7th, 2021. See the conference website for details.

We invite you all to attend the conference and hope to see you on Zoom!

Trevor E. Carlson
ISPASS 2021 Program Chair

Michael Ferdman
ISPASS 2021 General Chair

Call for Papers: NPC 2021

Submitted by Chen Liu

The 18th Annual IFIP International Conference on Network and Parallel Computing (NPC 2021)
Paris, France

Submissions Due: July 11, 2021

High Performance Computing and Big Data are two main areas where NPC 2021 will provide a dynamic forum to explore, discuss and debate state-of-the-art technology issues and challenges. High-performance computers and big-data systems are tied inextricably to the broader computing ecosystem and its designs and market adoption. We strongly believe that the stakes are high and are far beyond the boundaries of nations and continents. We invite all researchers around the world to
submit papers to NPC 2021.

We share the view that, during the past decade, the tools and cultures of high-performance computing and big data analytics are diverging to the detriment of both, and the international community should find a unified path that can best serve the needs of a broad spectrum of major
application areas. Unlike other tools, which are limited to particular scientific domains, computational modeling and data analytics are applicable to all areas of science and engineering, as they breathe life into the underlying mathematics of scientific models. Topics of interest
include, but are not limited to:

* Parallel and distributed applications and algorithms
– Parallel and distributed issues and opportunities on artificial intelligence applications.
– Parallel algorithms for computational and data-enabled scientific, engineering, biological and medical applications.
– Parallel algorithms for accelerators, neuromorphic architectures, and other emerging architectures.

* Parallel and distributed architectures and systems
– Domain-Specific Accelerators for AI, deep learning and applications in industry sectors (such as health: genomics, finance: block chain, and others)
– Non-traditional Computing Technology (Quantum/Optical/Superconducting computers)
– Emerging architectures and systems at all scales, from embedded to cloud.
– Systems for enabling parallelism at an extreme scale.
– Power-efficient and green computing systems.
– Neuromorphic architectures and cognitive computing accelerators.
– Heterogeneous multicore architectures and accelerators.
– In-Memory and near-data computing.
– Network and interconnect architectures.
– Storage systems in novel big data architectures.
– IoT and Edge Computing related topics.

* Parallel and distributed software environments and tools
– Programming models and compilation for existing and emerging platforms.
– Dataflow programming models, frameworks, languages and environments for data-enabled platforms.
– Virtualization of machines, networks, and storage.
– I/O, file systems, and data management.
– Resource management, scheduling, and load balancing.

Authors should submit the full version of the paper by July 11, 2021, AOE. The full version should be a PDF file following the submission guidelines that will be made available at the submission website. Papers should be submitted for blind review. New-idea papers as well as papers that significantly advance established areas are strongly encouraged. Submission issues should be directed to program chairs, Jean-Luc Gaudiot, Guangming Tan and Stéphane Zuckerman. We will publish top papers from NPC 2021 in a special issue of the International Journal of Parallel Programming (IJPP), and the proceedings will be published as part of Springer LNCS.

* Important Dates:
– Paper Submissions Due: July 11, 2021, AOE
– Results Notification: August 20, 2021
– Camera-ready Version: August 27, 2021

* Manuscript submission

Papers reporting original and unpublished research results and experience are solicited. All paper submissions will be handled electronically via EasyChair:

Papers must not exceed 12 pages in LNCS format. Authors must register and submit their paper through the online submission system.

For more information, please visit the NPC 2021 conference web site to be announced soon.

Workshops & Tutorials will also be announced later

Christophe Cérin, Université Sorbonne Paris Nord, France
Depei Qian, Beihang University, PRC

Jean-Luc Gaudiot, University of California, Irvine, USA
Stéphane Zuckerman, Université de Cergy-Pontoise, France
Guangming Tan, ICT, PRC

Call for Papers: NOCS 2021
Submitted by Jieming Yin

15th IEEE/ACM International Symposium on Networks-on-Chip
October 10 – 15, 2021, Virtual Conference
(Co-located with Embedded Systems Week 2021)

Submissions Due: May 21, 2021


The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on network-on-chip (NoC) innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to:

### NoC Architecture and Implementation
– Network architecture (topology, routing, arbitration)
– Timing, synchronous/asynchronous communication
– NoC reliability issues and solutions
– Security issues and solutions in NoC architectures
– Power/thermal issues at NoC un-core and system-level
– Network interface issues and solutions
– Signaling and circuit design for NoC links and routers

### Communication Analysis, Optimization, & Verification
– NoC performance analysis and Quality of Service
– Modeling, simulation, and synthesis of NoC
– Verification, debug and test of NoC
– NoC design and simulation methodologies and tools
– Benchmarks, experiences on NoC-based hardware
– Communication-efficient algorithms
– Communication workload characterization & evaluation

### Novel NoC Technologies
– Optical, wireless, CNT, and other emerging technologies
– NoC for 2.5D and 3D packages
– Package-specific NoC design
– Network coding and compression solutions
– Approximate computing for NoC and NoC-based systems

### NoC for Intelligent Physical Systems
– NoC design for Deep Learning
– Mapping of existing and emerging applications onto NoC
– NoC case studies, application-specific NoC design
– NoC for FPGA, structured ASIC, CMP and MPSoC
– NoC designs for heterogeneous systems
– NoC for CPU-GPU and data-center-on-a-chip (DCoC)
– Scalable modeling of NoC
– Machine learning for NoC and NoC-based Systems

### NoC at the Un-Core and System-level
– Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoC
– NoC for new memory/storage technologies
– NoC support for processing-in-memory
– OS support for NoC
– Programming models for NoCs
– Interactions between large-scale systems (datacenter, edge and fog computing) and NoC-based building blocks

### Inter/Intra-Chip and Rack-Scale Network
– Unified inter/intra-chip networks
– Hybrid chip-scale and datacenter rack-scale networks
– All aspects of inter-chip and rack-scale network design


Electronic paper submission requires a full paper, up to 8 double-column ACM (sigconf) format pages, including figures and references. The program committee will use a double-blind review process to evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference or journal at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Proposals for special sessions and demos are invited. Paper submissions and demo proposals by industry researchers or engineers to share their experiences and perspectives are also welcome.

**New in 2021**
Journal Special Issue: A selected number of accepted papers will be invited to be published in an ACM JETC Special Issue.

Please find the detailed submission instructions for paper submission, special session, and demo proposals at the submission webpage.


## Important Dates (Anywhere on Earth)
Abstract registration: May 14, 2021
Full paper submission: May 21, 2021
Notification of acceptance: July 23, 2021

## Organizing Committee
### General Chairs
Tushar Krishna (Georgia Institute of Technology)
John Kim (KAIST)

### Technical Program Chairs
Sergi Abadal (Universitat Politècnica de Catalunya)
Joshua San Miguel (University of Wisconsin-Madison)

Call for Papers: Workshop on Computer Architecture Research with RISC-V (CARRV)
Submitted by Trevor E. Carlson

Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021)
in conjunction with ISCA’21
Virtual Workshop
June 17, 2019

Abstract submission deadline: May 7, 2021
Full paper submission deadline: May 14, 2021, 23:59 PST
Author notification: May 21, 2021

The Fifth Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work across simulated, FPGA and hardware implementations is encouraged.

The topics of specific interest for the workshop include, but are not limited to:
– RISC-V cores and SoC architectures
– RISC-V ISA extensions
– RISC-V-based hardware accelerators
– Security architectures and techniques
– Formal methods
– Verification methodologies
– Hardware/software interfaces
– RISC-V ISA and implementation performance analysis
– RISC-V compilers and dynamic translation tools

Submission instructions are available at the workshop web site.

Call for Papers: I too can Quantum! (I2Q)
Submitted by Gokul Ravi

Workshop: I too can Quantum! (I2Q)
Held in conjunction with the 48th International Symposium on Computer Architecture

Submissions Due: March 22, 2021



Current trends anticipate that the demand for a quantum workforce will greatly outweigh the supply in the near term. To fill this gap, talent has to be cultivated from the classical fields of science and engineering. Directly or indirectly, classical computing ideas are applicable in the quantum world, allowing for contributions from scientists and engineers who may not be fully trained in the fine details of quantum mechanics. Computer architects are especially critical to this endeavor as they are adept at bridging the information gap between different layers of the computing stack and are well poised to apply their cross-layer experiences from classical computing to the quantum domain.

While educating classical computing experts and novices in the deeper mathematics and physics of the quantum world is challenging, enabling them to think about quantum from the perspective of classical computing control for quantum computing is more conceivable. In this spirit, the I2Q workshop is focused on recognizing and mentoring innovative PhD students across a broad range of technical research areas, with a goal of contributing towards and furthering quantum research. I2Q enables graduate students with a solid classical foundation, a passion for quantum computing and preliminary ideas in a specific quantum domain to be mentored by quantum experts from academia, industry and national labs and support them in their quest towards achieving their research goals. Afterwards, these classically-trained students will confidently say, “I too can Quantum!”


  1. Students will submit a proposal on any innovative idea targeting quantum computing and are encouraged to seek ideas inspired from their own classical computer architecture expertise.

  2. I2Q will carefully review submitted proposals based on their potential for quantum innovation and solidity in (classical) foundation and select the I2Q finalists.

  3. The I2Q finalists will be mentored by quantum experts over a 5-6 week period prior to the ISCA workshop to facilitate the successful formulation of the proposed research.

  4. The finalists will present their maturing research proposals at the I2Q workshop.

  5. Further, we strongly encourage the continuation of these research partnerships beyond the workshop scope and timeline.



Submissions are encouraged in quantum computing directions inspired by (but not limited to) computer architecture ideas such as:

Compilation, Scheduling, Approximate Computing, Error Correction, Verification, Design Automation, Simulation, Parallelism, Memory Management, Edge Computing, Distributed Computing, Heterogeneous Co-processing, Security, Communication, Benchmarking, Ultra-low Power/Temperature Computing, Modularity, Microarchitecture, Integration vs Abstraction, ISA.


The goal of this workshop is to help students think about a nascent quantum problem/idea in an holistic manner and communicate those ideas to the wider quantum community so that we can provide valuable early-stage feedback and mentorship, hopefully leading to long-term collaborations.

Submissions are loosely expected to discuss:

  • Description of the quantum problem and its scope.

  • Preliminary idea for a solution and its potential classical inspiration.

  • Evidence of building towards a realistic implementation of the solution as well as evaluation methodology.

  • Discussion of related ideas and future goals to provide more breadth to the proposal.

  • A short note on student background and skills and why they are suited to this project.


  • Submissions must be PDF files, in 2-column, single-spaced, 10pt format.

  • Submissions must be at most 2 pages long, not including references.

  • Submissions will be single-blind.

  • Please provide author information in the submission.

  • Submissions can be individual or in teams, but all are expected to be in early stages of their quantum research pursuits.

  • Tentative Deadline: March 22, 2021, 11:59pm EST.



The workshop is organized by members of EPiQC: Enabling Practical-scale Quantum Computation, an NSF Expedition in Computing.

Kaitlin N. Smith: Kate is a CQE/IBM Postdoctoral Scholar within EPiQC at the University of Chicago under the mentorship of Prof. Fred Chong.

Gokul Subramanian Ravi: Gokul is a 2020 Computing Innovation Fellow, pursuing a postdoc in the CS Department at the University of Chicago as part of EPiQC.

Prof. Frederic Chong: Fred Chong is the Seymour Goodman Professor in the Department of Computer Science at theUniversity of Chicago as well as the Lead Principal Investigator for the EPiQC Project.

Call for Papers: Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware
Submitted by Tom St. John

Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware
To be held with Fourth Conference on Machine Learning and Systems (MLSys)
Virtual conference
April 7, 2021

Submissions Due: March 5, 2021

With evolving system architectures, hardware and software stacks, diverse machine learning (ML) workloads, and data, it is important to understand how these components interact with each other. Well-defined benchmarking procedures help evaluate and reason the performance gains with ML workload-to-system mappings. We welcome all novel submissions in benchmarking machine learning workloads from all disciplines, such as image and speech recognition, language processing, drug discovery, simulations, and scientific applications. Key problems that we seek to address are: (i) which representative ML benchmarks cater to workloads seen in industry, national labs, and interdisciplinary sciences; (ii) how to characterize the ML workloads based on their interaction with hardware; (iii) which novel aspects of hardware, such as heterogeneity in compute, memory, and networking, will drive their adoption; (iv) performance modeling and projections to next-generation hardware. Along with selected publications, the workshop program will also have experts in these research areas presenting their recent work and potential directions to pursue.

We solicit both full papers (8-10 pages) and short/position papers (4 page). Submissions are not double blind (author names must be included). The page limit includes figures, tables, and appendices, but excludes references. Please use standard LaTeX or Word ACM templates. All submissions will need to be made via EasyChair ( Each submission will be reviewed by at least three reviewers from the program committee. Papers will be reviewed for novelty, quality, technical strength, and relevance to the workshop. All accepted papers will be published here.

Call for Papers: Workshop on Computer Architecture Education
Submitted by Ed Gehringer

Workshop on Computer Architecture Education (WCAE)
Held in conjunction with the 48th International Symposium on Computer Architecture
Valencia, Spain or online (TBD)

Submissions Due: 26 April, 2021

WCAE provides a forum for educators in computer architecture to discuss and share their experiences and teaching philosophy. Past WCAEs have been held in conjunction with HPCA, ISCA, and Micro. Over 220 papers on computer architecture education have been presented at the workshop since its inception in 1995. Participants will come away from the workshop with new ideas on delivering courses in computer architecture. Topics of interest include, but are not limited to, the following.

Approaches to introductory courses
Advanced courses
Online resources
Resources for “flipped” classes
Materials for active learning
Lecture vs. hybrid vs. flipped classes
Lab support for distance education
Textbook development
Critical evaluation of textbook approaches
Metrics for evaluating learning gains
Integration of research into teaching
Industrial support for teaching
Resources & techniques for teaching …
GPU architecture & programming
Multicore/many-core issues
Comp. arch. concepts with FPGAs
Issues specific to embedded systems
Hardware tools
Simulators and other software tools
Tools and techniques for autograding non-programming assignments
Visualization aids
Broadening participation in computer architecture
Encouraging undergraduate research
Encouraging students to pursue a Ph.D.

Authors should submit a full paper (not to exceed 8 pages), following the ACM proceedings templates.

Ed Gehringer,

We encourage participation by book publishers, computer manufacturers, software vendors, or companies which develop or market products used in the delivery of computer architecture education. Any company interested in participating in the workshop should contact the organizer at the address above.

Submission Due Date: Monday, April 26, 2021
Author Notification: Wednesday, May 5, 2021
Final Paper Due Date: Wednesday, May 12, 2021
Copies of papers presented at the workshop will be made available through the ACM Digital Library

Jim Conrad, University of North Carolina-Charlotte
Henry Duwe, Iowa State University
Subramanian Ganesan, Oakland University
Xinfei Guo, University of Virginia
Sarah Harris, University of Nevada-Las Vegas
Lei Jiang, Indiana University
Dave Kaeli, Northeastern University
Michael Manzke, Trinity College, Dublin
Yale Patt, University of Texas
Diane Rover, Iowa State University
Devesh Tiwari, Northeastern University

Call for Papers: IEEE Micro Special Issue on Compiling for Accelerators
Submitted by Lucas Wanner

IEEE Micro Special Issue on Compiling for Accelerators

Submission Due: December 15, 2021

Scope and Topics

Hardware accelerators are rapidly becoming a central architectural feature to improve computation power performance. CPU ISA extensions, custom-designed engines, and FPGA-based systems have been proposed as acceleration architectures to improve program execution in scientific, machine-learning, database, and other application domains. Although much effort has been devoted to the design of accelerators, there is still a large gap of knowledge on how to make effective use of and compile for such architectures. As history has already taught us, having a great architecture is only half of the path to designing an efficient computing machine. Understanding the techniques required for quality code generation is central to the long-term establishment of an acceleration-based architectural paradigm.

This special issue of IEEE Micro will explore academic and industrial research on topics that relate to compiling for accelerators. Topics of interest include, but are not limited to:

  • Compiling for CPU ISA extensions
  • Code generation for neural processing units
  • Compiling for neural network training
  • Programming linear algebra engines
  • Code generation and programming for database accelerators
  • Processor-accelerator interface design and programmability
  • Compiling for energy efficiency
  • Pattern matching and code replacement for acceleration instructions
  • High-level synthesis design of custom engines
  • DSL and parallel programming models for accelerators
  • Compiler intermediate representation (IR) and optimization techniques for accelerators
  • Programming FPGAs for custom computing engines
  • Tools and libraries to support code generation for accelerators

Important Dates

Submission Deadline: December 15, 2021
Initial notifications: March 15, 2022
Revised papers due: April 8, 2022
Final notifications: May 13, 2022
Final versions due: May 31, 2022
Publication: July/August 2022

Submission Guidelines

Please see the Author Information page and the Magazine Peer Review page for more information. Please submit electronically through ScholarOne Manuscripts, selecting this special-issue option. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. All previously published papers must have at least 30% new content compared to any conference (or other) publication.


Contact guest editors Guido Araujo and Lucas Wanner at, or the editor-in-chief Lizy John at

Please direct ScholarOne-related questions to the IEEE Micro magazine assistant at

Call for Workshops/Tutorials: ICS 2021
Submitted by Xu Liu

35th ACM International Conference on Supercomputing (ICS 2021)
June 14, 2021

Proposals Due: February 14, 2021

The organizers of the 35th ACM International Conference on Supercomputing (ICS-2021) call for proposals for workshops and tutorials to be held virtually in conjunction with ICS-2021 on June 14 2021.

Proposals for both half-day and full-day tutorials and workshops are solicited on any topic that is relevant to the ICS audience.

Tutorials that focus on tools and techniques that enable research across layers of the computational stack are strongly encouraged. Tutorials may have one of the following goals:

  • Describe an important piece of research infrastructure
  • Educate the community on an emerging topic

Workshops should provide forums for discussion among researchers and practitioners on focused topics or emerging research areas relevant to the community of High Performance Computing (HPC). Workshop organizers may structure workshops as they prefer, including invited talks, panel discussions, presentations of work in progress, fully peer-reviewed papers, or some combination of the above. Workshops could be scheduled for half a day or a full day on June 14th, 2021, depending on interests, space constraints, and the organizer’s preference. Organizers should design workshops for approximately 20-40 participants, to balance the impact and effective discussion.

The deadline for submission of a proposal is February 14th, 2021. We strongly encourage workshop and tutorials organizers to submit their proposals early so that there is enough time to organize the program before the conference. We also encourage proposals for new events that have not been held before. Notification of acceptance will be on February 28 2021.

Workshop and tutorials proposals should include the following items:

  • The title (and acronym, if applicable) of the workshop/tutorial
  • 1-3 page description (for evaluation), including:
    • Scope and objectives
    • Topics of interest to be covered
    • Scheduling and format of the sessions of the workshop (papers, invited talks, panel discussions, etc.) or tutorial (lecture, hands-on, etc.)
    • Proposed duration (full day, half day)
    • How the workshop/tutorial will work in the virtual format (videos, zoom live call, etc.) and how to foster interactivity and discussions in such scenario.
    • Description (one paragraph) on the relevance ot the topics for ICS
    • Target audience
    • Expected number of attendees
    • If the workshop/tutorial has been held previously, the location (i.e., conference), date, number of attendees, link to website (if applicable)
  • The names and affiliations of the workshop/tutorial organizers, and if applicable, the name and affiliation of the PC chair, and of a significant portion of the program committee
  • A description (0.5-1 page) of the theme of the workshop/tutorial, suitable for tutorial publicity
  • A publicity plan for attracting submissions and attendees
  • Follow-up plans (if any) to disseminate the ideas from the workshop/tutorial. For example, through position paper or special-issues in a journal

Please, send proposals by e-mail to the ICS-2021 Workshops and Tutorials Co-Chairs list,

Your submission will be received by the Workshops and Tutorials co-chairs:

  • Antonino Tumeo, PNNL
  • Miquel Moreto, UPC and BSC

Feel free to contact us if you have any questions about the suitability of a workshop for ICS-2021 or for any other related matters.

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.

- Samira Khan
SIGARCH Content Editor