This is the 1st May 2019 digest of SIGARCH Messages.

In This Issue

Call for Nominations: Call for Nominations: B. Ramakrishna Rau Award
Submitted by Milagros Lovos

Established in memory of Dr. B. (Bob) Ramakrishna Rau, this award recognizes his distinguished career in promoting and expanding the use of innovative computer microarchitecture techniques, including his innovation in compiler technology, his leadership in academic and industrial computer architecture, and his extremely high personal and ethical standards.

A certificate and a $2,000 honorarium are awarded.

The award is presented annually at the ACM/IEEE International Symposium on Microarchitecture.

The candidate will have made an outstanding innovative contribution or contributions to microarchitecture and use of novel microarchitectural techniques or compiler/architecture interfacing. It is hoped, but not required, that the winner will have also contributed to the computer microarchitecture community through teaching, mentoring, or community service. This award requires 3 endorsements.

Nominations are being accepted electronically by 1 May 2019 to

Email to

Call for Papers: Workshop on Hardware and Architectural Support for Security and Privacy
Submitted by Jakub Szefer

Workshop on Hardware and Architectural Support for Security and Privacy (HASP)
in conjunction with ISCA 2019
Phoenix, Arizona, USA
June 23, 2019

Submission Deadline: April 28, 2019 AOE (extended)
Notification of Acceptance: May 12, 2019
Camera-Ready Version: May 26, 2019

Although much attention has been directed to the study of security at the system and application levels, security and privacy research focusing on hardware and architecture aspects is still a new frontier. In the era of cloud computing, smart devices, and novel nano-scale devices, practitioners and researchers have to address new challenges and requirements in order to meet the ever-changing landscape of security research and new demands from consumers, enterprises, governments, defense and other industries.

HASP is intended to bring together researchers, developers, and practitioners from academia and industry, to share practical implementations and experiences related to all aspects of hardware and architectural support for security and privacy, and to discuss future trends in research and applications. To that end, papers are solicited from the areas, including, but not limited to:

– Secure hardware processor architectures and implementations
– Side-channel attacks, evaluations, and defenses
– Secure cache designs and evaluation, focusing on side-channels
– SGX, SEV and Trustzone based systems and security solutions
– Hardware-enhanced cloud security
– Hardware support for secure Internet-of-Things
– Smartphone hardware security
– Hardware fingerprinting and PUFs
– Hardware and architectural support for trust management
– Hardware trojan threat evaluation, detection, and prevention
– Attack resilient hardware and architectural design
– Cryptographic hardware design, implementation, and evaluation
– Security simulation, testing, validation and verification
– Analysis of real attacks and threat evaluation

In addition to regular research papers, authors are also invited to submit position papers or systemization-of-knowledge papers. Position papers should define new problems in hardware or architecture security and privacy topics. Titles of position papers should have Postition Paper: as their prefix.

Systemization-of-Knowledge papers should consicely, but exhaustively, systematize and conceptualize existing knowledge (similar to SoK papers in S&P conferences, but focusing on hardware and architecture). Titles of Systemization-of-Knowledge papers should have SoK: as their prefix.

Finally, researchers wishing to share their ongoing work without publishing a paper should submit application for a Work-in-Progress presentation. To be considered, a short 4-page paper should be submitted, with WiP: as the prefix to the title. These papers will not be published in the proceedings, but the title and authors will be listed on the HASP web page as a public record of the presentation.

Submissions must be written in English with at most 8 pages including the bibliography and appendices. Submissions must be in double-column ISCA 2019 format. All accepted full papers will be included in the ACM Digital Library; Work-in-Progress papers are not included. The proceedings will be published throuh ACM ICPS and available through the ACM Digital Library.

Papers can be submitted on the EasyChair web page:

Prof. Ruby Lee, Princeton University
Prof. Weidong Shi, University of Houston
Prof. Jakub Szefer, Yale University

Call for Papers: IEEE Micro Special Issue on Monolithic 3D Architectures
Submitted by Lizy K John

IEEE MICRO Special Issue on Monolithic 3D Architectures

Going vertical is a promising option to continue density scaling beyond traditional transistor scaling. The initial wave of three-dimensional architectures have focused on connecting stacked chip layers by through silicon vias (TSVs). However, the challenges with dimensional scaling of TSVs has limited the degree of interaction across different layers. New monolithic 3D integration technologies have enabled nanoscale interconnections, orders of magnitude smaller than TSVs, providing massive vertical connectivity. This data connectivity provides new opportunities for micro-architectural and architectural innovations to reduce the energy associated with data movement and enhance the performance of applications that operate on massive amount of data. The integration of heterogeneous technologies within the same chip can also drive innovations in algorithms and system realizations. This special issue of IEEE Micro will explore academic and industrial research on all topics related to monolithic 3D architectures.

Such topics include, but are not limited to:
– Survey and tutorial on monolithic process technologies
– Application specific customization leveraging monolithic 3D integration
– Micro-architectural innovations using monolithic 3D
– In-memory computational fabrics leveraging 3D interconnects
– Thermal and power analysis of monolithic systems
– 3D Reconfigurable Architectures and FPGA Designs
– Heterogeneous systems on a chip
– Network on Chip fabrics for monolithic 3D technologies
– Processor Design using monolithic 3D
– Benchmarking of processor architectures using different 3D technologies

Submissions due: June 11, 2019
Initial notifications: July 22, 2019
Revised papers due: August 15, 2019
Final notifications: September 12, 2019
Final versions due: September 19, 2019
Publication date: Nov/Dec 2019

Please see the Write for Us page and the general author guidelines for more information. Please submit electronically through ScholarOne Manuscripts, selecting this special-issue option.

Contact the guest editor, Vijay Narayanan ( or the editor-in-chief, Lizy John (

Call for Presentations: ModSim 2019
Submitted by Jason Lowe-Power

Workshop on Modeling & Simulation of Systems and Applications
Seattle, USA
August 14-16, 2019

To promote advancements in modeling and simulation (ModSim) research, we are soliciting community input in the form of abstracts. If accepted, author(s) will be invited to offer a presentation at the annual gathering of our community, the ModSim 2019 Workshop.

Submission URL:

WICARCH YouTube channel
Submitted by Natalie Enright Jerger

WICARCH has launched a new monthly webinar series. Recordings of our webinars can be found on our YouTube channel: You can also find us as a featured channel on the SIGARCH YouTube channel (

Members of WICARCH are also invited to join the webinars live and to participate in the post-webinar Q&A which covers a variety of technical and non-technical topics (the live webinars are restricted to WICARCH members to maintain a safe space for non-technical Q&A which is not part of the recorded material). Information on how to join the webinars is available through our slack channel. Women are encouraged to email for an invitation to join the slack channel. The slack channel boasts a vibrant online community of nearly 200 women in computer architecture celebrating each others’ successes, sharing technical knowledge, mentoring and socializing.

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Boris Grot
SIGARCH Content Editor