This is the 1st March 2020 digest of SIGARCH Messages.

In This Issue


Call for Nominations: VCLA International Student Awards 2020
https://logic-cs.at/vcla-awards-2020
Submitted by Mihaela Rozman

VCLA International Student Awards 2020
Nominations Due: March 25, 2020

The Vienna Center for Logic and Algorithms of TU Wien (Vienna University of Technology), calls for the nomination of authors of outstanding theses and scientific works in the field of Logic and Computer Science, in the following two categories:

= Outstanding Master Thesis Award

= Outstanding Undergraduate Thesis Award (Bachelor thesis or equivalent, 1st cycle of the Bologna process)

———————————-The main areas of interest are: ———

*Computational Logic, covering theoretical and mathematical foundations such as proof theory, model theory, computability theory, Boolean satisfiability (SAT), QBF, constraint satisfaction, satisfiability modulo theories, automated deduction (resolution, refutation, theorem proving), non-classical logics (substructural logics, multi-valued logics, deontic logics, modal and temporal logics).

*Algorithms and Computational Complexity, including design and analysis of discrete algorithms, complexity analysis, algorithmic lower bounds, parameterized and exact algorithms, decomposition methods, approximation algorithms, randomized algorithms, algorithm engineering, as well as algorithmic game theory, computational social choice, parallel algorithms, graph drawing algorithms, and distributed algorithms.

*Databases and Artificial Intelligence, concerned with logical methods for modeling, storing, and drawing inferences from data and knowledge. This includes subjects like query languages based on logical concepts (Datalog, variants of SQL, XML, and SPARQL), novel database-theoretical methods (schema mappings, information extraction and integration), logic programming, knowledge representation and reasoning (ontologies, answer-set programming, belief change, inconsistency handling, argumentation, planning).

*Verification, concerned with logical methods and automated tools for reasoning about the behavior and correctness of complex state-based systems such as software and hardware designs as well as hybrid systems. This ranges from model checking, program analysis and abstraction to new interdisciplinary areas such as fault localization, program repair, program synthesis, and the analysis of biological systems.

*Formal Methods for Security ad Privacy, covering design and analysis techniques for security and privacy critical systems, such as cryptographic protocols, software, hardware and so on. The category of formal methods is to be meant in a broad sense, including related questions in logic, model checking, static analysis, dynamic monitoring, theorem proving, and artificial intelligence.

 

———————————-In Memory of Helmut Veith—————

The award is dedicated to the memory of Helmut Veith, the brilliant computer scientist who tragically passed away in March 2016, and aims to carry on his commitment to promoting young talent and promising researchers in these areas.

———————————-Awards———————————-

*The Outstanding Master Thesis Award:  1200 EUR

*The Outstanding Undergraduate Thesis Award: 800 EUR

*The winners will be invited to present their work at an award ceremony in Vienna.

———————————-Eligibility—————————-

*The degree must have been awarded between November 15th, 2018 and December 31st, 2019 (inclusive).

*Students who obtained their degree at TU Wien are not eligible.

———————————-Nomination Requirements—————-

Nominations must include:

*A cover page that contains the name and contact details of the nominated person, the title of the work for which the person is being nominated, award category, the date on which the degree was awarded, and the name of the university

*An English summary of the thesis of maximum 3 pages, excluding references (A4 or letter page size, 11pt font min). The summary must clearly state the main contribution of the work, its novelty, and its relevance to some of the aforementioned areas of interest

*The CV of the nominated person, including publication list (if applicable)

*An endorsement letter from a supervisor or another proposing person. The letter must clearly state the independent and novel contribution of the student, and why the proposer believes the student deserves the award. The endorsement letter may be provided after the submission deadline, and emailed directly to award (AT) logic-cs.at.

*The full thesis

All documents should be in English, with the exception of the thesis. In case the thesis is in a different language, it must be accompanied by a research report in English of at least 10 pages that should be sufficient for the committee to evaluate the merit and quality of the submitted work.

———————————-Instructions for submitting nominations–

*Nominations should be submitted electronically using the following link to EasyChair here: https://easychair.org/account/signin?l=YM7S3LYB9EcHisWn1s3722#

*Submissions consist of two pdf files. The first is a single pdf file containing all documents for the nomination except the full thesis; the documents should appear in the order they are listed above. The second pdf file is the full thesis

*The endorsement letter may optionally be sent by email by the endorser and omitted from the Easychair submission. In this case, please email the letter as a pdf file, including the name of the nominated person in the subject, to award (AT) logic-cs DOT at

*The submission must be accompanied by a plain text electronic abstract of the thesis of at most 400 words, and three keywords.

*The nominated student must be listed as the first and corresponding author in the submission form.

———————————-Important dates————————-

*Submission deadline: March 25, 2020 (anywhere on Earth)

*Notification of decision: end of June 2020

*Award ceremony: TBA

———————————-Contact———————————

Please send all inquiries to award (AT) logic-cs.at

———————————-Website———————————

https://logic-cs.at/vcla-awards-2020


Call for Participation: ISCA Undergrad Mentoring Workshop 2020
https://sites.google.com/view/uarch2020/home
Submitted by Lena Olson

Computer Architecture Undergraduate Mentoring Workshop
Co-located with ISCA 2020
Valencia, Spain

Applications Due: March 13, 2020

Applications for funding to attend the Second Annual Computer Architecture Undergraduate Mentoring Workshop are now open.

The workshop will be held as part of ISCA 2020, and is aimed at undergraduate students with an interest in computer architecture. We expect the workshop will most benefit students who will receive their undergraduate degree in 2021 or 2022, and funding priority will go to students from Europe, the Middle East, and Africa. Women and underrepresented minorities are particularly encouraged to apply for funding.

The workshop will introduce students to research and career opportunities in the field of computer architecture in particular and graduate school lifestyle and survival skills in general. The program will include technical sessions that cover past, current and future research directions in computer architecture, mentoring sessions that cover how to apply to graduate school and how to navigate the architecture research landscape effectively, and networking sessions that create opportunities for students to interact with their peers and established architects in academia and industry.

Selected applicants will have travel, hotel, and conference registration costs covered for the workshop and the main program of the conference. Funded attendees are expected to stay from Sunday through Wednesday morning and to attend both the workshop and the conference main program.

Location: Valencia, Spain

Important Dates:

  • March 13th: Application deadline.
  • March 23rd: Notification to accepted applicants.
  • May 31-June 3rd: Workshop and ISCA.

Website and link to application form: https://sites.google.com/view/uarch2020/home

Organizers: Newsha Ardalani, Bobbie Manne, Lena Olson, Joshua San Miguel

Questions? Please contact isca2020.uarch@gmail.com


Call for Papers: MCSoC 2020
http://www.mcsoc-forum.org/
Submitted by Ben Abdallah Abderazek

14th International Symposium on Embedded Multicore/Many- core Systems-on-Chip (MCSoC-2020)
Singapore University of Technology and Design
Dec 20-23, 2020

Submissions Due: May 31, 2020

The IEEE 14th MCSoC-2020 aims to provide the world’s premier forum of leading researchers in the Embedded Multicore/Many-core SoCs software, tools and applications design areas for academia and industries. From the 2018 edition, the MCSoC symposium targets new emerging topic related to neuro-inspired/neuromorphic computing architectures and systems. Prospective authors are invited to submit their contributions. Submission of a contribution implies that at least one of the authors will have a full registration to the symposium upon acceptance of his/her contribution. Submission can include, technical and experimental, theoretical, conceptual, or survey. All submissions will be peer-reviewed on the basis of relevance, originality, importance, and clarity. Topics of interest will fall under one or more of the following symposium tracks:

Track 1: Embedded Multicore/Manycore SoC Programming
Track 2: Embedded Multicore/Manycore SoC Architectures
Track 3: Embedded Multicore/Manycore SoC Design
Track 4: Embedded Multicore/Manycore SoC Interconnection Networks
Track 5: Embedded Multicore/Manycore SoC and System Security
Track 6: Embedded Multicore/Manycore SoC Design Automation and Low-power Design
Track 7: Embedded Multicore/Manycore SoC Real-Time Systems
Track 8: Operating Systems Platforms for Real-Time Embedded Applications
Track 9: Embedded Multicore/Manycore SoC Applications
Track 10: Algorithms and Hardware for Learning On-chip
Track 11: Embedded Neuromorphic Computing Systems
Track 12: Secure and Fault-Tolerant Embedded Computing
Track 13: Machine Learning for Energy-efficient, Reliable Manycore Interconnects
Special Sessions
Special Session on Auto-Tuning for Multicore and GPU (ATMG2020)
Special Session on Intelligent Systems and Learning Technologies: Models, Methods, and Applications (ISLT)
Special Session on Low-power Solutions for Future SoC design
Special Session on Applications and Architectures designed for Energy-efficient Hardware
Special Session on Traffic-aware Design for Multicore/Manycore SoCs
Special Session on Scalable and Flexible Many-Core Mapping and Runtime Techniques
Submission Guidelines and Proceedings
Electronic paper submission should not exceed 8 double-column IEEE format pages, including figures and references. Papers should be formatted as close as possible to the final format – double column, single-spaced, and Times or equivalent font of minimum, 10pt size. The acceptable format is PDF only. Any other file format and manuscripts received in hard-copy form will not be processed. Please use IEEE Formats for paper formatting.

Every submitted paper will be evaluated by at least three reviewers in technical quality, originality, significance to the symposium, and organization. We encourage authors to proofread and spell check their papers before submission.MCSoC 2020 proceedings will be published by IEEE Computer Society, which will be included in the Computer Society Digital Library CSDL and IEEE Xplore. All CPS conference publications are also submitted for indexing to EI’s Engineering Information Index, Compendex, and ISI Thomson’s Scientific and Technical Proceedings, ISTP/ISI Proceedings, and ISI Thomson.

Important Dates
Abstract submission: May 25, 2020
Full paper submission: May 31, 2020
Acceptance notification: July 15, 2020.
Camera-ready paper: July 31, 2020
Submission System
The submission system is: https://edas.info/N27016

Special Issues

Selected papers from the IEEE MCSSoC 2020 symposium will be invited to submit an extended version to the following journals:


Call for Papers: NOCS 2020
https://www.engr.colostate.edu/nocs2020/
Submitted by Lizhong Chen

14th IEEE/ACM International Symposium on Networks-on-Chip
October 15 – 16, 2020, Shanghai, China
(Co-located with Embedded Systems Week 2020)

Submissions Due: May 1, 2020

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on network-on-chip (NoC) innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to:

## NoC Architecture and Implementation
– Network architecture (topology, routing, arbitration)
– Timing, synchronous/asynchronous communication
– NoC reliability issues and solutions
– Security issues and solutions in NoC architectures
– Power/thermal issues at NoC un-core and system-level
– Network interface issues and solutions
– Signaling and circuit design for NoC links and routers

## Communication Analysis, Optimization, & Verification
– NoC performance analysis and Quality of Service
– Modeling, simulation, and synthesis of NoC
– Verification, debug and test of NoC
– NoC design and simulation methodologies and tools
– Benchmarks, experiences on NoC-based hardware
– Communication-efficient algorithms
– Communication workload characterization & evaluation

## Novel NoC Technologies
– Optical, wireless, CNT, and other emerging technologies
– NoC for 2.5D and 3D packages
– Package-specific NoC design
– Network coding and compression solutions
– Approximate computing for NoC and NoC-based systems

## NoC for Intelligent Physical Systems
– NoC design for Deep Learning
– Mapping of existing and emerging applications onto NoC
– NoC case studies, application-specific NoC design
– NoC for FPGA, structured ASIC, CMP and MPSoC
– NoC designs for heterogeneous systems
– NoC for CPU-GPU and data-center-on-a-chip (DCoC)
– Scalable modeling of NoC
– Machine learning for NoC and NoC-based Systems

## NoC at the Un-Core and System-level
– Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoC
– NoC for new memory/storage technologies
– NoC support for processing-in-memory
– OS support for NoC
– Programming models for NoCs
– Interactions between large-scale systems (datacenter, edge and fog computing) and NoC-based building blocks

## Inter/Intra-Chip and Rack-Scale Network
– Unified inter/intra-chip networks
– Hybrid chip-scale and datacenter rack-scale networks
– All aspects of inter-chip and rack-scale network design

#############################################

Electronic paper submission requires a full paper, up to 8 double-column ACM (sigconf) format pages, including figures and references. The program committee will use a double-blind review process to evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference or journal at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Proposals for special sessions and demos are invited. Paper submissions and demo proposals by industry researchers or engineers to share their experiences and perspectives are also welcome. A percentage of accepted papers will be recommended for publication in an IEEE journal after revision according to the reviewers?comments. Please find the detailed submission instructions for paper submission, special session, and demo proposals at the submission webpage.

############################################

Important Dates (Anywhere on Earth)
Abstract registration: Apr 24, 2020
Full paper submission: May 1, 2020
Notification of acceptance: July 08, 2020
Final version due: August 07, 2020

General Chairs
Sudeep Pasricha (Colorado State University)
Ajay Joshi (Boston University)

Technical Program Chairs
Tushar Krishna (Georgia Institute of Technology)
John Kim (KAIST)


Call for Papers: MICRO 2020
http://microarch.org/micro53
Submitted by Dimitrios Skarlatos

53rd IEEE/ACM International Symposium on Microarchitecture (MICRO-53)
17-21 October 2020, Athens, Greece
https://www.microarch.org/micro53/

Submissions Due: April 3, 2020

The International Symposium on Microarchitecture® (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers—we aim to continue and strengthen this longstanding tradition at the 53rd MICRO in Athens, Greece.

Abstract Deadline: March 27, 2020 at 11:59 PM PDT

Full Paper Deadline: April 3, 2020 at 11:59 PM PDT

Notification: July 1, 2020

We invite original paper submissions related to (but not limited to) the following topics:

  • Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, etc.
  • Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc.
  • Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, reconfigurable, near-data and in-memory accelerators, etc.
  • Architectural support for security, side-channel attacks and mitigation, privacy preserving computation, IoT/Cloud/Cyber-Physical-System security, security primitives, trusted execution environments, etc.
  • Architecture, microarchitecture and/or compiler optimizations for graphics processor units (GPUs) or other programmable accelerators
  • Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies
  • Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc.
  • Processor, memory, interconnect, and storage architectures
  • Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP)
  • Microarchitecture techniques to better support system software, programming languages, programmability, and compilation
  • Advanced software/hardware speculation and prediction schemes
  • Microarchitecture modeling and simulation methodology
  • Low-power, high-performance, and cost/complexity-efficient architectures
  • Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc.
  • Architecture and/or compiler optimizations for embedded processors, DSPs, ASIPs (network processors, multimedia, wireless, etc.)
  • Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads

Submissions should follow the guidelines and formatting rules specified on the conference website. Papers that violate these guidelines and rules may be returned to author(s) without review.


Call for Papers: PACT 2020
https://pact20.cc.gatech.edu
Submitted by Jiajia Li

29th International Conference on Parallel Architectures and Compilation Techniques (PACT 2020)
Atlanta, GA, USA
October 3-7 2020
https://pact20.cc.gatech.edu

Submissions Due: April 17, 2020

PACT is a long-running and unique conference at the intersection of classical parallel architectures and compilers that brings together researchers from architecture, compilers, programming languages, and applications to present and discuss their latest research results. Applications as a driver for innovations in architectures and compilers is an important theme of the conference.

We solicit contributions in a broad range of topics, including (but not limited to) the following:
* Parallel architectures and computational models
* Compilers and tools for parallel computer systems
* Multicore, multithreaded, superscalar, and VLIW architectures
* Compiler/hardware support for hiding memory latencies
* Support for correctness in hardware and software
* Reconfigurable parallel computing
* Dynamic translation and optimization
* I/O issues in parallel computing and their relation to applications
* Parallel programming languages, algorithms and applications
* Middleware and run time system support for parallel computing
* Application-specific parallel systems
* Applications and experimental systems studies of parallel processing
* Relevant aspects of distributed computing and mobile computing
* Heterogeneous systems using various types of accelerators
* Insights for the design of parallel architectures and compilers from modern parallel applications (e.g., machine learning, data analytics, and computational biology)
* Future parallel systems for beyond Moore’s law and/or beyond Exascale
* Security issues in parallel computing
* Compiler techniques for Quantum computing

Information for Authors:
Abstract deadline: April 10, 2020
Paper deadline: April 17, 2020, AOE (no extensions)
Round 1 rebuttal period: May 27 to May 29, 2020
Round 2 rebuttal: June 30 to July 2, 2020
Author notifications: July 15, 2020

Detailed instructions for electronic submission, templates, other information are posted on the Paper Submission Information page.


Call for Papers: CF 2020: ACM International Conference on Computing Frontiers
http://computingfrontiers.org/
Submitted by Salvatore Monteleone

==================================================================
ACM International Conference on Computing Frontiers 2020 (CF’20)
May 11 – 13, 2020
Catania, Sicily, Italy

Submissions Due: February 11, 2020

www.computingfrontiers.org
==================================================================

The next ACM International Conference on Computing Frontiers will be held May 11th – 13th in Sicily, Italy in the town of Catania. Computing Frontiers is an eclectic, interdisciplinary, collaborative community of researchers who investigate emerging technologies in the broad field of computing: our common goal is to drive the scientific breakthroughs that transform society.

CF’s broad scope is driven by recent technological advances in wide-ranging fields impacting computing, such as memory hardware and systems, network and systems architecture, cloud computing, novel device physics and materials, power efficiency, new application domains of machine and deep learning and big data analytics, and systems portability and wearability. The boundaries between the state-of-the-art and revolutionary innovation constitute the advancing frontiers of science, engineering, and information technology — and are the CF community focus. CF provides a venue to share, discuss and advance broad, forward-thinking, early research on the future of computing and welcomes work on a wide spectrum of computer systems, from embedded and hand-held/wearable to supercomputers and datacenters.

IMPORTANT DATES
===============

Submissions deadline: February 11th, 2020
Notification: March 15th, 2020
Camera-Ready Papers Due: April 5th, 2020
Conference Dates: May 11-13th, 2020

TOPICS OF INTEREST
==================

We seek original research contributions at the frontiers of a wide range of topics, including novel computational models and algorithms, new application paradigms, computer architecture (from embedded to HPC systems), computing hardware, memory technologies, networks, storage solutions, compilers, and environments.

* Innovative Computing Approaches, Architectures, Accelerators, Algorithms and Models
– Approximate, analog, inexact, probabilistic computing
– Quantum computing
– Neuromorphic, biologically-inspired computing and optical computing
– Dataflow architectures, near-data and in-memory processing

* Technological Scaling Limits and Beyond
– Limits: Defect- and variability-tolerant designs, graphene and other novel materials, nanoscale design, dark silicon
– Extending past Moore’s law: 3D-stacking, many-core architectures and accelerators, distributed computing on mobile devices and their challenges

* Machine Learning, Deep Learning and Big Data Analytics
– Novel architecture and systems across computing systems (IoT to datacenter)
– High performance data analytics
– Exascale data management

* Embedded, IoT and Cyber-Physical Systems
– Ultra-low power designs, energy scavenging
– Physical security, attack detection and prevention
– Reactive, real-time, scalable, reconfigurable and self-aware systems
– Sensor networks, IoT, and architectural innovation for wearable computing

* Large-Scale System Design and Networking
– Large-scale homogeneous/heterogeneous architectures and networking
– System-balance and CPU-offloading
– Power- and energy-management for clouds, datacenters and exascale systems

* System Software, Compiler Technologies and Programming Languages
– Technologies that push the limits of operating systems, virtualization, and container technologies
– Large scale frameworks for distributed computing and communication
– Resource and job management, scheduling, workflow systems for managing large-scale heterogeneous systems
– Compiler technologies: hardware/software integrated solutions, high-level synthesis
– Tools for analyzing and managing performance at large scale
– Novel programming approaches

* Fault Tolerance and Resilience
– Solutions for ultra-large and safety-critical systems (e.g. infrastructure, airlines)
– Hardware and software approaches in adverse environments such as space

* Security
– Methods, system support, and hardware for protecting against malicious code
– Real-time implementations of security algorithms and protocols
– Quantum and post-quantum cryptography

* Computers and Society
– Artificial Intelligence (AI) Ethics and AI environmental impact
– Education, health, cost/energy-efficient design, smart cities, and emerging markets, interdisciplinary applications

We strongly encourage submissions in emerging fields that may not fit into traditional categories — if in doubt, contact the PC co-chairs by email.

CONFERENCE WEBSITE
==================

http://www.computingfrontiers.org/

SUBMISSION
==========

We encourage the submission of both full and short papers containing high-quality research describing original and unpublished work.

Papers must be submitted through

https://easychair.org/conferences/?conf=cf2020

Short papers describe preliminary or highly speculative work as well as position papers. Full papers are a maximum of eight (8) (excluding references) and short papers a maximum of four (4) double-column pages (including references) in ACM conference format. Authors may buy up to two (2) extra pages for accepted full papers. Page limits include figures, tables and appendices. The review process is double-blind and removal of all identifying information from paper submissions (i.e. cite own work in third person) is required. Papers not conforming to the above submission policies on formatting, page limits and the removal of identifying information will be automatically rejected.

No-show policy: Any accepted papers are expected to be presented at the conference and at least one full registration is required from a submission author for each accepted paper. A no-show of papers will result in exclusion from the ACM digital library proceedings. If circumstances arise such that authors are unable to present their papers at the conference, they must contact the PC co-chairs.

ORGANIZATION
============

Computing Frontiers 2020 Chairs

General Co-Chairs:
Maurizio Palesi, University of Catania, IT
Gianluca Palermo, Politechnico di Milano, IT

Program Co-Chairs:
Cat Graves, Hewlett Packard Labs, US
Eishi Arima, ITC University of Tokyo, JP

FURTHER INFORMATION
===================

For further information and updates, check the CF20 website at

www.computingfrontiers.org


Call for Papers: Workshop on AI-assisted Design for Architecture (AIDArc)
https://eecs.oregonstate.edu/aidarc/
Submitted by Lizhong Chen

The 3rd International Workshop on AI-assisted Design for Architecture (AIDArc-3)
in conjunction with ISCA 2020
Valencia, Spain
May 30, 2020

Submissions Due: May 2, 2020

Given the success of AIDArc workshops in 2019 and 2018, and the significantly increased interest in utilizing AI to improve computer architecture in past years, we are thrilled to organize the 3rd AIDArc workshop in 2020, held in conjunction with ISCA-47.

Recent advancements in machine learning algorithms, fueled by increased data availability and high-performance computing infrastructure, have led to successful applications of machine learning (and AI in general) in numerous disciplines and domains. Although much attention has been drawn in the computer architecture community on accelerating machine learning, limited research has been conducted to utilize the power of AI/ML to help architects design better computer architectures and systems.

The AIDArc Workshop is intended to bring together researchers, scientists and practitioners across academia and industry, to share early discoveries, successful examples, and opinions on opportunities and challenges regarding utilizing AI to assist computer architecture designs. Research along this line may potentially transform the way computers are designed and optimized. It may also lead to interesting “self-evolving architecture”, where AI helps to speed up computers which, in turn, are used to speed up the AI.

Topics of submitted papers include, but not limited to, the exploration of artificial intelligence in assisting the design and optimization of:

– Various components of computer system architecture, e.g., branch predictor, cache, memory, I/O, interconnection networks, etc.
– Various design objectives of computer system architecture, e.g., power/energy, performance, resource, reliability, security, etc.
– Different types of computer architectures and systems, e.g., embedded/mobile/wearable devices, CPUs, GPUs, special-purpose accelerators, datacenters, HPCs, etc.
– Interaction of computer architecture with other layers, e.g., operating systems, compilers, circuit-level designs, etc.

Papers of up to 6 pages will be reviewed based on originality, novelty, technical strength, presentation quality, correctness and relevance to the workshop scope. Early but novel works on related topics are highly encouraged. Detailed submission instructions are available at the workshop https://eecs.oregonstate.edu/aidarc/

IMPORTANT DATES
Paper submission due: May 2, 2020
Notification of acceptance: May 9, 2020
Camera-ready papers due: May 23, 2020
Workshop’s date: May 30, 2020

Organizers
Lizhong Chen, Oregon State University


Call for Papers: Special issue on Chip-scale Nanonetworks
https://www.journals.elsevier.com/nano-communication-networks/call-for-papers/special-issue-on-chip-scale-nanonetworks
Submitted by Sergi Abadal

================================================
NANO COMMUNICATION NETWORKS (Elsevier, IF: 2.25)

https://www.journals.elsevier.com/nano-communication-networks  
Special issue on Chip-scale Nanonetworks:
Recent Trends, Emerging Technologies, Disruptive Applications
Submissions Due: 28 February, 2020
================================================
EDITORS
– Sergi Abadal, Universitat Politècnica de Catalunya, Spain
– Salvatore Monteleone, University of Catania, Italy
– Kun-Chih Chen, National Sun Yat-sen University, Taiwan
– Maurizio Palesi, University of Catania, Italy
================================================
IMPORTANT DATES
– Manuscript submissions due: 28 February 2020
– Notification of acceptance: 15 June 2020
– Final manuscripts due: 1 July 2020
================================================
SUBMISSION INSTRUCTIONS
Go to https://www.evise.com/profile/api/navigate/NANOCOMNET and choose “VSI: Chip-Scale Nanonetworks” when submitting
================================================
Aims and Scope
Recent years have witnessed the emergence of computing architectures that integrate up to a thousand processor cores and memory on a single die as a result of relentless semiconductor device scaling. This opens up a plethora of architectural challenges in terms of efficiency or specialization, among others, and supports the spread of various applications and novel computational paradigms, ranging from massive manycore processing to reconfigurable, quantum, in-memory, or neuromorphic computing.As a side effect of such wild increase in integration, communication (and not computation) has gradually become the main determinant of performance in nowadays computers. To address this, processors integrate interconnection networks that manage the movement of data in a scalable and cost-effective manner at the chip scale, i.e., for ranges between hundreds of nanometers to a few millimeters. The main challenge is for these chip-scale nanonetworks to provide the efficiency, versatility, scalability and reliability necessary to tackle the growing technological, architectural and workload heterogeneity in this new era of computing.The special issue seeks contributions addressing the different challenges of chip-scale nanocommunications and networking, putting emphasis on emerging technologies (e.g., wireless, RF interconnects, optics), new approaches (e.g., approximate computing, machine-learning-based design) and disruptive applications (e.g., quantum computers). The editors equally welcome submissions about physical prototypes realizable in the near future and more prospective contributions with clear longer-term potential. While the scope of the special issue revolves around communications and networking aspects, submissions discussing frontier aspects such as memory architectures, 2.5D/3D packages, or application mapping are also welcome.Topics of Interest
The special issue solicits high-quality and original contributions on topics including, but not limited to:

  • Wireless chip-scale nanonetworks: mmWave-THz channel models, on-chip antenna design, transceiver implementation, MAC protocols, graphene-based wireless designs, wireless manycore architectures, hybrid wired-wireless nanonetworks.
  • Nanophotonic chip-scale nanonetworks: integrated nanophotonic component design, laser integration, novel network architectures, thermal-aware design, optical-wireless channel modeling.
  • Integrated 2.5D/3D nanonetworks: stacked and monolithic 3D Network-on-Chip (NoC), TSV placement, TSV-aware topologies, off-chip communication in interposer-based systems
  • Machine learning (ML) and chip-scale nanonetworks: Interconnects for ML systems/accelerators, Memory access for the nanonetwork-based ML systems, interconnect-centric ML algorithm design.
  • Communication within quantum computers: qubit mapping, SWAP-aware routing algorithms, qubit shuttling and swapping mechanisms, multi-chip quantum architectures.
  • Approximate computing for NoC and NoC-based systems: approximate communication in on-chip networks, approximate computing-communications interplay, adaptive error control.
  • NoC in emerging architectures/applications: NoCs for FPGAs, ASICs, heterogeneous systems; neural network accelerators, massive manycore processors, neuromorphic (spike-based) computers, software-defined metamaterials, programmable matter.
  • Extreme embedded nano-systems: real-time, mission-critical, intermittent computing, energy-harvesting-based embedded networks.
  • Quantum Cellular Automata: integrated communication modules, prototypes, QCA-network-on-chip.
  • NoC architecture and implementation: impact of novel technologies to topologies, routing, flow control, QoS management, reliability, security, design methodologies and tools, application mapping. Real and industrial NoC case studies. Thermal-aware routing, multicast and broadcast in manycore processors.

Call for Presentations: Persistent Programming in Real Life 2020
http://pirl.nvsl.io/pirl2020
Submitted by Steven Swanson

Persistent Programming in Real Life (PIRL)
University of California, San Diego, USA
July 13-14, 2020

Proposal Deadline:  June 1st, 2020

You are invited to propose a presentation at the second annual Persistent Programming in Real Life (PIRL).  PIRL brings together software development leaders interested in learning about programming methodologies for persistent memories and sharing their experiences with others.

OVERVIEW

This is a meeting for developer project leads on the front lines of persistent programming, not sales, marketing, or non-technical management. Tell us about what you have done (and want to do) with persistent memory, what worked, what didn’t, what was hard, what was easy, what was surprising, and what did you learn? How can others learn from your experience?

PIRL is small.  We are limiting attendance this year to under 150 people, including speakers.  There will be lots of time for informal discussion and networking. If you would like to present at PIRL, fill out this form.  For instance,  a proposal might include:

• What you did or are trying to do.
• Your experience, and the lessons others can learn from it.
• We expect to see code!

We welcome talks that describe new tools, but we are not interested in sales pitches.  Attendees should come away from every session with actionable information that can be utilized to use persistent memory more effectively.

PRESENTATION FORMAT

We are open to many different kinds of talks.  Possibilities include:

• Talks about experiences on a particular project
• Potentially develop or write code live or provide samples during the presentation.

PIRL will be hosted by the Non-Volatile Systems Laboratory at the University of California, San Diego.  It will be held at Scripps Forum on July 13th to 14th, 2020, with optional events starting July 12th.

CO-LOCATING WORKING MEETINGS WITH PIRL

This year, PIRL is hosting working meetings for persistent-memory related projects. If you’re involved in such a project, we’d love to have you hold your face-to-face near the beach at PIRL.  Members of your group (e.g., core developers of persistent memory software project) could attend PIRL and a group meeting before or after the conference.

UC San Diego and the Non-Volatile Systems Laboratory can provide meeting space hosted and sponsored by SNIA for eligible working groups. In return, we just ask that all the attendees register for PIRL. We would prefer that the meeting be open to other PIRL attendees, but this is not a requirement.  We are accepting submissions today. If you are interested, please fill out this form, and select “group meeting” as the presentation type.

KEY DATES

• Presentation proposal deadline:  June 1st (midnight, AOE)
• Selected presenters notified:  June 15th.
• PIRL Meeting: July 13-14

MORE DETAILS

Watch the PIRL Blog (http://pirl.nvsl.io) or follow us on twitter @pirlconf for more details about PIRL 2020 as they become available. If you have any questions, please contact Steven Swanson (swanson@cs.ucsd.edu).


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SIGARCH Content Editor

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