This is the 1st January 2019 digest of SIGARCH Messages.

In This Issue

Call for Nominations: SIGARCH Executive Committee Elections

Submitted by Sarita Adve

Call for Nominations for SIGARCH Executive Committee Elections

The SIGARCH elections nominating committee invites nominations (including self-nominations) for candidates to serve on the SIGARCH Executive Committee (EC). The nominating committee will select the final slate of candidates for elections to be held according to ACM rules. The initial term for the EC is for two years, beginning July 1, 2019, with a possible extension for another two years.

The EC positions are:
Board of Directors (4 members)

The SIGARCH EC is a working committee where each member is responsible for at least one substantive project in the service of the architecture community. In addition to overseeing our rich portfolio of conferences and awards, the current EC initiated many new initiatives such as the Computer Architecture Today blog, lightning mentoring sessions, the CARES committee, the dissertation award, the visioning workshops, and more – see the last SIGARCH annual report for the portfolio of current activities. Joining the SIGARCH EC therefore requires a significant time commitment in exchange for an opportunity to make an impact on our community and enjoy a rewarding service experience.

The nominating committee will select the final slate of candidates based on enthusiasm, vision, past record of service (commensurate with seniority), and multiple dimensions of diversity.

Please submit a nomination with the following information to by 5pm CST January 10, 2019.
– Name, affiliation, and email address of the nominee.
– Position sought (chair/vice-chair/treasurer/director).
– Previous significant service to SIGARCH and ACM.
– Other significant service and relevant experience.
– A brief biography or curriculum vitae.
– Recent institutional affiliations.
– Areas of research expertise within computer architecture.
– A brief statement from the nominee (e.g., 150 words) in support of the nomination; e.g., a description of their ideas and commitment if elected.

All final candidates must be professional ACM members and SIGARCH members by the time of final selection.

The nominating committee consists of current and past SIGARCH chairs: Sarita Adve (chair), Norm Jouppi, David Wood.

Call for Participation: Workshop on ACM SIG Heritage

Submitted by Sarita Adve

Workshop on ACM SIG Heritage
Minneapolis, Minnesota, USA
May 20-21, 2019

The Association for Computing Machinery, founded in 1947, is the oldest and largest educational and scientific society dedicated to the computing profession, and today has more than 100,000 members around the world. The ACM History Committee is sponsoring a SIG Heritage workshop to help diffuse knowledge of professional archival practices into ACM’s membership and to others with an active interest in preserving our computer heritage/history.

Applications are invited to a one-and-a-half day workshop to be held 20-21 May 2019 at the Charles Babbage Institute (CBI) in Minneapolis, Minnesota. For each successful application, one person’s expenses for workshop travel, lodging, and meals will be paid by the ACM History Committee.

This is a hands-on workshop with detailed examples. The workshop will be kept small to maximize hands-on aspects and personal interaction. At most 20 attendees.

Who should attend?
ACM members and others who are planning or actually doing SIG history/heritage (archiving/documentation/oral history/publishing) projects. The workshop should be of special interest to ACM officers and staff, SIG leaders, historically minded ACM members, and others working on SIG history projects. Priority will be given to ACM members and members of other national computer societies affiliated to the ACM, but others who are actively engaged in preserving ACM SIG-related history are also encouraged to apply.

Workshop activities include:
a) presentations on basic SIG history preservation, including identification, ACM support, priorities, assessment, and example projects; privacy and legal issues; preparing for public deposit
b) hands-on individual exploration of CBI holdings, including ACM records
c) short presentations on each attendee’s SIG heritage project/plans, with group discussion
d) CBI archival cavern tour
e) ample networking time, including lunches and workshop dinner

Participants will leave with a “tool kit” of practical, useful procedures as well as insight into other SIG heritage techniques, projects, and practices.

Applicants should send a 2-page CV as well as a 250-word project description that
– explains the significance of the existing or planned archiving/history project and its importance;
– describes the archiving/history project’s raw materials including types of images, documents, reports, publications, oral histories (including format of digital materials)
– affirms the applicant’s willingness to make a short presentation to the workshop and participate fully in its day and a half agenda

The ACM History Committee will fund accepted invitees (travel, hotel, meals).

Applications are due by February 1, 2019.
Applications should be submitted as a single pdf-format document to Notification of project acceptance will be made within six weeks.

Questions about the workshop or requests for clarification may be directed, at any time, to

Call for Papers: Workshop on High-Level Parallel Programming Models and Supportive Environments
Submitted by Changhee Jung

24th International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS 2019)
in conjunction with IPDPS 2019
Rio de Janeiro, Brazil
May 20, 2019

The 24th HIPS workshop, to be held as a full-day meeting on May 20th at the IEEE IPDPS 2019 conference in Rio de Janeiro, Brazil, focuses on high-level programming of multiprocessors, compute clusters, and massively parallel machines. Like previous workshops in the series, which was established in 1996, this event serves as a forum for research in the areas of parallel applications, language design, compilers, runtime systems, and programming tools. It provides a timely and lightweight forum for scientists and engineers to present the latest ideas and findings in these rapidly changing fields. In our call for papers, we especially encouraged innovative approaches in the areas of emerging programming models for large-scale parallel systems and many-core architectures.

– Programming models for heterogeneous compute capabilities and deep memories
– Languages and runtime support for multi-science/coupled codes
– New programming languages and constructs for exploiting parallelism/locality
– Experience with and improvements for existing parallel languages and run-time environments such as MPI, OpenMP, Cilk, UPC, Co-array Fortran, X10, Chapel, Charm++, and OpenCL
– Parallel compilers, programming tools, and environments
– Parallelism in emerging fields such as analytics, cloud, and machine learning
– (Scalable) tools for power & performance analysis, modeling, monitoring, and debugging and core correctness
– OS and architectural support for parallel programming and debugging
– Software and system support for extreme scalability including fault tolerance and power-aware HPC
– Programming environments for heterogeneous multicore systems and accelerators such as GPUs, FPGAs, and MICs
– Performance portability in heterogeneous parallel programming environment
– Performance Reproducibility in HPC: tools for quantifying and minimizing performance variability

HIPS 2019 accepts two types of submissions:

1. Full papers (10 pages max)
Submission deadline: Jan 22, 2019
Notification of acceptance: Feb 8, 2019
Camera-ready papers due: Feb 26, 2019

2. Short papers (4 pages max)
Submission deadline: Jan 29, 2019
Notification of acceptance: Feb 19, 2019
Camera-ready papers due: Feb 26, 2019

Submissions are handled through the EasyChair conference management system:

More information at

Workshop Co-chairs:
Neha Gholkar, Intel – Santa Clara, CA
Changhee Jung, Virginia Tech – Blacksburg, VA

Program Committee:
Sriram Krishnamoorthy, Pacific Northwest National Laboratory
Devesh Tiwari, Northeastern University
Barry Rountree, Lawrence Livermore National Laboratory
Qingrui, Liu Xilinx
Simone Atzeni, NVIDIA
Pedro Valero-Lara, The University of Manchester
Xu Liu, College of William and Mary
Shuaiwen Song, Pacific Northwest National Laboratory
Bin Ren, College of William and Mary
Seyong Lee, Oak Ridge National Laboratory
Dongyoon Lee, Virginia Tech
Joachim Protze, RWTH Aachen University
Thomas Scogland, Lawrence Livermore National Laboratory
Yun Liang, Peking University
Ryan Grant, Sandia National Laboratories
Tapasya Patki, Lawrence Livermore National Laboratory
Allen Malony, University of Oregon
Uday Khedker, IIT Bombay
Mitsuhisa Sato, RIKEN
Mark Hoemmen, Sandia National Laboratories

Call for Papers: Embedded Systems Week 2019
Submitted by Lars Bauer

Embedded Systems Week (ESWEEK)
New York City, USA,
October 13 – 18, 2019

Embedded Systems Week (ESWEEK) is the premier event covering all aspects of embedded systems and software. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), a special IoMT Day, a symposium (NOCS), and hot-topic workshops and tutorials, ESWEEK presents attendees a wide range of topics unveiling the state of the art in embedded systems design and HW/SW architectures.

Registered attendees are entitled to attend sessions of all conferences CASES, CODES+ISSS, EMSOFT, and the IoMT Day. Symposia, workshops, and tutorials require separate registration.

Journal Track:
– Abstract Submission: April 5, 2019
– Full Paper Submission: April 12, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Work-in-Progress Track:
– Paper Submission: June 7, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Workshop Proposals: April 18, 2019
Tutorial Proposals: April 30, 2019
Special Session Proposals: April 30, 2019

ESWEEK 2019 continues a dual publication model comprising the Journal track and the Work-in-Progress (WiP) track. Journal track papers, which are full-length (10-page) papers describing mature work, will be published in the ACM Transactions on Embedded Computing Systems (TECS). The WiP track papers, which are short (2-page) papers representing not-yet-mature but promising research, will be published in the ESWEEK proceedings and will be listed as regular publications within the IEEE and/or ACM digital libraries. Authors of WiP papers have the opportunity to publish the extended form of their work in any conference or journal they prefer. Journal and WiP papers are mutually exclusive, i.e., a work can only be in submission in one of the two tracks.
For more information, please refer to:

* CASES: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
CASES is a premier forum where researchers, developers and practitioners exchange information on the latest advances in compilers and architectures for high-performance, low-power embedded systems. The conference has a long tradition of showcasing leading edge research in embedded processor, memory, interconnect, storage architectures and related compiler techniques targeting performance, power, predictability, security, reliability issues for traditional and emerging applications. In addition, we invite innovative papers that address design, synthesis, and optimization in heterogeneous and accelerator-rich architectures.

CASES Program Chairs:
Akash Kumar, Technical University of Dresden, DE
Partha Pande, Washington State University, US

* CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis
The International Conference on Hardware/Software Codesign and System Synthesis is the premier event in system-level design, modeling, analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hardware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design. High-quality original papers will be accepted for oral presentation followed by interactive poster sessions.

CODES+ISSS Program Chairs:
Sudeep Pasricha, Colorado State University, US
Roman Lysecky, Arizona State University, US

* EMSOFT: International Conference on Embedded Software
The ACM SIGBED International Conference on Embedded Software (EMSOFT) brings together researchers and developers from academia, industry, and government to advance the science, engineering, and technology of embedded software development. Since 2001, EMSOFT has been the premier venue for cutting-edge research in the design and analysis of software that interacts with physical processes, with a long-standing tradition for results on cyber-physical systems, which compose computation, networking, and physical dynamics.

EMSOFT Program Chairs:
Sriram Sankaranarayanan, University of Colorado Boulder, US
Timothy Bourke, Inria Paris, FR

* IoMT: Internet of Medical Things
The Internet of Medical Things (IoMT) paves the foundations for intelligent and reliable personalized precision medicine. Grounded in the mathematical and physical modeling of human anatomy and physiology, it offers accurate multiscale medical monitoring through smart sensing, enabling continuous diagnosis via on-fly communication with medical experts. It provides hyperspectral and hyperdimensional processing and restores health through patient-specific actuation. The IoMT special day provides a forum for academic and industry representatives from areas such as medical and bio-engineering and embedded systems to discuss innovative ideas and solutions for precise personalized medicine. Sub-missions to the IoMT day are via the three conferences.

IoMT Chairs:
Insup Lee, University of Pennsylvania, US
Paul Bogdan, University of Southern California, US

* Call for Workshop Proposals
ESWEEK 2019 will host several workshops on Oct. 17/18th. ESWEEK workshops are excellent opportunities to bring together researchers and practitioners from different communities to share their experiences in an interactive atmosphere.
We invite you to submit workshop proposals on any topic related to the broad set of research, education, and application areas in embedded systems before the deadline of April 18, 2019.

Workshop Chair:
Laura Pozzi, USI Lugano, CH

* Call for Tutorial Proposals
ESWEEK 2019 is looking for high-quality tutorials that will take place on Oct. 13th. Tutorials offer a unique opportunity where presenters can interact with attendees and attendees can gain in-depth knowledge on specific topics. Tutorials on all topics related to embedded system design, analysis and development are welcome and can be either half or full day, lecture style or hands on.
We invite you to submit tutorial proposals before the deadline of April 30, 2019.

* Call for Special Session Proposals
ESWEEK 2019 will host several special sessions. They should cover hot, contemporary topics that are complementary to regular sessions and can constitute individual presentations, panels or other formats. Participants of each accepted special session will have the opportunity to co-author an overview paper (maximum 10 pages) of the session, published in the ESWEEK proceedings. We invite you to submit special session proposals on any topic related to the broad areas of interest of the conference or beyond before the deadline of April 30, 2019.

Tutorials and Special Sessions Chair:
Andreas Gerstlauer, University of Texas Austin, US

Petru Eles, Linköping University, SE
Tulika Mitra, National University of Singapore, SG (Vice General Chair)
Soonhoi Ha, Seoul National University, KR (Past Chair)

ESWEEK Local Arrangement Chairs:
Ramesh Karri, New York University, US
Siddarth Garg, New York University, US

Call for Papers: GPGPU 2019
Submitted by Ashutosh Pattnaik

12th Workshop on General Purpose Processing Using GPU (GPGPU 2019)
in conjunction with ASPLOS 2019
Providence, RI, USA
April 13, 2019

Papers due: January 21, 2019
Notification: February 18, 2019
Final paper due: March 1, 2019

The goal of this workshop is to provide a forum to discuss new and emerging general-purpose programming architectures, environments, and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. This year’s workshop is particularly interested in security, new heterogeneous architecture or platforms, new forms of concurrency, and novel or irregular applications that can leverage these platforms.

Papers are being sought on many aspects of GPUs or accelerators, including (but not limited to):
– GPU applications
– GPU programming environments
– GPU runtime systems
– GPU compilation
– GPU architectures
– Multi-GPU systems
– GPU power/efficiency
– GPU reliability
– GPU benchmarking/measurements
– Heterogeneous architectures/platforms
– GPU security (NEW)
– Non-von Neumann architectures (NEW)
– Domain-specific architectures (NEW)

Full paper submissions must be in PDF format for US letter-size paper. They must not exceed 10 pages (all inclusive) in standard ACM two-column conference format (preprint mode, with page number). Templates for ACM format are available for Microsoft Word, and LaTeX can be found here. The submission site will be up soon.

Adwait Jog (co-chair), College of William & Mary
Onur Kayiran (co-chair), AMD Research
Ashutosh Pattnaik (submission/web chair), Penn State

Please contact the organizers if you have any questions.

David Kaeli (Northeastern) and John Cavazos (Delaware) very successfully organized the previous versions of the GPGPU workshop. GPGPU workshop was first held in 2007 at Northeastern University. In 2008, the meeting was held with ASPLOS 2008. This trend continued and the GPGPU workshop was held with ASPLOS for the next 6 years. From 2015 and 2018, GPGPU workshop was co-located with PPoPP. GPGPU 2019 workshop returns to ASPLOS. The average citation count (as per Google Scholar), for a GPGPU workshop paper, is currently 37.5, where there have been 8 influential papers with 100+ citations.

Call for Papers: SELSE 2019
Submitted by Michael Sullivan

The 15th IEEE Workshop on Silicon Errors in Logic – System Effects
Stanford, Palo Alto, CA, USA
March 27 – March 28, 2019

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high-performance applications.

The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.

We are happy to announce that selected SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Portland, Oregon on June 24 – 27, 2019.

Key areas of interest include (but are not limited to):
– Error rates and trends in current and emerging technologies, including experimental failure data and the reliability characterization of deployed systems.
– New error mitigation techniques, robust software frameworks, and error handling protocols for resilient system design.
– Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.
– Resilience characterization and strategies for machine learning applications, including autonomous vehicles.
– Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.
– The design of resilient systems for space exploration.
– The interplay between system security issues and reliability.

Additional information and guidelines for submission are available at Submissions and final papers should be PDF files following the IEEE two-column transactions format with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries—however, they are distributed to attendees of the workshop.

Call for Presentations: ASPLOS 2019 Student Research Competition
Submitted by Jishen Zhao

The 24rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
Providence, RI, USA
April 13-17, 2019

Abstract submission: Friday, December 21, 2018 (11:59pm PST)
Acceptance notification: Friday, Feb 2, 2019

The 24rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) invites participation in the ACM Student Research Competition (SRC). Sponsored by ACM and Microsoft Research, the SRC is a forum for undergraduates and graduate students to share their research results, exchange ideas, and improve their communication skills while competing for prizes. Students accepted to participate in the SRC are entitled to a travel grant (up to $500) to help cover travel expenses. The top 3 undergraduate and graduate winners will receive all of the following prizes:

1. Monetary prizes of $500, $300, and $200, respectively.

2. An award medal (gold, silver or bronze) and a one-year complimentary ACM membership with a subscription to ACM’s Digital Library.

3. The names of the winners and their placement will be posted on the ACM SRC web site.

4. In addition, the first place winner in each category (undergraduate, graduate) will receive an invitation to participate in the SRC Grand Finals, an on-line round of competitions among the first place winners of individual conference-hosted SRCs. The top three graduate and undergraduate Grand Finalists will receive an additional $500, $300, and $200, respectively, along with Grand Finalist medals (gold, silver, bronze). Grand Finalists and their advisors will be invited to the Annual ACM Awards Banquet for an all-expenses-paid trip, where they will be recognized for their accomplishments, along with other prestigious ACM award winners, including the winner of the Turing Award.

The SRC consists of two rounds: a poster session and a presentation session. A panel of judges will select a number of finalists from the poster session, who will be invited to the presentation session at ASPLOS 2018 and compete for the prizes. The evaluation will be concentrated on the quality of both visual and oral presentation, the research methods, and the significance of contribution. You can find more information on the ACM Student Research Competition site.

A participant in the SRC must meet all following conditions:
– The participant must submit an up to 800-word abstract outlining the content of a poster that is going to be presented during the competition.
– The abstract must include the poster title, author names, affiliations, and the name of the academic advisor.
– It should describe the research problem, motivation and background, techniques and results, and the prospect for clearly and concisely conveying the work in a poster format.
– It should state the novelty and contributions of the work explicitly.
– The abstract must have not appeared before. Novelty is one of the criteria for selection.
– The abstract and the poster must be authored solely by the participant.
– The participant can be from anywhere in the world, but must be an ACM student member, and must maintain an undergraduate or graduate student status as of December 8th, 2018.
– In your submission, please indicate whether you are an undergraduate or a graduate student.
– You may join ACM prior to entering. Basic student membership is $19 per year or less
– The submission deadline is December 8th, 2018 at 23:59 PST.

For each accepted SRC poster, a one-page extended abstract in the ACM format will be included in the ASPLOS 2019 conference proceedings. The content, however, can be included in a future submission to other conferences or journals.

Extended abstracts of up to 800 words should be submitted through the following link on or before December 8, 2017:

The ACM Student Research Competition at ASPLOS 2019 is sponsored by the ACM and Microsoft Research.

SRC Chairs:
Yufei Ding, University of California, Santa Barbara
Linhai Song, The Pennsylvania State University

SRC Committee:
Shuaiwen (Leon) Song, PNNL & William Mary
Yufei Ding, University of California, Santa Barbara
Linhai Song, The Pennsylvania State University
Dorian Arnold, Emory University
Hung-Wei Tseng, North Carolina State University
Jiajia Li, Georgia Institute of Technology
Amanda Randles, Duke University
Daniel Wong, University of California, Riverside
Dongyoon Lee, Virginia Tech
Ang Li, Pacific Northwest National Lab
Huiyang Zhou, North Carolina State University
Kathryn Mohror, Lawrence Livermore National Laboratory
Xiaochen Guo, Lehigh University
Aparna Chandramowlishwaran, University of California, Irvine
Yingyan Lin, Rice University
Jishen Zhao, University of California, San Diego
Yuxiong He, Microsoft

AutomataZoo: a Benchmark Suite for Automata Processing
Submitted by Tommy Tracy II


High performance automata processing engines are traditionally evaluated against a limited set of regular expression rulesets. These serve as valid, real-World example use cases, but they only represent a small proportion of all automata-based applications. With the recent availability of architectures and software frameworks for automata processing, many new applications have been discovered that benefit from automata processing. These demonstrate a broad variety of characteristics that differ from prior regular expression-based applications and warrant their own benchmarks.

We released an earlier benchmark suite, ANMLZoo, in 2016 to fulfill this need. We have improved upon ANMLZoo with AutomataZoo [Wadden et al., IISWC 2018] in the following ways:

– The suite of benchmarks is no longer standardized to a particular architecture, and does not inherit the same architectural biases as ANMLZoo.
– The benchmarks implement full kernels, which allows for comparisons between automata and non-automata approaches.
– The suite includes open-source tools for generating benchmark automata and inputs of various sizes, allowing for design space explorations.

– Snort: A widely used network intrusion detection system.
– ClamAV: A virus-detection tool that relies on a publicly-available database of malware patterns.
– Protomata: An automata-based application that searches for a set of 1309 protein motif patterns from the PROSITE database.
– Brill Tagging: A rule-based approach to part-of-speech tagging.
– Random Forest: A machine learning model based on ensembles of decision trees.
– Hamming Distance: A string-scoring kernel that accepts inputs that are within a set hamming distance of a configured pattern.
– Levenshtein Distance: A string-scoring kernel that accepts inputs that are within a set edit distance of a configured pattern.
– Sequence Matching: An automata application that counts sorted sequences of item sets to identify frequently-occurring sets.
– Entity Resolution: An automata application that attempts to find duplicate entries in a streaming database.
– CRISPR/Cas9: An automata application that enabled gene editing by identifying targeted locations.
– YARA: An automata application that discovers malware described in the YARA malware pattern description language.
– File Carving: An automata application that identifies files in a stream of input bytes.
– Pseudo Random Number Generation (PRNG): An automata application that models Markov Chains with finite automata to generate high-throughput PRNG streams.

The benchmark suite can be found here:

[Wadden et al., IISWC 2018] Wadden, J., Tracy II, T., Sadredini, E., Wu, L., Bo, C., Du, J., Wei, Y., Wallace, M., Udall, J., Stan, M., and Skadron, K. “ANMLZoo: A Benchmark Suite for Exploring Bottlenecks in Automata Processing Engines and Architectures.” 2018 IEEE International Symposium on Workload Characterization (IISWC’18). IEEE, 2018.

We hope this new benchmark suite will fulfill your current and future research efforts related to automata computing.

Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the SIGARCH Blog.

- Boris Grot
SIGARCH Content Editor