Call for Papers: Workshop on High-Level Parallel Programming Models and Supportive Environments
http://hosting.cs.vt.edu/hips2019/
Submitted by Changhee Jung

24th International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS 2019)
in conjunction with IPDPS 2019
Rio de Janeiro, Brazil
May 20, 2019

The 24th HIPS workshop, to be held as a full-day meeting on May 20th at the IEEE IPDPS 2019 conference in Rio de Janeiro, Brazil, focuses on high-level programming of multiprocessors, compute clusters, and massively parallel machines. Like previous workshops in the series, which was established in 1996, this event serves as a forum for research in the areas of parallel applications, language design, compilers, runtime systems, and programming tools. It provides a timely and lightweight forum for scientists and engineers to present the latest ideas and findings in these rapidly changing fields. In our call for papers, we especially encouraged innovative approaches in the areas of emerging programming models for large-scale parallel systems and many-core architectures.

Topics:
– Programming models for heterogeneous compute capabilities and deep memories
– Languages and runtime support for multi-science/coupled codes
– New programming languages and constructs for exploiting parallelism/locality
– Experience with and improvements for existing parallel languages and run-time environments such as MPI, OpenMP, Cilk, UPC, Co-array Fortran, X10, Chapel, Charm++, and OpenCL
– Parallel compilers, programming tools, and environments
– Parallelism in emerging fields such as analytics, cloud, and machine learning
– (Scalable) tools for power & performance analysis, modeling, monitoring, and debugging and core correctness
– OS and architectural support for parallel programming and debugging
– Software and system support for extreme scalability including fault tolerance and power-aware HPC
– Programming environments for heterogeneous multicore systems and accelerators such as GPUs, FPGAs, and MICs
– Performance portability in heterogeneous parallel programming environment
– Performance Reproducibility in HPC: tools for quantifying and minimizing performance variability

SUBMISSION GUIDELINES:
HIPS 2019 accepts two types of submissions:

1. Full papers (10 pages max)
Submission deadline: Jan 22, 2019
Notification of acceptance: Feb 8, 2019
Camera-ready papers due: Feb 26, 2019

2. Short papers (4 pages max)
Submission deadline: Jan 29, 2019
Notification of acceptance: Feb 19, 2019
Camera-ready papers due: Feb 26, 2019

Submissions are handled through the EasyChair conference management system:
https://www.easychair.org/conferences/?conf=hips2019

More information at http://cs.vt.edu/hips2019/

ORGANIZERS:
Workshop Co-chairs:
Neha Gholkar, Intel – Santa Clara, CA
Changhee Jung, Virginia Tech – Blacksburg, VA

Program Committee:
Sriram Krishnamoorthy, Pacific Northwest National Laboratory
Devesh Tiwari, Northeastern University
Barry Rountree, Lawrence Livermore National Laboratory
Qingrui, Liu Xilinx
Simone Atzeni, NVIDIA
Pedro Valero-Lara, The University of Manchester
Xu Liu, College of William and Mary
Shuaiwen Song, Pacific Northwest National Laboratory
Bin Ren, College of William and Mary
Seyong Lee, Oak Ridge National Laboratory
Dongyoon Lee, Virginia Tech
Joachim Protze, RWTH Aachen University
Thomas Scogland, Lawrence Livermore National Laboratory
Yun Liang, Peking University
Ryan Grant, Sandia National Laboratories
Tapasya Patki, Lawrence Livermore National Laboratory
Allen Malony, University of Oregon
Uday Khedker, IIT Bombay
Mitsuhisa Sato, RIKEN
Mark Hoemmen, Sandia National Laboratories

Call for Papers: Embedded Systems Week 2019
https://www.esweek.org
Submitted by Lars Bauer

Embedded Systems Week (ESWEEK)
New York City, USA,
October 13 – 18, 2019

Embedded Systems Week (ESWEEK) is the premier event covering all aspects of embedded systems and software. By bringing together three leading conferences (CASES, CODES+ISSS, EMSOFT), a special IoMT Day, a symposium (NOCS), and hot-topic workshops and tutorials, ESWEEK presents attendees a wide range of topics unveiling the state of the art in embedded systems design and HW/SW architectures.

Registered attendees are entitled to attend sessions of all conferences CASES, CODES+ISSS, EMSOFT, and the IoMT Day. Symposia, workshops, and tutorials require separate registration.

IMPORTANT DATES:
Journal Track:
– Abstract Submission: April 5, 2019
– Full Paper Submission: April 12, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Work-in-Progress Track:
– Paper Submission: June 7, 2019 (firm)
– Notification of Acceptance: July 10, 2019

Workshop Proposals: April 18, 2019
Tutorial Proposals: April 30, 2019
Special Session Proposals: April 30, 2019

SUBMISSION GUIDELINES:
ESWEEK 2019 continues a dual publication model comprising the Journal track and the Work-in-Progress (WiP) track. Journal track papers, which are full-length (10-page) papers describing mature work, will be published in the ACM Transactions on Embedded Computing Systems (TECS). The WiP track papers, which are short (2-page) papers representing not-yet-mature but promising research, will be published in the ESWEEK proceedings and will be listed as regular publications within the IEEE and/or ACM digital libraries. Authors of WiP papers have the opportunity to publish the extended form of their work in any conference or journal they prefer. Journal and WiP papers are mutually exclusive, i.e., a work can only be in submission in one of the two tracks.
For more information, please refer to: https://www.esweek.org/author-information

* CASES: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
CASES is a premier forum where researchers, developers and practitioners exchange information on the latest advances in compilers and architectures for high-performance, low-power embedded systems. The conference has a long tradition of showcasing leading edge research in embedded processor, memory, interconnect, storage architectures and related compiler techniques targeting performance, power, predictability, security, reliability issues for traditional and emerging applications. In addition, we invite innovative papers that address design, synthesis, and optimization in heterogeneous and accelerator-rich architectures.
https://esweek.org/sites/default/files/2019-CASES-cfp_0.pdf

CASES Program Chairs:
Akash Kumar, Technical University of Dresden, DE
Partha Pande, Washington State University, US

* CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis
The International Conference on Hardware/Software Codesign and System Synthesis is the premier event in system-level design, modeling, analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hardware/software implementations. The conference is a forum bringing together academic research and industrial practice for all aspects related to system-level and hardware/software co-design. High-quality original papers will be accepted for oral presentation followed by interactive poster sessions.
https://esweek.org/sites/default/files/CODES%2BISSS-2019-CFP.pdf

CODES+ISSS Program Chairs:
Sudeep Pasricha, Colorado State University, US
Roman Lysecky, Arizona State University, US

* EMSOFT: International Conference on Embedded Software
The ACM SIGBED International Conference on Embedded Software (EMSOFT) brings together researchers and developers from academia, industry, and government to advance the science, engineering, and technology of embedded software development. Since 2001, EMSOFT has been the premier venue for cutting-edge research in the design and analysis of software that interacts with physical processes, with a long-standing tradition for results on cyber-physical systems, which compose computation, networking, and physical dynamics.
https://esweek.org/sites/default/files/EMSOFT2019_CfP_0.pdf

EMSOFT Program Chairs:
Sriram Sankaranarayanan, University of Colorado Boulder, US
Timothy Bourke, Inria Paris, FR

* IoMT: Internet of Medical Things
The Internet of Medical Things (IoMT) paves the foundations for intelligent and reliable personalized precision medicine. Grounded in the mathematical and physical modeling of human anatomy and physiology, it offers accurate multiscale medical monitoring through smart sensing, enabling continuous diagnosis via on-fly communication with medical experts. It provides hyperspectral and hyperdimensional processing and restores health through patient-specific actuation. The IoMT special day provides a forum for academic and industry representatives from areas such as medical and bio-engineering and embedded systems to discuss innovative ideas and solutions for precise personalized medicine. Sub-missions to the IoMT day are via the three conferences.
https://esweek.org/iomt/about

IoMT Chairs:
Insup Lee, University of Pennsylvania, US
Paul Bogdan, University of Southern California, US

* Call for Workshop Proposals
ESWEEK 2019 will host several workshops on Oct. 17/18th. ESWEEK workshops are excellent opportunities to bring together researchers and practitioners from different communities to share their experiences in an interactive atmosphere.
We invite you to submit workshop proposals on any topic related to the broad set of research, education, and application areas in embedded systems before the deadline of April 18, 2019.
https://esweek.org/sites/default/files/ESWEEK2019_CfP_1.pdf

Workshop Chair:
Laura Pozzi, USI Lugano, CH

* Call for Tutorial Proposals
ESWEEK 2019 is looking for high-quality tutorials that will take place on Oct. 13th. Tutorials offer a unique opportunity where presenters can interact with attendees and attendees can gain in-depth knowledge on specific topics. Tutorials on all topics related to embedded system design, analysis and development are welcome and can be either half or full day, lecture style or hands on.
We invite you to submit tutorial proposals before the deadline of April 30, 2019.

* Call for Special Session Proposals
ESWEEK 2019 will host several special sessions. They should cover hot, contemporary topics that are complementary to regular sessions and can constitute individual presentations, panels or other formats. Participants of each accepted special session will have the opportunity to co-author an overview paper (maximum 10 pages) of the session, published in the ESWEEK proceedings. We invite you to submit special session proposals on any topic related to the broad areas of interest of the conference or beyond before the deadline of April 30, 2019.
https://esweek.org/sites/default/files/ESWEEK2019_CfP_1.pdf

Tutorials and Special Sessions Chair:
Andreas Gerstlauer, University of Texas Austin, US

ESWEEK ORGANIZERS:
Petru Eles, Linköping University, SE
Tulika Mitra, National University of Singapore, SG (Vice General Chair)
Soonhoi Ha, Seoul National University, KR (Past Chair)

ESWEEK Local Arrangement Chairs:
Ramesh Karri, New York University, US
Siddarth Garg, New York University, US

www.esweek.org

Call for Papers: GPGPU 2019
https://insight-archlab.github.io/gpgpu.html
Submitted by Ashutosh Pattnaik

12th Workshop on General Purpose Processing Using GPU (GPGPU 2019)
in conjunction with ASPLOS 2019
Providence, RI, USA
April 13, 2019

IMPORTANT DATES:
Papers due: January 21, 2019
Notification: February 18, 2019
Final paper due: March 1, 2019

The goal of this workshop is to provide a forum to discuss new and emerging general-purpose programming architectures, environments, and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. This year’s workshop is particularly interested in security, new heterogeneous architecture or platforms, new forms of concurrency, and novel or irregular applications that can leverage these platforms.

Papers are being sought on many aspects of GPUs or accelerators, including (but not limited to):
– GPU applications
– GPU programming environments
– GPU runtime systems
– GPU compilation
– GPU architectures
– Multi-GPU systems
– GPU power/efficiency
– GPU reliability
– GPU benchmarking/measurements
– Heterogeneous architectures/platforms
– GPU security (NEW)
– Non-von Neumann architectures (NEW)
– Domain-specific architectures (NEW)

SUBMISSION GUIDELINES:
Full paper submissions must be in PDF format for US letter-size paper. They must not exceed 10 pages (all inclusive) in standard ACM two-column conference format (preprint mode, with page number). Templates for ACM format are available for Microsoft Word, and LaTeX can be found here. The submission site will be up soon.

ORGANIZERS:
Adwait Jog (co-chair), College of William & Mary
Onur Kayiran (co-chair), AMD Research
Ashutosh Pattnaik (submission/web chair), Penn State

Please contact the organizers if you have any questions.

HISTORY AND IMPACT
David Kaeli (Northeastern) and John Cavazos (Delaware) very successfully organized the previous versions of the GPGPU workshop. GPGPU workshop was first held in 2007 at Northeastern University. In 2008, the meeting was held with ASPLOS 2008. This trend continued and the GPGPU workshop was held with ASPLOS for the next 6 years. From 2015 and 2018, GPGPU workshop was co-located with PPoPP. GPGPU 2019 workshop returns to ASPLOS. The average citation count (as per Google Scholar), for a GPGPU workshop paper, is currently 37.5, where there have been 8 influential papers with 100+ citations.

Call for Papers: SELSE 2019
https://www.selse.org/
Submitted by Michael Sullivan

The 15th IEEE Workshop on Silicon Errors in Logic – System Effects
Stanford, Palo Alto, CA, USA
March 27 – March 28, 2019

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high-performance applications.

The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.

We are happy to announce that selected SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Portland, Oregon on June 24 – 27, 2019.

Key areas of interest include (but are not limited to):
– Error rates and trends in current and emerging technologies, including experimental failure data and the reliability characterization of deployed systems.
– New error mitigation techniques, robust software frameworks, and error handling protocols for resilient system design.
– Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.
– Resilience characterization and strategies for machine learning applications, including autonomous vehicles.
– Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.
– The design of resilient systems for space exploration.
– The interplay between system security issues and reliability.

SUBMISSION GUIDELINES:
Additional information and guidelines for submission are available at http://www.selse.org. Submissions and final papers should be PDF files following the IEEE two-column transactions format with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries—however, they are distributed to attendees of the workshop.